X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm_dpm.c;h=b8107d78549f1c91640ee4f59775f375aee14e6c;hb=97fbd793b3a4edec490b2b034f7b6fe5261ca03e;hp=18a9dcc74f771f985cd690fc0851e4a9302328b5;hpb=e6dc927e972bb2d91131b0193b676c531377f318;p=openocd

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 18a9dcc7..b8107d78 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -52,10 +52,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
 
 	retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 
-	/* REVISIT on Cortex-A8, we need a Prefetch Flush operation too ...
-			cortex_a8_exec_opcode(target,
-					ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
-	 */
+	if (dpm->instr_cpsr_sync)
+		retval = dpm->instr_cpsr_sync(dpm);
 
 	return retval;
 }
@@ -142,11 +140,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 				ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 				value);
 
-		/* REVISIT on Cortex-A8, we need a Prefetch Flush operation
-		 * after writing CPSR ...
-			cortex_a8_exec_opcode(target,
-					ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
-		 */
+		if (regnum == 16 && dpm->instr_cpsr_sync)
+			retval = dpm->instr_cpsr_sync(dpm);
 
 		break;
 	}