X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=b21ea4a8865cf5b15c210e5a4f03141dd481c2bb;hb=490e2712904a718efb320d0557f3bb8485676709;hp=217633e898b05b7acf28afc72b4a2106f5b62bb1;hpb=5f993dc17c92630514287f886cffefc560a98c42;p=openocd

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 217633e8..b21ea4a8 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -415,7 +415,12 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 		u8 carry_out;
 		
 		Rd = 0x0;
-		Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+		/* ARM_MOV and ARM_MVN does not use Rn */
+		if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
+			Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+		else
+			Rn = 0;
+
 		shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
 
 		/* adjust Rn in case the PC is being read */
@@ -446,6 +451,8 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
 			Rd = shifter_operand;
 		else if (instruction.type == ARM_MVN)
 			Rd = ~shifter_operand;
+		else
+			LOG_WARNING("unhandled instruction type");
 		
 		if (dry_run_pc)
 		{