X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=4a7fd7a4ba2e9db60bdc0b1a42427e4e69153004;hb=00fd07336e2bf99ad630c6c3a7a337b5f37df638;hp=cf0632f1ac6fc530372b9bfe81d8fb3e9eb3c47e;hpb=2aed5dd40b42f8381d62658522a7ada453e22022;p=openocd

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index cf0632f1..4a7fd7a4 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -231,7 +231,7 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
 			}
 		}
 
-		if (armv4_5_target->core_mode != (value & 0x1f))
+		if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
 		{
 			LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
 			armv4_5_target->core_mode = value & 0x1f;
@@ -661,10 +661,15 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
 	for (i = 0; i <= 16; i++)
 	{
-		LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+		u32 regvalue;
+		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+		if (regvalue != context[i])
+		{
+			LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+		}
 	}
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;