X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=7a6cb61865d52f98db6304ca955fda4b03b89ddc;hb=144e3678bd2d518388b6c2d7f3d2a912a9ac2abd;hp=5bce30b3b1a5f24b4cb2ab5f553184717b304d31;hpb=5706fd7860ea01c591ecf74880a5a5e04e6df22e;p=openocd

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5bce30b3..7a6cb618 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -67,9 +67,6 @@ enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -85,6 +82,11 @@ struct arm
 	/** Handle to the CPSR; valid in all core modes. */
 	struct reg *cpsr;
 
+	/** Handle to the SPSR; valid only in core modes with an SPSR. */
+	struct reg *spsr;
+
+	const int *map;
+
 	/**
 	 * Indicates what registers are in the ARM state core register set.
 	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
@@ -99,6 +101,12 @@ struct arm
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
+	/** Backpointer to the target. */
+	struct target *target;
+
+	/** Handle for the debug module, if one is present. */
+	struct arm_dpm *dpm;
+
 	/** Handle for the Embedded Trace Module, if one is present. */
 	struct etm_context *etm;
 
@@ -161,6 +169,9 @@ int arm_checksum_memory(struct target *target,
 int arm_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;