X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=7a6cb61865d52f98db6304ca955fda4b03b89ddc;hb=144e3678bd2d518388b6c2d7f3d2a912a9ac2abd;hp=81eac476d8871d683f8b2931c28982bed4560fa6;hpb=181d401d59419ec2f5a5d89e2600d9a6dbf8f9ed;p=openocd

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 81eac476..7a6cb618 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -52,31 +52,21 @@ typedef enum armv4_5_state
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern const int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
 
-/* offsets into armv4_5 core register cache */
-enum
-{
-	ARMV4_5_CPSR = 31,
-	ARMV4_5_SPSR_FIQ = 32,
-	ARMV4_5_SPSR_IRQ = 33,
-	ARMV4_5_SPSR_SVC = 34,
-	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36
-};
+/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
+enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -89,19 +79,41 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	int /* armv4_5_mode */ core_mode;
+	/** Handle to the CPSR; valid in all core modes. */
+	struct reg *cpsr;
+
+	/** Handle to the SPSR; valid only in core modes with an SPSR. */
+	struct reg *spsr;
+
+	const int *map;
+
+	/**
+	 * Indicates what registers are in the ARM state core register set.
+	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+	 * more registers are shadowed, for "Secure Monitor" mode.
+	 */
+	enum armv4_5_mode core_type;
+
+	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
+	/** Backpointer to the target. */
+	struct target *target;
+
+	/** Handle for the debug module, if one is present. */
+	struct arm_dpm *dpm;
+
 	/** Handle for the Embedded Trace Module, if one is present. */
 	struct etm_context *etm;
 
 	int (*full_context)(struct target *target);
-	int (*read_core_reg)(struct target *target,
+	int (*read_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target *target,
+	int (*write_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 };
@@ -127,12 +139,13 @@ struct armv4_5_algorithm
 	enum armv4_5_state core_state;
 };
 
-struct armv4_5_core_reg
+struct arm_reg
 {
 	int num;
 	enum armv4_5_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
+	uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
@@ -151,13 +164,14 @@ int armv4_5_run_algorithm(struct target *target,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(struct target *target);
-
 int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum);
 int arm_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;