X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5_mmu.c;h=b7573687b29abde5800a526ea4d13b6134992750;hb=7b97e5b1cc86b7fede586bd65d7b3302f659b9c0;hp=cc8fb3a23a5fa022abc5d3fc0c0da896f491ecc2;hpb=68b05c55759970657c32607b3ce27c42e65cdad0;p=openocd

diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index cc8fb3a2..b7573687 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -25,23 +25,23 @@
 #include "armv4_5_mmu.h"
 
 
-u32 armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap);
+uint32_t armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap);
 
 char* armv4_5_mmu_page_type_names[] =
 {
 	"section", "large page", "small page", "tiny page"
 };
 
-u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap)
+uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap)
 {
-	u32 first_lvl_descriptor = 0x0;
-	u32 second_lvl_descriptor = 0x0;
-	u32 ttb = armv4_5_mmu->get_ttb(target);
+	uint32_t first_lvl_descriptor = 0x0;
+	uint32_t second_lvl_descriptor = 0x0;
+	uint32_t ttb = armv4_5_mmu->get_ttb(target);
 
 	armv4_5_mmu_read_physical(target, armv4_5_mmu,
 		(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
-		4, 1, (u8*)&first_lvl_descriptor);
-	first_lvl_descriptor = target_buffer_get_u32(target, (u8*)&first_lvl_descriptor);
+		4, 1, (uint8_t*)&first_lvl_descriptor);
+	first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
 
 	LOG_DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
 
@@ -76,17 +76,17 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
 		/* coarse page table */
 		armv4_5_mmu_read_physical(target, armv4_5_mmu,
 			(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
-			4, 1, (u8*)&second_lvl_descriptor);
+			4, 1, (uint8_t*)&second_lvl_descriptor);
 	}
 	else if ((first_lvl_descriptor & 0x3) == 3)
 	{
 		/* fine page table */
 		armv4_5_mmu_read_physical(target, armv4_5_mmu,
 			(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
-			4, 1, (u8*)&second_lvl_descriptor);
+			4, 1, (uint8_t*)&second_lvl_descriptor);
 	}
 
-	second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor);
+	second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
 
 	LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
 
@@ -130,7 +130,7 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
 	return ERROR_TARGET_TRANSLATION_FAULT;
 }
 
-int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer)
+int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 
@@ -150,7 +150,7 @@ int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mm
 	return retval;
 }
 
-int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer)
+int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 
@@ -172,12 +172,12 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m
 
 int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
 {
-	u32 va;
-	u32 pa;
+	uint32_t va;
+	uint32_t pa;
 	int type;
-	u32 cb;
+	uint32_t cb;
 	int domain;
-	u32 ap;
+	uint32_t ap;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -219,7 +219,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 {
 	int count = 1;
 	int size = 4;
-	u32 address = 0;
+	uint32_t address = 0;
 	int i;
 
 	char output[128];
@@ -227,7 +227,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 
 	int retval;
 
-	u8 *buffer;
+	uint8_t *buffer;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -299,7 +299,7 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 
 		if ((i % 8 == 7) || (i == count - 1))
 		{
-			command_print(cmd_ctx, output);
+			command_print(cmd_ctx, "%s", output);
 			output_len = 0;
 		}
 	}
@@ -311,10 +311,10 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
 
 int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
 {
-	u32 address = 0;
-	u32 value = 0;
+	uint32_t address = 0;
+	uint32_t value = 0;
 	int retval;
-	u8 value_buf[4];
+	uint8_t value_buf[4];
 
 	if (target->state != TARGET_HALTED)
 	{