X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Farmv7m.c;h=712b5ae341f4b1b28e9f2898bab52a485521d541;hb=391e1b0a57a5308391c2cb3dae18141ee7535ee8;hp=2258967a316821f2cdd7356cb115d8b3c45ef321;hpb=5aa7985bc7156eb357c08e33bcf7de0596634433;p=openocd diff --git a/src/target/armv7m.c b/src/target/armv7m.c index 2258967a..712b5ae3 100644 --- a/src/target/armv7m.c +++ b/src/target/armv7m.c @@ -289,7 +289,7 @@ int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_ /* ARMV7M is always in thumb mode, try to make GDB understand this * if it does not support this arch */ - armv7m->core_cache->reg_list[15].value[0] |= 1; + *((char*)armv7m->core_cache->reg_list[15].value) |= 1; #else (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR]; #endif @@ -303,14 +303,14 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim u32 pc; int retval; /* This code relies on the target specific resume() and poll()->debug_entry() - sequence to write register values to the processor and the read them back */ + * sequence to write register values to the processor and the read them back */ if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK) { return retval; } retval = target_wait_state(target, TARGET_HALTED, timeout_ms); - // If the target fails to halt due to the breakpoint, force a halt + /* If the target fails to halt due to the breakpoint, force a halt */ if (retval != ERROR_OK || target->state != TARGET_HALTED) { if ((retval=target_halt(target))!=ERROR_OK) @@ -322,7 +322,6 @@ static int armv7m_run_and_wait(struct target_s *target, u32 entry_point, int tim return ERROR_TARGET_TIMEOUT; } - armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc); if (pc != exit_point) { @@ -373,7 +372,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ for (i = 0; i < num_reg_params; i++) { reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0); - u32 regvalue; +// u32 regvalue; if (!reg) { @@ -387,7 +386,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ exit(-1); } - regvalue = buf_get_u32(reg_params[i].value, 0, 32); +// regvalue = buf_get_u32(reg_params[i].value, 0, 32); armv7m_set_core_reg(reg, reg_params[i].value); } @@ -450,10 +449,15 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_ for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) { - LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]); - buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); - armv7m->core_cache->reg_list[i].valid = 1; - armv7m->core_cache->reg_list[i].dirty = 1; + u32 regvalue; + regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); + if (regvalue != context[i]) + { + LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]); + buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); + armv7m->core_cache->reg_list[i].valid = 1; + armv7m->core_cache->reg_list[i].dirty = 1; + } } armv7m->core_mode = core_mode; @@ -546,6 +550,14 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m) int armv7m_register_commands(struct command_context_s *cmd_ctx) { + command_t *arm_adi_v5_dap_cmd; + + arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num], default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "return id reg from AP [num], default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "return debug base address from AP [num], default currently selected AP"); + return ERROR_OK; } @@ -587,7 +599,7 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */ }; - int i; + u32 i; if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK) { @@ -636,7 +648,7 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u reg_param_t reg_params[3]; armv7m_algorithm_t armv7m_info; int retval; - int i; + u32 i; u16 erase_check_code[] = { @@ -691,3 +703,114 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u return ERROR_OK; } + +/******************************************************************************************************************** +* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing +*********************************************************************************************************************/ +int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + u32 apsel, apselsave, baseaddr; + int retval; + + apsel = swjdp->apsel; + apselsave = swjdp->apsel; + if (argc > 0) + { + apsel = strtoul(args[0], NULL, 0); + } + if (apselsave != apsel) + { + dap_ap_select(swjdp, apsel); + } + + dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8x", baseaddr); + + if (apselsave != apsel) + { + dap_ap_select(swjdp, apselsave); + } + + return retval; +} + + +/******************************************************************************************************************** +* Return the debug ap id in hexadecimal, no extra output to simplify script processing +*********************************************************************************************************************/ +extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + u32 apsel, apselsave, apid; + int retval; + + apsel = swjdp->apsel; + apselsave = swjdp->apsel; + if (argc > 0) + { + apsel = strtoul(args[0], NULL, 0); + } + + if (apselsave != apsel) + { + dap_ap_select(swjdp, apsel); + } + + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8x", apid); + if (apselsave != apsel) + { + dap_ap_select(swjdp, apselsave); + } + + return retval; +} + +int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + u32 apsel, apid; + int retval; + + apsel = 0; + if (argc > 0) + { + apsel = strtoul(args[0], NULL, 0); + } + + dap_ap_select(swjdp, apsel); + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid); + + return retval; +} + +int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv7m_common_t *armv7m = target->arch_info; + swjdp_common_t *swjdp = &armv7m->swjdp_info; + int retval; + u32 apsel; + + apsel = swjdp->apsel; + if (argc > 0) + { + apsel = strtoul(args[0], NULL, 0); + } + + retval = dap_info_command(cmd_ctx, swjdp, apsel); + + return retval; +} +