X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Fcortex_m3.c;h=be81af98a1644977f8b7aab42be3e7125df10b4c;hb=97fbd793b3a4edec490b2b034f7b6fe5261ca03e;hp=058443457ef9daefff97285691d7e4fccbe265b7;hpb=7bf1a86e473a12882bf6f71cb4d0d416394b69d4;p=openocd diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index 05844345..be81af98 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -221,7 +221,7 @@ static int cortex_m3_endreset_event(struct target *target) } swjdp_transaction_endcheck(swjdp); - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); /* make sure we have latest dhcsr flags */ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); @@ -334,6 +334,9 @@ static int cortex_m3_debug_entry(struct target *target) xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32); #ifdef ARMV7_GDB_HACKS + /* FIXME this breaks on scan chains with more than one Cortex-M3. + * Instead, each CM3 should have its own dummy value... + */ /* copy real xpsr reg for gdb, setting thumb bit */ buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR); buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1); @@ -507,7 +510,7 @@ static int cortex_m3_soft_reset_halt(struct target *target) target->state = TARGET_RESET; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); while (timeout < 100) { @@ -614,7 +617,8 @@ static int cortex_m3_resume(struct target *target, int current, target->debug_reason = DBG_REASON_NOTHALTED; /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(armv7m->core_cache); + if (!debug_execution) { target->state = TARGET_RUNNING; @@ -670,7 +674,7 @@ static int cortex_m3_step(struct target *target, int current, mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr); /* registers are now invalid */ - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); if (breakpoint) cortex_m3_set_breakpoint(target, breakpoint); @@ -809,7 +813,7 @@ static int cortex_m3_assert_reset(struct target *target) target->state = TARGET_RESET; jtag_add_sleep(50000); - armv7m_invalidate_core_regs(target); + register_cache_invalidate(cortex_m3->armv7m.core_cache); if (target->reset_halt) { @@ -1769,26 +1773,26 @@ static int cortex_m3_verify_pointer(struct command_context *cmd_ctx, COMMAND_HANDLER(handle_cortex_m3_disassemble_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); uint32_t address; unsigned long count = 1; struct arm_instruction cur_instruction; - retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); if (retval != ERROR_OK) return retval; errno = 0; switch (CMD_ARGC) { case 2: - COMMAND_PARSE_NUMBER(ulong, args[1], count); + COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], count); /* FALL THROUGH */ case 1: - COMMAND_PARSE_NUMBER(u32, args[0], address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address); break; default: - command_print(cmd_ctx, + command_print(CMD_CTX, "usage: cortex_m3 disassemble
[]"); return ERROR_OK; } @@ -1797,7 +1801,7 @@ COMMAND_HANDLER(handle_cortex_m3_disassemble_command) retval = thumb2_opcode(target, address, &cur_instruction); if (retval != ERROR_OK) return retval; - command_print(cmd_ctx, "%s", cur_instruction.text); + command_print(CMD_CTX, "%s", cur_instruction.text); address += cur_instruction.instruction_size; } @@ -1820,13 +1824,14 @@ static const struct { COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); struct armv7m_common *armv7m = &cortex_m3->armv7m; struct swjdp_common *swjdp = &armv7m->swjdp_info; uint32_t demcr = 0; int retval; - retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); if (retval != ERROR_OK) return retval; @@ -1836,25 +1841,25 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command) unsigned catch = 0; if (CMD_ARGC == 1) { - if (strcmp(args[0], "all") == 0) { + if (strcmp(CMD_ARGV[0], "all") == 0) { catch = VC_HARDERR | VC_INTERR | VC_BUSERR | VC_STATERR | VC_CHKERR | VC_NOCPERR | VC_MMERR | VC_CORERESET; goto write; - } else if (strcmp(args[0], "none") == 0) { + } else if (strcmp(CMD_ARGV[0], "none") == 0) { goto write; } } while (CMD_ARGC-- > 0) { unsigned i; for (i = 0; i < ARRAY_SIZE(vec_ids); i++) { - if (strcmp(args[CMD_ARGC], vec_ids[i].name) != 0) + if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0) continue; catch |= vec_ids[i].mask; break; } if (i == ARRAY_SIZE(vec_ids)) { - LOG_ERROR("No CM3 vector '%s'", args[CMD_ARGC]); + LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]); return ERROR_INVALID_ARGUMENTS; } } @@ -1868,71 +1873,83 @@ write: } for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) - command_print(cmd_ctx, "%9s: %s", vec_ids[i].name, + { + command_print(CMD_CTX, "%9s: %s", vec_ids[i].name, (demcr & vec_ids[i].mask) ? "catch" : "ignore"); + } return ERROR_OK; } COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct cortex_m3_common *cortex_m3 = target_to_cm3(target); int retval; - retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3); + retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } if (CMD_ARGC > 0) { - if (!strcmp(args[0], "on")) - { - cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0); - } - else if (!strcmp(args[0], "off")) - { - cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS); - } - else - { - command_print(cmd_ctx, "usage: cortex_m3 maskisr ['on'|'off']"); - } + bool enable; + COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable); + uint32_t mask_on = C_HALT | (enable ? C_MASKINTS : 0); + uint32_t mask_off = enable ? 0 : C_MASKINTS; + cortex_m3_write_debug_halt_mask(target, mask_on, mask_off); } - command_print(cmd_ctx, "cortex_m3 interrupt mask %s", + command_print(CMD_CTX, "cortex_m3 interrupt mask %s", (cortex_m3->dcb_dhcsr & C_MASKINTS) ? "on" : "off"); return ERROR_OK; } +static const struct command_registration cortex_m3_exec_command_handlers[] = { + { + .name = "disassemble", + .handler = &handle_cortex_m3_disassemble_command, + .mode = COMMAND_EXEC, + .help = "disassemble Thumb2 instructions", + .usage = "
[]", + }, + { + .name = "maskisr", + .handler = &handle_cortex_m3_mask_interrupts_command, + .mode = COMMAND_EXEC, + .help = "mask cortex_m3 interrupts", + .usage = "['on'|'off']", + }, + { + .name = "vector_catch", + .handler = &handle_cortex_m3_vector_catch_command, + .mode = COMMAND_EXEC, + .help = "catch hardware vectors", + .usage = "['all'|'none'|]", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration cortex_m3_command_handlers[] = { + { + .name = "cortex_m3", + .mode = COMMAND_ANY, + .help = "Cortex-M3 command group", + .chain = cortex_m3_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + static int cortex_m3_register_commands(struct command_context *cmd_ctx) { - int retval; - struct command *cortex_m3_cmd; - - retval = armv7m_register_commands(cmd_ctx); - - cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", - NULL, COMMAND_ANY, "cortex_m3 specific commands"); - - register_command(cmd_ctx, cortex_m3_cmd, "disassemble", - handle_cortex_m3_disassemble_command, COMMAND_EXEC, - "disassemble Thumb2 instructions
[]"); - register_command(cmd_ctx, cortex_m3_cmd, "maskisr", - handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, - "mask cortex_m3 interrupts ['on'|'off']"); - register_command(cmd_ctx, cortex_m3_cmd, "vector_catch", - handle_cortex_m3_vector_catch_command, COMMAND_EXEC, - "catch hardware vectors ['all'|'none'|]"); - - return retval; + armv7m_register_commands(cmd_ctx); + return register_commands(cmd_ctx, NULL, cortex_m3_command_handlers); } struct target_type cortexm3_target =