X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Fembeddedice.h;h=08e42c9267f263f5c500629c1d46684246238d55;hb=028e535604bf52761115c81ed65c07d0a4a64cd0;hp=0062153f15f39d3382356b45ad4015fe442172ef;hpb=8b4e882a1630d63bbc9840fa3f968e36b6ac3702;p=openocd diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 0062153f..08e42c92 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -1,7 +1,13 @@ /*************************************************************************** - * Copyright (C) 2005 by Dominic Rath * + * Copyright (C) 2005, 2006 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -20,9 +26,7 @@ #ifndef EMBEDDED_ICE_H #define EMBEDDED_ICE_H -#include "target.h" -#include "register.h" -#include "arm_jtag.h" +#include "arm7_9_common.h" enum { @@ -41,11 +45,14 @@ enum EICE_W1_DATA_VALUE = 12, EICE_W1_DATA_MASK = 13, EICE_W1_CONTROL_VALUE = 14, - EICE_W1_CONTROL_MASK = 15 + EICE_W1_CONTROL_MASK = 15, + EICE_VEC_CATCH = 16 }; enum { + EICE_DBG_CONTROL_ICEDIS = 5, + EICE_DBG_CONTROL_MONEN = 4, EICE_DBG_CONTROL_INTDIS = 2, EICE_DBG_CONTROL_DBGRQ = 1, EICE_DBG_CONTROL_DBGACK = 0, @@ -53,6 +60,7 @@ enum enum { + EICE_DBG_STATUS_IJBIT = 5, EICE_DBG_STATUS_ITBIT = 4, EICE_DBG_STATUS_SYSCOMP = 3, EICE_DBG_STATUS_IFEN = 2, @@ -73,18 +81,49 @@ enum EICE_W_CTRL_nRW = 0x1 }; +enum +{ + EICE_COMM_CTRL_WBIT = 1, + EICE_COMM_CTRL_RBIT = 0 +}; + typedef struct embeddedice_reg_s { int addr; arm_jtag_t *jtag_info; } embeddedice_reg_t; -extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg); +extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9); +extern int embeddedice_setup(target_t *target); extern int embeddedice_read_reg(reg_t *reg); -extern int embeddedice_write_reg(reg_t *reg, u32 value); -extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask); -extern int embeddedice_store_reg(reg_t *reg); -extern int embeddedice_set_reg(reg_t *reg, u32 value); -extern int embeddedice_set_reg_w_exec(reg_t *reg, u32 value); +extern void embeddedice_write_reg(reg_t *reg, uint32_t value); +extern int embeddedice_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask); +extern void embeddedice_store_reg(reg_t *reg); +extern void embeddedice_set_reg(reg_t *reg, uint32_t value); +extern int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf); +extern int embeddedice_receive(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); +extern int embeddedice_send(arm_jtag_t *jtag_info, uint32_t *data, uint32_t size); +extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, uint32_t timeout); + +/* If many embeddedice_write_reg() follow eachother, then the >1 invocations can be this faster version of + * embeddedice_write_reg + */ +static __inline__ void embeddedice_write_reg_inner(jtag_tap_t *tap, int reg_addr, uint32_t value) +{ + static const int embeddedice_num_bits[]={32,5,1}; + uint32_t values[3]; + + values[0]=value; + values[1]=reg_addr; + values[2]=1; + + jtag_add_dr_out(tap, + 3, + embeddedice_num_bits, + values, + jtag_get_end_state()); +} + +void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int little, int count); #endif /* EMBEDDED_ICE_H */