X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Fmips32.h;h=bc88bc37c500d0384660812e8a3db59439da5fb3;hb=d5e183c31f3e6f95f41dd72ac530e1c3dc5adc11;hp=646edb7dedba69f2ad19283b5e4b67275928cf0b;hpb=0cba0d4df3fe120f08945703506f8405760325c9;p=openocd

diff --git a/src/target/mips32.h b/src/target/mips32.h
index 646edb7d..bc88bc37 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -25,13 +25,13 @@
 
 #include "target.h"
 #include "register.h"
-#include "mips_ejtag.h"
 #include "mips32_pracc.h"
 
+
 #define MIPS32_COMMON_MAGIC		0xB320B320
 
 /* offsets into mips32 core register cache */
-enum 
+enum
 {
 	MIPS32_PC = 37,
 	MIPS32NUMCOREREGS
@@ -41,18 +41,18 @@ typedef struct mips32_comparator_s
 {
 	int used;
 	//int type;
-	u32 bp_value;
-	u32 reg_address;
+	uint32_t bp_value;
+	uint32_t reg_address;
 } mips32_comparator_t;
 
 typedef struct mips32_common_s
 {
-	int common_magic;
+	uint32_t common_magic;
 	void *arch_info;
 	reg_cache_t *core_cache;
 	mips_ejtag_t ejtag_info;
-	u32 core_regs[MIPS32NUMCOREREGS];
-	
+	uint32_t core_regs[MIPS32NUMCOREREGS];
+
 	int bp_scanned;
 	int num_inst_bpoints;
 	int num_data_bpoints;
@@ -60,7 +60,7 @@ typedef struct mips32_common_s
 	int num_data_bpoints_avail;
 	mips32_comparator_t *inst_break_list;
 	mips32_comparator_t *data_break_list;
-	
+
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target_s *target, int num);
 	int (*write_core_reg)(struct target_s *target, int num);
@@ -68,12 +68,13 @@ typedef struct mips32_common_s
 
 typedef struct mips32_core_reg_s
 {
-	u32 num;
-	target_t *target;
+	uint32_t num;
+	struct target_s *target;
 	mips32_common_t *mips32_common;
 } mips32_core_reg_t;
 
 #define MIPS32_OP_BEQ	0x04
+#define MIPS32_OP_BNE	0x05
 #define MIPS32_OP_ADDI	0x08
 #define MIPS32_OP_AND	0x24
 #define MIPS32_OP_COP0	0x10
@@ -93,15 +94,16 @@ typedef struct mips32_core_reg_s
 #define MIPS32_COP0_MF	0x00
 #define MIPS32_COP0_MT	0x04
 
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<5) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr)	(((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd)	(((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
+#define MIPS32_J_INST(opcode, addr)	(((opcode) << 26) |(addr))
 
 #define MIPS32_NOP					0
 #define MIPS32_ADDI(tar, src, val)	MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
 #define MIPS32_AND(reg, off, val)	MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
 #define MIPS32_B(off)				MIPS32_BEQ(0, 0, off)
 #define MIPS32_BEQ(src,tar,off)		MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
+#define MIPS32_BNE(src,tar,off)		MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
 #define MIPS32_MFC0(gpr, cpr, sel)	MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
 #define MIPS32_MTC0(gpr,cpr, sel)	MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
 #define MIPS32_LBU(reg, off, base)	MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
@@ -110,21 +112,26 @@ typedef struct mips32_core_reg_s
 #define MIPS32_LW(reg, off, base)	MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
 #define MIPS32_MFLO(reg)			MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
 #define MIPS32_MFHI(reg)			MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
-#define MIPS32_MTLO(reg)			MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTLO)
-#define MIPS32_MTHI(reg)			MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MTHI)
+#define MIPS32_MTLO(reg)			MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
+#define MIPS32_MTHI(reg)			MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
 #define MIPS32_ORI(src, tar, val)	MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
 #define MIPS32_SB(reg, off, base)	MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
 #define MIPS32_SH(reg, off, base)	MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
 #define MIPS32_SW(reg, off, base)	MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
+
+/* ejtag specific instructions */
 #define MIPS32_DRET					0x4200001F
+#define MIPS32_SDBBP				0x7000003F
+#define MIPS16_SDBBP 				0xE801
 
 extern int mips32_arch_state(struct target_s *target);
 extern int mips32_init_arch_info(target_t *target, mips32_common_t *mips32, jtag_tap_t *tap);
 extern int mips32_restore_context(target_t *target);
 extern int mips32_save_context(target_t *target);
 extern reg_cache_t *mips32_build_reg_cache(target_t *target);
-extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int mips32_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 extern int mips32_configure_break_unit(struct target_s *target);
+extern int mips32_enable_interrupts(struct target_s *target, int enable);
 extern int mips32_examine(struct target_s *target);
 
 extern int mips32_register_commands(struct command_context_s *cmd_ctx);