X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Fmips32_dmaacc.c;h=d756928a09a6a4a915939f92fab70a9ce95b0aa5;hb=18918a0423e04180f580a4a9453e190488aab17d;hp=9194bf6176f6070c1e7520c3f63d0c86a48ad7ee;hpb=3c2eabd20f5182c53f0bfb0c6f2a9f2595434e87;p=openocd

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index 9194bf61..d756928a 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -28,6 +28,19 @@
 
 #include "mips32_dmaacc.h"
 
+static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint8_t *buf);
+static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint16_t *buf);
+static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint32_t *buf);
+
+static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint8_t *buf);
+static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint16_t *buf);
+static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
+		uint32_t addr, int count, uint32_t *buf);
 
 /*
  * The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
@@ -39,7 +52,7 @@
  * displaying/modifying memory and memory mapped registers.
  */
 
-static int ejtag_dma_read(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t *data)
+static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -49,11 +62,11 @@ begin_ejtag_dma_read:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -61,31 +74,31 @@ begin_ejtag_dma_read:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, data);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read;
 		}
 		else
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
 	return ERROR_OK;
 }
 
-static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint16_t *data)
+static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -95,11 +108,11 @@ begin_ejtag_dma_read_h:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -107,24 +120,24 @@ begin_ejtag_dma_read_h:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read_h;
 		}
 		else
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -137,7 +150,7 @@ begin_ejtag_dma_read_h:
 	return ERROR_OK;
 }
 
-static int ejtag_dma_read_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint8_t *data)
+static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -147,11 +160,11 @@ begin_ejtag_dma_read_b:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -159,24 +172,24 @@ begin_ejtag_dma_read_b:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ (retrying)\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ (retrying)\n", addr);
 			goto begin_ejtag_dma_read_b;
 		}
 		else
-			LOG_ERROR("DMA Read Addr = %08x  Data = ERROR ON READ\n", addr);
+			LOG_ERROR("DMA Read Addr = %08" PRIx32 "  Data = ERROR ON READ\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -191,7 +204,7 @@ begin_ejtag_dma_read_b:
 		case 2:
 			*data = (v >> 16) & 0xff;
 			break;
-		case 3: 
+		case 3:
 			*data = (v >> 24) & 0xff;
 			break;
 	}
@@ -199,7 +212,7 @@ begin_ejtag_dma_read_b:
 	return ERROR_OK;
 }
 
-static int ejtag_dma_write(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data)
+static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -209,16 +222,16 @@ begin_ejtag_dma_write:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -226,27 +239,27 @@ begin_ejtag_dma_write:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write;
 		}
 		else
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
 	return ERROR_OK;
 }
 
-static int ejtag_dma_write_h(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data)
+static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -260,16 +273,16 @@ begin_ejtag_dma_write_h:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -277,27 +290,27 @@ begin_ejtag_dma_write_h:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write_h;
 		}
 		else
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
 	return ERROR_OK;
 }
 
-static int ejtag_dma_write_b(mips_ejtag_t *ejtag_info, uint32_t addr, uint32_t data)
+static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
 {
 	uint32_t v;
 	uint32_t ejtag_ctrl;
@@ -312,16 +325,16 @@ begin_ejtag_dma_write_b:
 
 	/*  Setup Address*/
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -329,27 +342,27 @@ begin_ejtag_dma_write_b:
 	do {
 		ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	} while(ejtag_ctrl & EJTAG_CTRL_DSTRT);
+	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl & EJTAG_CTRL_DERR)
 	{
 		if (retries--) {
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE (retrying)\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE (retrying)\n", addr);
 			goto begin_ejtag_dma_write_b;
 		}
 		else
-			LOG_ERROR("DMA Write Addr = %08x  Data = ERROR ON WRITE\n", addr);
+			LOG_ERROR("DMA Write Addr = %08" PRIx32 "  Data = ERROR ON WRITE\n", addr);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf)
+int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
 {
 	switch (size)
 	{
@@ -364,46 +377,46 @@ int mips32_dmaacc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, in
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf)
+static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
 {
 	int i;
 	int	retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_read(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_read(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf)
+static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
 {
 	int i;
 	int retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_read_h(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_read_h(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_read_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf)
+static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
 {
 	int i;
 	int retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_read_b(ejtag_info, addr+i*sizeof(*buf), &buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_read_b(ejtag_info, addr + i*sizeof(*buf), &buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf)
+int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
 {
 	switch (size)
 	{
@@ -418,39 +431,39 @@ int mips32_dmaacc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, i
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem32(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint32_t *buf)
+static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
 {
 	int i;
 	int retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_write(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_write(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem16(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint16_t *buf)
+static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
 {
 	int i;
 	int retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_write_h(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_write_h(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}
 
 	return ERROR_OK;
 }
 
-int mips32_dmaacc_write_mem8(mips_ejtag_t *ejtag_info, uint32_t addr, int count, uint8_t *buf)
+static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
 {
 	int i;
 	int retval;
 
-	for (i=0; i<count; i++) {
-		if ((retval = ejtag_dma_write_b(ejtag_info, addr+i*sizeof(*buf), buf[i])) != ERROR_OK)
+	for (i = 0; i < count; i++) {
+		if ((retval = ejtag_dma_write_b(ejtag_info, addr + i*sizeof(*buf), buf[i])) != ERROR_OK)
 			return retval;
 	}