X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=src%2Ftarget%2Fxscale.c;h=4630f68a56ca174fbc369f309d640f07245b0f42;hb=56944ac1c83c0e420117ef9f0c6f2de53c8ed424;hp=d0180b97676cc6a7f9942715a4c65ae9486c8e81;hpb=f90d8fa45f2d4c9d4b7990f198b232ee55cbb4e1;p=openocd

diff --git a/src/target/xscale.c b/src/target/xscale.c
index d0180b97..4630f68a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -959,7 +959,7 @@ int xscale_arch_state(struct target_s *target)
 			"MMU: %s, D-Cache: %s, I-Cache: %s"
 			"%s",
 			 armv4_5_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
+			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 			 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
@@ -1202,7 +1202,7 @@ int xscale_halt(target_t *target)
 	xscale_common_t *xscale = armv4_5->arch_info;
 
 	LOG_DEBUG("target->state: %s",
-		  Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+		  target_state_name(target));
 
 	if (target->state == TARGET_HALTED)
 	{
@@ -1568,7 +1568,7 @@ int xscale_assert_reset(target_t *target)
 	xscale_common_t *xscale = armv4_5->arch_info;
 
 	LOG_DEBUG("target->state: %s",
-		  Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
+		  target_state_name(target));
 
 	/* select DCSR instruction (set endstate to R-T-I to ensure we don't
 	 * end up in T-L-R, which would reset JTAG