X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=tcl%2Ftarget%2Fat91sam9g20.cfg;h=3f5e3c6264d3e63834e4abe48ea180d34be0ac58;hb=d4e195ad1b544b0396cab4c70437371958769196;hp=8a2e69b91f97530884e0e902064e7e74f2fded56;hpb=2b10052097c882cf0ed92748c15ff6ee001c1f8f;p=openocd

diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg
index 8a2e69b9..3f5e3c62 100644
--- a/tcl/target/at91sam9g20.cfg
+++ b/tcl/target/at91sam9g20.cfg
@@ -12,7 +12,7 @@ source [find target/at91sam9.cfg]
 
 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
 
-jtag_rclk 5
+adapter_khz 5
 
 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.