X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=tcl%2Ftarget%2Fimx27.cfg;h=dabae6d70f8d621cc59dfb5d07e990f84eb7099a;hb=00635e28ba5c405742cae261d8551f165dc78ba3;hp=837ea6146ac7025ef6825afdb7a47f9c2bde4281;hpb=71af49ca7fb11b0bd0c1ba9578826f49288b68ef;p=openocd

diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg
index 837ea614..dabae6d7 100644
--- a/tcl/target/imx27.cfg
+++ b/tcl/target/imx27.cfg
@@ -21,13 +21,13 @@ if { [info exists ENDIAN] } {
 
 # Note above there are 2 taps
 
-# The bs tap
-if { [info exists BSTAPID ] } {
-   set _BSTAPID $BSTAPID
+# trace buffer
+if { [info exists ETBTAPID ] } {
+   set _ETBTAPID $ETBTAPID
 } else {
-   set _BSTAPID 0x1b900f0f
+   set _ETBTAPID 0x1b900f0f
 }
-jtag newtap $_CHIPNAME bs  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME etb  -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
 
 # The CPU tap
 if { [info exists CPUTAPID ] } {
@@ -40,8 +40,14 @@ jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_C
 # Create the GDB Target.
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size  0x8000 -work-area-backup 1
+# REVISIT what operating environment sets up this virtual address mapping?
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
+	-work-area-size  0x8000 -work-area-backup 1
 # Internal to the chip, there is 45K of SRAM
 #
 
 arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb