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(parent: c46a78b) | patch
RISC-V:
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 12 Sep 2018 16:33:05 +0000 (16:33 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 12 Sep 2018 16:33:05 +0000 (16:33 +0000)
commit3341a29bfc974113e126cbf374cc52282627c898
tree319344ec0b73a2c0c9d25bf4c7ade3f7eae29bbftree | snapshot
parentc46a78b713f1aa838e0c0c6f66209a0f4b7fde8ecommit | diff
RISC-V:
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2583 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c diff | blob | history
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h diff | blob | history
FreeRTOS imported from SF.net SVN