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RISC-V port updates: The machine timer compare register can now be for any HART...
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 4 Sep 2019 15:46:45 +0000 (15:46 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Wed, 4 Sep 2019 15:46:45 +0000 (15:46 +0000)
commit5c0dcccf48ce65dce0860170de3b6f02d409e4cd
tree3d6437598b7484868a3a510af7f0e0292ba7a5b1tree | snapshot
parent704f0f76a7645c232157e1dbf6ed0a062f990954commit | diff
RISC-V port updates:  The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2720 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/RISC-V/port.c diff | blob | history
FreeRTOS/Source/portable/GCC/RISC-V/portASM.S diff | blob | history
FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h [deleted file] blob | history
FreeRTOS/Source/portable/IAR/RISC-V/port.c diff | blob | history
FreeRTOS/Source/portable/IAR/RISC-V/portASM.s diff | blob | history
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