jtag: usb_blaster: fix initialization regression

jtag: usb_blaster: fix initialization regression

As Daniel pointed out, since the rewrite of the USB Blaster driver, the
initialization behaviour has change. The initial flush of the FIFOs is
not longer done with a specific USB setup packet, but with a write
filling up the blaster queues.

The problem is, quoting Daniel :

    When the CPLD is in bit banging mode (as is usually the case), the
    first 0x00 byte sets all pins to low and disables the output
    driver. Disabling the output drivers is a few nanoseconds slower
    than changing a pin from high to low, so I see a spike towards GND
    on my reset line when that byte is sent over USB. The spike is too
    short to have an effect on the board.

    When the 4096 0x00 bytes are processed and the TMS=1 is to be
    generated, all I see is several microseconds of low level on all
    pins, resetting my board.

This patch changes the way the initialization is done :
 - at driver init, nothing is sent towards the usb-blaster
   This gives time for init script to setup PIN6 and PIN8 (resets)
 - at the very first driver command, the initialization is done :
   - the output is in bit bigbang mode
   - the PIN6 and PIN8 are computed according to init script
   - the 4096 computed output is sent

Change-Id: If7ceee957f6b59bcb27c8f912f1cfdd0f94f75ed
Reported-by: Daniel Glöckner <daniel-gl@gmx.net>
Cc: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/2229
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Daniel Glöckner <daniel-gl@gmx.net>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>