]> git.sur5r.net Git - freertos/commit
Update RISC-V port to use a separate interrupt stack.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 4 Dec 2018 01:23:41 +0000 (01:23 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 4 Dec 2018 01:23:41 +0000 (01:23 +0000)
commit8cab7d96ec46edb803583a41bb1c906fc76bcd18
tree2d9e78b1eaf94075b6231a4969ba5f1d39894bb5
parentb1a107796313c5a64ee33ca3accff1a701b2cc71
Update RISC-V port to use a separate interrupt stack.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2598 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portmacro.h