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(parent: cf532a6) | patch
Provide each Risc V task with an initial mstatus register value.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 20 Nov 2018 20:12:35 +0000 (20:12 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Tue, 20 Nov 2018 20:12:35 +0000 (20:12 +0000)
commit8d4bce922ee92c68de2e71a69d04c7779b521311
tree61a23cec1564e1035a4edd044adf16cc1c2dc6bdtree | snapshot
parentcf532a6b7f9e3f6f07f9c013644a9afe0ec52b68commit | diff
Provide each Risc V task with an initial mstatus register value.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2593 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/RISC-V-RV32/port.c diff | blob | history
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S diff | blob | history
FreeRTOS imported from SF.net SVN