]> git.sur5r.net Git - openocd/commit
David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen...
authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Fri, 28 Aug 2009 06:52:08 +0000 (06:52 +0000)
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Fri, 28 Aug 2009 06:52:08 +0000 (06:52 +0000)
commit997d5284cb5c8961ec11c3225fad7692efec6e9a
treebb50c31c3be0f31ca1506a342cc0bdd72d4552ec
parentae17ce23eb7bf4c0892c609f0a49daa8cd63d8c5
David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
src/target/arm_disassembler.c