]> git.sur5r.net Git - freertos/commit
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into...
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 21 Apr 2019 20:15:34 +0000 (20:15 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 21 Apr 2019 20:15:34 +0000 (20:15 +0000)
commitc16304777037ac92d50e86e1535c29b37518a1b0
tree7a82f9705998a2f1cf32b1ec18a7f8110366e90f
parent87c1213e45a8d47f4c8023bc302808c3d34c925b
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2650 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h