git.sur5r.net Git - openocd/commit

]> git.sur5r.net Git - openocd/commit

author	drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
	Wed, 22 Nov 2006 13:03:10 +0000 (13:03 +0000)
committer	drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
	Wed, 22 Nov 2006 13:03:10 +0000 (13:03 +0000)
commit	e9297b40b994f071474210e7d9e224d50e25fcaf
tree	c04957b7721ab6825e73fad0775677643f82fc23	tree \| snapshot
parent	03e8f264f4c66baec9b86778d3488b23e0a8c0b6	commit \| diff

- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration
- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes

git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60

16 files changed:

src/Makefile.am		diff \| blob \| history
src/flash/cfi.c		diff \| blob \| history
src/helper/binarybuffer.c		diff \| blob \| history
src/jtag/Makefile.am		diff \| blob \| history
src/jtag/ft2232.c		diff \| blob \| history
src/jtag/gw16012.c	[new file with mode: 0644]	blob
src/jtag/jtag.c		diff \| blob \| history
src/openocd.c		diff \| blob \| history
src/pld/Makefile.am	[new file with mode: 0644]	blob
src/pld/pld.c	[new file with mode: 0644]	blob
src/pld/pld.h	[new file with mode: 0644]	blob
src/pld/virtex2.c	[new file with mode: 0644]	blob
src/pld/virtex2.h	[new file with mode: 0644]	blob
src/pld/xilinx_bit.c	[new file with mode: 0644]	blob
src/pld/xilinx_bit.h	[new file with mode: 0644]	blob
src/target/armv4_5.c		diff \| blob \| history

Cloned from https://git.code.sf.net/p/openocd/code

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