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(parent: 61ff033) | patch
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 30 Dec 2018 23:11:40 +0000 (23:11 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 30 Dec 2018 23:11:40 +0000 (23:11 +0000)
commit829657a8119bfebf67c1f8a845652dcd5ca7262c
treea13cb21940a922b5aa9ca1b6307a49377fb20ac4tree | snapshot
parent61ff033c790eab87bc90169ee89e47ad7340789ecommit | diff
Update RSIC-V port layer after testing saving and receiving of chip specific registers.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2617 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h diff | blob | history
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S diff | blob | history
FreeRTOS imported from SF.net SVN