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536ea7c)
16 files changed:
{\r
uint32_t ulMaskBits;\r
\r
{\r
uint32_t ulMaskBits;\r
\r
- __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) );\r
+ __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );\r
configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\r
}\r
#endif /* configASSERT_DEFINED */\r
configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );\r
}\r
#endif /* configASSERT_DEFINED */\r
updated. */\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb sy \n"\r
updated. */\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb sy \n"\r
+ "isb sy \n" ::: "memory" );\r
\r
/* Ok to enable interrupts after the interrupt source has been cleared. */\r
configCLEAR_TICK_INTERRUPT();\r
\r
/* Ok to enable interrupts after the interrupt source has been cleared. */\r
configCLEAR_TICK_INTERRUPT();\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb sy \n"\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb sy \n"\r
+ "isb sy \n" ::: "memory" );\r
}\r
portENABLE_INTERRUPTS();\r
\r
}\r
portENABLE_INTERRUPTS();\r
\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
#if defined( GUEST )\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
#if defined( GUEST )\r
- #define portYIELD() __asm volatile ( "SVC 0" )\r
+ #define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )\r
- #define portYIELD() __asm volatile ( "SMC 0" )\r
+ #define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )\r
#endif\r
/*-----------------------------------------------------------\r
* Critical section control\r
#endif\r
/*-----------------------------------------------------------\r
* Critical section control\r
extern void vPortInstallFreeRTOSVectorTable( void );\r
\r
#define portDISABLE_INTERRUPTS() \\r
extern void vPortInstallFreeRTOSVectorTable( void );\r
\r
#define portDISABLE_INTERRUPTS() \\r
- __asm volatile ( "MSR DAIFSET, #2" ); \\r
+ __asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \\r
__asm volatile ( "DSB SY" ); \\r
__asm volatile ( "ISB SY" );\r
\r
#define portENABLE_INTERRUPTS() \\r
__asm volatile ( "DSB SY" ); \\r
__asm volatile ( "ISB SY" );\r
\r
#define portENABLE_INTERRUPTS() \\r
- __asm volatile ( "MSR DAIFCLR, #2" ); \\r
+ __asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \\r
__asm volatile ( "DSB SY" ); \\r
__asm volatile ( "ISB SY" );\r
\r
__asm volatile ( "DSB SY" ); \\r
__asm volatile ( "ISB SY" );\r
\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
- __asm volatile ( "CPSID i" ); \\r
+ __asm volatile ( "CPSID i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
- __asm volatile ( "CPSIE i" ); \\r
+ __asm volatile ( "CPSIE i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
/*\r
* If the application provides an implementation of vApplicationIRQHandler(),\r
* then it will get called directly without saving the FPU registers on\r
/*\r
* If the application provides an implementation of vApplicationIRQHandler(),\r
* then it will get called directly without saving the FPU registers on\r
- * interrupt entry, and this weak implementation of \r
+ * interrupt entry, and this weak implementation of\r
* vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\r
* it should never actually get called so its implementation contains a\r
* call to configASSERT() that will always fail.\r
*\r
* vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -\r
* it should never actually get called so its implementation contains a\r
* call to configASSERT() that will always fail.\r
*\r
- * If the application provides its own implementation of \r
- * vApplicationFPUSafeIRQHandler() then the implementation of \r
+ * If the application provides its own implementation of\r
+ * vApplicationFPUSafeIRQHandler() then the implementation of\r
* vApplicationIRQHandler() provided in portASM.S will save the FPU registers\r
* before calling it.\r
*\r
* Therefore, if the application writer wants FPU registers to be saved on\r
* vApplicationIRQHandler() provided in portASM.S will save the FPU registers\r
* before calling it.\r
*\r
* Therefore, if the application writer wants FPU registers to be saved on\r
- * interrupt entry their IRQ handler must be called \r
+ * interrupt entry their IRQ handler must be called\r
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want\r
* FPU registers to be saved on interrupt entry their IRQ handler must be\r
* called vApplicationIRQHandler().\r
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want\r
* FPU registers to be saved on interrupt entry their IRQ handler must be\r
* called vApplicationIRQHandler().\r
#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\r
}\r
#endif\r
#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.\r
}\r
#endif\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
ulPortTaskHasFPUContext = pdTRUE;\r
\r
/* Initialise the floating point status register. */\r
ulPortTaskHasFPUContext = pdTRUE;\r
\r
/* Initialise the floating point status register. */\r
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
}\r
\r
#endif /* configUSE_TASK_FPU_SUPPORT */\r
}\r
\r
#endif /* configUSE_TASK_FPU_SUPPORT */\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
}\r
portCPU_IRQ_ENABLE();\r
\r
}\r
portCPU_IRQ_ENABLE();\r
\r
}\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
}\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-#define portYIELD() __asm volatile ( "SWI 0" );\r
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );\r
\r
\r
/*-----------------------------------------------------------\r
\r
\r
/*-----------------------------------------------------------\r
#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )\r
#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )\r
#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )\r
-#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )\r
-#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )\r
-#define portNVIC_SYSTICK_CLK 0x00000004\r
-#define portNVIC_SYSTICK_INT 0x00000002\r
-#define portNVIC_SYSTICK_ENABLE 0x00000001\r
-#define portNVIC_PENDSVSET 0x10000000\r
-#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
-#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
-#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
+#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK 0x00000004\r
+#define portNVIC_SYSTICK_INT 0x00000002\r
+#define portNVIC_SYSTICK_ENABLE 0x00000001\r
+#define portNVIC_PENDSVSET 0x10000000\r
+#define portMIN_INTERRUPT_PRIORITY ( 255UL )\r
+#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
+#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
\r
/* Constants required to set up the initial stack. */\r
#define portINITIAL_XPSR ( 0x01000000 )\r
\r
/* Barriers are normally not required but do ensure the code is completely\r
within the specified behaviour for the architecture. */\r
\r
/* Barriers are normally not required but do ensure the code is completely\r
within the specified behaviour for the architecture. */\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
{\r
portDISABLE_INTERRUPTS();\r
uxCriticalNesting++;\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
__asm volatile( "isb" );\r
}\r
/*-----------------------------------------------------------*/\r
" mrs r0, PRIMASK \n"\r
" cpsid i \n"\r
" bx lr "\r
" mrs r0, PRIMASK \n"\r
" cpsid i \n"\r
" bx lr "\r
);\r
\r
/* To avoid compiler warnings. This line will never be reached. */\r
);\r
\r
/* To avoid compiler warnings. This line will never be reached. */\r
__asm volatile(\r
" msr PRIMASK, r0 \n"\r
" bx lr "\r
__asm volatile(\r
" msr PRIMASK, r0 \n"\r
" bx lr "\r
);\r
\r
/* Just to avoid compiler warning. */\r
);\r
\r
/* Just to avoid compiler warning. */\r
\r
#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
\r
#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
-#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " )\r
-#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
\r
#define portENTER_CRITICAL() vPortEnterCritical()\r
#define portEXIT_CRITICAL() vPortExitCritical()\r
\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" ldmia sp!, {r3, r14} \n"\r
" mov r0, #0 \n"\r
" msr basepri, r0 \n"\r
" ldmia sp!, {r3, r14} \n"\r
- " \n" /* Restore the context, including the critical nesting count. */\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
" ldr r1, [r3] \n"\r
" ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
" ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
- \r
- /* Disable the SysTick clock without reading the \r
- portNVIC_SYSTICK_CTRL_REG register to ensure the \r
+ __asm volatile( "cpsie i" ::: "memory" );\r
+\r
+ /* Disable the SysTick clock without reading the\r
+ portNVIC_SYSTICK_CTRL_REG register to ensure the\r
portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */\r
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
\r
portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */\r
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\r
\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
- __asm volatile( "dsb" ); \\r
+ __asm volatile( "dsb" ::: "memory" ); \\r
__asm volatile( "isb" ); \\r
}\r
\r
__asm volatile( "isb" ); \\r
}\r
\r
{\r
uint8_t ucReturn;\r
\r
{\r
uint8_t ucReturn;\r
\r
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
return ucReturn;\r
}\r
\r
return ucReturn;\r
}\r
\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
__asm volatile\r
(\r
" mrs %0, basepri \n" \\r
__asm volatile\r
(\r
" mrs %0, basepri \n" \\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
);\r
}\r
/*-----------------------------------------------------------*/\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )\r
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )\r
\r
typedef struct MPU_REGION_REGISTERS\r
{\r
\r
typedef struct MPU_REGION_REGISTERS\r
{\r
\r
/* Scheduler utilities. */\r
\r
\r
/* Scheduler utilities. */\r
\r
-#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) )\r
+#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" )\r
#define portYIELD_WITHIN_API() \\r
{ \\r
/* Set a PendSV to request a context switch. */ \\r
#define portYIELD_WITHIN_API() \\r
{ \\r
/* Set a PendSV to request a context switch. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
- __asm volatile( "dsb" ); \\r
+ __asm volatile( "dsb" ::: "memory" ); \\r
__asm volatile( "isb" ); \\r
}\r
\r
__asm volatile( "isb" ); \\r
}\r
\r
{\r
uint8_t ucReturn;\r
\r
{\r
uint8_t ucReturn;\r
\r
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
return ucReturn;\r
}\r
\r
return ucReturn;\r
}\r
\r
__asm volatile ( " mrs r0, control \n" \\r
" orr r0, #1 \n" \\r
" msr control, r0 \n" \\r
__asm volatile ( " mrs r0, control \n" \\r
" orr r0, #1 \n" \\r
" msr control, r0 \n" \\r
}\r
}\r
/*-----------------------------------------------------------*/\r
}\r
}\r
/*-----------------------------------------------------------*/\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
\r
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
\r
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
- __asm volatile( "dsb" ); \\r
+ __asm volatile( "dsb" ::: "memory" ); \\r
__asm volatile( "isb" ); \\r
}\r
\r
__asm volatile( "isb" ); \\r
}\r
\r
{\r
uint8_t ucReturn;\r
\r
{\r
uint8_t ucReturn;\r
\r
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
return ucReturn;\r
}\r
\r
return ucReturn;\r
}\r
\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
);\r
}\r
/*-----------------------------------------------------------*/\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
\r
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" )\r
+#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )\r
\r
typedef struct MPU_REGION_REGISTERS\r
{\r
\r
typedef struct MPU_REGION_REGISTERS\r
{\r
\r
/* Scheduler utilities. */\r
\r
\r
/* Scheduler utilities. */\r
\r
-#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) )\r
+#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) : "memory" )\r
#define portYIELD_WITHIN_API() \\r
{ \\r
/* Set a PendSV to request a context switch. */ \\r
#define portYIELD_WITHIN_API() \\r
{ \\r
/* Set a PendSV to request a context switch. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
- __asm volatile( "dsb" ); \\r
+ __asm volatile( "dsb" ::: "memory" ); \\r
__asm volatile( "isb" ); \\r
}\r
\r
__asm volatile( "isb" ); \\r
}\r
\r
{\r
uint8_t ucReturn;\r
\r
{\r
uint8_t ucReturn;\r
\r
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
return ucReturn;\r
}\r
\r
return ucReturn;\r
}\r
\r
__asm volatile ( " mrs r0, control \n" \\r
" orr r0, #1 \n" \\r
" msr control, r0 \n" \\r
__asm volatile ( " mrs r0, control \n" \\r
" orr r0, #1 \n" \\r
" msr control, r0 \n" \\r
}\r
}\r
/*-----------------------------------------------------------*/\r
}\r
}\r
/*-----------------------------------------------------------*/\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %0 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
" msr basepri, %1 \n" \\r
" isb \n" \\r
" dsb \n" \\r
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
);\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
\r
/* Enter a critical section but don't use the taskENTER_CRITICAL()\r
method as that will mask interrupts that should exit sleep mode. */\r
- __asm volatile( "cpsid i" );\r
+ __asm volatile( "cpsid i" ::: "memory" );\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
__asm volatile( "dsb" );\r
__asm volatile( "isb" );\r
\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
if( xModifiableIdleTime > 0 )\r
{\r
- __asm volatile( "dsb" );\r
+ __asm volatile( "dsb" ::: "memory" );\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
__asm volatile( "wfi" );\r
__asm volatile( "isb" );\r
}\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
\r
/* Re-enable interrupts - see comments above the cpsid instruction()\r
above. */\r
- __asm volatile( "cpsie i" );\r
+ __asm volatile( "cpsie i" ::: "memory" );\r
\r
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
\r
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
{\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
uint8_t ucCurrentPriority;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\r
/* Is the interrupt number a user defined interrupt? */\r
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
\\r
/* Barriers are normally not required but do ensure the code is completely \\r
within the specified behaviour for the architecture. */ \\r
- __asm volatile( "dsb" ); \\r
+ __asm volatile( "dsb" ::: "memory" ); \\r
__asm volatile( "isb" ); \\r
}\r
\r
__asm volatile( "isb" ); \\r
}\r
\r
{\r
uint8_t ucReturn;\r
\r
{\r
uint8_t ucReturn;\r
\r
- __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );\r
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );\r
return ucReturn;\r
}\r
\r
return ucReturn;\r
}\r
\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
BaseType_t xReturn;\r
\r
/* Obtain the number of the currently executing interrupt. */\r
- __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
\r
if( ulCurrentInterrupt == 0 )\r
{\r
" isb \n" \\r
" dsb \n" \\r
" cpsie i \n" \\r
" isb \n" \\r
" dsb \n" \\r
" cpsie i \n" \\r
- :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
" isb \n" \\r
" dsb \n" \\r
" cpsie i \n" \\r
" isb \n" \\r
" dsb \n" \\r
" cpsie i \n" \\r
- :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
+ :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
);\r
\r
/* This return will not be reached but is necessary to prevent compiler\r
- " msr basepri, %0 " :: "r" ( ulNewMaskValue )\r
+ " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"\r
);\r
}\r
/*-----------------------------------------------------------*/\r
);\r
}\r
/*-----------------------------------------------------------*/\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
determined priority level. Sometimes it is necessary to turn interrupt off in\r
the CPU itself before modifying certain hardware registers. */\r
#define portCPU_IRQ_DISABLE() \\r
- __asm volatile ( "CPSID i" ); \\r
+ __asm volatile ( "CPSID i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
#define portCPU_IRQ_ENABLE() \\r
- __asm volatile ( "CPSIE i" ); \\r
+ __asm volatile ( "CPSIE i" ::: "memory" ); \\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
__asm volatile ( "DSB" ); \\r
__asm volatile ( "ISB" );\r
\r
{ \\r
portCPU_IRQ_DISABLE(); \\r
portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
{ \\r
portCPU_IRQ_DISABLE(); \\r
portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \\r
- __asm( "DSB \n" \\r
- "ISB \n" ); \\r
+ __asm volatile ( "DSB \n" \\r
+ "ISB \n" ); \\r
portCPU_IRQ_ENABLE(); \\r
}\r
\r
portCPU_IRQ_ENABLE(); \\r
}\r
\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
\r
/* Only continue if the CPU is not in User mode. The CPU must be in a\r
Privileged mode for the scheduler to start. */\r
- __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );\r
+ __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
ulAPSR &= portAPSR_MODE_BITS_MASK;\r
configASSERT( ulAPSR != portAPSR_USER_MODE );\r
\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
portCPU_IRQ_DISABLE();\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
portCPU_IRQ_ENABLE();\r
\r
/* Increment the RTOS tick. */\r
ulPortTaskHasFPUContext = pdTRUE;\r
\r
/* Initialise the floating point status register. */\r
ulPortTaskHasFPUContext = pdTRUE;\r
\r
/* Initialise the floating point status register. */\r
- __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );\r
+ __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );\r
}\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
ulReturn = pdFALSE;\r
portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );\r
__asm volatile ( "dsb \n"\r
+ "isb \n" ::: "memory" );\r
}\r
portCPU_IRQ_ENABLE();\r
\r
}\r
portCPU_IRQ_ENABLE();\r
\r
}\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
}\r
\r
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
-#define portYIELD() __asm volatile ( "SWI 0" );\r
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );\r
\r
\r
/*-----------------------------------------------------------\r
\r
\r
/*-----------------------------------------------------------\r