+ asm volatile ( "reg_test_1_start: \n\t"\r
+ " moveq #1, %d0 \n\t"\r
+ " moveq #2, %d1 \n\t"\r
+ " moveq #3, %d2 \n\t"\r
+ " moveq #4, %d3 \n\t"\r
+ " moveq #5, %d4 \n\t"\r
+ " moveq #6, %d5 \n\t"\r
+ " moveq #7, %d6 \n\t"\r
+ " moveq #8, %d7 \n\t"\r
+ " move #9, %a0 \n\t"\r
+ " move #10, %a1 \n\t"\r
+ " move #11, %a2 \n\t"\r
+ " move #12, %a3 \n\t"\r
+ " move #13, %a4 \n\t"\r
+ " move #14, %a5 \n\t"\r
+ " move #15, %a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #1, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #2, %d1 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #3, %d2 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #4, %d3 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #5, %d4 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #6, %d5 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #7, %d6 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #8, %d7 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a0, %d0 \n\t"\r
+ " cmpi.l #9, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a1, %d0 \n\t"\r
+ " cmpi.l #10, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a2, %d0 \n\t"\r
+ " cmpi.l #11, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a3, %d0 \n\t"\r
+ " cmpi.l #12, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a4, %d0 \n\t"\r
+ " cmpi.l #13, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a5, %d0 \n\t"\r
+ " cmpi.l #14, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move %a6, %d0 \n\t"\r
+ " cmpi.l #15, %d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " movel ulRegTest1Counter, %d0 \n\t"\r
+ " addql #1, %d0 \n\t"\r
+ " movel %d0, ulRegTest1Counter \n\t"\r
+ " bra reg_test_1_start \n\t"\r
+ "reg_test_1_error: \n\t"\r
+ " bra reg_test_1_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+ ( void ) pvParameters;\r
+\r
+ asm volatile ( "reg_test_2_start: \n\t"\r
+ " moveq #10, %d0 \n\t"\r
+ " moveq #20, %d1 \n\t"\r
+ " moveq #30, %d2 \n\t"\r
+ " moveq #40, %d3 \n\t"\r
+ " moveq #50, %d4 \n\t"\r
+ " moveq #60, %d5 \n\t"\r
+ " moveq #70, %d6 \n\t"\r
+ " moveq #80, %d7 \n\t"\r
+ " move #90, %a0 \n\t"\r
+ " move #100, %a1 \n\t"\r
+ " move #110, %a2 \n\t"\r
+ " move #120, %a3 \n\t"\r
+ " move #130, %a4 \n\t"\r
+ " move #140, %a5 \n\t"\r
+ " move #150, %a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #10, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #20, %d1 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #30, %d2 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #40, %d3 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #50, %d4 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #60, %d5 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #70, %d6 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #80, %d7 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a0, %d0 \n\t"\r
+ " cmpi.l #90, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a1, %d0 \n\t"\r
+ " cmpi.l #100, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a2, %d0 \n\t"\r
+ " cmpi.l #110, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a3, %d0 \n\t"\r
+ " cmpi.l #120, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a4, %d0 \n\t"\r
+ " cmpi.l #130, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a5, %d0 \n\t"\r
+ " cmpi.l #140, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move %a6, %d0 \n\t"\r
+ " cmpi.l #150, %d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " movel ulRegTest1Counter, %d0 \n\t"\r
+ " addql #1, %d0 \n\t"\r
+ " movel %d0, ulRegTest2Counter \n\t"\r
+ " bra reg_test_2_start \n\t"\r
+ "reg_test_2_error: \n\t"\r
+ " bra reg_test_2_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r