+ .size _vector_14, $-_vector_14\r
+ .endsec\r
+\r
+;-----------------------------------------------------------\r
+\r
+; This function is an XMC4000 silicon errata workaround. It will get used when\r
+; the SILICON_BUG_PMC_CM_001 linker macro is defined.\r
+ .section .text\r
+ .thumb\r
+ .align 4\r
+_lc_ref__vector_pp_14: .type func\r
+\r
+ mrs r0, psp\r
+\r
+ ;Get the location of the current TCB.\r
+ ldr.w r3, =pxCurrentTCB\r
+ ldr r2, [r3]\r
+\r
+ ;Is the task using the FPU context? If so, push high vfp registers.\r
+ tst r14, #0x10\r
+ it eq\r
+ vstmdbeq r0!, {s16-s31}\r
+\r
+ ;Save the core registers.\r
+ stmdb r0!, {r4-r11, r14}\r
+\r
+ ;Save the new top of stack into the first member of the TCB.\r
+ str r0, [r2]\r
+\r
+ stmdb sp!, {r3, r14}\r
+ ldr.w r0, =ulMaxSyscallInterruptPriorityConst\r
+ msr basepri, r0\r
+ bl vTaskSwitchContext\r
+ mov r0, #0\r
+ msr basepri, r0\r
+ ldmia sp!, {r3, r14}\r
+\r
+ ;The first item in pxCurrentTCB is the task top of stack.\r
+ ldr r1, [r3]\r
+ ldr r0, [r1]\r
+\r
+ ;Pop the core registers.\r
+ ldmia r0!, {r4-r11, r14}\r
+\r
+ ;Is the task using the FPU context? If so, pop the high vfp registers too.\r
+ tst r14, #0x10\r
+ it eq\r
+ vldmiaeq r0!, {s16-s31}\r
+\r
+ msr psp, r0\r
+ push { lr }\r
+ pop { pc } ; XMC4000 specific errata workaround. Do not used "bx lr" here.\r
+\r
+ .size _lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14\r