+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*------------------------------------------------------------------------------\r
+ * Port specific definitions.\r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the given hardware\r
+ * and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *------------------------------------------------------------------------------\r
+ */\r
+\r
+#ifndef configENABLE_FPU\r
+ #error configENABLE_FPU must be defined in FreeRTOSConfig.h. Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.\r
+#endif /* configENABLE_FPU */\r
+\r
+#ifndef configENABLE_MPU\r
+ #error configENABLE_MPU must be defined in FreeRTOSConfig.h. Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.\r
+#endif /* configENABLE_MPU */\r
+\r
+#ifndef configENABLE_TRUSTZONE\r
+ #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h. Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Type definitions.\r
+ */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE uint32_t\r
+#define portBASE_TYPE long\r
+\r
+typedef portSTACK_TYPE StackType_t;\r
+typedef long BaseType_t;\r
+typedef unsigned long UBaseType_t;\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef uint16_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffff\r
+#else\r
+ typedef uint32_t TickType_t;\r
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
+\r
+ /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\r
+ * not need to be guarded with a critical section. */\r
+ #define portTICK_TYPE_IS_ATOMIC 1\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * Architecture specifics.\r
+ */\r
+#define portARCH_NAME "Cortex-M23"\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
+#define portBYTE_ALIGNMENT 8\r
+#define portNOP()\r
+#define portINLINE __inline\r
+#ifndef portFORCE_INLINE\r
+ #define portFORCE_INLINE inline __attribute__(( always_inline ))\r
+#endif\r
+#define portHAS_STACK_OVERFLOW_CHECKING 1\r
+#define portDONT_DISCARD __attribute__(( used ))\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Extern declarations.\r
+ */\r
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;\r
+\r
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */\r
+ extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;\r
+#endif /* configENABLE_TRUSTZONE */\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;\r
+ extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief MPU specific constants.\r
+ */\r
+#if( configENABLE_MPU == 1 )\r
+ #define portUSING_MPU_WRAPPERS 1\r
+ #define portPRIVILEGE_BIT ( 0x80000000UL )\r
+#else\r
+ #define portPRIVILEGE_BIT ( 0x0UL )\r
+#endif /* configENABLE_MPU */\r
+\r
+\r
+/* MPU regions. */\r
+#define portPRIVILEGED_FLASH_REGION ( 0UL )\r
+#define portUNPRIVILEGED_FLASH_REGION ( 1UL )\r
+#define portUNPRIVILEGED_SYSCALLS_REGION ( 2UL )\r
+#define portPRIVILEGED_RAM_REGION ( 3UL )\r
+#define portSTACK_REGION ( 4UL )\r
+#define portFIRST_CONFIGURABLE_REGION ( 5UL )\r
+#define portLAST_CONFIGURABLE_REGION ( 7UL )\r
+#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )\r
+#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */\r
+\r
+/* Device memory attributes used in MPU_MAIR registers.\r
+ *\r
+ * 8-bit values encoded as follows:\r
+ * Bit[7:4] - 0000 - Device Memory\r
+ * Bit[3:2] - 00 --> Device-nGnRnE\r
+ * 01 --> Device-nGnRE\r
+ * 10 --> Device-nGRE\r
+ * 11 --> Device-GRE\r
+ * Bit[1:0] - 00, Reserved.\r
+ */\r
+#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 ) /* 0000 0000 */\r
+#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 ) /* 0000 0100 */\r
+#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 ) /* 0000 1000 */\r
+#define portMPU_DEVICE_MEMORY_GRE ( 0x0C ) /* 0000 1100 */\r
+\r
+/* Normal memory attributes used in MPU_MAIR registers. */\r
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */\r
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */\r
+\r
+/* Attributes used in MPU_RBAR registers. */\r
+#define portMPU_REGION_NON_SHAREABLE ( 0UL << 3UL )\r
+#define portMPU_REGION_INNER_SHAREABLE ( 1UL << 3UL )\r
+#define portMPU_REGION_OUTER_SHAREABLE ( 2UL << 3UL )\r
+\r
+#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0UL << 1UL )\r
+#define portMPU_REGION_READ_WRITE ( 1UL << 1UL )\r
+#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2UL << 1UL )\r
+#define portMPU_REGION_READ_ONLY ( 3UL << 1UL )\r
+\r
+#define portMPU_REGION_EXECUTE_NEVER ( 1UL )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Settings to define an MPU region.\r
+ */\r
+typedef struct MPURegionSettings\r
+{\r
+ uint32_t ulRBAR; /**< RBAR for the region. */\r
+ uint32_t ulRLAR; /**< RLAR for the region. */\r
+} MPURegionSettings_t;\r
+\r
+/**\r
+ * @brief MPU settings as stored in the TCB.\r
+ */\r
+typedef struct MPU_SETTINGS\r
+{\r
+ uint32_t ulMAIR0; /**< MAIR0 for the task containing attributes for all the 4 per task regions. */\r
+ MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */\r
+} xMPU_SETTINGS;\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief SVC numbers.\r
+ */\r
+#define portSVC_ALLOCATE_SECURE_CONTEXT 0\r
+#define portSVC_FREE_SECURE_CONTEXT 1\r
+#define portSVC_START_SCHEDULER 2\r
+#define portSVC_RAISE_PRIVILEGE 3\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Scheduler utilities.\r
+ */\r
+#define portYIELD() vPortYield()\r
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\r
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT\r
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Critical section management.\r
+ */\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )\r
+#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )\r
+#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.\r
+ */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_TRUSTZONE == 1 )\r
+ /**\r
+ * @brief Allocate a secure context for the task.\r
+ *\r
+ * Tasks are not created with a secure context. Any task that is going to call\r
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a\r
+ * secure context before it calls any secure function.\r
+ *\r
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.\r
+ */\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) vPortAllocateSecureContext( ulSecureStackSize )\r
+\r
+ /**\r
+ * @brief Called when a task is deleted to delete the task's secure context,\r
+ * if it has one.\r
+ *\r
+ * @param[in] pxTCB The TCB of the task being deleted.\r
+ */\r
+ #define portCLEAN_UP_TCB( pxTCB ) vPortFreeSecureContext( ( uint32_t * ) pxTCB )\r
+#else\r
+ #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\r
+ #define portCLEAN_UP_TCB( pxTCB )\r
+#endif /* configENABLE_TRUSTZONE */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configENABLE_MPU == 1 )\r
+ /**\r
+ * @brief Checks whether or not the processor is privileged.\r
+ *\r
+ * @return 1 if the processor is already privileged, 0 otherwise.\r
+ */\r
+ #define portIS_PRIVILEGED() xIsPrivileged()\r
+\r
+ /**\r
+ * @brief Raise an SVC request to raise privilege.\r
+ *\r
+ * The SVC handler checks that the SVC was raised from a system call and only\r
+ * then it raises the privilege. If this is called from any other place,\r
+ * the privilege is not raised.\r
+ */\r
+ #define portRAISE_PRIVILEGE() __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );\r
+\r
+ /**\r
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
+ * register.\r
+ */\r
+ #define portRESET_PRIVILEGE() vResetPrivilege()\r
+#else\r
+ #define portIS_PRIVILEGED()\r
+ #define portRAISE_PRIVILEGE()\r
+ #define portRESET_PRIVILEGE()\r
+#endif /* configENABLE_MPU */\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Barriers.\r
+ */\r
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r