Move new MicroBlaze V8 port from the project directory into its correct location...

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1510 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

diff --git a/Source/portable/GCC/MicroBlazeV8/port.c b/Source/portable/GCC/MicroBlazeV8/port.c
new file mode 100644 (file)
index 0000000..77b3301
--- /dev/null
+++ b/Source/portable/GCC/MicroBlazeV8/port.c
@@ -0,0 +1,470 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the MicroBlaze port.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Hardware includes. */\r
+#include <xintc_i.h>\r
+#include <xil_exception.h>\r
+#include <microblaze_exceptions_g.h>\r
+\r
+/* Tasks are started with a critical section nesting of 0 - however, prior to \r
+the scheduler being commenced interrupts should not be enabled, so the critical \r
+nesting variable is initialised to a non-zero value. */\r
+#define portINITIAL_NESTING_VALUE      ( 0xff )\r
+\r
+/* The bit within the MSR register that enabled/disables interrupts. */\r
+#define portMSR_IE                                     ( 0x02U )\r
+\r
+/* If the floating point unit is included in the MicroBlaze build, then the\r
+FSR register is saved as part of the task context.  portINITIAL_FSR is the value\r
+given to the FSR register when the initial context is set up for a task being\r
+created. */\r
+#define portINITIAL_FSR                                ( 0U )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the interrupt controller instance.\r
+ */\r
+static long prvInitialiseInterruptController( void );\r
+\r
+/* Ensure the interrupt controller instance variable is initialised before it is \r
+ * used, and that the initialisation only happens once. \r
+ */\r
+static long prvEnsureInterruptControllerIsInitialised( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task \r
+maintains its own count, so this variable is saved as part of the task\r
+context. */\r
+volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;\r
+\r
+/* This port uses a separate stack for interrupts.  This prevents the stack of\r
+every task needing to be large enough to hold an entire interrupt stack on top\r
+of the task stack. */\r
+unsigned long *pulISRStack;\r
+\r
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will\r
+get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt\r
+handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel\r
+will call vTaskSwitchContext() to ensure the task that runs immediately after\r
+the interrupt exists is the highest priority task that is able to run.  This is \r
+an unusual mechanism, but is used for this port because a single interrupt can \r
+cause the servicing of multiple peripherals - and it is inefficient to call\r
+vTaskSwitchContext() multiple times as each peripheral is serviced. */\r
+volatile unsigned long ulTaskSwitchRequested = 0UL;\r
+\r
+/* The instance of the interrupt controller used by this port.  This is required\r
+by the Xilinx library API functions. */\r
+static XIntc xInterruptControllerInstance;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Initialise the stack of a task to look exactly as if a call to \r
+ * portSAVE_CONTEXT had been made.\r
+ * \r
+ * See the portable.h header file.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+extern void *_SDA2_BASE_, *_SDA_BASE_;\r
+const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;\r
+const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;\r
+\r
+       /* Place a few bytes of known values on the bottom of the stack. \r
+       This is essential for the Microblaze port and these lines must\r
+       not be omitted. */\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;\r
+       pxTopOfStack--;\r
+\r
+       #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+               /* The FSR value placed in the initial task context is just 0. */\r
+               *pxTopOfStack = portINITIAL_FSR;\r
+               pxTopOfStack--;\r
+       #endif\r
+\r
+       /* The MSR value placed in the initial task context should have interrupts\r
+       disabled.  Each task will enable interrupts automatically when it enters\r
+       the running state for the first time. */\r
+       *pxTopOfStack = mfmsr() & ~portMSR_IE;\r
+       pxTopOfStack--;\r
+\r
+       /* First stack an initial value for the critical section nesting.  This\r
+       is initialised to zero. */\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00;\r
+       \r
+       /* R0 is always zero. */\r
+       /* R1 is the SP. */\r
+\r
+       /* Place an initial value for all the general purpose registers. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) ulR2;        /* R2 - read only small data area. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x03;        /* R3 - return values and temporaries. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x04;        /* R4 - return values and temporaries. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */\r
+\r
+       #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x06;        /* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x07;        /* R7 - other parameters and temporaries. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x08;        /* R8 - other parameters and temporaries. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x09;        /* R9 - other parameters and temporaries. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x0a;        /* R10 - other parameters and temporaries. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x0b;        /* R11 - temporaries. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x0c;        /* R12 - temporaries. */\r
+               pxTopOfStack--;\r
+       #else\r
+               pxTopOfStack-= 8;\r
+       #endif\r
+       \r
+       *pxTopOfStack = ( portSTACK_TYPE ) ulR13;       /* R13 - read/write small data area. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* R14 - return address for interrupt. */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) NULL;        /* R15 - return address for subroutine. */\r
+       \r
+       #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x10;        /* R16 - return address for trap (debugger). */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x11;        /* R17 - return address for exceptions, if configured. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x12;        /* R18 - reserved for assembler and compiler temporaries. */\r
+               pxTopOfStack--;\r
+       #else\r
+               pxTopOfStack -= 4;\r
+       #endif\r
+       \r
+       *pxTopOfStack = ( portSTACK_TYPE ) 0x00;        /* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */\r
+       \r
+       #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING \r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x14;        /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x15;        /* R21 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x16;        /* R22 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x17;        /* R23 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x18;        /* R24 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x19;        /* R25 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1a;        /* R26 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1b;        /* R27 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1c;        /* R28 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1d;        /* R29 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1e;        /* R30 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+               *pxTopOfStack = ( portSTACK_TYPE ) 0x1f;        /* R31 - must be saved across function calls. Callee-save. */\r
+               pxTopOfStack--;\r
+       #else\r
+               pxTopOfStack -= 13;\r
+       #endif\r
+\r
+       /* Return a pointer to the top of the stack that has been generated so this \r
+       can     be stored in the task control block for the task. */\r
+       return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+extern void ( vPortStartFirstTask )( void );\r
+extern unsigned long _stack[];\r
+\r
+       /* Setup the hardware to generate the tick.  Interrupts are disabled when\r
+       this function is called.  \r
+       \r
+       This port uses an application defined callback function to install the tick\r
+       interrupt handler because the kernel will run on lots of different \r
+       MicroBlaze and FPGA configurations - not all of which will have the same \r
+       timer peripherals defined or available.  An example definition of\r
+       vApplicationSetupTimerInterrupt() is provided in the official demo\r
+       application that accompanies this port. */\r
+       vApplicationSetupTimerInterrupt();\r
+\r
+       /* Reuse the stack from main() as the stack for the interrupts/exceptions. */\r
+       pulISRStack = ( unsigned long * ) _stack;\r
+\r
+       /* Ensure there is enough space for the functions called from the interrupt\r
+       service routines to write back into the stack frame of the caller. */
+       pulISRStack -= 2;\r
+\r
+       /* Restore the context of the first task that is going to run.  From here\r
+       on, the created tasks will be executing. */\r
+       vPortStartFirstTask();\r
+\r
+       /* Should not get here as the tasks are now running! */\r
+       return pdFALSE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+       /* Not implemented. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Manual context switch called by portYIELD or taskYIELD.  \r
+ */\r
+void vPortYield( void )\r
+{\r
+extern void VPortYieldASM( void );\r
+\r
+       /* Perform the context switch in a critical section to assure it is\r
+       not interrupted by the tick ISR.  It is not a problem to do this as\r
+       each task maintains its own interrupt status. */\r
+       portENTER_CRITICAL();\r
+       {\r
+               /* Jump directly to the yield function to ensure there is no\r
+               compiler generated prologue code. */\r
+               asm volatile (  "bralid r14, VPortYieldASM              \n\t" \\r
+                                               "or r0, r0, r0                                  \n\t" );\r
+       }\r
+       portEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnableInterrupt( unsigned char ucInterruptID )\r
+{\r
+long lReturn;\r
+\r
+       /* An API function is provided to enable an interrupt in the interrupt\r
+       controller because the interrupt controller instance variable is private\r
+       to this file. */\r
+       lReturn = prvEnsureInterruptControllerIsInitialised();\r
+       if( lReturn == pdPASS )\r
+       {\r
+               XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );\r
+       }\r
+       \r
+       configASSERT( lReturn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortDisableInterrupt( unsigned char ucInterruptID )\r
+{\r
+long lReturn;\r
+\r
+       /* An API function is provided to disable an interrupt in the interrupt\r
+       controller because the interrupt controller instance variable is private\r
+       to this file. */\r
+       lReturn = prvEnsureInterruptControllerIsInitialised();\r
+       \r
+       if( lReturn == pdPASS )\r
+       {\r
+               XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );\r
+       }\r
+       \r
+       configASSERT( lReturn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )\r
+{\r
+long lReturn;\r
+\r
+       /* An API function is provided to install an interrupt handler because the \r
+       interrupt controller instance variable is private to this file. */\r
+\r
+       lReturn = prvEnsureInterruptControllerIsInitialised();\r
+       \r
+       if( lReturn == pdPASS )\r
+       {\r
+               lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );\r
+       }\r
+\r
+       if( lReturn == XST_SUCCESS )\r
+       {\r
+               lReturn = pdPASS;\r
+       }\r
+       \r
+       configASSERT( lReturn == pdPASS );\r
+\r
+       return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static long prvEnsureInterruptControllerIsInitialised( void )\r
+{\r
+static long lInterruptControllerInitialised = pdFALSE;\r
+long lReturn;\r
+\r
+       /* Ensure the interrupt controller instance variable is initialised before\r
+       it is used, and that the initialisation only happens once. */\r
+       if( lInterruptControllerInitialised != pdTRUE )\r
+       {\r
+               lReturn = prvInitialiseInterruptController();\r
+               \r
+               if( lReturn == pdPASS )\r
+               {\r
+                       lInterruptControllerInitialised = pdTRUE;\r
+               }\r
+       }\r
+       else\r
+       {\r
+               lReturn = pdPASS;\r
+       }\r
+\r
+       return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * Handler for the timer interrupt.  This is the handler that the application\r
+ * defined callback function vApplicationSetupTimerInterrupt() should install.\r
+ */\r
+void vPortTickISR( void *pvUnused )\r
+{\r
+extern void vApplicationClearTimerInterrupt( void );\r
+\r
+       /* Ensure the unused parameter does not generate a compiler warning. */\r
+       ( void ) pvUnused;\r
+\r
+       /* This port uses an application defined callback function to clear the tick\r
+       interrupt because the kernel will run on lots of different MicroBlaze and \r
+       FPGA configurations - not all of which will have the same timer peripherals \r
+       defined or available.  An example definition of\r
+       vApplicationClearTimerInterrupt() is provided in the official demo\r
+       application that accompanies this port. */      \r
+       vApplicationClearTimerInterrupt();\r
+\r
+       /* Increment the RTOS tick - this might cause a task to unblock. */\r
+       vTaskIncrementTick();\r
+\r
+       /* If the preemptive scheduler is being used then a context switch should be\r
+       requested in case incrementing the tick unblocked a task, or a time slice\r
+       should cause another task to enter the Running state. */\r
+       #if configUSE_PREEMPTION == 1\r
+               /* Force vTaskSwitchContext() to be called as the interrupt exits. */\r
+               ulTaskSwitchRequested = 1;\r
+       #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static long prvInitialiseInterruptController( void )\r
+{\r
+long lStatus;\r
+\r
+       lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );\r
+\r
+       if( lStatus == XST_SUCCESS )\r
+       {\r
+               /* Initialise the exception table. */\r
+               Xil_ExceptionInit();\r
+\r
+           /* Service all pending interrupts each time the handler is entered. */\r
+           XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );\r
+\r
+           /* Install exception handlers if the MicroBlaze is configured to handle\r
+           exceptions, and the application defined constant\r
+           configINSTALL_EXCEPTION_HANDLERS is set to 1. */\r
+               #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )\r
+           {\r
+               vPortExceptionsInstallHandlers();\r
+           }\r
+               #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */\r
+\r
+               /* Start the interrupt controller.  Interrupts are enabled when the\r
+               scheduler starts. */\r
+               lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );\r
+\r
+               if( lStatus == XST_SUCCESS )\r
+               {\r
+                       lStatus = pdPASS;\r
+               }\r
+               else\r
+               {\r
+                       lStatus = pdFAIL;\r
+               }\r
+       }\r
+\r
+       configASSERT( lStatus == pdPASS );\r
+\r
+       return lStatus;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r

diff --git a/Source/portable/GCC/MicroBlazeV8/port_exceptions.c b/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
new file mode 100644 (file)
index 0000000..f5ed3c9
--- /dev/null
+++ b/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -0,0 +1,307 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware includes. */\r
+#include <microblaze_exceptions_i.h>\r
+#include <microblaze_exceptions_g.h>\r
+\r
+/* The Xilinx library defined exception entry point stacks a number of\r
+registers.  These definitions are offsets from the stack pointer to the various\r
+stacked register values. */\r
+#define portexR3_STACK_OFFSET  4\r
+#define portexR4_STACK_OFFSET  5\r
+#define portexR5_STACK_OFFSET  6\r
+#define portexR6_STACK_OFFSET  7\r
+#define portexR7_STACK_OFFSET  8\r
+#define portexR8_STACK_OFFSET  9\r
+#define portexR9_STACK_OFFSET  10\r
+#define portexR10_STACK_OFFSET 11\r
+#define portexR11_STACK_OFFSET 12\r
+#define portexR12_STACK_OFFSET 13\r
+#define portexR15_STACK_OFFSET 16\r
+#define portexR18_STACK_OFFSET  19\r
+#define portexMSR_STACK_OFFSET 20\r
+#define portexR19_STACK_OFFSET  -1\r
+\r
+/* This is defined to equal the size, in bytes, of the stack frame generated by\r
+the Xilinx standard library exception entry point.  It is required to determine\r
+the stack pointer value prior to the exception being entered. */\r
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL\r
+\r
+/* The number of bytes a MicroBlaze instruction consumes. */\r
+#define portexINSTRUCTION_SIZE 4\r
+\r
+/* Exclude this entire file if the MicroBlaze is not configured to handle\r
+exceptions, or the application defined configuration constant\r
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */\r
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )\r
+\r
+/* This variable is set in the exception entry code, before\r
+vPortExceptionHandler is called. */\r
+unsigned long *pulStackPointerOnFunctionEntry = NULL;\r
+\r
+/* This is the structure that is filled with the MicroBlaze context as it\r
+existed immediately prior to the exception occurrence.  A pointer to this\r
+structure is passed into the vApplicationExceptionRegisterDump() callback\r
+function, if one is defined. */\r
+static xPortRegisterDump xRegisterDump;\r
+\r
+/* This is the FreeRTOS exception handler that is installed for all exception\r
+types.  It is called from vPortExceptionHanlderEntry() - which is itself defined\r
+in portasm.S. */\r
+void vPortExceptionHandler( void *pvExceptionID );\r
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* vApplicationExceptionRegisterDump() is a callback function that the \r
+application can optionally define to receive a populated xPortRegisterDump\r
+structure.  If the application chooses not to define a version of \r
+vApplicationExceptionRegisterDump() then this weekly defined default \r
+implementation will be called instead. */\r
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));\r
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )\r
+{\r
+       ( void ) xRegisterDump;\r
+\r
+       for( ;; )\r
+       {\r
+               portNOP();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExceptionHandler( void *pvExceptionID )\r
+{\r
+extern void *pxCurrentTCB;\r
+\r
+       /* Fill an xPortRegisterDump structure with the MicroBlaze context as it\r
+       was immediately before the exception occurrence. */\r
+       \r
+       /* First fill in the name and handle of the task that was in the Running \r
+       state when the exception occurred. */\r
+       xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;\r
+       xRegisterDump.pcCurrentTaskName = pcTaskGetTaskName( NULL );\r
+\r
+       configASSERT( pulStackPointerOnFunctionEntry );\r
+\r
+       /* Obtain the values of registers that were stacked prior to this function\r
+       being called, and may have changed since they were stacked. */
+       xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];\r
+       xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];\r
+       xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];\r
+       xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];\r
+       xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];\r
+       xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];\r
+       xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];\r
+       xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];\r
+       xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];\r
+       xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];\r
+       xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];\r
+       xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];\r
+       xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];\r
+       xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];\r
+       \r
+       /* Obtain the value of all other registers. */\r
+       xRegisterDump.ulR2_small_data_area = mfgpr( R2 );\r
+       xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );\r
+       xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );\r
+       xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );\r
+       xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );\r
+       xRegisterDump.ulR20 = mfgpr( R20 );\r
+       xRegisterDump.ulR21 = mfgpr( R21 );\r
+       xRegisterDump.ulR22 = mfgpr( R22 );\r
+       xRegisterDump.ulR23 = mfgpr( R23 );\r
+       xRegisterDump.ulR24 = mfgpr( R24 );\r
+       xRegisterDump.ulR25 = mfgpr( R25 );\r
+       xRegisterDump.ulR26 = mfgpr( R26 );\r
+       xRegisterDump.ulR27 = mfgpr( R27 );\r
+       xRegisterDump.ulR28 = mfgpr( R28 );\r
+       xRegisterDump.ulR29 = mfgpr( R29 );\r
+       xRegisterDump.ulR30 = mfgpr( R30 );\r
+       xRegisterDump.ulR31 = mfgpr( R31 );\r
+       xRegisterDump.ulR1_SP = ( ( unsigned long ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;\r
+       xRegisterDump.ulEAR = mfear();\r
+       xRegisterDump.ulESR = mfesr();\r
+       xRegisterDump.ulEDR = mfedr();\r
+       \r
+       /* Move the saved program counter back to the instruction that was executed\r
+       when the exception occurred.  This is only valid for certain types of\r
+       exception. */\r
+       xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;\r
+\r
+       #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+       {\r
+               xRegisterDump.ulFSR = mffsr();\r
+       }\r
+       #else\r
+       {\r
+               xRegisterDump.ulFSR = 0UL;\r
+       }\r
+       #endif\r
+\r
+       /* Also fill in a string that describes what type of exception this is.\r
+       The string uses the same ID names as defined in the MicroBlaze standard\r
+       library exception header files. */\r
+       switch( ( unsigned long ) pvExceptionID )\r
+       {\r
+               case XEXC_ID_FSL :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FSL";\r
+                               break;\r
+\r
+               case XEXC_ID_UNALIGNED_ACCESS :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_UNALIGNED_ACCESS";\r
+                               break;\r
+\r
+               case XEXC_ID_ILLEGAL_OPCODE :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_ILLEGAL_OPCODE";\r
+                               break;\r
+\r
+               case XEXC_ID_M_AXI_I_EXCEPTION :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";\r
+                               break;\r
+\r
+               case XEXC_ID_M_AXI_D_EXCEPTION :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";\r
+                               break;\r
+\r
+               case XEXC_ID_DIV_BY_ZERO :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_DIV_BY_ZERO";\r
+                               break;\r
+\r
+               case XEXC_ID_STACK_VIOLATION :\r
+                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";\r
+                               break;\r
+\r
+               #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+\r
+                       case XEXC_ID_FPU :\r
+                                               /*_RB_ More decoding required here and in other exceptions. */\r
+                                               xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU see ulFSR value";\r
+                                               break;\r
+\r
+               #endif /* XPAR_MICROBLAZE_0_USE_FPU */\r
+       }\r
+\r
+       /* vApplicationExceptionRegisterDump() is a callback function that the \r
+       application can optionally define to receive the populated xPortRegisterDump\r
+       structure.  If the application chooses not to define a version of \r
+       vApplicationExceptionRegisterDump() then the weekly defined default \r
+       implementation within this file will be called instead. */\r
+       vApplicationExceptionRegisterDump( &xRegisterDump );\r
+\r
+       /* Must not attempt to leave this function! */\r
+       for( ;; )\r
+       {\r
+               portNOP();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExceptionsInstallHandlers( void )\r
+{\r
+static unsigned long ulHandlersAlreadyInstalled = pdFALSE;\r
+\r
+       if( ulHandlersAlreadyInstalled == pdFALSE )\r
+       {\r
+               ulHandlersAlreadyInstalled = pdTRUE;\r
+\r
+               #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
+               #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
+\r
+               #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
+               #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
+               #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
+               #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
+               #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
+               #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
+               #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );\r
+               #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
+\r
+               #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
+                       microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );\r
+               #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
+       }\r
+}\r
+\r
+/* Exclude the entire file if the MicroBlaze is not configured to handle\r
+exceptions, or the application defined configuration item \r
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */\r
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */\r
+\r
+\r
+\r

diff --git a/Source/portable/GCC/MicroBlazeV8/portasm.S b/Source/portable/GCC/MicroBlazeV8/portasm.S
new file mode 100644 (file)
index 0000000..8d99520
--- /dev/null
+++ b/Source/portable/GCC/MicroBlazeV8/portasm.S
@@ -0,0 +1,360 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+       FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+       Atollic AB - Atollic provides professional embedded systems development\r
+       tools for C/C++ development, code analysis and test automation.\r
+       See http://www.atollic.com\r
+\r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/* Xilinx library includes. */\r
+#include "microblaze_exceptions_g.h"\r
+#include "xparameters.h"\r
+\r
+/* The context is oversized to allow functions called from the ISR to write\r
+back into the caller stack. */\r
+#if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+       #define portCONTEXT_SIZE 136\r
+       #define portMINUS_CONTEXT_SIZE -136\r
+#else\r
+       #define portCONTEXT_SIZE 132\r
+       #define portMINUS_CONTEXT_SIZE -132\r
+#endif\r
+\r
+/* Offsets from the stack pointer at which saved registers are placed. */\r
+#define portR31_OFFSET 4\r
+#define portR30_OFFSET 8\r
+#define portR29_OFFSET 12\r
+#define portR28_OFFSET 16\r
+#define portR27_OFFSET 20\r
+#define portR26_OFFSET 24\r
+#define portR25_OFFSET 28\r
+#define portR24_OFFSET 32\r
+#define portR23_OFFSET 36\r
+#define portR22_OFFSET 40\r
+#define portR21_OFFSET 44\r
+#define portR20_OFFSET 48\r
+#define portR19_OFFSET 52\r
+#define portR18_OFFSET 56\r
+#define portR17_OFFSET 60\r
+#define portR16_OFFSET 64\r
+#define portR15_OFFSET 68\r
+#define portR14_OFFSET 72\r
+#define portR13_OFFSET 76\r
+#define portR12_OFFSET 80\r
+#define portR11_OFFSET 84\r
+#define portR10_OFFSET 88\r
+#define portR9_OFFSET  92\r
+#define portR8_OFFSET  96\r
+#define portR7_OFFSET  100\r
+#define portR6_OFFSET  104\r
+#define portR5_OFFSET  108\r
+#define portR4_OFFSET  112\r
+#define portR3_OFFSET  116\r
+#define portR2_OFFSET  120\r
+#define portCRITICAL_NESTING_OFFSET 124\r
+#define portMSR_OFFSET 128\r
+#define portFSR_OFFSET 132\r
+\r
+       .extern pxCurrentTCB\r
+       .extern XIntc_DeviceInterruptHandler\r
+       .extern vTaskSwitchContext\r
+       .extern uxCriticalNesting\r
+       .extern pulISRStack\r
+       .extern ulTaskSwitchRequested\r
+       .extern vPortExceptionHandler\r
+       .extern pulStackPointerOnFunctionEntry\r
+\r
+       .global _interrupt_handler\r
+       .global VPortYieldASM\r
+       .global vPortStartFirstTask\r
+       .global vPortExceptionHandlerEntry\r
+\r
+\r
+.macro portSAVE_CONTEXT\r
+\r
+       /* Make room for the context on the stack. */\r
+       addik r1, r1, portMINUS_CONTEXT_SIZE\r
+\r
+       /* Stack general registers. */\r
+       swi r31, r1, portR31_OFFSET\r
+       swi r30, r1, portR30_OFFSET\r
+       swi r29, r1, portR29_OFFSET\r
+       swi r28, r1, portR28_OFFSET\r
+       swi r27, r1, portR27_OFFSET\r
+       swi r26, r1, portR26_OFFSET\r
+       swi r25, r1, portR25_OFFSET\r
+       swi r24, r1, portR24_OFFSET\r
+       swi r23, r1, portR23_OFFSET\r
+       swi r22, r1, portR22_OFFSET\r
+       swi r21, r1, portR21_OFFSET\r
+       swi r20, r1, portR20_OFFSET\r
+       swi r19, r1, portR19_OFFSET\r
+       swi r18, r1, portR18_OFFSET\r
+       swi r17, r1, portR17_OFFSET\r
+       swi r16, r1, portR16_OFFSET\r
+       swi r15, r1, portR15_OFFSET\r
+       /* R14 is saved later as it needs adjustment if a yield is performed. */\r
+       swi r13, r1, portR13_OFFSET\r
+       swi r12, r1, portR12_OFFSET\r
+       swi r11, r1, portR11_OFFSET\r
+       swi r10, r1, portR10_OFFSET\r
+       swi r9, r1, portR9_OFFSET\r
+       swi r8, r1, portR8_OFFSET\r
+       swi r7, r1, portR7_OFFSET\r
+       swi r6, r1, portR6_OFFSET\r
+       swi r5, r1, portR5_OFFSET\r
+       swi r4, r1, portR4_OFFSET\r
+       swi r3, r1, portR3_OFFSET\r
+       swi r2, r1, portR2_OFFSET\r
+\r
+       /* Stack the critical section nesting value. */\r
+       lwi r18, r0, uxCriticalNesting\r
+       swi r18, r1, portCRITICAL_NESTING_OFFSET\r
+\r
+       /* Stack MSR. */\r
+       mfs r18, rmsr\r
+       swi r18, r1, portMSR_OFFSET\r
+\r
+       #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+               /* Stack FSR. */\r
+               mfs r18, rfsr\r
+               swi r18, r1, portFSR_OFFSET\r
+       #endif\r
+\r
+       /* Save the top of stack value to the TCB. */\r
+       lwi r3, r0, pxCurrentTCB\r
+       sw      r1, r0, r3\r
+       \r
+       .endm\r
+\r
+.macro portRESTORE_CONTEXT\r
+\r
+       /* Load the top of stack value from the TCB. */\r
+       lwi r18, r0, pxCurrentTCB\r
+       lw      r1, r0, r18\r
+\r
+       /* Restore the general registers. */\r
+       lwi r31, r1, portR31_OFFSET\r
+       lwi r30, r1, portR30_OFFSET\r
+       lwi r29, r1, portR29_OFFSET\r
+       lwi r28, r1, portR28_OFFSET\r
+       lwi r27, r1, portR27_OFFSET\r
+       lwi r26, r1, portR26_OFFSET\r
+       lwi r25, r1, portR25_OFFSET\r
+       lwi r24, r1, portR24_OFFSET\r
+       lwi r23, r1, portR23_OFFSET\r
+       lwi r22, r1, portR22_OFFSET\r
+       lwi r21, r1, portR21_OFFSET\r
+       lwi r20, r1, portR20_OFFSET\r
+       lwi r19, r1, portR19_OFFSET\r
+       lwi r17, r1, portR17_OFFSET\r
+       lwi r16, r1, portR16_OFFSET\r
+       lwi r15, r1, portR15_OFFSET\r
+       lwi r14, r1, portR14_OFFSET\r
+       lwi r13, r1, portR13_OFFSET\r
+       lwi r12, r1, portR12_OFFSET\r
+       lwi r11, r1, portR11_OFFSET\r
+       lwi r10, r1, portR10_OFFSET\r
+       lwi r9, r1, portR9_OFFSET\r
+       lwi r8, r1, portR8_OFFSET\r
+       lwi r7, r1, portR7_OFFSET\r
+       lwi r6, r1, portR6_OFFSET\r
+       lwi r5, r1, portR5_OFFSET\r
+       lwi r4, r1, portR4_OFFSET\r
+       lwi r3, r1, portR3_OFFSET\r
+       lwi r2, r1, portR2_OFFSET\r
+\r
+       /* Reload the rmsr from the stack. */\r
+       lwi r18, r1, portMSR_OFFSET\r
+       mts rmsr, r18\r
+\r
+       #if XPAR_MICROBLAZE_0_USE_FPU == 1\r
+               /* Reload the FSR from the stack. */\r
+               lwi r18, r1, portFSR_OFFSET\r
+               mts rfsr, r18\r
+       #endif\r
+\r
+       /* Load the critical nesting value. */\r
+       lwi r18, r1, portCRITICAL_NESTING_OFFSET\r
+       swi r18, r0, uxCriticalNesting\r
+\r
+       /* Test the critical nesting value.  If it is non zero then the task last\r
+       exited the running state using a yield.  If it is zero, then the task\r
+       last exited the running state through an interrupt. */\r
+       xori r18, r18, 0\r
+       bnei r18, exit_from_yield\r
+\r
+       /* r18 was being used as a temporary.  Now restore its true value from the\r
+       stack. */\r
+       lwi r18, r1, portR18_OFFSET\r
+\r
+       /* Remove the stack frame. */\r
+       addik r1, r1, portCONTEXT_SIZE\r
+\r
+       /* Return using rtid so interrupts are re-enabled as this function is\r
+       exited. */\r
+       rtid r14, 0\r
+       or r0, r0, r0\r
+\r
+       .endm\r
+\r
+/* This function is used to exit portRESTORE_CONTEXT() if the task being\r
+returned to last left the Running state by calling taskYIELD() (rather than\r
+being preempted by an interrupt). */\r
+       .text\r
+       .align  2\r
+exit_from_yield:\r
+\r
+       /* r18 was being used as a temporary.  Now restore its true value from the\r
+       stack. */\r
+       lwi r18, r1, portR18_OFFSET\r
+\r
+       /* Remove the stack frame. */\r
+       addik r1, r1, portCONTEXT_SIZE\r
+\r
+       /* Return to the task. */\r
+       rtsd r14, 0\r
+       or r0, r0, r0\r
+\r
+\r
+       .text\r
+       .align  2\r
+_interrupt_handler:\r
+\r
+       portSAVE_CONTEXT\r
+\r
+       /* Stack the return address. */\r
+       swi r14, r1, portR14_OFFSET\r
+\r
+       /* Switch to the ISR stack. */\r
+       lwi r1, r0, pulISRStack\r
+\r
+       /* The parameter to the interrupt handler. */\r
+       ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE\r
+\r
+       /* Execute any pending interrupts. */\r
+       bralid r15, XIntc_DeviceInterruptHandler\r
+       or r0, r0, r0\r
+\r
+       /* See if a new task should be selected to execute. */\r
+       lwi r18, r0, ulTaskSwitchRequested\r
+       or r18, r18, r0\r
+\r
+       /* If ulTaskSwitchRequested is already zero, then jump straight to\r
+       restoring the task that is already in the Running state. */\r
+       beqi r18, task_switch_not_requested\r
+\r
+       /* Set ulTaskSwitchRequested back to zero as a task switch is about to be\r
+       performed. */\r
+       swi r0, r0, ulTaskSwitchRequested\r
+\r
+       /* ulTaskSwitchRequested was not 0 when tested.  Select the next task to\r
+       execute. */\r
+       bralid r15, vTaskSwitchContext\r
+       or r0, r0, r0\r
+\r
+task_switch_not_requested:\r
+\r
+       /* Restore the context of the next task scheduled to execute. */\r
+       portRESTORE_CONTEXT\r
+\r
+\r
+       .text\r
+       .align  2\r
+VPortYieldASM:\r
+\r
+       portSAVE_CONTEXT\r
+\r
+       /* Modify the return address so a return is done to the instruction after\r
+       the call to VPortYieldASM. */\r
+       addi r14, r14, 8\r
+       swi r14, r1, portR14_OFFSET\r
+\r
+       /* Switch to use the ISR stack. */\r
+       lwi r1, r0, pulISRStack\r
+\r
+       /* Select the next task to execute. */\r
+       bralid r15, vTaskSwitchContext\r
+       or r0, r0, r0\r
+\r
+       /* Restore the context of the next task scheduled to execute. */\r
+       portRESTORE_CONTEXT\r
+\r
+       .text\r
+       .align  2\r
+vPortStartFirstTask:\r
+\r
+       portRESTORE_CONTEXT\r
+       \r
+\r
+\r
+#if MICROBLAZE_EXCEPTIONS_ENABLED == 1\r
+       \r
+       .text\r
+       .align 2\r
+vPortExceptionHandlerEntry:\r
+\r
+       /* Take a copy of the stack pointer before vPortExecptionHandler is called,\r
+       storing its value prior to the function stack frame being created. */\r
+       swi r1, r0, pulStackPointerOnFunctionEntry\r
+       bralid r15, vPortExceptionHandler\r
+       or r0, r0, r0\r
+\r
+#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */\r
+\r
+\r
+\r

diff --git a/Source/portable/GCC/MicroBlazeV8/portmacro.h b/Source/portable/GCC/MicroBlazeV8/portmacro.h
new file mode 100644 (file)
index 0000000..940444f
--- /dev/null
+++ b/Source/portable/GCC/MicroBlazeV8/portmacro.h
@@ -0,0 +1,361 @@
+/*\r
+    FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+       \r
+\r
+    ***************************************************************************\r
+     *                                                                       *\r
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
+     *    Complete, revised, and edited pdf reference manuals are also       *\r
+     *    available.                                                         *\r
+     *                                                                       *\r
+     *    Purchasing FreeRTOS documentation will not only help you, by       *\r
+     *    ensuring you get running as quickly as possible and with an        *\r
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
+     *    the FreeRTOS project to continue with its mission of providing     *\r
+     *    professional grade, cross platform, de facto standard solutions    *\r
+     *    for microcontrollers - completely free of charge!                  *\r
+     *                                                                       *\r
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
+     *                                                                       *\r
+     *    Thank you for using FreeRTOS, and thank you for your support!      *\r
+     *                                                                       *\r
+    ***************************************************************************\r
+\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    >>>NOTE<<< The modification to the GPL is included to allow you to\r
+    distribute a combined work that includes FreeRTOS without being obliged to\r
+    provide the source code for proprietary components outside of the FreeRTOS\r
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* BSP includes. */\r
+#include <mb_interface.h>\r
+#include <xparameters.h>\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.  \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR               char\r
+#define portFLOAT              float\r
+#define portDOUBLE             double\r
+#define portLONG               long\r
+#define portSHORT              short\r
+#define portSTACK_TYPE unsigned long\r
+#define portBASE_TYPE  long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+       typedef unsigned portSHORT portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+       typedef unsigned portLONG portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/        \r
+\r
+/* Interrupt control macros and functions. */\r
+void microblaze_disable_interrupts( void );\r
+void microblaze_enable_interrupts( void );\r
+#define portDISABLE_INTERRUPTS()       microblaze_disable_interrupts()\r
+#define portENABLE_INTERRUPTS()                microblaze_enable_interrupts()\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Critical section macros. */\r
+void vPortEnterCritical( void );\r
+void vPortExitCritical( void );\r
+#define portENTER_CRITICAL()           {                                                                                                                               \\r
+                                                                               extern volatile unsigned portBASE_TYPE uxCriticalNesting;       \\r
+                                                                               microblaze_disable_interrupts();                                                        \\r
+                                                                               uxCriticalNesting++;                                                                            \\r
+                                                                       }\r
+\r
+#define portEXIT_CRITICAL()                    {                                                                                                                               \\r
+                                                                               extern volatile unsigned portBASE_TYPE uxCriticalNesting;       \\r
+                                                                               /* Interrupts are disabled, so we can */                                        \\r
+                                                                               /* access the variable directly. */                                                     \\r
+                                                                               uxCriticalNesting--;                                                                            \\r
+                                                                               if( uxCriticalNesting == 0 )                                                            \\r
+                                                                               {                                                                                                                       \\r
+                                                                                       /* The nesting has unwound and we                                               \\r
+                                                                                       can enable interrupts again. */                                                 \\r
+                                                                                       portENABLE_INTERRUPTS();                                                                \\r
+                                                                               }                                                                                                                       \\r
+                                                                       }\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The yield macro maps directly to the vPortYield() function. */\r
+void vPortYield( void );\r
+#define portYIELD() vPortYield()\r
+\r
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead\r
+sets a flag to say that a yield has been requested.  The interrupt exit code\r
+then checks this flag, and calls vTaskSwitchContext() before restoring a task\r
+context, if the flag is not false.  This is done to prevent multiple calls to\r
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt\r
+can result in multiple peripherals being serviced. */\r
+extern volatile unsigned long ulTaskSwitchRequested;\r
+#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) ulTaskSwitchRequested = 1\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Hardware specifics. */\r
+#define portBYTE_ALIGNMENT                     4\r
+#define portSTACK_GROWTH                       ( -1 )\r
+#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )\r
+#define portNOP()                                      asm volatile ( "NOP" )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following structure is used by the FreeRTOS exception handler.  It is\r
+filled with the MicroBlaze context as it was at the time the exception occurred.\r
+This is done as an aid to debugging exception occurrences. */\r
+typedef struct PORT_REGISTER_DUMP\r
+{\r
+       /* The following structure members hold the values of the MicroBlaze\r
+       registers at the time the exception was raised. */\r
+       unsigned long ulR1_SP;\r
+       unsigned long ulR2_small_data_area;\r
+       unsigned long ulR3;\r
+       unsigned long ulR4;\r
+       unsigned long ulR5;\r
+       unsigned long ulR6;\r
+       unsigned long ulR7;\r
+       unsigned long ulR8;\r
+       unsigned long ulR9;\r
+       unsigned long ulR10;\r
+       unsigned long ulR11;\r
+       unsigned long ulR12;\r
+       unsigned long ulR13_read_write_small_data_area;\r
+       unsigned long ulR14_return_address_from_interrupt;\r
+       unsigned long ulR15_return_address_from_subroutine;\r
+       unsigned long ulR16_return_address_from_trap;\r
+       unsigned long ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */\r
+       unsigned long ulR18;\r
+       unsigned long ulR19;\r
+       unsigned long ulR20;\r
+       unsigned long ulR21;\r
+       unsigned long ulR22;\r
+       unsigned long ulR23;\r
+       unsigned long ulR24;\r
+       unsigned long ulR25;\r
+       unsigned long ulR26;\r
+       unsigned long ulR27;\r
+       unsigned long ulR28;\r
+       unsigned long ulR29;\r
+       unsigned long ulR30;\r
+       unsigned long ulR31;\r
+       unsigned long ulPC;\r
+       unsigned long ulESR;\r
+       unsigned long ulMSR;\r
+       unsigned long ulEAR;\r
+       unsigned long ulFSR;\r
+       unsigned long ulEDR;\r
+\r
+       /* A human readable description of the exception cause.  The strings used\r
+       are the same as the #define constant names found in the\r
+       microblaze_exceptions_i.h header file */\r
+       signed char *pcExceptionCause;\r
+\r
+       /* The human readable name of the task that was running at the time the\r
+       exception occurred.  This is the name that was given to the task when the\r
+       task was created using the FreeRTOS xTaskCreate() API function. */\r
+       signed char *pcCurrentTaskName;\r
+\r
+       /* The handle of the task that was running a the time the exception\r
+       occurred. */\r
+       void * xCurrentTaskHandle;\r
+\r
+} xPortRegisterDump;\r
+\r
+\r
+/*\r
+ * Installs pxHandler as the interrupt handler for the peripheral specified by \r
+ * the ucInterruptID parameter.\r
+ *\r
+ * ucInterruptID:\r
+ * \r
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt\r
+ * handler.  Peripheral IDs are defined in the xparameters.h header file, which \r
+ * is itself part of the BSP project.  For example, in the official demo \r
+ * application for this port, xparameters.h defines the following IDs for the \r
+ * four possible interrupt sources:\r
+ *\r
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.\r
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.\r
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.\r
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.\r
+ *\r
+ *\r
+ * pxHandler:\r
+ * \r
+ * A pointer to the interrupt handler function itself.  This must be a void\r
+ * function that takes a (void *) parameter.\r
+ *\r
+ *\r
+ * pvCallBackRef:\r
+ *\r
+ * The parameter passed into the handler function.  In many cases this will not\r
+ * be used and can be NULL.  Some times it is used to pass in a reference to\r
+ * the peripheral instance variable, so it can be accessed from inside the\r
+ * handler function.\r
+ *\r
+ * \r
+ * pdPASS is returned if the function executes successfully.  Any other value\r
+ * being returned indicates that the function did not execute correctly.\r
+ */\r
+portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );\r
+\r
+\r
+/*\r
+ * Enables the interrupt, within the interrupt controller, for the peripheral \r
+ * specified by the ucInterruptID parameter.\r
+ *\r
+ * ucInterruptID:\r
+ * \r
+ * The ID of the peripheral that will have its interrupt enabled in the\r
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header \r
+ * file, which is itself part of the BSP project.  For example, in the official \r
+ * demo application for this port, xparameters.h defines the following IDs for \r
+ * the four possible interrupt sources:\r
+ *\r
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.\r
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.\r
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.\r
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.\r
+ *\r
+ */\r
+void vPortEnableInterrupt( unsigned char ucInterruptID );\r
+\r
+/*\r
+ * Disables the interrupt, within the interrupt controller, for the peripheral \r
+ * specified by the ucInterruptID parameter.\r
+ *\r
+ * ucInterruptID:\r
+ * \r
+ * The ID of the peripheral that will have its interrupt disabled in the\r
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header \r
+ * file, which is itself part of the BSP project.  For example, in the official \r
+ * demo application for this port, xparameters.h defines the following IDs for \r
+ * the four possible interrupt sources:\r
+ *\r
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.\r
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.\r
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.\r
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.\r
+ *\r
+ */\r
+void vPortDisableInterrupt( unsigned char ucInterruptID );\r
+\r
+/*\r
+ * This is an application defined callback function used to install the tick\r
+ * interrupt handler.  It is provided as an application callback because the \r
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not \r
+ * all of which will have the same timer peripherals defined or available.  This \r
+ * example uses the AXI Timer 0.  If that is available on your hardware platform \r
+ * then this example callback implementation should not require modification.  \r
+ * The name of the interrupt handler that should be installed is vPortTickISR(), \r
+ * which the function below declares as an extern.\r
+ */ \r
+void vApplicationSetupTimerInterrupt( void );\r
+\r
+/* \r
+ * This is an application defined callback function used to clear whichever\r
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback\r
+ * function - in this case the interrupt generated by the AXI timer.  It is \r
+ * provided as an application callback because the kernel will run on lots of \r
+ * different MicroBlaze and FPGA configurations - not all of which will have the \r
+ * same timer peripherals defined or available.  This example uses the AXI Timer 0.  \r
+ * If that is available on your hardware platform then this example callback \r
+ * implementation should not require modification provided the example definition\r
+ * of vApplicationSetupTimerInterrupt() is also not modified. \r
+ */\r
+void vApplicationClearTimerInterrupt( void );\r
+\r
+/*\r
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze\r
+ * is configured to include exception functionality, and \r
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.\r
+ *\r
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler\r
+ * for every possible exception cause.  \r
+ *\r
+ * vPortExceptionsInstallHandlers() can be called explicitly from application\r
+ * code.  After that is done, the default FreeRTOS exception handler that will\r
+ * have been installed can be replaced for any specific exception cause by using \r
+ * the standard Xilinx library function microblaze_register_exception_handler().\r
+ *\r
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the \r
+ * application, it will be called automatically by the kernel the first time\r
+ * xPortInstallInterruptHandler() is called.  At that time, any exception \r
+ * handlers that may have already been installed will be replaced.\r
+ *\r
+ * See the description of vApplicationExceptionRegisterDump() for information\r
+ * on the processing performed by the FreeRTOS exception handler.\r
+ */\r
+void vPortExceptionsInstallHandlers( void );\r
+\r
+/*\r
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined \r
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the \r
+ * exception occurred.  The exception handler then calls\r
+ * vApplicationExceptionRegisterDump(), passing in the completed\r
+ * xPortRegisterDump structure as its parameter.\r
+ *\r
+ * The FreeRTOS kernel provides its own implementation of\r
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation \r
+ * is declared as being 'weak'.  The weak definition allows the application \r
+ * writer to provide their own implementation, should they wish to use the \r
+ * register dump information.  For example, an implementation could be provided\r
+ * that wrote the register dump data to a display, or a UART port.\r
+ */\r
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r