+/*
+ * The reference schematic from TI for the XDS100v2 has a CPLD on which opens
+ * the door for a number of different configurations
+ *
+ * Known Implementations:
+ * http://processors.wiki.ti.com/images/9/93/TMS570LS20216_USB_STICK_Schematic.pdf
+ *
+ * http://processors.wiki.ti.com/index.php/XDS100 (rev2)
+ * * CLPD logic: Rising edge to enable outputs (XDS100_PWR_RST)
+ * * ACBUS3 to transition 0->1 (OE rising edge)
+ * * CPLD logic: Put the EMU0/1 pins in Hi-Z:
+ * * ADBUS5/GPIOL1 = EMU_EN = 1
+ * * ADBUS6/GPIOL2 = EMU0 = 0
+ * * ACBUS4/SPARE0 = EMU1 = 0
+ * * CPLD logic: Disable loopback
+ * * ACBUS6/SPARE2 = LOOPBACK = 0
+ */
+#define XDS100_nEMU_EN (1<<5)
+#define XDS100_nEMU0 (1<<6)
+
+#define XDS100_PWR_RST (1<<3)
+#define XDS100_nEMU1 (1<<4)
+#define XDS100_LOOPBACK (1<<6)