/* select main OSC, 12MHz, as the PLL clock source. */\r
SC->CLKSRCSEL = 0x1; \r
\r
/* select main OSC, 12MHz, as the PLL clock source. */\r
SC->CLKSRCSEL = 0x1; \r
\r
+ SC->PLL0CFG = 0x20031;\r
SC->PLL0FEED = PLLFEED_FEED1;\r
SC->PLL0FEED = PLLFEED_FEED2;\r
\r
SC->PLL0FEED = PLLFEED_FEED1;\r
SC->PLL0FEED = PLLFEED_FEED2;\r
\r
SC->CCLKCFG = 0x03;\r
\r
/* Configure flash accelerator. */\r
SC->CCLKCFG = 0x03;\r
\r
/* Configure flash accelerator. */\r
- SC->FLASHCFG = 0x303a;\r
+ SC->FLASHCFG = 0x403a;\r
\r
/* Check lock bit status. */\r
while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) ); \r
\r
/* Check lock bit status. */\r
while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) ); \r