-/* Flash Accelerator Module */\r
-#define FLASHCTRL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))\r
-#define FLASHTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004))\r
-\r
-/* Phase Locked Loop (Main PLL0) */\r
-#define PLL0CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080))\r
-#define PLL0CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084))\r
-#define PLL0STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088))\r
-#define PLL0FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C))\r
-\r
-/* Phase Locked Loop (USB PLL1) */\r
-#define PLL1CON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A0))\r
-#define PLL1CFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A4))\r
-#define PLL1STAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0A8))\r
-#define PLL1FEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0AC))\r
-\r
-/* Power Control */\r
-#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0))\r
-#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4))\r
-\r
-/* Clock Selection and Dividers */\r
-#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104))\r
-#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108))\r
-#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))\r
-#define IRCTRIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A4))\r
-#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))\r
-#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))\r
- \r
-/* External Interrupts */\r
-#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))\r
-#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148))\r
-#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C))\r
-\r
-/* Reset */\r
-#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180))\r
-\r
-/* System Controls and Status */\r
-#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) \r
-\r
-\r
-/* Pin Connect Block */\r
-#define PINCON_BASE_ADDR 0x4002C000\r
-#define PINSEL0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x00))\r
-#define PINSEL1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x04))\r
-#define PINSEL2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x08))\r
-#define PINSEL3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x0C))\r
-#define PINSEL4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x10))\r
-#define PINSEL5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x14))\r
-#define PINSEL6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x18))\r
-#define PINSEL7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x1C))\r
-#define PINSEL8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x20))\r
-#define PINSEL9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x24))\r
-#define PINSEL10 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x28))\r
-\r
-#define PINMODE0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x40))\r
-#define PINMODE1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x44))\r
-#define PINMODE2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x48))\r
-#define PINMODE3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x4C))\r
-#define PINMODE4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x50))\r
-#define PINMODE5 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x54))\r
-#define PINMODE6 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x58))\r
-#define PINMODE7 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x5C))\r
-#define PINMODE8 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x60))\r
-#define PINMODE9 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x64))\r
-#define PINMODE_OD0 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x68))\r
-#define PINMODE_OD1 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x6C))\r
-#define PINMODE_OD2 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x70))\r
-#define PINMODE_OD3 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x74))\r
-#define PINMODE_OD4 (*(volatile unsigned long *)(PINCON_BASE_ADDR + 0x78))\r
-\r
-\r
-/* General Purpose Input/Output (GPIO) - Fast GPIO */\r
-// #define GPIO_BASE_ADDR 0x50014000 /* For the first silicon v0.00 */\r
-#define GPIO_BASE_ADDR 0x2009C000 /* For silicon v0.01 or newer */\r
-#define FIO0DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) \r
-#define FIO0MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10))\r
-#define FIO0PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14))\r
-#define FIO0SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18))\r
-#define FIO0CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))\r
-\r
-#define FIO1DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x20)) \r
-#define FIO1MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x30))\r
-#define FIO1PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x34))\r
-#define FIO1SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x38))\r
-#define FIO1CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x3C))\r
-\r
-#define FIO2DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x40)) \r
-#define FIO2MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x50))\r
-#define FIO2PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x54))\r
-#define FIO2SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x58))\r
-#define FIO2CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x5C))\r
-\r
-#define FIO3DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x60)) \r
-#define FIO3MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x70))\r
-#define FIO3PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x74))\r
-#define FIO3SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x78))\r
-#define FIO3CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x7C))\r
-\r
-#define FIO4DIR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) \r
-#define FIO4MASK (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))\r
-#define FIO4PIN (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))\r
-#define FIO4SET (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x98))\r
-#define FIO4CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x9C))\r
-\r
-/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */\r
-#define FIO0DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x00)) \r
-#define FIO1DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x20)) \r
-#define FIO2DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40)) \r
-#define FIO3DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x60)) \r
-#define FIO4DIR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x80)) \r
-\r
-#define FIO0DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x01)) \r
-#define FIO1DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x21)) \r
-#define FIO2DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41)) \r
-#define FIO3DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x61)) \r
-#define FIO4DIR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x81)) \r
-\r
-#define FIO0DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x02)) \r
-#define FIO1DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x22)) \r
-#define FIO2DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42)) \r
-#define FIO3DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x62)) \r
-#define FIO4DIR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x82)) \r
-\r
-#define FIO0DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x03)) \r
-#define FIO1DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x23)) \r
-#define FIO2DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43)) \r
-#define FIO3DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x63)) \r
-#define FIO4DIR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x83)) \r
-\r
-#define FIO0DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x00)) \r
-#define FIO1DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x20)) \r
-#define FIO2DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40)) \r
-#define FIO3DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x60)) \r
-#define FIO4DIRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x80)) \r
-\r
-#define FIO0DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x02)) \r
-#define FIO1DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x22)) \r
-#define FIO2DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42)) \r
-#define FIO3DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x62)) \r
-#define FIO4DIRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x82)) \r
-\r
-#define FIO0MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x10)) \r
-#define FIO1MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x30)) \r
-#define FIO2MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x40)) \r
-#define FIO3MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x50)) \r
-#define FIO4MASK0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x90)) \r
-\r
-#define FIO0MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x11)) \r
-#define FIO1MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x31)) \r
-#define FIO2MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x41)) \r
-#define FIO3MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x51)) \r
-#define FIO4MASK1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x91)) \r
-\r
-#define FIO0MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x12)) \r
-#define FIO1MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x32)) \r
-#define FIO2MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x42)) \r
-#define FIO3MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x52)) \r
-#define FIO4MASK2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x92)) \r
-\r
-#define FIO0MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x13)) \r
-#define FIO1MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x33)) \r
-#define FIO2MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x43)) \r
-#define FIO3MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x53)) \r
-#define FIO4MASK3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x93)) \r
-\r
-#define FIO0MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x10)) \r
-#define FIO1MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x30)) \r
-#define FIO2MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x40)) \r
-#define FIO3MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x50)) \r
-#define FIO4MASKL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x90)) \r
-\r
-#define FIO0MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x12)) \r
-#define FIO1MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x32)) \r
-#define FIO2MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x42)) \r
-#define FIO3MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x52)) \r
-#define FIO4MASKU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x92)) \r
-\r
-#define FIO0PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x14)) \r
-#define FIO1PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x34)) \r
-#define FIO2PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x44)) \r
-#define FIO3PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x54)) \r
-#define FIO4PIN0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x94)) \r
-\r
-#define FIO0PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x15)) \r
-#define FIO1PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x35)) \r
-#define FIO2PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x45)) \r
-#define FIO3PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x55)) \r
-#define FIO4PIN1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x95)) \r
-\r
-#define FIO0PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x16)) \r
-#define FIO1PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x36)) \r
-#define FIO2PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x46)) \r
-#define FIO3PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x56)) \r
-#define FIO4PIN2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x96)) \r
-\r
-#define FIO0PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x17)) \r
-#define FIO1PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x37)) \r
-#define FIO2PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x47)) \r
-#define FIO3PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x57)) \r
-#define FIO4PIN3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x97)) \r
-\r
-#define FIO0PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x14)) \r
-#define FIO1PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x34)) \r
-#define FIO2PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x44)) \r
-#define FIO3PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x54)) \r
-#define FIO4PINL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x94)) \r
-\r
-#define FIO0PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x16)) \r
-#define FIO1PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x36)) \r
-#define FIO2PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x46)) \r
-#define FIO3PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x56)) \r
-#define FIO4PINU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x96)) \r
-\r
-#define FIO0SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x18)) \r
-#define FIO1SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x38)) \r
-#define FIO2SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x48)) \r
-#define FIO3SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x58)) \r
-#define FIO4SET0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x98)) \r
-\r
-#define FIO0SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x19)) \r
-#define FIO1SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x39)) \r
-#define FIO2SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x49)) \r
-#define FIO3SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x59)) \r
-#define FIO4SET1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x99)) \r
-\r
-#define FIO0SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1A)) \r
-#define FIO1SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3A)) \r
-#define FIO2SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4A)) \r
-#define FIO3SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5A)) \r
-#define FIO4SET2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9A)) \r
-\r
-#define FIO0SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1B)) \r
-#define FIO1SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3B)) \r
-#define FIO2SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4B)) \r
-#define FIO3SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5B)) \r
-#define FIO4SET3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9B)) \r
-\r
-#define FIO0SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x18)) \r
-#define FIO1SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x38)) \r
-#define FIO2SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x48)) \r
-#define FIO3SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x58)) \r
-#define FIO4SETL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x98)) \r
-\r
-#define FIO0SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1A)) \r
-#define FIO1SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3A)) \r
-#define FIO2SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4A)) \r
-#define FIO3SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5A)) \r
-#define FIO4SETU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9A)) \r
-\r
-#define FIO0CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1C)) \r
-#define FIO1CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3C)) \r
-#define FIO2CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4C)) \r
-#define FIO3CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5C)) \r
-#define FIO4CLR0 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9C)) \r
-\r
-#define FIO0CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1D)) \r
-#define FIO1CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3D)) \r
-#define FIO2CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4D)) \r
-#define FIO3CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5D)) \r
-#define FIO4CLR1 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9D)) \r
-\r
-#define FIO0CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1E)) \r
-#define FIO1CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3E)) \r
-#define FIO2CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4E)) \r
-#define FIO3CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5E)) \r
-#define FIO4CLR2 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9E)) \r
-\r
-#define FIO0CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x1F)) \r
-#define FIO1CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x3F)) \r
-#define FIO2CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x4F)) \r
-#define FIO3CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5F)) \r
-#define FIO4CLR3 (*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9F)) \r
-\r
-#define FIO0CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1C)) \r
-#define FIO1CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3C)) \r
-#define FIO2CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4C)) \r
-#define FIO3CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5C)) \r
-#define FIO4CLRL (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9C)) \r
-\r
-#define FIO0CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x1E)) \r
-#define FIO1CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x3E)) \r
-#define FIO2CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x4E)) \r
-#define FIO3CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x5E)) \r
-#define FIO4CLRU (*(volatile unsigned short *)(GPIO_BASE_ADDR + 0x9E)) \r
-\r
-/* GPIO Interrupt Registers */\r
-#define GPIO_INT_BASE_ADDR 0x40028000\r
-#define IO0IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x90)) \r
-#define IO0IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x94))\r
-#define IO0IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x84))\r
-#define IO0IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x88))\r
-#define IO0IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x8C))\r
-\r
-#define IO2IntEnR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB0)) \r
-#define IO2IntEnF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xB4))\r
-#define IO2IntStatR (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA4))\r
-#define IO2IntStatF (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xA8))\r
-#define IO2IntClr (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0xAC))\r
-\r
-#define IOIntStatus (*(volatile unsigned long *)(GPIO_INT_BASE_ADDR + 0x80))\r
-\r
-\r
-/* Timer 0 */\r
-#define TMR0_BASE_ADDR 0x40004000\r
-#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))\r
-#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))\r
-#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))\r
-#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C))\r
-#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10))\r
-#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14))\r
-#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18))\r
-#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C))\r
-#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20))\r
-#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24))\r
-#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28))\r
-#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C))\r
-#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30))\r
-#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34))\r
-#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38))\r
-#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C))\r
-#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))\r
-\r
-/* Timer 1 */\r
-#define TMR1_BASE_ADDR 0x40008000\r
-#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))\r
-#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))\r
-#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))\r
-#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C))\r
-#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10))\r
-#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14))\r
-#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18))\r
-#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C))\r
-#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20))\r
-#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24))\r
-#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28))\r
-#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C))\r
-#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30))\r
-#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34))\r
-#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38))\r
-#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C))\r
-#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))\r
-\r
-/* Timer 2 */\r
-#define TMR2_BASE_ADDR 0x40090000\r
-#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))\r
-#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))\r
-#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))\r
-#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C))\r
-#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10))\r
-#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14))\r
-#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18))\r
-#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C))\r
-#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20))\r
-#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24))\r
-#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28))\r
-#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C))\r
-#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30))\r
-#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34))\r
-#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38))\r
-#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C))\r
-#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))\r
-\r
-/* Timer 3 */\r
-#define TMR3_BASE_ADDR 0x40094000\r
-#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))\r
-#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))\r
-#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))\r
-#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C))\r
-#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10))\r
-#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14))\r
-#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18))\r
-#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C))\r
-#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20))\r
-#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24))\r
-#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28))\r
-#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C))\r
-#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30))\r
-#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34))\r
-#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38))\r
-#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C))\r
-#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70))\r
-\r
-\r
-/* Pulse Width Modulator (PWM) */\r
-#define PWM1_BASE_ADDR 0x40018000\r
-#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))\r
-#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))\r
-#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))\r
-#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C))\r
-#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10))\r
-#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14))\r
-#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18))\r
-#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C))\r
-#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20))\r
-#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24))\r
-#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28))\r
-#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C))\r
-#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30))\r
-#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34))\r
-#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38))\r
-#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40))\r
-#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44))\r
-#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48))\r
-#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C))\r
-#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50))\r
-#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70))\r
-\r
-\r
-/* Universal Asynchronous Receiver Transmitter 0 (UART0) */\r
-#define UART0_BASE_ADDR 0x4000C000\r
-#define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
-#define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
-#define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))\r
-#define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
-#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04))\r
-#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
-#define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08))\r
-#define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C))\r
-#define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14))\r
-#define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C))\r
-#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20))\r
-#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28))\r
-#define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))\r
-#define U0RS485CTRL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x4C))\r
-#define U0ADRMATCH (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x50))\r
-\r
-/* Universal Asynchronous Receiver Transmitter 1 (UART1) */\r
-#define UART1_BASE_ADDR 0x40010000\r
-#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
-#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
-#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))\r
-#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
-#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04))\r
-#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
-#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08))\r
-#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C))\r
-#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10))\r
-#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14))\r
-#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18))\r
-#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C))\r
-#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20))\r
-#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28))\r
-#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))\r
-#define U1RS485CTRL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x4C))\r
-#define U1ADRMATCH (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x50))\r
-#define U1RS485DLY (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x54))\r
-\r
-/* Universal Asynchronous Receiver Transmitter 2 (UART2) */\r
-#define UART2_BASE_ADDR 0x40098000\r
-#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
-#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
-#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))\r
-#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
-#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04))\r
-#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
-#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08))\r
-#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C))\r
-#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14))\r
-#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C))\r
-#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20))\r
-#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28))\r
-#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))\r
-#define U2RS485CTRL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x4C))\r
-#define U2ADRMATCH (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x50))\r
-\r
-/* Universal Asynchronous Receiver Transmitter 3 (UART3) */\r
-#define UART3_BASE_ADDR 0x4009C000\r
-#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
-#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
-#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))\r
-#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
-#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04))\r
-#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
-#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08))\r
-#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C))\r
-#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14))\r
-#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C))\r
-#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20))\r
-#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24))\r
-#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28))\r
-#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))\r
-#define U3RS485CTRL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x4C))\r
-#define U3ADRMATCH (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x50))\r
-\r
-\r
-/* SPI0 (Serial Peripheral Interface 0) */\r
-#define SPI0_BASE_ADDR 0x40020000\r
-#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))\r
-#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))\r
-#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))\r
-#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C))\r
-#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))\r
-\r
-/* SSP0 Controller */\r
-#define SSP0_BASE_ADDR 0x40088000\r
-#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))\r
-#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))\r
-#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))\r
-#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C))\r
-#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10))\r
-#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14))\r
-#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18))\r
-#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C))\r
-#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20))\r
-#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))\r
-\r
-/* SSP1 Controller */\r
-#define SSP1_BASE_ADDR 0x40030000\r
-#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))\r
-#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))\r
-#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))\r
-#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C))\r
-#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10))\r
-#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14))\r
-#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18))\r
-#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C))\r
-#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20))\r
-#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24))\r
-\r
-\r
-/* I2C Interface 0 */\r
-#define I2C0_BASE_ADDR 0x4001C000\r
-#define I2C0CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))\r
-#define I2C0STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))\r
-#define I2C0DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))\r
-#define I2C0ADR0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C))\r
-#define I2C0SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10))\r
-#define I2C0SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14))\r
-#define I2C0CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))\r
-#define I2C0MMCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x1C))\r
-#define I2C0ADR1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x20))\r
-#define I2C0ADR2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x24))\r
-#define I2C0ADR3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x28))\r
-#define I2C0DATBUFFER (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x2C))\r
-#define I2C0MASK0 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x30))\r
-#define I2C0MASK1 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x34))\r
-#define I2C0MASK2 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x38))\r
-#define I2C0MASK3 (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x3C))\r
-\r
-/* I2C Interface 1 */\r
-#define I2C1_BASE_ADDR 0x4005C000\r
-#define I2C1CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))\r
-#define I2C1STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))\r
-#define I2C1DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))\r
-#define I2C1ADR0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C))\r
-#define I2C1SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10))\r
-#define I2C1SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14))\r
-#define I2C1CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))\r
-#define I2C1MMCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x1C))\r
-#define I2C1ADR1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x20))\r
-#define I2C1ADR2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x24))\r
-#define I2C1ADR3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x28))\r
-#define I2C1DATBUFFER (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x2C))\r
-#define I2C1MASK0 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x30))\r
-#define I2C1MASK1 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x34))\r
-#define I2C1MASK2 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x38))\r
-#define I2C1MASK3 (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x3C))\r
-\r
-/* I2C Interface 2 */\r
-#define I2C2_BASE_ADDR 0x400A0000\r
-#define I2C2CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))\r
-#define I2C2STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))\r
-#define I2C2DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))\r
-#define I2C2ADR0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C))\r
-#define I2C2SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10))\r
-#define I2C2SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14))\r
-#define I2C2CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))\r
-#define I2C2MMCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x1C))\r
-#define I2C2ADR1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x20))\r
-#define I2C2ADR2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x24))\r
-#define I2C2ADR3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x28))\r
-#define I2C2DATBUFFER (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x2C))\r
-#define I2C2MASK0 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x30))\r
-#define I2C2MASK1 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x34))\r
-#define I2C2MASK2 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x38))\r
-#define I2C2MASK3 (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x3C))\r
-\r
-\r
-/* I2S Interface Controller (I2S) */\r
-#define I2S_BASE_ADDR 0x400A8000\r
-#define I2SDAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))\r
-#define I2SDAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))\r
-#define I2STXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))\r
-#define I2SRXFIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C))\r
-#define I2SSTATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10))\r
-#define I2SDMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14))\r
-#define I2SDMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18))\r
-#define I2SIRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C))\r
-#define I2STXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20))\r
-#define I2SRXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24))\r
-#define I2STXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x28))\r
-#define I2SRXBITRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x2C))\r
-#define I2STXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x30))\r
-#define I2SRXMODE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x34))\r
-\r
-\r
-/* Repetitive Interrupt Timer (RIT) */\r
-#define RIT_BASE_ADDR 0x400B4000\r
-#define RICOMPVAL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x00))\r
-#define RIMASK (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x04))\r
-#define RICTRL (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x08))\r
-#define RICOUNTER (*(volatile unsigned long *)(RIT_BASE_ADDR + 0x0C))\r
-\r
-\r
-/* Real Time Clock (RTC) */\r
-#define RTC_BASE_ADDR 0x40024000\r
-#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))\r
-#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))\r
-#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C))\r
-#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10))\r
-#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14))\r
-#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18))\r
-#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C))\r
-#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20))\r
-#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24))\r
-#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28))\r
-#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C))\r
-#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30))\r
-#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34))\r
-#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38))\r
-#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C))\r
-#define RTC_CALIBRATION (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40))\r
-#define RTC_GPREG0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x44))\r
-#define RTC_GPREG1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x48))\r
-#define RTC_GPREG2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x4C))\r
-#define RTC_GPREG3 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x50))\r
-#define RTC_GPREG4 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x54))\r
-#define RTC_WAKEUPDIS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x58))\r
-#define RTC_PWRCTRL (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x5c))\r
-#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60))\r
-#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64))\r
-#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68))\r
-#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C))\r
-#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70))\r
-#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74))\r
-#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78))\r
-#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C))\r
-\r
-\r
-/* Watchdog Timer (WDT) */\r
-#define WDT_BASE_ADDR 0x40000000\r
-#define WDMOD (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x00))\r
-#define WDTC (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x04))\r
-#define WDFEED (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x08))\r
-#define WDTV (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x0C))\r
-#define WDCLKSEL (*(volatile unsigned long *)(WDT_BASE_ADDR + 0x10))\r
-\r
-\r
-/* A/D Converter 0 (ADC0) */\r
-#define AD0_BASE_ADDR 0x40034000\r
-#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))\r
-#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))\r
-#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))\r
-#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10))\r
-#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14))\r
-#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18))\r
-#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C))\r
-#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20))\r
-#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24))\r
-#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28))\r
-#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C))\r
-#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30))\r
-#define ADTRIM (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x34))\r
-\r
-\r
-/* D/A Converter (DAC) */\r
-#define DAC_BASE_ADDR 0x4008C000\r
-#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))\r
-#define DACCTRL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x04))\r
-#define DACCNTVAL (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x08))\r
-\r
-\r
-/* Motor Control PWM */\r
-#define MCPWM_BASE_ADDR 0x400B8000\r
-#define MCCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x00))\r
-#define MCCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x04))\r
-#define MCCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x08))\r
-#define MCCAPCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x0C))\r
-#define MCCAPCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x10))\r
-#define MCCAPCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x14))\r
-#define MCTIM0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x18))\r
-#define MCTIM1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x1C))\r
-#define MCTIM2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x20))\r
-#define MCPER0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x24))\r
-#define MCPER1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x28))\r
-#define MCPER2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x2C))\r
-#define MCPW0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x30))\r
-#define MCPW1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x34))\r
-#define MCPW2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x38))\r
-#define MCDEADTIME (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x3C))\r
-#define MCCCP (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x40))\r
-#define MCCR0 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x44))\r
-#define MCCR1 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x48))\r
-#define MCCR2 (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x4C))\r
-#define MCINTEN (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x50))\r
-#define MCINTEN_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x54))\r
-#define MCINTEN_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x58))\r
-#define MCCNTCON (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x5C))\r
-#define MCCNTCON_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x60))\r
-#define MCCNTCON_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x64))\r
-#define MCINTFLAG (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x68))\r
-#define MCINTFLAG_SET (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x6C))\r
-#define MCINTFLAG_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x70))\r
-#define MCCAP_CLR (*(volatile unsigned long *)(MCPWM_BASE_ADDR + 0x74))\r
-\r
-\r
-/* Quadrature Encoder Interface (QEI) */\r
-#define QEI_BASE_ADDR 0x400BC000\r
-\r
-/* QEI Control Registers */\r
-#define QEICON (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x000))\r
-#define QEISTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x004))\r
-#define QEICONF (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x008))\r
-\r
-/* QEI Position, Index, and Timer Registers */\r
-#define QEIPOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x00C))\r
-#define QEIMAXPSOS (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x010))\r
-#define CMPOS0 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x014))\r
-#define CMPOS1 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x018))\r
-#define CMPOS2 (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x01C))\r
-#define INXCNT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x020))\r
-#define INXCMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x024))\r
-#define QEILOAD (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x028))\r
-#define QEITIME (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x02C))\r
-#define QEIVEL (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x030))\r
-#define QEICAP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x034))\r
-#define VELCOMP (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x038))\r
-#define FILTER (*(volatile unsigned long *)(QEI_BASE_ADDR + 0x03C))\r
-\r
-/* QEI Interrupt registers */\r
-#define QEIIES (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFDC))\r
-#define QEIIEC (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFD8))\r
-#define QEIINTSTAT (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE0))\r
-#define QEIIE (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE4))\r
-#define QEICLR (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFE8))\r
-#define QEISET (*(volatile unsigned long *)(QEI_BASE_ADDR + 0xFEC))\r
-\r
-\r
-/* CAN Controllers and Acceptance Filter */\r
-\r
-/* CAN Acceptance Filter */\r
-#define CAN_AF_BASE_ADDR 0x4003C000\r
-#define AFMR (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x00)) \r
-#define SFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x04)) \r
-#define SFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x08))\r
-#define EFF_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x0C))\r
-#define EFF_GRP_sa (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x10)) \r
-#define ENDofTable (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x14))\r
-#define LUTerrAd (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x18)) \r
-#define LUTerr (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x1C))\r
-#define FCANIE (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x20))\r
-#define FCANIC0 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x24))\r
-#define FCANIC1 (*(volatile unsigned long *)(CAN_AF_BASE_ADDR + 0x28))\r
-\r
-/* CAN Centralized Registers */\r
-#define CAN_BASE_ADDR 0x40040000 \r
-#define CANTxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x00)) \r
-#define CANRxSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x04)) \r
-#define CANMSR (*(volatile unsigned long *)(CAN_BASE_ADDR + 0x08))\r
-\r
-/* CAN1 Controller */\r
-#define CAN1_BASE_ADDR 0x40044000\r
-#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) \r
-#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) \r
-#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) \r
-#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) \r
-#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))\r
-#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) \r
-#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) \r
-#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) \r
-#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) \r
-#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))\r
-#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) \r
-#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) \r
-#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) \r
-#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) \r
-#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))\r
-#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) \r
-#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) \r
-#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) \r
-#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) \r
-#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))\r
-#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) \r
-#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) \r
-#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) \r
-#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))\r
-\r
-/* CAN2 Controller */\r
-#define CAN2_BASE_ADDR 0x40048000\r
-#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) \r
-#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) \r
-#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) \r
-#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) \r
-#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))\r
-#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) \r
-#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) \r
-#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) \r
-#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) \r
-#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))\r
-#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) \r
-#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) \r
-#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) \r
-#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) \r
-#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))\r
-#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) \r
-#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) \r
-#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) \r
-#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) \r
-#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))\r
-#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) \r
-#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) \r
-#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) \r
-#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))\r
-\r
-\r
-/* General Purpose DMA Controller (GPDMA) */\r
-#define DMA_BASE_ADDR 0x50004000\r
-#define DMACIntStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))\r
-#define DMACIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))\r
-#define DMACIntTCClear (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))\r
-#define DMACIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C))\r
-#define DMACIntErrClr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010))\r
-#define DMACRawIntTCStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014))\r
-#define DMACRawIntErrStat (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018))\r
-#define DMACEnbldChns (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C))\r
-#define DMACSoftBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020))\r
-#define DMACSoftSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024))\r
-#define DMACSoftLBReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028))\r
-#define DMACSoftLSReq (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C))\r
-#define DMACConfig (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030))\r
-#define DMACSync (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034))\r
-\r
-/* DMA Channel 0 Registers */\r
-#define DMACC0SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100))\r
-#define DMACC0DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104))\r
-#define DMACC0LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108))\r
-#define DMACC0Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C))\r
-#define DMACC0Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110))\r
-\r
-/* DMA Channel 1 Registers */\r
-#define DMACC1SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120))\r
-#define DMACC1DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124))\r
-#define DMACC1LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128))\r
-#define DMACC1Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C))\r
-#define DMACC1Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130))\r
-\r
-/* DMA Channel 2 Registers */\r
-#define DMACC2SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x140))\r
-#define DMACC2DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x144))\r
-#define DMACC2LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x148))\r
-#define DMACC2Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x14C))\r
-#define DMACC2Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x150))\r
-\r
-/* DMA Channel 3 Registers */\r
-#define DMACC3SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x160))\r
-#define DMACC3DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x164))\r
-#define DMACC3LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x168))\r
-#define DMACC3Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x16C))\r
-#define DMACC3Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x170))\r
-\r
-/* DMA Channel 4 Registers */\r
-#define DMACC4SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x180))\r
-#define DMACC4DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x184))\r
-#define DMACC4LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x188))\r
-#define DMACC4Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x18C))\r
-#define DMACC4Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x190))\r
-\r
-/* DMA Channel 5 Registers */\r
-#define DMACC5SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A0))\r
-#define DMACC5DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A4))\r
-#define DMACC5LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1A8))\r
-#define DMACC5Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1AC))\r
-#define DMACC5Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1B0))\r
-\r
-/* DMA Channel 6 Registers */\r
-#define DMACC6SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C0))\r
-#define DMACC6DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C4))\r
-#define DMACC6LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1C8))\r
-#define DMACC6Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1CC))\r
-#define DMACC6Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1D0))\r
-\r
-/* DMA Channel 7 Registers */\r
-#define DMACC7SrcAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E0))\r
-#define DMACC7DestAddr (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E4))\r
-#define DMACC7LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1E8))\r
-#define DMACC7Control (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1EC))\r
-#define DMACC7Config (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x1F0))\r
-\r
-\r
-/* USB Controller */\r
-#define USB_BASE_ADDR 0x5000C000\r
-\r
-#define USBIntSt (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1C0))\r
-\r
-\r
-/* USB Device Controller */\r
-\r
-/* USB Device Clock Control Registers */\r
-#define USBClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))\r
-#define USBClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))\r
-\r
-/* USB Device Interrupt Registers */\r
-#define USBDevIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x200))\r
-#define USBDevIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x204))\r
-#define USBDevIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x208))\r
-#define USBDevIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20C))\r
-#define USBDevIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x22C))\r
-\r
-/* USB Device Endpoint Interrupt Registers */\r
-#define USBEpIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x230))\r
-#define USBEpIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x234))\r
-#define USBEpIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x238))\r
-#define USBEpIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x23C))\r
-#define USBEpIntPri (*(volatile unsigned long *)(USB_BASE_ADDR + 0x240))\r
-\r
-/* USB Device Endpoint Realization Registers */\r
-#define USBReEp (*(volatile unsigned long *)(USB_BASE_ADDR + 0x244))\r
-#define USBEpInd (*(volatile unsigned long *)(USB_BASE_ADDR + 0x248))\r
-#define USBMaxPSize (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24C))\r
-\r
-/* USB Device SIE Command Reagisters */\r
-#define USBCmdCode (*(volatile unsigned long *)(USB_BASE_ADDR + 0x210))\r
-#define USBCmdData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x214))\r
-\r
-/* USB Device Data Transfer Registers */\r
-#define USBRxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x218))\r
-#define USBTxData (*(volatile unsigned long *)(USB_BASE_ADDR + 0x21C))\r
-#define USBRxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x220))\r
-#define USBTxPLen (*(volatile unsigned long *)(USB_BASE_ADDR + 0x224))\r
-#define USBCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x228))\r
-\r
-/* USB Device DMA Registers */\r
-#define USBDMARSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x250))\r
-#define USBDMARClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x254))\r
-#define USBDMARSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x258))\r
-#define USBUDCAH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x280))\r
-#define USBEpDMASt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x284))\r
-#define USBEpDMAEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x288))\r
-#define USBEpDMADis (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28C))\r
-#define USBDMAIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x290))\r
-#define USBDMAIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x294))\r
-#define USBEoTIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A0))\r
-#define USBEoTIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A4))\r
-#define USBEoTIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2A8))\r
-#define USBNDDRIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2AC))\r
-#define USBNDDRIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B0))\r
-#define USBNDDRIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B4))\r
-#define USBSysErrIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2B8))\r
-#define USBSysErrIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2BC))\r
-#define USBSysErrIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C0))\r
-\r
-\r
-/* USB Host Controller */\r
-#define HcRevision (*(volatile unsigned long *)(USB_BASE_ADDR + 0x000))\r
-#define HcControl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x004))\r
-#define HcCommandStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x008))\r
-#define HcInterruptStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00C))\r
-#define HcInterruptEnable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x010))\r
-#define HcInterruptDisable (*(volatile unsigned long *)(USB_BASE_ADDR + 0x014))\r
-#define HcHCCA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x018))\r
-#define HcPeriodCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x01C))\r
-#define HcControlHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x020))\r
-#define HcControlCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x024))\r
-#define HcBulkHeadED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x028))\r
-#define HcBulkCurrentED (*(volatile unsigned long *)(USB_BASE_ADDR + 0x02C))\r
-#define HcDoneHead (*(volatile unsigned long *)(USB_BASE_ADDR + 0x030))\r
-#define HcFmInterval (*(volatile unsigned long *)(USB_BASE_ADDR + 0x034))\r
-#define HcFmRemaining (*(volatile unsigned long *)(USB_BASE_ADDR + 0x038))\r
-#define HcFmNumber (*(volatile unsigned long *)(USB_BASE_ADDR + 0x03C))\r
-#define HcPeriodStart (*(volatile unsigned long *)(USB_BASE_ADDR + 0x040))\r
-#define HcLSThreshold (*(volatile unsigned long *)(USB_BASE_ADDR + 0x044))\r
-#define HcRhDescriptorA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x048))\r
-#define HcRhDescriptorB (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04C))\r
-#define HcRhStatus (*(volatile unsigned long *)(USB_BASE_ADDR + 0x050))\r
-#define HcRhPortStatus1 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x054))\r
-#define HcRhPortStatus2 (*(volatile unsigned long *)(USB_BASE_ADDR + 0x058))\r
-\r
-\r
-/* USB OTG Controller */\r
-\r
-/* USB OTG Registers */\r
-#define OTGIntSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0x100))\r
-#define OTGIntEn (*(volatile unsigned long *)(USB_BASE_ADDR + 0x104))\r
-#define OTGIntSet (*(volatile unsigned long *)(USB_BASE_ADDR + 0x108))\r
-#define OTGIntClr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10C))\r
-#define OTGIntCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0x110))\r
-#define OTGTmr (*(volatile unsigned long *)(USB_BASE_ADDR + 0x114))\r
-\r
-/* USB OTG I2C Registers */\r
-#define I2C_RX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))\r
-#define I2C_TX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x300))\r
-#define I2C_STS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x304))\r
-#define I2C_CTL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x308))\r
-#define I2C_CLKHI (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30C))\r
-#define I2C_CLKLO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x310))\r
-\r
-/* USB OTG Clock Control Registers */\r
-#define OTGClkCtrl (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF4))\r
-#define OTGClkSt (*(volatile unsigned long *)(USB_BASE_ADDR + 0xFF8))\r
-\r
-\r
-/* Ethernet MAC */\r
-#define MAC_BASE_ADDR 0x50000000\r
-\r
-/* MAC Registers */\r
-#define ETH_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000))\r
-#define ETH_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004))\r
-#define ETH_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008))\r
-#define ETH_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C))\r
-#define ETH_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010))\r
-#define ETH_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014))\r
-#define ETH_PHYSUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018))\r
-#define ETH_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C))\r
-#define ETH_MIICFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020))\r
-#define ETH_MIICMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024))\r
-#define ETH_MIIADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028))\r
-#define ETH_MIIWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C))\r
-#define ETH_MIIRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030))\r
-#define ETH_MIIIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034))\r
-#define ETH_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040))\r
-#define ETH_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044))\r
-#define ETH_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048))\r
-\r
-/* MAC Control Registers */\r
-#define ETH_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100))\r
-#define ETH_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104))\r
-#define ETH_RXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108))\r
-#define ETH_RXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C))\r
-#define ETH_RXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110))\r
-#define ETH_RXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114))\r
-#define ETH_RXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118))\r
-#define ETH_TXDESC (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C))\r
-#define ETH_TXSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120))\r
-#define ETH_TXDESCRNO (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124))\r
-#define ETH_TXPRODIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128))\r
-#define ETH_TXCONSIX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C))\r
-#define ETH_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158))\r
-#define ETH_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C))\r
-#define ETH_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160))\r
-#define ETH_FLOWCNTCOUNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170))\r
-#define ETH_FLOWCNTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174))\r
-\r
-/* MAX Rx Filter Registers */\r
-#define ETH_RXFILTERCTL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200))\r
-#define ETH_RXFILTERWOLSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204))\r
-#define ETH_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208))\r
-#define ETH_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210))\r
-#define ETH_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214))\r
-\r
-/* MAC Module Control Registers */\r
-#define ETH_INSTSTAT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0))\r
-#define ETH_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4))\r
-#define ETH_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8))\r
-#define ETH_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC))\r
-#define ETH_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4))\r
-\r
-#define MAC_Module_ID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC))\r
-\r
-/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */\r
-#define MAC_BASE_ADDR 0x50000000\r
-#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */\r
-#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */\r
-#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */\r
-#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */\r
-#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */\r
-#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */\r
-#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */\r
-#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */\r
-#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */\r
-#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */\r
-#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */\r
-#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */\r
-#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */\r
-#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */\r
-\r
-#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */\r
-#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */\r
-#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */\r
-\r
-#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */\r
-#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */\r
-#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */\r
-#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */\r
-#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */\r
-#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */\r
-#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */\r
-#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */\r
-#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */\r
-#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */\r
-#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */\r
-#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */\r
-\r
-#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */\r
-#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */\r
-#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */\r
-\r
-#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */\r
-#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */\r
-\r
-#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */\r
-#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */\r
-#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */\r
-\r
-#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */\r
-#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */\r
-\r
-#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */\r
-#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */\r
-#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */\r
-#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */\r
-\r
-#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */\r
-#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */\r
-\r