-/*----------------------------------------------------------------------------\r
- * LPC2378 Ethernet Definitions\r
- *----------------------------------------------------------------------------\r
- * Name: EMAC.H\r
- * Purpose: Philips LPC2378 EMAC hardware definitions\r
- *----------------------------------------------------------------------------\r
- * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved.\r
- *---------------------------------------------------------------------------*/\r
-#ifndef __EMAC_H\r
-#define __EMAC_H\r
-\r
-/* MAC address definition. The MAC address must be unique on the network. */\r
-#define emacETHADDR0 0\r
-#define emacETHADDR1 0xbd\r
-#define emacETHADDR2 0x33\r
-#define emacETHADDR3 0x02\r
-#define emacETHADDR4 0x64\r
-#define emacETHADDR5 0x24\r
-\r
-\r
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
-#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */\r
-#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */\r
-#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */\r
-\r
-#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */\r
-\r
-/* EMAC variables located in 16K Ethernet SRAM */\r
-//extern unsigned char xEthDescriptors[];\r
-#define RX_DESC_BASE (0x2007c000UL)\r
-#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)\r
-#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)\r
-#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)\r
-#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)\r
-#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)\r
-#define TX_BUF_END (TX_BUF_BASE + NUM_TX_FRAG*ETH_FRAG_SIZE)\r
-\r
-/* RX and TX descriptor and status definitions. */\r
-#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))\r
-#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
-#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))\r
-#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
-#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))\r
-#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
-#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))\r
-#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)\r
-#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)\r
-\r
-/* MAC Configuration Register 1 */\r
-#define MAC1_REC_EN 0x00000001 /* Receive Enable */\r
-#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */\r
-#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */\r
-#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */\r
-#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */\r
-#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */\r
-#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */\r
-#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */\r
-#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */\r
-#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */\r
-#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */\r
-\r
-/* MAC Configuration Register 2 */\r
-#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */\r
-#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */\r
-#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */\r
-#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */\r
-#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */\r
-#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */\r
-#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */\r
-#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */\r
-#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */\r
-#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */\r
-#undef MAC2_NO_BACKOFF /* Remove compiler warning. */\r
-#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */\r
-#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */\r
-#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */\r
-\r
-/* Back-to-Back Inter-Packet-Gap Register */\r
-#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */\r
-#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */\r
-\r
-/* Non Back-to-Back Inter-Packet-Gap Register */\r
-#define IPGR_DEF 0x00000012 /* Recommended value */\r
-\r
-/* Collision Window/Retry Register */\r
-#define CLRT_DEF 0x0000370F /* Default value */\r
-\r
-/* PHY Support Register */\r
-#undef SUPP_SPEED /* Remove compiler warning. */\r
-#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */\r
-#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */\r
-\r
-/* Test Register */\r
-#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */\r
-#define TEST_TST_PAUSE 0x00000002 /* Test Pause */\r
-#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */\r
-\r
-/* MII Management Configuration Register */\r
-#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */\r
-#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */\r
-#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */\r
-#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */\r
-\r
-/* MII Management Command Register */\r
-#undef MCMD_READ /* Remove compiler warning. */\r
-#define MCMD_READ 0x00000001 /* MII Read */\r
-#undef MCMD_SCAN /* Remove compiler warning. */\r
-#define MCMD_SCAN 0x00000002 /* MII Scan continuously */\r
-\r
-#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */\r
-#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */\r
-\r
-/* MII Management Address Register */\r
-#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */\r
-#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */\r
-\r
-/* MII Management Indicators Register */\r
-#undef MIND_BUSY /* Remove compiler warning. */\r
-#define MIND_BUSY 0x00000001 /* MII is Busy */\r
-#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */\r
-#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */\r
-#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */\r
-\r
-/* Command Register */\r
-#define CR_RX_EN 0x00000001 /* Enable Receive */\r
-#define CR_TX_EN 0x00000002 /* Enable Transmit */\r
-#define CR_REG_RES 0x00000008 /* Reset Host Registers */\r
-#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */\r
-#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */\r
-#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */\r
-#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */\r
-#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */\r
-#define CR_RMII 0x00000200 /* Reduced MII Interface */\r
-#define CR_FULL_DUP 0x00000400 /* Full Duplex */\r
-\r
-/* Status Register */\r
-#define SR_RX_EN 0x00000001 /* Enable Receive */\r
-#define SR_TX_EN 0x00000002 /* Enable Transmit */\r
-\r
-/* Transmit Status Vector 0 Register */\r
-#define TSV0_CRC_ERR 0x00000001 /* CRC error */\r
-#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */\r
-#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */\r
-#define TSV0_DONE 0x00000008 /* Tramsmission Completed */\r
-#define TSV0_MCAST 0x00000010 /* Multicast Destination */\r
-#define TSV0_BCAST 0x00000020 /* Broadcast Destination */\r
-#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */\r
-#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */\r
-#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */\r
-#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */\r
-#define TSV0_GIANT 0x00000400 /* Giant Frame */\r
-#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */\r
-#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */\r
-#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */\r
-#define TSV0_PAUSE 0x20000000 /* Pause Frame */\r
-#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */\r
-#define TSV0_VLAN 0x80000000 /* VLAN Frame */\r
-\r
-/* Transmit Status Vector 1 Register */\r
-#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */\r
-#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */\r
-\r
-/* Receive Status Vector Register */\r
-#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */\r
-#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */\r
-#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */\r
-#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */\r
-#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */\r
-#define RSV_CRC_ERR 0x00100000 /* CRC Error */\r
-#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */\r
-#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */\r
-#define RSV_REC_OK 0x00800000 /* Frame Received OK */\r
-#define RSV_MCAST 0x01000000 /* Multicast Frame */\r
-#define RSV_BCAST 0x02000000 /* Broadcast Frame */\r
-#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */\r
-#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */\r
-#define RSV_PAUSE 0x10000000 /* Pause Frame */\r
-#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */\r
-#define RSV_VLAN 0x40000000 /* VLAN Frame */\r
-\r
-/* Flow Control Counter Register */\r
-#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */\r
-#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */\r
-\r
-/* Flow Control Status Register */\r
-#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */\r
-\r
-/* Receive Filter Control Register */\r
-#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */\r
-#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */\r
-#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */\r
-#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */\r
-#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/\r
-#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */\r
-#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */\r
-#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */\r
-\r
-/* Receive Filter WoL Status/Clear Registers */\r
-#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */\r
-#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */\r
-#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */\r
-#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */\r
-#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */\r
-#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */\r
-#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */\r
-#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */\r
-\r
-/* Interrupt Status/Enable/Clear/Set Registers */\r
-#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */\r
-#define INT_RX_ERR 0x00000002 /* Receive Error */\r
-#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */\r
-#define INT_RX_DONE 0x00000008 /* Receive Done */\r
-#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */\r
-#define INT_TX_ERR 0x00000020 /* Transmit Error */\r
-#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */\r
-#define INT_TX_DONE 0x00000080 /* Transmit Done */\r
-#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */\r
-#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */\r
-\r
-/* Power Down Register */\r
-#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */\r
-\r
-/* RX Descriptor Control Word */\r
-#define RCTRL_SIZE 0x000007FF /* Buffer size mask */\r
-#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */\r
-\r
-/* RX Status Hash CRC Word */\r
-#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */\r
-#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */\r
-\r
-/* RX Status Information Word */\r
-#define RINFO_SIZE 0x000007FF /* Data size in bytes */\r
-#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */\r
-#define RINFO_VLAN 0x00080000 /* VLAN Frame */\r
-#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */\r
-#define RINFO_MCAST 0x00200000 /* Multicast Frame */\r
-#define RINFO_BCAST 0x00400000 /* Broadcast Frame */\r
-#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */\r
-#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */\r
-#define RINFO_LEN_ERR 0x02000000 /* Length Error */\r
-#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */\r
-#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */\r
-#define RINFO_OVERRUN 0x10000000 /* Receive overrun */\r
-#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */\r
-#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */\r
-#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
-\r
-#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \\r
- RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
-\r
-/* TX Descriptor Control Word */\r
-#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */\r
-#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */\r
-#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */\r
-#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */\r
-#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */\r
-#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */\r
-#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */\r
-\r
-/* TX Status Information Word */\r
-#define TINFO_COL_CNT 0x01E00000 /* Collision Count */\r
-#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */\r
-#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */\r
-#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */\r
-#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */\r
-#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */\r
-#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */\r
-#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */\r
-\r
-/* DP83848C PHY Registers */\r
-#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */\r
-#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */\r
-#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */\r
-#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */\r
-#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */\r
-#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */\r
-#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */\r
-#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */\r
-\r
-/* PHY Extended Registers */\r
-#define PHY_REG_STS 0x10 /* Status Register */\r
-#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */\r
-#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */\r
-#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */\r
-#define PHY_REG_RECR 0x15 /* Receive Error Counter */\r
-#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */\r
-#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */\r
-#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */\r
-#define PHY_REG_PHYCR 0x19 /* PHY Control Register */\r
-#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */\r
-#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */\r
-#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */\r
-\r
-#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */\r
-#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */\r
-#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */\r
-#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */\r
-#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */\r
-\r
-#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */\r
-#define DP83848C_ID 0x20005C90 /* PHY Identifier */\r
-\r
-// prototypes\r
-portBASE_TYPE Init_EMAC(void);\r
-unsigned short ReadFrameBE_EMAC(void);\r
-void CopyToFrame_EMAC(void *Source, unsigned int Size);\r
-void CopyFromFrame_EMAC(void *Dest, unsigned short Size);\r
-void DummyReadFrame_EMAC(unsigned short Size);\r
-unsigned short StartReadFrame(void);\r
-void EndReadFrame(void);\r
-unsigned int CheckFrameReceived(void);\r
-void RequestSend(void);\r
-unsigned int Rdy4Tx(void);\r
-void DoSend_EMAC(unsigned short FrameSize);\r
-void vEMACWaitForInput( void );\r
-unsigned int uiGetEMACRxData( unsigned char *ucBuffer );\r
-\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
- * end of file\r
- *---------------------------------------------------------------------------*/\r
-\r