+/*-----------------------------------------------------------*/\r
+\r
+__asm unsigned long vPortGetIPSR( void )\r
+{\r
+ PRESERVE8\r
+ \r
+ mrs r0, ipsr\r
+ bx r14\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configASSERT_DEFINED == 1 )\r
+\r
+ void vPortValidateInterruptPriority( void )\r
+ {\r
+ unsigned long ulCurrentInterrupt;\r
+ unsigned char ucCurrentPriority;\r
+\r
+ /* Obtain the number of the currently executing interrupt. */\r
+ ulCurrentInterrupt = vPortGetIPSR();\r
+\r
+ /* Is the interrupt number a user defined interrupt? */\r
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
+ {\r
+ /* Look up the interrupt's priority. */\r
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
+\r
+ /* The following assertion will fail if a service routine (ISR) for \r
+ an interrupt that has been assigned a priority above\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
+ function. ISR safe FreeRTOS API functions must *only* be called \r
+ from interrupts that have been assigned a priority at or below\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ \r
+ Numerically low interrupt priority numbers represent logically high\r
+ interrupt priorities, therefore the priority of the interrupt must \r
+ be set to a value equal to or numerically *higher* than \r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
+ \r
+ Interrupts that use the FreeRTOS API must not be left at their\r
+ default priority of zero as that is the highest possible priority,\r
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
+ and therefore also guaranteed to be invalid. \r
+ \r
+ FreeRTOS maintains separate thread and ISR API functions to ensure \r
+ interrupt entry is as fast and simple as possible.\r
+ \r
+ The following links provide detailed information:\r
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
+ http://www.freertos.org/FAQHelp.html */\r
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
+ }\r
+\r
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits \r
+ that define each interrupt's priority to be split between bits that \r
+ define the interrupt's pre-emption priority bits and bits that define\r
+ the interrupt's sub-priority. For simplicity all bits must be defined \r
+ to be pre-emption priority bits. The following assertion will fail if\r
+ this is not the case (if some bits represent a sub-priority). \r
+ \r
+ If CMSIS libraries are being used then the correct setting can be \r
+ achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the \r
+ scheduler. */\r
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
+ }\r
+\r
+#endif /* configASSERT_DEFINED */\r
+\r
+\r