tcl/target: ti_tms570.cfg restructure dap support

ti_tms570 was probably omitted in commit
2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f

Change-Id: Idd4828fd5ea3641bda6c73c7f07a598c1e512ef6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4762
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg
index 21da6c017a0a8f32e9eb7cf9b261a457ecce1b6a..1c89b8ce51c176aa498c391086127488095dd3aa 100644 (file)
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti_tms570.cfg
@@ -20,8 +20,8 @@ source [find target/icepick.cfg]
 if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
 }
 if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
 }

-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"

 
 # ICEpick-C (JTAG route controller)
 # JRC_TAPID should be set before source-ing this file
 
 # ICEpick-C (JTAG route controller)
 # JRC_TAPID should be set before source-ing this file


@@ -50,16 +50,18 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
        -expected-id $_JRC_TAPID8 \
        -expected-id $_JRC_TAPID9 \
        -ignore-version
        -expected-id $_JRC_TAPID8 \
        -expected-id $_JRC_TAPID9 \
        -ignore-version

-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"

 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
 

+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+

 # Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
 # Cortex-R4 target
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \

-       -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
+       -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003

 
 # TMS570 uses quirky BE-32 mode
 
 # TMS570 uses quirky BE-32 mode

-$_TARGETNAME dap ti_be_32_quirks 1
+$_CHIPNAME.dap ti_be_32_quirks 1

 
 $_TARGETNAME configure -event gdb-attach {
        cortex_r4 dbginit
 
 $_TARGETNAME configure -event gdb-attach {
        cortex_r4 dbginit