+++ /dev/null
-/*\r
- FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section\r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- ***************************************************************************\r
- * *\r
- * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
- * and even write all or part of your application on your behalf. *\r
- * See http://www.OpenRTOS.com for details of the services we provide to *\r
- * expedite your project. *\r
- * *\r
- ***************************************************************************\r
- ***************************************************************************\r
-\r
- Please ensure to read the configuration and relevant port sections of the\r
- online documentation.\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
- licensing and training services.\r
-*/\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
- *----------------------------------------------------------*/\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 0\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 )\r
-#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 100000000 ) /* Clock setup from start.asm in the demo application. */\r
-#define configTICK_RATE_HZ ( (portTickType) 1000 )\r
-#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )\r
-#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) )\r
-#define configMAX_TASK_NAME_LEN ( 20 )\r
-#define configUSE_16_BIT_TICKS 1\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_MUTEXES 1\r
-#define configUSE_TRACE_FACILITY 0\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 4 )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 1\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vResumeFromISR 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-#define INCLUDE_xTaskGetSchedulerState 1\r
-#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
-#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
-\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
+++ /dev/null
-/*******************************************************************/\r
-/* */\r
-/* This file is automatically generated by linker script generator.*/\r
-/* */\r
-/* Version: Xilinx EDK 8.2.02EDK_Im_Sp2.4 */\r
-/* */\r
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-/* */\r
-/* Description : PowerPC405 Linker Script */\r
-/* */\r
-/*******************************************************************/\r
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-/* Define Memories in the system */\r
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-MEMORY\r
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-}\r
-\r
-/* Specify the default entry point to the program */\r
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-STARTUP(boot.o)\r
-\r
-/* Define the sections, and where they are mapped in memory */\r
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-{\r
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-\r
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-.stack : {\r
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-\r
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-\r
-}\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section\r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- ***************************************************************************\r
- * *\r
- * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
- * and even write all or part of your application on your behalf. *\r
- * See http://www.OpenRTOS.com for details of the services we provide to *\r
- * expedite your project. *\r
- * *\r
- ***************************************************************************\r
- ***************************************************************************\r
-\r
- Please ensure to read the configuration and relevant port sections of the\r
- online documentation.\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
- licensing and training services.\r
-*/\r
-\r
-/*\r
- * Creates all the demo application tasks, then starts the scheduler. The WEB\r
- * documentation provides more details of the demo application tasks.\r
- * \r
- * In addition to the standard demo tasks, the follow demo specific tasks are\r
- * create:\r
- *\r
- * The "Check" task. This only executes every three seconds but has the highest \r
- * priority so is guaranteed to get processor time. Its main function is to \r
- * check that all the other tasks are still operational. Most tasks maintain \r
- * a unique count that is incremented each time the task successfully completes \r
- * its function. Should any error occur within such a task the count is \r
- * permanently halted. The check task inspects the count of each task to ensure \r
- * it has changed since the last time the check task executed. If all the count \r
- * variables have changed all the tasks are still executing error free, and the \r
- * check task toggles the onboard LED. Should any task contain an error at any time \r
- * the LED toggle rate will change from 3 seconds to 500ms.\r
- *\r
- * The "Register Check" tasks. These tasks fill the CPU registers with known\r
- * values, then check that each register still contains the expected value, the\r
- * discovery of an unexpected value being indicative of an error in the RTOS\r
- * context switch mechanism. The register check tasks operate at low priority\r
- * so are switched in and out frequently.\r
- *\r
- */\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Xilinx library includes. */\r
-#include "xcache_l.h"\r
-#include "xintc.h"\r
-\r
-/* Demo application includes. */\r
-#include "flash.h"\r
-#include "integer.h"\r
-#include "comtest2.h"\r
-#include "semtest.h"\r
-#include "BlockQ.h"\r
-#include "dynamic.h"\r
-#include "flop.h"\r
-#include "GenQTest.h"\r
-#include "QPeek.h"\r
-#include "blocktim.h"\r
-#include "death.h"\r
-#include "partest.h"\r
-\r
-/* Priorities assigned to the demo tasks. */\r
-#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )\r
-#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
-#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY )\r
-\r
-/* The first LED used by the COM test and check tasks respectively. */\r
-#define mainCOM_TEST_LED ( 4 )\r
-#define mainCHECK_TEST_LED ( 3 )\r
-\r
-/* The baud rate used by the comtest tasks is set by the hardware, so the\r
-baud rate parameters passed into the comtest initialisation has no effect. */\r
-#define mainBAUD_SET_IN_HARDWARE ( 0 )\r
-\r
-/* Delay periods used by the check task. If no errors have been found then\r
-the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an\r
-error has been found at any time then the toggle rate will increase to \r
-mainERROR_CHECK_DELAY milliseconds. */\r
-#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )\r
-#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )\r
-\r
-\r
-/* \r
- * The tasks defined within this file - described within the comments at the\r
- * head of this page. \r
- */\r
-static void prvRegTestTask1( void *pvParameters );\r
-static void prvRegTestTask2( void *pvParameters );\r
-static void prvErrorChecks( void *pvParameters );\r
-\r
-/*\r
- * Called by the 'check' task to inspect all the standard demo tasks within\r
- * the system, as described within the comments at the head of this page.\r
- */\r
-static portSHORT prvCheckOtherTasksAreStillRunning( void );\r
-\r
-/*\r
- * Perform any hardware initialisation required by the demo application.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they\r
-discover an unexpected value. */\r
-static unsigned portBASE_TYPE xRegTestStatus = pdPASS;\r
-\r
-/* Counters used to ensure the regtest tasks are still running. */\r
-static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* Must be called prior to installing any interrupt handlers! */\r
- vPortSetupInterruptController();\r
-\r
- /* In this case prvSetupHardware() just enables the caches and and\r
- configures the IO ports for the LED outputs. */\r
- prvSetupHardware();\r
-\r
- /* Start the standard demo application tasks. Note that the baud rate used\r
- by the comtest tasks is set by the hardware, so the baud rate parameter\r
- passed has no effect. */\r
- vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); \r
- vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
- vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED );\r
- vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
- vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); \r
- vStartDynamicPriorityTasks(); \r
- vStartMathTasks( tskIDLE_PRIORITY ); \r
- vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY );\r
- vStartQueuePeekTasks();\r
- vCreateBlockTimeTasks();\r
-\r
- /* Create the tasks defined within this file. */\r
- xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
-\r
- /* The suicide tasks must be started last as they record the number of other\r
- tasks that exist within the system. The value is then used to ensure at run\r
- time the number of tasks that exists is within expected bounds. */\r
- vCreateSuicidalTasks( mainDEATH_PRIORITY );\r
-\r
- /* Now start the scheduler. Following this call the created tasks should\r
- be executing. */ \r
- vTaskStartScheduler( );\r
-\r
- /* vTaskStartScheduler() will only return if an error occurs while the \r
- idle task is being created. */\r
- for( ;; );\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static portSHORT prvCheckOtherTasksAreStillRunning( void )\r
-{\r
-portBASE_TYPE lReturn = pdPASS;\r
-static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL;\r
-\r
- /* The demo tasks maintain a count that increments every cycle of the task\r
- provided that the task has never encountered an error. This function \r
- checks the counts maintained by the tasks to ensure they are still being\r
- incremented. A count remaining at the same value between calls therefore\r
- indicates that an error has been detected. */\r
-\r
- if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
-\r
- if( xAreComTestTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xAreMathsTaskStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xIsCreateTaskStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- \r
- if ( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
-\r
- /* Have the register test tasks found any errors? */\r
- if( xRegTestStatus != pdPASS )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
-\r
- /* Are the register test tasks still looping? */\r
- if( ulLastRegTest1Counter == ulRegTest1Counter )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- else\r
- {\r
- ulLastRegTest1Counter = ulRegTest1Counter;\r
- }\r
-\r
- if( ulLastRegTest2Counter == ulRegTest2Counter )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
- else\r
- {\r
- ulLastRegTest2Counter = ulRegTest2Counter;\r
- }\r
-\r
- return lReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvErrorChecks( void *pvParameters )\r
-{\r
-portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;\r
-volatile unsigned portBASE_TYPE uxFreeStack;\r
-\r
- /* This call is just to demonstrate the use of the function - nothing is\r
- done with the value. You would expect the stack high water mark to be\r
- lower (the function to return a larger value) here at function entry than\r
- later following calls to other functions. */\r
- uxFreeStack = uxTaskGetStackHighWaterMark( NULL );\r
-\r
- /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
- works correctly. */\r
- xLastExecutionTime = xTaskGetTickCount();\r
-\r
- /* Cycle for ever, delaying then checking all the other tasks are still\r
- operating without error. */\r
- for( ;; )\r
- {\r
- /* Again just for demo purposes - uxFreeStack should have a lower value\r
- here than following the call to uxTaskGetStackHighWaterMark() on the\r
- task entry. */\r
- uxFreeStack = uxTaskGetStackHighWaterMark( NULL );\r
-\r
- /* Wait until it is time to check again. The time we wait here depends\r
- on whether an error has been detected or not. When an error is \r
- detected the time is shortened resulting in a faster LED flash rate. */\r
- vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod );\r
-\r
- /* See if the other tasks are all ok. */\r
- if( prvCheckOtherTasksAreStillRunning() != pdPASS )\r
- {\r
- /* An error occurred in one of the tasks so shorten the delay \r
- period - which has the effect of increasing the frequency of the\r
- LED toggle. */\r
- xDelayPeriod = mainERROR_CHECK_DELAY;\r
- }\r
-\r
- /* Flash! */\r
- vParTestToggleLED( mainCHECK_TEST_LED );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- XCache_EnableICache( 0x80000000 );\r
- XCache_EnableDCache( 0x80000000 );\r
-\r
- /* Setup the IO port for use with the LED outputs. */\r
- vParTestInitialise();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void prvRegTest1Pass( void )\r
-{\r
- /* Called from the inline assembler - this cannot be static\r
- otherwise it can get optimised away. */\r
- ulRegTest1Counter++;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void prvRegTest2Pass( void )\r
-{\r
- /* Called from the inline assembler - this cannot be static\r
- otherwise it can get optimised away. */\r
- ulRegTest2Counter++;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void prvRegTestFail( void )\r
-{\r
- /* Called from the inline assembler - this cannot be static\r
- otherwise it can get optimised away. */\r
- xRegTestStatus = pdFAIL;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRegTestTask1( void *pvParameters )\r
-{\r
- /* The first register test task as described at the top of this file. The\r
- values used in the registers are different to those use in the second \r
- register test task. Also, unlike the second register test task, this task\r
- yields between setting the register values and subsequently checking the\r
- register values. */\r
- asm volatile\r
- (\r
- "RegTest1Start: \n\t" \\r
- " \n\t" \\r
- " li 0, 301 \n\t" \\r
- " mtspr 256, 0 #USPRG0 \n\t" \\r
- " li 0, 501 \n\t" \\r
- " mtspr 8, 0 #LR \n\t" \\r
- " li 0, 4 \n\t" \\r
- " mtspr 1, 0 #XER \n\t" \\r
- " \n\t" \\r
- " li 0, 1 \n\t" \\r
- " li 2, 2 \n\t" \\r
- " li 3, 3 \n\t" \\r
- " li 4, 4 \n\t" \\r
- " li 5, 5 \n\t" \\r
- " li 6, 6 \n\t" \\r
- " li 7, 7 \n\t" \\r
- " li 8, 8 \n\t" \\r
- " li 9, 9 \n\t" \\r
- " li 10, 10 \n\t" \\r
- " li 11, 11 \n\t" \\r
- " li 12, 12 \n\t" \\r
- " li 13, 13 \n\t" \\r
- " li 14, 14 \n\t" \\r
- " li 15, 15 \n\t" \\r
- " li 16, 16 \n\t" \\r
- " li 17, 17 \n\t" \\r
- " li 18, 18 \n\t" \\r
- " li 19, 19 \n\t" \\r
- " li 20, 20 \n\t" \\r
- " li 21, 21 \n\t" \\r
- " li 22, 22 \n\t" \\r
- " li 23, 23 \n\t" \\r
- " li 24, 24 \n\t" \\r
- " li 25, 25 \n\t" \\r
- " li 26, 26 \n\t" \\r
- " li 27, 27 \n\t" \\r
- " li 28, 28 \n\t" \\r
- " li 29, 29 \n\t" \\r
- " li 30, 30 \n\t" \\r
- " li 31, 31 \n\t" \\r
- " \n\t" \\r
- " sc \n\t" \\r
- " nop \n\t" \\r
- " \n\t" \\r
- " cmpwi 0, 1 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 2, 2 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 3, 3 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 4, 4 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 5, 5 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 6, 6 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 7, 7 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 8, 8 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 9, 9 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 10, 10 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 11, 11 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 12, 12 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 13, 13 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 14, 14 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 15, 15 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 16, 16 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 17, 17 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 18, 18 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 19, 19 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 20, 20 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 21, 21 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 22, 22 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 23, 23 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 24, 24 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 25, 25 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 26, 26 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 27, 27 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 28, 28 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 29, 29 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 30, 30 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " cmpwi 31, 31 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " \n\t" \\r
- " mfspr 0, 256 #USPRG0 \n\t" \\r
- " cmpwi 0, 301 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " mfspr 0, 8 #LR \n\t" \\r
- " cmpwi 0, 501 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " mfspr 0, 1 #XER \n\t" \\r
- " cmpwi 0, 4 \n\t" \\r
- " bne RegTest1Fail \n\t" \\r
- " \n\t" \\r
- " bl prvRegTest1Pass \n\t" \\r
- " b RegTest1Start \n\t" \\r
- " \n\t" \\r
- "RegTest1Fail: \n\t" \\r
- " \n\t" \\r
- " \n\t" \\r
- " bl prvRegTestFail \n\t" \\r
- " b RegTest1Start \n\t" \\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvRegTestTask2( void *pvParameters )\r
-{\r
- /* The second register test task as described at the top of this file. \r
- Note that this task fills the registers with different values to the\r
- first register test task. */\r
- asm volatile\r
- (\r
- "RegTest2Start: \n\t" \\r
- " \n\t" \\r
- " li 0, 300 \n\t" \\r
- " mtspr 256, 0 #USPRG0 \n\t" \\r
- " li 0, 500 \n\t" \\r
- " mtspr 8, 0 #LR \n\t" \\r
- " li 0, 4 \n\t" \\r
- " mtspr 1, 0 #XER \n\t" \\r
- " \n\t" \\r
- " li 0, 11 \n\t" \\r
- " li 2, 12 \n\t" \\r
- " li 3, 13 \n\t" \\r
- " li 4, 14 \n\t" \\r
- " li 5, 15 \n\t" \\r
- " li 6, 16 \n\t" \\r
- " li 7, 17 \n\t" \\r
- " li 8, 18 \n\t" \\r
- " li 9, 19 \n\t" \\r
- " li 10, 110 \n\t" \\r
- " li 11, 111 \n\t" \\r
- " li 12, 112 \n\t" \\r
- " li 13, 113 \n\t" \\r
- " li 14, 114 \n\t" \\r
- " li 15, 115 \n\t" \\r
- " li 16, 116 \n\t" \\r
- " li 17, 117 \n\t" \\r
- " li 18, 118 \n\t" \\r
- " li 19, 119 \n\t" \\r
- " li 20, 120 \n\t" \\r
- " li 21, 121 \n\t" \\r
- " li 22, 122 \n\t" \\r
- " li 23, 123 \n\t" \\r
- " li 24, 124 \n\t" \\r
- " li 25, 125 \n\t" \\r
- " li 26, 126 \n\t" \\r
- " li 27, 127 \n\t" \\r
- " li 28, 128 \n\t" \\r
- " li 29, 129 \n\t" \\r
- " li 30, 130 \n\t" \\r
- " li 31, 131 \n\t" \\r
- " \n\t" \\r
- " cmpwi 0, 11 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 2, 12 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 3, 13 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 4, 14 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 5, 15 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 6, 16 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 7, 17 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 8, 18 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 9, 19 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 10, 110 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 11, 111 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 12, 112 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 13, 113 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 14, 114 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 15, 115 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 16, 116 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 17, 117 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 18, 118 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 19, 119 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 20, 120 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 21, 121 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 22, 122 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 23, 123 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 24, 124 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 25, 125 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 26, 126 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 27, 127 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 28, 128 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 29, 129 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 30, 130 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " cmpwi 31, 131 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " \n\t" \\r
- " mfspr 0, 256 #USPRG0 \n\t" \\r
- " cmpwi 0, 300 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " mfspr 0, 8 #LR \n\t" \\r
- " cmpwi 0, 500 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " mfspr 0, 1 #XER \n\t" \\r
- " cmpwi 0, 4 \n\t" \\r
- " bne RegTest2Fail \n\t" \\r
- " \n\t" \\r
- " bl prvRegTest2Pass \n\t" \\r
- " b RegTest2Start \n\t" \\r
- " \n\t" \\r
- "RegTest2Fail: \n\t" \\r
- " \n\t" \\r
- " \n\t" \\r
- " bl prvRegTestFail \n\t" \\r
- " b RegTest2Start \n\t" \\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* This hook function will get called if there is a suspected stack overflow.\r
-An overflow can cause the task name to be corrupted, in which case the task\r
-handle needs to be used to determine the offending task. */\r
-void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName );\r
-void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName )\r
-{\r
- /* The following three calls are simply to stop compiler warnings about the\r
- functions not being used - they are called from the inline assembly. */\r
- prvRegTest1Pass();\r
- prvRegTest2Pass();\r
- prvRegTestFail();\r
-\r
- for( ;; );\r
-}\r
-\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section\r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- ***************************************************************************\r
- * *\r
- * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
- * and even write all or part of your application on your behalf. *\r
- * See http://www.OpenRTOS.com for details of the services we provide to *\r
- * expedite your project. *\r
- * *\r
- ***************************************************************************\r
- ***************************************************************************\r
-\r
- Please ensure to read the configuration and relevant port sections of the\r
- online documentation.\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
- licensing and training services.\r
-*/\r
-\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-\r
-/* Demo application includes. */\r
-#include "partest.h"\r
-\r
-/* Library includes. */\r
-#include "xparameters.h"\r
-#include "xgpio_l.h"\r
-\r
-/* Misc hardware specific definitions. */\r
-#define partstALL_AS_OUTPUT 0x00\r
-#define partstCHANNEL_1 0x01\r
-#define partstMAX_4BIT_LED 0x03\r
-\r
-/* The outputs are split into two IO sections, these variables maintain the \r
-current value of either section. */\r
-static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit;\r
-\r
-/*-----------------------------------------------------------*/\r
-/*\r
- * Setup the IO for the LED outputs.\r
- */\r
-void vParTestInitialise( void )\r
-{\r
- /* Set both sets of LED's on the demo board to outputs. */\r
- XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
- XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT );\r
-\r
- /* Start with all outputs off. */\r
- uxCurrentOutput4Bit = 0;\r
- XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 );\r
- uxCurrentOutput5Bit = 0;\r
- XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
-{\r
-unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* Which IO section does the LED being set/cleared belong to? The\r
- 4 bit or 5 bit outputs? */\r
- if( uxLED <= partstMAX_4BIT_LED )\r
- {\r
- uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput4Bit;\r
- } \r
- else\r
- {\r
- uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput5Bit;\r
- uxLED -= partstMAX_4BIT_LED;\r
- }\r
-\r
- /* Setup the bit mask accordingly. */\r
- uxLED = 0x01 << uxLED;\r
-\r
- /* Maintain the current output value. */\r
- if( xValue )\r
- {\r
- *puxCurrentValue |= uxLED;\r
- }\r
- else\r
- {\r
- *puxCurrentValue &= ~uxLED;\r
- }\r
-\r
- /* Write the value to the port. */\r
- XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
-{\r
-unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* Which IO section does the LED being toggled belong to? The\r
- 4 bit or 5 bit outputs? */\r
- if( uxLED <= partstMAX_4BIT_LED )\r
- {\r
- uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput4Bit;\r
- } \r
- else\r
- {\r
- uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR;\r
- puxCurrentValue = &uxCurrentOutput5Bit;\r
- uxLED -= partstMAX_4BIT_LED;\r
- }\r
-\r
- /* Setup the bit mask accordingly. */\r
- uxLED = 0x01 << uxLED;\r
-\r
- /* Maintain the current output value. */\r
- if( *puxCurrentValue & uxLED )\r
- {\r
- *puxCurrentValue &= ~uxLED;\r
- }\r
- else\r
- {\r
- *puxCurrentValue |= uxLED;\r
- }\r
-\r
- /* Write the value to the port. */\r
- XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue );\r
- }\r
- portEXIT_CRITICAL();\r
-}\r
-\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
-\r
- This file is part of the FreeRTOS.org distribution.\r
-\r
- FreeRTOS.org is free software; you can redistribute it and/or modify\r
- it under the terms of the GNU General Public License as published by\r
- the Free Software Foundation; either version 2 of the License, or\r
- (at your option) any later version.\r
-\r
- FreeRTOS.org is distributed in the hope that it will be useful,\r
- but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- GNU General Public License for more details.\r
-\r
- You should have received a copy of the GNU General Public License\r
- along with FreeRTOS.org; if not, write to the Free Software\r
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
-\r
- A special exception to the GPL can be applied should you wish to distribute\r
- a combined work that includes FreeRTOS.org, without being obliged to provide\r
- the source code for any proprietary components. See the licensing section \r
- of http://www.FreeRTOS.org for full details of how and when the exception\r
- can be applied.\r
-\r
- ***************************************************************************\r
- ***************************************************************************\r
- * *\r
- * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
- * and even write all or part of your application on your behalf. *\r
- * See http://www.OpenRTOS.com for details of the services we provide to *\r
- * expedite your project. *\r
- * *\r
- ***************************************************************************\r
- ***************************************************************************\r
-\r
- Please ensure to read the configuration and relevant port sections of the\r
- online documentation.\r
-\r
- http://www.FreeRTOS.org - Documentation, latest information, license and \r
- contact details.\r
-\r
- http://www.SafeRTOS.com - A version that is certified for use in safety \r
- critical systems.\r
-\r
- http://www.OpenRTOS.com - Commercial support, development, porting, \r
- licensing and training services.\r
-*/\r
-\r
-\r
-/* \r
- BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART\r
-*/\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "queue.h"\r
-#include "task.h"\r
-\r
-/* Demo application includes. */\r
-#include "serial.h"\r
-\r
-/* Library includes. */\r
-#include "xparameters.h"\r
-#include "xuartlite.h"\r
-#include "xuartlite_l.h"\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Queues used to hold received characters, and characters waiting to be\r
-transmitted. */\r
-static xQueueHandle xRxedChars; \r
-static xQueueHandle xCharsForTx; \r
-\r
-/* Structure that maintains information on the UART being used. */\r
-static XUartLite xUART;\r
-\r
-/*\r
- * Sample UART interrupt handler. Note this is used to demonstrate the kernel\r
- * features and test the port - it is not intended to represent an efficient\r
- * implementation.\r
- */\r
-static void vSerialISR( XUartLite *pxUART );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
-{\r
- /* NOTE: The baud rate used by this driver is determined by the hardware\r
- parameterization of the UART Lite peripheral, and the baud value passed to\r
- this function has no effect. */\r
- ( void ) ulWantedBaud;\r
-\r
- /* Create the queues used to hold Rx and Tx characters. */\r
- xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
- xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );\r
-\r
- /* Only initialise the UART if the queues were created correctly. */\r
- if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) )\r
- {\r
-\r
- XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID );\r
- XUartLite_ResetFifos( &xUART );\r
- XUartLite_DisableInterrupt( &xUART );\r
-\r
- if( xPortInstallInterruptHandler( XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS )\r
- {\r
- /* xPortInstallInterruptHandler() could fail if \r
- vPortSetupInterruptController() has not been called prior to this \r
- function. */\r
- XUartLite_EnableInterrupt( &xUART );\r
- }\r
- }\r
- \r
- /* There is only one port so the handle is not used. */\r
- return ( xComPortHandle ) 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )\r
-{\r
- /* The port handle is not required as this driver only supports one UART. */\r
- ( void ) pxPort;\r
-\r
- /* Get the next character from the buffer. Return false if no characters\r
- are available, or arrive before xBlockTime expires. */\r
- if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )\r
- {\r
- return pdTRUE;\r
- }\r
- else\r
- {\r
- return pdFALSE;\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
-{\r
-portBASE_TYPE xReturn = pdTRUE;\r
-\r
- portENTER_CRITICAL();\r
- {\r
- /* If the UART FIFO is full we can block posting the new data on the\r
- Tx queue. */\r
- if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )\r
- {\r
- if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
- {\r
- xReturn = pdFAIL;\r
- }\r
- }\r
- /* Otherwise, if there is data already in the queue we should add the\r
- new data to the back of the queue to ensure the sequencing is \r
- maintained. */\r
- else if( uxQueueMessagesWaiting( xCharsForTx ) )\r
- {\r
- if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
- {\r
- xReturn = pdFAIL;\r
- } \r
- }\r
- /* If the UART FIFO is not full and there is no data already in the\r
- queue we can write directly to the FIFO without disrupting the \r
- sequence. */\r
- else\r
- {\r
- XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );\r
- }\r
- }\r
- portEXIT_CRITICAL();\r
-\r
- return xReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vSerialClose( xComPortHandle xPort )\r
-{\r
- /* Not supported as not required by the demo application. */\r
- ( void ) xPort;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void vSerialISR( XUartLite *pxUART )\r
-{\r
-unsigned portLONG ulISRStatus;\r
-portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE, lDidSomething;\r
-portCHAR cChar;\r
-\r
- do\r
- {\r
- lDidSomething = pdFALSE;\r
-\r
- ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );\r
-\r
- if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 )\r
- {\r
- /* A character is available - place it in the queue of received\r
- characters. This might wake a task that was blocked waiting for \r
- data. */\r
- cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );\r
- xTaskWokenByRx = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByRx );\r
- lDidSomething = pdTRUE;\r
- }\r
- \r
- if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )\r
- {\r
- /* There is space in the FIFO - if there are any characters queue for\r
- transmission they can be sent to the UART now. This might unblock a\r
- task that was waiting for space to become available on the Tx queue. */\r
- if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )\r
- {\r
- XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );\r
- lDidSomething = pdTRUE;\r
- } \r
- }\r
- } while( lDidSomething == pdTRUE );\r
-\r
- /* If we woke any tasks we may require a context switch. */\r
- if( xTaskWokenByTx || xTaskWokenByRx )\r
- {\r
- portYIELD_FROM_ISR();\r
- }\r
-}\r
-\r
-\r
-\r
+++ /dev/null
- -p virtex4\r
+++ /dev/null
- -p virtex4 -lang vhdl
-\r
+++ /dev/null
-ppc405_0\r
-RTOSDEMO_SOURCES = RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S \r
-RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h \r
-RTOSDEMO_CC = powerpc-eabi-gcc\r
-RTOSDEMO_CC_SIZE = powerpc-eabi-size\r
-RTOSDEMO_CC_OPT = -Os\r
-RTOSDEMO_CFLAGS = -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall\r
-RTOSDEMO_CC_SEARCH = # -B\r
-RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L\r
-RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include \r
-RTOSDEMO_LFLAGS = # -l\r
-RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo.ld\r
-RTOSDEMO_CC_DEBUG_FLAG = -g \r
-RTOSDEMO_CC_PROFILE_FLAG = # -pg\r
-RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi\r
-RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=\r
-RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=\r
-RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=\r
+++ /dev/null
- -p virtex4 -lang vhdl -s mti\r
+++ /dev/null
-guiSettings=FILTER=0;BUS_FLAT_VIEW=false;BUS_TREE_VIEW_HEADER=Name,Net,Direction,Range,Class,Sensitivity,Description,Frequency,Reset Polarity,IP Type,IP Version,IP Classification,Bus Connection,Mastership,Bus Standard,Address,Base Address,High Address,Size,Lock,ICache,DCache;BUS_TREE_VIEW_HEADER_MAP=0,15,16,17,18,19,20,21,12,13,14,1,2,4,5,3,7,8,9,10,11,6;BUS_TREE_VIEW_HIDDEN_SECTION=15,16,17,18,19,20,21,13,14,1,2,4,5,3,7,8,11,6;BUS_EXPANDED_NODE=RS232_Uart;BUS_TREE_VERTICAL_SCROLL=0;BUS_TREE_HORIZONTAL_SCROLL=0;\r
+++ /dev/null
- -p xc4vfx12ff668-10\r
+++ /dev/null
--device xc4vfx12ff668-10data/system.ucf7 0\r
+++ /dev/null
--device xc4vfx12ff668-10data/system.ucf 0\r
+++ /dev/null
-############################################################################\r
-## This system.ucf file is generated by Base System Builder based on the\r
-## settings in the selected Xilinx Board Definition file. Please add other\r
-## user constraints to this file based on customer design specifications.\r
-############################################################################\r
-\r
-Net sys_clk_pin LOC=AE14;\r
-Net sys_clk_pin IOSTANDARD = LVCMOS33;\r
-Net sys_rst_pin LOC=D6;\r
-Net sys_rst_pin PULLUP;\r
-## System level constraints\r
-Net sys_clk_pin TNM_NET = sys_clk_pin;\r
-TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;\r
-Net sys_rst_pin TIG;\r
-NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";\r
-NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";\r
-NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";\r
-TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;\r
-Net fpga_0_SRAM_CLOCK LOC=AF7;\r
-Net fpga_0_SRAM_CLOCK SLEW = FAST;\r
-Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_CLOCK DRIVE = 16;\r
-\r
-## IO Devices constraints\r
-\r
-#### Module RS232_Uart constraints\r
-\r
-Net fpga_0_RS232_Uart_RX_pin LOC=W2;\r
-Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;\r
-Net fpga_0_RS232_Uart_TX_pin LOC=W1;\r
-Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;\r
-\r
-#### Module LEDs_4Bit constraints\r
-\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;\r
-Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;\r
-\r
-#### Module LEDs_Positions constraints\r
-\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;\r
-Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;\r
-\r
-#### Module SRAM_256Kx32 constraints\r
-\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> LOC=Y1;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<29> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> LOC=Y2;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<28> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> LOC=AA1;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<27> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> LOC=AB1;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<26> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> LOC=AB2;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<25> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> LOC=AC1;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<24> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> LOC=AC2;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<23> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> LOC=AD1;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<22> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> LOC=AD2;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<21> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> LOC=AE3;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<20> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> LOC=AF3;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<19> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> LOC=W3;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<18> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> LOC=W6;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<17> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> LOC=W5;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<16> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> LOC=AA3;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<15> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> LOC=AA4;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<14> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> LOC=AB3;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<13> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> LOC=AB4;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<12> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> LOC=AC4;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<11> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> LOC=AB5;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<10> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> LOC=AC5;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_A_pin<9> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> LOC=Y6;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<3> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> LOC=Y5;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<2> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> LOC=Y4;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<1> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> LOC=Y3;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_BEN_pin<0> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_WEN_pin LOC=AB6;\r
-Net fpga_0_SRAM_256Kx32_Mem_WEN_pin IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_WEN_pin SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_WEN_pin DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> LOC=AD13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<31> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> LOC=AC13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<30> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> LOC=AC15;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<29> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> LOC=AC16;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<28> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> LOC=AA11;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<27> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> LOC=AA12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<26> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> LOC=AD14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<25> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> LOC=AC14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<24> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> LOC=AA13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<23> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> LOC=AB13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<22> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> LOC=AA15;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<21> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> LOC=AA16;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<20> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> LOC=AC11;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<19> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> LOC=AC12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<18> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> LOC=AB14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<17> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> LOC=AA14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<16> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> LOC=D12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<15> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> LOC=E13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<14> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> LOC=C16;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<13> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> LOC=D16;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<12> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> LOC=D11;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<11> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> LOC=C11;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<10> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> LOC=E14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<9> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> LOC=D15;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<8> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> LOC=D13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<7> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> LOC=D14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<6> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> LOC=F15;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<5> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> LOC=F16;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<4> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> LOC=F11;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<3> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> LOC=F12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<2> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> LOC=F13;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<1> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> LOC=F14;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_DQ_pin<0> DRIVE = 12;\r
-Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> LOC=AC6;\r
-Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_OEN_pin<0> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> LOC=V7;\r
-Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_CEN_pin<0> DRIVE = 8;\r
-Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin LOC=W4;\r
-Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33;\r
-Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin SLEW = FAST;\r
-Net fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin DRIVE = 8;\r
-\r
+++ /dev/null
--g CclkPin:PULLUP
--g TdoPin:PULLNONE
--g M1Pin:PULLDOWN
--g DonePin:PULLUP
--g DriveDone:No
--g StartUpClk:JTAGCLK
--g DONE_cycle:4
--g GTS_cycle:5
--g M0Pin:PULLUP
--g M2Pin:PULLUP
--g ProgPin:PULLUP
--g TckPin:PULLUP
--g TdiPin:PULLUP
--g TmsPin:PULLUP
--g DonePipe:No
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:NONE
-#-m
--g Persist:No
+++ /dev/null
-setMode -bscan\r
-setCable -p auto\r
-identify\r
-assignfile -p 3 -file implementation/download.bit\r
-program -p 3\r
-quit\r
+++ /dev/null
-FLOWTYPE = FPGA;
-###############################################################
-## Filename: fast_runtime.opt
-##
-## Option File For Xilinx FPGA Implementation Flow for Fast
-## Runtime.
-##
-## Version: 4.1.1
-###############################################################
-#
-# Options for Translator
-#
-# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
-#
-Program ngdbuild
--p <partname>; # Partname to use - picked from xflow commandline
--nt timestamp; # NGO File generation. Regenerate only when
- # source netlist is newer than existing
- # NGO file (default)
--bm <design>.bmm # Block RAM memory map file
-<userdesign>; # User design - pick from xflow command line
--uc <design>.ucf; # ucf constraints
-<design>.ngd; # Name of NGD file. Filebase same as design filebase
-End Program ngdbuild
-
-#
-# Options for Mapper
-#
-# Type "map -h <arch>" for a detailed list of map command line options
-#
-Program map
--o <design>_map.ncd; # Output Mapped ncd file
--pr b; # Pack internal FF/latches into IOBs
-#-fp <design>.mfp; # Floorplan file
-<inputdir><design>.ngd; # Input NGD file
-<inputdir><design>.pcf; # Physical constraints file
-END Program map
-
-#
-# Options for Post Map Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_map_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>_map.twr; # Output trace report file
--xml <design>_map.twx; # Output XML version of the timing report
-#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>_map.ncd; # Input mapped ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_map_trce
-
-#
-# Options for Place and Route
-#
-# Type "par -h" for a detailed list of par command line options
-#
-Program par
--w; # Overwrite existing placed and routed ncd
--ol high; # Overall effort level
-<inputdir><design>_map.ncd; # Input mapped NCD file
-<design>.ncd; # Output placed and routed NCD
-<inputdir><design>.pcf; # Input physical constraints file
-END Program par
-
-#
-# Options for Post Par Trace
-#
-# Type "trce -h" for a detailed list of trce command line options
-#
-Program post_par_trce
--e 3; # Produce error report limited to 3 items per constraint
-#-o <design>.twr; # Output trace report file
--xml <design>.twx; # Output XML version of the timing report
-#-tsi <design>.tsi; # Produce Timing Specification Interaction report
-<inputdir><design>.ncd; # Input placed and routed ncd
-<inputdir><design>.pcf; # Physical constraints file
-END Program post_par_trce
-
-
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp\r
-#################################################################\r
-\r
-# Name of the Microprocessor system\r
-# The hardware specification of the system is in file :\r
-# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs\r
-# The software specification of the system is in file :\r
-# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss\r
-\r
-include system_incl.make\r
-\r
-\r
-#################################################################\r
-# EXTERNAL TARGETS\r
-#################################################################\r
-all:\r
- @echo "Makefile to build a Microprocessor system :"\r
- @echo "Run make with any of the following targets"\r
- @echo " "\r
- @echo " netlist : Generates the netlist for the given MHS "\r
- @echo " bits : Runs Implementation tools to generate the bitstream"\r
- @echo " exporttopn:Export to ProjNav"\r
- @echo " "\r
- @echo " libs : Configures the sw libraries for this system"\r
- @echo " program : Compiles the program sources for all the processor instances"\r
- @echo " "\r
- @echo " init_bram: Initializes bitstream with BRAM data"\r
- @echo " ace : Generate ace file from bitstream and elf"\r
- @echo " download : Downloads the bitstream onto the board"\r
- @echo " "\r
- @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"\r
- @echo " simmodel : Generates HDL simulation models for chosen simulation mode"\r
- @echo " behavioral:Generates behavioral HDL models with BRAM initialization"\r
- @echo " structural:Generates structural simulation HDL models with BRAM initialization"\r
- @echo " timing : Generates timing simulation HDL models with BRAM initialization"\r
- @echo " vp : Generates virtual platform model"\r
- @echo " "\r
- @echo " netlistclean: Deletes netlist"\r
- @echo " bitsclean: Deletes bit, ncd, bmm files"\r
- @echo " hwclean : Deletes implementation dir"\r
- @echo " libsclean: Deletes sw libraries"\r
- @echo " programclean: Deletes compiled ELF files"\r
- @echo " swclean : Deletes sw libraries and ELF files"\r
- @echo " simclean : Deletes simulation dir"\r
- @echo " vpclean : Deletes virtualplatform dir"\r
- @echo " clean : Deletes all generated files/directories"\r
- @echo " "\r
- @echo " make <target> : (Default)"\r
- @echo " Creates a Microprocessor system using default initializations"\r
- @echo " specified for each processor in MSS file"\r
-\r
-\r
-bits: $(SYSTEM_BIT)\r
-\r
-ace: $(SYSTEM_ACE)\r
-\r
-netlist: $(POSTSYN_NETLIST)\r
-\r
-libs: $(LIBRARIES)\r
-\r
-program: $(ALL_USER_ELF_FILES)\r
-\r
-download: $(DOWNLOAD_BIT) dummy\r
- @echo "*********************************************"\r
- @echo "Downloading Bitstream onto the target board"\r
- @echo "*********************************************"\r
- impact -batch etc/download.cmd\r
-\r
-init_bram: $(DOWNLOAD_BIT)\r
-\r
-sim: $(DEFAULT_SIM_SCRIPT)\r
- cd simulation/behavioral; \\r
- $(SIM_CMD) &\r
-\r
-simmodel: $(DEFAULT_SIM_SCRIPT)\r
-\r
-behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-structural_model: $(STRUCTURAL_SIM_SCRIPT)\r
-\r
-vp: $(VPEXEC)\r
-\r
-clean: hwclean libsclean programclean simclean vpclean\r
- rm -f _impact.cmd\r
-\r
-hwclean: netlistclean bitsclean\r
- rm -rf implementation synthesis xst hdl\r
- rm -rf xst.srp $(SYSTEM).srp\r
-\r
-netlistclean:\r
- rm -f $(POSTSYN_NETLIST)\r
- rm -f $(BMM_FILE)\r
-\r
-bitsclean:\r
- rm -f $(SYSTEM_BIT)\r
- rm -f implementation/$(SYSTEM).ncd\r
- rm -f implementation/$(SYSTEM)_bd.bmm \r
-\r
-bitsclean:\r
-\r
-simclean: \r
- rm -rf simulation/behavioral\r
-\r
-swclean: libsclean programclean\r
- @echo ""\r
-\r
-libsclean: $(LIBSCLEAN_TARGETS)\r
-\r
-programclean: $(PROGRAMCLEAN_TARGETS)\r
-\r
-vpclean:\r
- rm -rf virtualplatform\r
-\r
-#################################################################\r
-# SOFTWARE PLATFORM FLOW\r
-#################################################################\r
-\r
-\r
-$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt\r
- @echo "*********************************************"\r
- @echo "Creating software libraries..."\r
- @echo "*********************************************"\r
- libgen $(LIBGEN_OPTIONS) $(MSSFILE)\r
-\r
-\r
-ppc405_0_libsclean:\r
- rm -rf ppc405_0/lib/\r
-\r
-#################################################################\r
-# SOFTWARE APPLICATION RTOSDEMO\r
-#################################################################\r
-\r
-RTOSDemo_program: $(RTOSDEMO_OUTPUT) \r
-\r
-$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \\r
- $(LIBRARIES) __xps/rtosdemo_compiler.opt\r
- @mkdir -p $(RTOSDEMO_OUTPUT_DIR) \r
- $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \\r
- $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \\r
- $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) \r
- $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) \r
- @echo ""\r
-\r
-RTOSDemo_programclean:\r
- rm -f $(RTOSDEMO_OUTPUT) \r
-\r
-#################################################################\r
-# BOOTLOOP ELF FILES\r
-#################################################################\r
-\r
-\r
-\r
-$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)\r
- @mkdir -p $(BOOTLOOP_DIR)\r
- cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)\r
-\r
-#################################################################\r
-# HARDWARE IMPLEMENTATION FLOW\r
-#################################################################\r
-\r
-\r
-$(BMM_FILE) \\r
-$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \\r
- $(CORE_STATE_DEVELOPMENT_FILES)\r
- @echo "****************************************************"\r
- @echo "Creating system netlist for hardware specification.."\r
- @echo "****************************************************"\r
- platgen $(PLATGEN_OPTIONS) $(MHSFILE)\r
-\r
-$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)\r
- @echo "Running synthesis..."\r
- bash -c "cd synthesis; ./synthesis.sh"\r
-\r
-$(SYSTEM_BIT): $(FPGA_IMP_DEPENDENCY)\r
- @echo "*********************************************"\r
- @echo "Running Xilinx Implementation tools.."\r
- @echo "*********************************************"\r
- @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf\r
- @cp -f $(XFLOW_OPT_FILE) implementation/xflow.opt\r
- xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc\r
- @echo "*********************************************"\r
- @echo "Running Bitgen.."\r
- @echo "*********************************************"\r
- @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut\r
- cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)\r
-\r
-exporttopn: \r
- @echo "You have chosen XPS for implementation tool flow."\r
- @echo "Please select ProjNav as your implementation flow in Project Options."\r
- @echo "In batch mode, use commad xset pnproj <nplfile>."\r
-\r
-$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt\r
- @cp -f implementation/$(SYSTEM)_bd.bmm .\r
- @echo "*********************************************"\r
- @echo "Initializing BRAM contents of the bitstream"\r
- @echo "*********************************************"\r
- bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \\r
- -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)\r
- @rm -f $(SYSTEM)_bd.bmm\r
-\r
-$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) \r
- @echo "*********************************************"\r
- @echo "Creating system ace file"\r
- @echo "*********************************************"\r
- xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE)\r
-\r
-#################################################################\r
-# SIMULATION FLOW\r
-#################################################################\r
-\r
-\r
-################## BEHAVIORAL SIMULATION ##################\r
-\r
-$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating behavioral simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)\r
-\r
-################## STRUCTURAL SIMULATION ##################\r
-\r
-$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating structural simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)\r
-\r
-\r
-################## TIMING SIMULATION ##################\r
-\r
-$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \\r
- $(BRAMINIT_ELF_FILES)\r
- @echo "*********************************************"\r
- @echo "Creating timing simulation models..."\r
- @echo "*********************************************"\r
- simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)\r
-\r
-#################################################################\r
-# VIRTUAL PLATFORM FLOW\r
-#################################################################\r
-\r
-\r
-$(VPEXEC): $(MHSFILE) __xps/vpgen.opt\r
- @echo "****************************************************"\r
- @echo "Creating virtual platform for hardware specification.."\r
- @echo "****************************************************"\r
- vpgen $(VPGEN_OPTIONS) $(MHSFILE)\r
-\r
-dummy:\r
- @echo ""\r
-\r
+++ /dev/null
-# \r
-# ##############################################################################\r
-# \r
-# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4\r
-# \r
-# Tue Mar 04 08:41:46 2008\r
-# \r
-# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1\r
-# Family: virtex4\r
-# Device: xc4vfx12\r
-# Package: ff668\r
-# Speed Grade: -10\r
-# \r
-# Processor: PPC 405\r
-# Processor clock frequency: 100.000000 MHz\r
-# Bus clock frequency: 100.000000 MHz\r
-# Debug interface: FPGA JTAG\r
-# Data Cache: 16 KB\r
-# Instruction Cache: 16 KB\r
-# On Chip Memory : 4 KB\r
-# Total Off Chip Memory : 1 MB\r
-# - SRAM_256Kx32 = 1 MB\r
-# \r
-# ##############################################################################\r
-\r
-\r
- PARAMETER VERSION = 2.1.0\r
-\r
-\r
- PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I\r
- PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O\r
- PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]\r
- PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]\r
- PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]\r
- PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]\r
- PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O\r
- PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]\r
- PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]\r
- PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]\r
- PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O\r
- PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O\r
- PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000\r
- PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST\r
-\r
-\r
-BEGIN ppc405_virtex4\r
- PARAMETER INSTANCE = ppc405_0\r
- PARAMETER HW_VER = 1.01.a\r
- BUS_INTERFACE JTAGPPC = jtagppc_0_0\r
- BUS_INTERFACE IPLB = plb\r
- BUS_INTERFACE DPLB = plb\r
- PORT PLBCLK = sys_clk_s\r
- PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ\r
- PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ\r
- PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ\r
- PORT RSTC405RESETCHIP = RSTC405RESETCHIP\r
- PORT RSTC405RESETCORE = RSTC405RESETCORE\r
- PORT RSTC405RESETSYS = RSTC405RESETSYS\r
- PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ\r
- PORT CPMC405CLOCK = sys_clk_s\r
-END\r
-\r
-BEGIN jtagppc_cntlr\r
- PARAMETER INSTANCE = jtagppc_0\r
- PARAMETER HW_VER = 2.00.a\r
- BUS_INTERFACE JTAGPPC0 = jtagppc_0_0\r
-END\r
-\r
-BEGIN proc_sys_reset\r
- PARAMETER INSTANCE = reset_block\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_EXT_RESET_HIGH = 0\r
- PORT Ext_Reset_In = sys_rst_s\r
- PORT Slowest_sync_clk = sys_clk_s\r
- PORT Chip_Reset_Req = C405RSTCHIPRESETREQ\r
- PORT Core_Reset_Req = C405RSTCORERESETREQ\r
- PORT System_Reset_Req = C405RSTSYSRESETREQ\r
- PORT Rstc405resetchip = RSTC405RESETCHIP\r
- PORT Rstc405resetcore = RSTC405RESETCORE\r
- PORT Rstc405resetsys = RSTC405RESETSYS\r
- PORT Bus_Struct_Reset = sys_bus_reset\r
- PORT Dcm_locked = dcm_0_lock\r
-END\r
-\r
-BEGIN plb_v34\r
- PARAMETER INSTANCE = plb\r
- PARAMETER HW_VER = 1.02.a\r
- PARAMETER C_DCR_INTFCE = 0\r
- PARAMETER C_EXT_RESET_HIGH = 1\r
- PORT SYS_Rst = sys_bus_reset\r
- PORT PLB_Clk = sys_clk_s\r
-END\r
-\r
-BEGIN opb_v20\r
- PARAMETER INSTANCE = opb\r
- PARAMETER HW_VER = 1.10.c\r
- PARAMETER C_EXT_RESET_HIGH = 1\r
- PORT SYS_Rst = sys_bus_reset\r
- PORT OPB_Clk = sys_clk_s\r
-END\r
-\r
-BEGIN plb2opb_bridge\r
- PARAMETER INSTANCE = plb2opb\r
- PARAMETER HW_VER = 1.01.a\r
- PARAMETER C_DCR_INTFCE = 0\r
- PARAMETER C_NUM_ADDR_RNG = 1\r
- PARAMETER C_RNG0_BASEADDR = 0x40000000\r
- PARAMETER C_RNG0_HIGHADDR = 0x7fffffff\r
- BUS_INTERFACE SPLB = plb\r
- BUS_INTERFACE MOPB = opb\r
-END\r
-\r
-BEGIN opb_uartlite\r
- PARAMETER INSTANCE = RS232_Uart\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER C_BAUDRATE = 115200\r
- PARAMETER C_DATA_BITS = 8\r
- PARAMETER C_ODD_PARITY = 0\r
- PARAMETER C_USE_PARITY = 0\r
- PARAMETER C_CLK_FREQ = 100000000\r
- PARAMETER C_BASEADDR = 0x40600000\r
- PARAMETER C_HIGHADDR = 0x4060ffff\r
- BUS_INTERFACE SOPB = opb\r
- PORT Interrupt = RS232_Uart_Interrupt\r
- PORT RX = fpga_0_RS232_Uart_RX\r
- PORT TX = fpga_0_RS232_Uart_TX\r
-END\r
-\r
-BEGIN opb_gpio\r
- PARAMETER INSTANCE = LEDs_4Bit\r
- PARAMETER HW_VER = 3.01.b\r
- PARAMETER C_GPIO_WIDTH = 4\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_IS_BIDIR = 1\r
- PARAMETER C_ALL_INPUTS = 0\r
- PARAMETER C_BASEADDR = 0x40000000\r
- PARAMETER C_HIGHADDR = 0x4000ffff\r
- BUS_INTERFACE SOPB = opb\r
- PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO\r
-END\r
-\r
-BEGIN opb_gpio\r
- PARAMETER INSTANCE = LEDs_Positions\r
- PARAMETER HW_VER = 3.01.b\r
- PARAMETER C_GPIO_WIDTH = 5\r
- PARAMETER C_IS_DUAL = 0\r
- PARAMETER C_IS_BIDIR = 1\r
- PARAMETER C_ALL_INPUTS = 0\r
- PARAMETER C_BASEADDR = 0x40020000\r
- PARAMETER C_HIGHADDR = 0x4002ffff\r
- BUS_INTERFACE SOPB = opb\r
- PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO\r
-END\r
-\r
-BEGIN plb_emc\r
- PARAMETER INSTANCE = SRAM_256Kx32\r
- PARAMETER HW_VER = 2.00.a\r
- PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1\r
- PARAMETER C_PLB_CLK_PERIOD_PS = 10000\r
- PARAMETER C_NUM_BANKS_MEM = 1\r
- PARAMETER C_MAX_MEM_WIDTH = 32\r
- PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1\r
- PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1\r
- PARAMETER C_MEM0_WIDTH = 32\r
- PARAMETER C_SYNCH_MEM_0 = 1\r
- PARAMETER C_TCEDV_PS_MEM_0 = 0\r
- PARAMETER C_TWC_PS_MEM_0 = 0\r
- PARAMETER C_TAVDV_PS_MEM_0 = 0\r
- PARAMETER C_TWP_PS_MEM_0 = 0\r
- PARAMETER C_THZCE_PS_MEM_0 = 0\r
- PARAMETER C_TLZWE_PS_MEM_0 = 0\r
- PARAMETER C_MEM0_BASEADDR = 0x00000000\r
- PARAMETER C_MEM0_HIGHADDR = 0x000fffff\r
- BUS_INTERFACE SPLB = plb\r
- PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split\r
- PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN\r
- PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN\r
- PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ\r
- PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN\r
- PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN\r
- PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN\r
-END\r
-\r
-BEGIN plb_bram_if_cntlr\r
- PARAMETER INSTANCE = plb_bram_if_cntlr_1\r
- PARAMETER HW_VER = 1.00.b\r
- PARAMETER c_include_burst_cacheln_support = 0\r
- PARAMETER c_plb_clk_period_ps = 10000\r
- PARAMETER c_baseaddr = 0xfffff000\r
- PARAMETER c_highaddr = 0xffffffff\r
- BUS_INTERFACE SPLB = plb\r
- BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port\r
-END\r
-\r
-BEGIN bram_block\r
- PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram\r
- PARAMETER HW_VER = 1.00.a\r
- BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port\r
-END\r
-\r
-BEGIN opb_intc\r
- PARAMETER INSTANCE = opb_intc_0\r
- PARAMETER HW_VER = 1.00.c\r
- PARAMETER C_BASEADDR = 0x41200000\r
- PARAMETER C_HIGHADDR = 0x4120ffff\r
- BUS_INTERFACE SOPB = opb\r
- PORT Irq = EICC405EXTINPUTIRQ\r
- PORT Intr = RS232_Uart_Interrupt\r
-END\r
-\r
-BEGIN util_bus_split\r
- PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_0\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_SIZE_IN = 32\r
- PARAMETER C_LEFT_POS = 9\r
- PARAMETER C_SPLIT = 30\r
- PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split\r
- PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A\r
-END\r
-\r
-BEGIN dcm_module\r
- PARAMETER INSTANCE = dcm_0\r
- PARAMETER HW_VER = 1.00.a\r
- PARAMETER C_CLK0_BUF = TRUE\r
- PARAMETER C_CLKIN_PERIOD = 10.000000\r
- PARAMETER C_CLK_FEEDBACK = 1X\r
- PARAMETER C_DLL_FREQUENCY_MODE = LOW\r
- PARAMETER C_EXT_RESET_HIGH = 1\r
- PORT CLKIN = dcm_clk_s\r
- PORT CLK0 = sys_clk_s\r
- PORT CLKFB = sys_clk_s\r
- PORT RST = net_gnd\r
- PORT LOCKED = dcm_0_lock\r
-END\r
-\r
+++ /dev/null
-\r
- PARAMETER VERSION = 2.2.0\r
-\r
-\r
-BEGIN OS\r
- PARAMETER OS_NAME = standalone\r
- PARAMETER OS_VER = 1.00.a\r
- PARAMETER PROC_INSTANCE = ppc405_0\r
-END\r
-\r
-\r
-BEGIN PROCESSOR\r
- PARAMETER DRIVER_NAME = cpu_ppc405\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = ppc405_0\r
- PARAMETER COMPILER = powerpc-eabi-gcc\r
- PARAMETER ARCHIVER = powerpc-eabi-ar\r
- PARAMETER CORE_CLOCK_FREQ_HZ = 100000000\r
-END\r
-\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = generic\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = jtagppc_0\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = plbarb\r
- PARAMETER DRIVER_VER = 1.01.a\r
- PARAMETER HW_INSTANCE = plb\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = opbarb\r
- PARAMETER DRIVER_VER = 1.02.a\r
- PARAMETER HW_INSTANCE = opb\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = plb2opb\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = plb2opb\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = uartlite\r
- PARAMETER DRIVER_VER = 1.01.a\r
- PARAMETER HW_INSTANCE = RS232_Uart\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 2.01.a\r
- PARAMETER HW_INSTANCE = LEDs_4Bit\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = gpio\r
- PARAMETER DRIVER_VER = 2.01.a\r
- PARAMETER HW_INSTANCE = LEDs_Positions\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = emc\r
- PARAMETER DRIVER_VER = 2.00.a\r
- PARAMETER HW_INSTANCE = SRAM_256Kx32\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = bram\r
- PARAMETER DRIVER_VER = 1.00.a\r
- PARAMETER HW_INSTANCE = plb_bram_if_cntlr_1\r
-END\r
-\r
-BEGIN DRIVER\r
- PARAMETER DRIVER_NAME = intc\r
- PARAMETER DRIVER_VER = 1.00.c\r
- PARAMETER HW_INSTANCE = opb_intc_0\r
-END\r
-\r
-\r
+++ /dev/null
-#Please do not modify this file by hand\r
-XmpVersion: 8.2.02\r
-IntStyle: default\r
-MHS File: system.mhs\r
-MSS File: system.mss\r
-NPL File: projnav/system.ise\r
-Architecture: virtex4\r
-Device: xc4vfx12\r
-Package: ff668\r
-SpeedGrade: -10\r
-UseProjNav: 0\r
-PNImportBitFile: \r
-PNImportBmmFile: \r
-UserCmd1: \r
-UserCmd1Type: 0\r
-UserCmd2: \r
-UserCmd2Type: 0\r
-TopInst: system_i\r
-ReloadPbde: 0\r
-MainMhsEditor: 0\r
-InsertNoPads: 0\r
-WarnForEAArch: 1\r
-HdlLang: VHDL\r
-Simulator: mti\r
-SimModel: BEHAVIORAL\r
-SimXLib: \r
-SimEdkLib: \r
-MixLangSim: 1\r
-UcfFile: data/system.ucf\r
-FpgaImpMode: 0\r
-ShowLicenseDialog: 1\r
-ICacheAddr: SRAM_256Kx32,C_MEM0_BASEADDR\r
-DCacheAddr: SRAM_256Kx32,C_MEM0_BASEADDR\r
-Processor: ppc405_0\r
-BootLoop: 0\r
-XmdStub: 0\r
-SwProj: RTOSDemo\r
-Processor: ppc405_0\r
-Executable: RTOSDemo/executable.elf\r
-Source: RTOSDemo/main.c\r
-Source: RTOSDemo/serial/serial.c\r
-Source: RTOSDemo/partest/partest.c\r
-Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c\r
-Source: RTOSDemo/../../../Source/tasks.c\r
-Source: RTOSDemo/../../../Source/list.c\r
-Source: RTOSDemo/../../../Source/queue.c\r
-Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c\r
-Source: RTOSDemo/../../Common/Minimal/flash.c\r
-Source: RTOSDemo/../../Common/Minimal/blocktim.c\r
-Source: RTOSDemo/../../Common/Minimal/dynamic.c\r
-Source: RTOSDemo/../../Common/Minimal/flop.c\r
-Source: RTOSDemo/../../Common/Minimal/GenQTest.c\r
-Source: RTOSDemo/../../Common/Minimal/integer.c\r
-Source: RTOSDemo/../../Common/Minimal/QPeek.c\r
-Source: RTOSDemo/../../Common/Minimal/semtest.c\r
-Source: RTOSDemo/../../Common/Minimal/BlockQ.c\r
-Source: RTOSDemo/../../Common/Minimal/death.c\r
-Source: RTOSDemo/../../Common/Minimal/comtest.c\r
-Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S\r
-Header: RTOSDemo/FreeRTOSConfig.h\r
-DefaultInit: EXECUTABLE\r
-InitBram: 0\r
-Active: 1\r
-CompilerOptLevel: 4\r
-GlobPtrOpt: 0\r
-DebugSym: 1\r
-ProfileFlag: 0\r
-SearchIncl: . ./RTOSDemo/ ../Common/include/ ../../Source/include/ ./ppc405_0/include/ ./ppc405_0/include\r
-ProgStart: \r
-StackSize: \r
-HeapSize: \r
-LinkerScript: RTOSDemo/RTOSDemo.ld\r
-ProgCCFlags: -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall\r
-CompileInXps: 1\r
-NonXpsApp: 0\r
+++ /dev/null
-#################################################################\r
-# Makefile generated by Xilinx Platform Studio \r
-# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp\r
-#################################################################\r
-\r
-XILINX_EDK_DIR = C:/devtools/XilinxEDK\r
-\r
-SYSTEM = system\r
-\r
-MHSFILE = system.mhs\r
-\r
-MSSFILE = system.mss\r
-\r
-FPGA_ARCH = virtex4\r
-\r
-DEVICE = xc4vfx12ff668-10\r
-\r
-LANGUAGE = vhdl\r
-\r
-SEARCHPATHOPT = \r
-\r
-SUBMODULE_OPT = \r
-\r
-PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT)\r
-\r
-LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT)\r
-\r
-VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT)\r
-\r
-RTOSDEMO_OUTPUT_DIR = RTOSDemo\r
-RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf\r
-\r
-MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf\r
-PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf\r
-PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf\r
-BOOTLOOP_DIR = bootloops\r
-\r
-PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf\r
-\r
-BRAMINIT_ELF_FILES = \r
-BRAMINIT_ELF_FILE_ARGS = \r
-\r
-ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) \r
-\r
-SIM_CMD = vsim\r
-\r
-BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM).do\r
-\r
-STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM).do\r
-\r
-TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM).do\r
-\r
-DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)\r
-\r
-MIX_LANG_SIM_OPT = -mixed yes\r
-\r
-SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti\r
-\r
-\r
-LIBRARIES = \\r
- ppc405_0/lib/libxil.a \r
-VPEXEC = virtualplatform/vpexec.exe\r
-\r
-LIBSCLEAN_TARGETS = ppc405_0_libsclean \r
-\r
-PROGRAMCLEAN_TARGETS = RTOSDemo_programclean \r
-\r
-CORE_STATE_DEVELOPMENT_FILES = \r
-\r
-WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \
-implementation/jtagppc_0_wrapper.ngc \
-implementation/reset_block_wrapper.ngc \
-implementation/plb_wrapper.ngc \
-implementation/opb_wrapper.ngc \
-implementation/plb2opb_wrapper.ngc \
-implementation/rs232_uart_wrapper.ngc \
-implementation/leds_4bit_wrapper.ngc \
-implementation/leds_positions_wrapper.ngc \
-implementation/sram_256kx32_wrapper.ngc \
-implementation/plb_bram_if_cntlr_1_wrapper.ngc \
-implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc \
-implementation/opb_intc_0_wrapper.ngc \
-implementation/sram_256kx32_util_bus_split_0_wrapper.ngc \
-implementation/dcm_0_wrapper.ngc\r
-\r
-POSTSYN_NETLIST = implementation/$(SYSTEM).ngc\r
-\r
-SYSTEM_BIT = implementation/$(SYSTEM).bit\r
-\r
-DOWNLOAD_BIT = implementation/download.bit\r
-\r
-SYSTEM_ACE = implementation/$(SYSTEM).ace\r
-\r
-UCF_FILE = data/system.ucf\r
-\r
-BMM_FILE = implementation/$(SYSTEM).bmm\r
-\r
-BITGEN_UT_FILE = etc/bitgen.ut\r
-\r
-XFLOW_OPT_FILE = etc/fast_runtime.opt\r
-XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)\r
-\r
-XPLORER_DEPENDENCY = __xps/xplorer.opt\r
-XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7\r
-\r
-FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY)\r
-\r
-#################################################################\r
-# SOFTWARE APPLICATION RTOSDEMO\r
-#################################################################\r
-\r
-RTOSDEMO_SOURCES = RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flop.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S \r
-\r
-RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h \r
-\r
-RTOSDEMO_CC = powerpc-eabi-gcc\r
-RTOSDEMO_CC_SIZE = powerpc-eabi-size\r
-RTOSDEMO_CC_OPT = -Os\r
-RTOSDEMO_CFLAGS = -D GCC_PPC405 -mregnames -Xlinker -Map=rtosdemo.map -Wall\r
-RTOSDEMO_CC_SEARCH = # -B\r
-RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L\r
-RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include \r
-RTOSDEMO_LFLAGS = # -l\r
-RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo.ld\r
-RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) \r
-RTOSDEMO_CC_DEBUG_FLAG = -g \r
-RTOSDEMO_CC_PROFILE_FLAG = # -pg\r
-RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi\r
-RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR=\r
-RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE=\r
-RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE=\r
-RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \\r
- $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \\r
- $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG) \r
projects / freertos / commitdiff