ARM: rename ARMV4_5_MODE_* as ARM_MODE_*

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 558ed94865fc780b2825fb616608c2a5b33cac4e..3991c0fb8f9d835c2729b8d5cfa0cfba7bf593fc 100644 (file)
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -137,7 +137,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 
        /* set up algorithm and parameters */
        algo.common_magic = ARMV4_5_COMMON_MAGIC;
-       algo.core_mode = ARMV4_5_MODE_SVC;
+       algo.core_mode = ARM_MODE_SVC;
        algo.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
@@ -213,7 +213,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 
        /* set up algorithm and parameters */
        algo.common_magic = ARMV4_5_COMMON_MAGIC;
-       algo.core_mode = ARMV4_5_MODE_SVC;
+       algo.core_mode = ARM_MODE_SVC;
        algo.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);

diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index c223ec470169acd348f560cd6fba1b9a005876b5..69c8274a0c0b3a6375a8cf994ff01111d0cc9871 100644 (file)
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -242,7 +242,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
        }
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);

diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 991110b8e8ca73efbfa5b94d648c56e7ac911738..16ba9996c326ba3455bd5a7a2364ee2d968b4da3 100644 (file)
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1086,7 +1086,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
        cfi_intel_clear_status_register(bank);
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        /* If we are setting up the write_algorith, we need target_code_src */
@@ -1409,7 +1409,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
        };
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        int target_code_size;

diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index 41b06b3ca446db723d46e4328f9581a66a540708..2524ae7f24c2eb4ee05386e538993541a979778d 100644 (file)
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -211,7 +211,7 @@ static int runCode(struct ecosflash_flash_bank *info,
        struct reg_param reg_params[3];
        struct armv4_5_algorithm armv4_5_info;
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);

diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 2b1e67177ebe755e9a9188d754984884b0236ef1..c14df1f879903a311df01203c50a70baaa43131e 100644 (file)
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -293,7 +293,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
                case lpc2000_v1:
                case lpc2000_v2:
                        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-                       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+                       armv4_5_info.core_mode = ARM_MODE_SVC;
                        armv4_5_info.core_state = ARM_STATE_ARM;
                        iap_entry_point = 0x7ffffff1;
                        break;

diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index 8dc06d1cf5dd5eacafc7235d523cddaf452948a3..aec8bcd6728b4391ddfff623cd6ee80090388d11 100644 (file)
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -1424,7 +1424,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
 
                        /* Execute algorithm, assume breakpoint for last instruction */
                        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-                       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+                       armv4_5_info.core_mode = ARM_MODE_SVC;
                        armv4_5_info.core_state = ARM_STATE_ARM;
 
                        retval = target_run_algorithm(target, 0, NULL, 5, reg_params,

diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index ea584a507a2f417bae8d153f6fc4bd5e635468a8..5767b9300219f1a955850f2c866e1c0de82d50f1 100644 (file)
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -372,7 +372,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
        }
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);

diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 21760f33fc9fc48586351f0284c3360e1b590492..60367cb9d71d48ccedf26b23bc7d0458d34ea46d 100644 (file)
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -409,7 +409,7 @@ static int str9x_write_block(struct flash_bank *bank,
        }
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 4d81189e4c58d7f268ea0e372023a18d0d18744e..928923dfbe1c81d3239a946d53b897b137b60a06 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1622,10 +1622,10 @@ int arm7_9_restore_context(struct target *target)
                                {
                                        dirty = 1;
                                        LOG_DEBUG("examining dirty reg: %s", reg->name);
-                                       if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
+                                       if ((reg_arch_info->mode != ARM_MODE_ANY)
                                                && (reg_arch_info->mode != current_mode)
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
-                                               && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
+                                               && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS))
+                                               && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR)))
                                        {
                                                mode_change = 1;
                                                LOG_DEBUG("require mode change");
@@ -1684,7 +1684,7 @@ int arm7_9_restore_context(struct target *target)
 
                        reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
                        reg_arch_info = reg->arch_info;
-                       if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
+                       if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
                        {
                                LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -2107,9 +2107,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))
+                       && (areg->mode != ARM_MODE_ANY))
        {
                uint32_t tmp_cpsr;
 
@@ -2132,7 +2132,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
-               arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
+               arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
        }
 
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2144,9 +2144,9 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        r->dirty = 0;
        buf_set_u32(r->value, 0, 32, value);
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2169,9 +2169,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_INVALID_ARGUMENTS;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
@@ -2193,7 +2193,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
-               int spsr = (areg->mode != ARMV4_5_MODE_ANY);
+               int spsr = (areg->mode != ARM_MODE_ANY);
 
                /* if we're writing the CPSR, mask the T bit */
                if (!spsr)
@@ -2205,9 +2205,9 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        r->valid = 1;
        r->dirty = 0;
 
-       if ((mode != ARMV4_5_MODE_ANY)
+       if ((mode != ARM_MODE_ANY)
                        && (mode != armv4_5->core_mode)
-                       && (areg->mode != ARMV4_5_MODE_ANY))    {
+                       && (areg->mode != ARM_MODE_ANY))        {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
                                buf_get_u32(armv4_5->cpsr->value, 0, 8)
@@ -2383,7 +2383,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2571,7 +2571,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT))
        {
                LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
@@ -2697,7 +2697,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
        struct reg_param reg_params[1];
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index df9bd958f8772ccdfdfce29ab93d8112c6f67b86..7cc48abfc36635ae13043950db086745f94b58fa 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -108,7 +108,7 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
        uint32_t cpsr;
 
        /* restore previous mode */
-       if (mode == ARMV4_5_MODE_ANY)
+       if (mode == ARM_MODE_ANY)
                cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 
        /* else force to the specified mode */
@@ -348,7 +348,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
         * actually find anything to do...
         */
        do {
-               enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+               enum armv4_5_mode mode = ARM_MODE_ANY;
 
                did_write = false;
 
@@ -382,10 +382,10 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                                         * we "know" core mode is accurate
                                         * since we haven't changed it yet
                                         */
-                                       if (arm->core_mode == ARMV4_5_MODE_FIQ
-                                                       && ARMV4_5_MODE_ANY
+                                       if (arm->core_mode == ARM_MODE_FIQ
+                                                       && ARM_MODE_ANY
                                                                != mode)
-                                               tmode = ARMV4_5_MODE_USR;
+                                               tmode = ARM_MODE_USR;
                                        break;
                                case 16:
                                        /* SPSR */
@@ -394,7 +394,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
                                }
 
                                /* REVISIT error checks */
-                               if (tmode != ARMV4_5_MODE_ANY)
+                               if (tmode != ARM_MODE_ANY)
                                        retval = dpm_modeswitch(dpm, tmode);
                        }
                        if (r->mode != mode)
@@ -412,7 +412,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
         * or it's dirty.  Must write PC to ensure the return address is
         * defined, and must not write it before CPSR.
         */
-       retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+       retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
        arm->cpsr->dirty = false;
 
        retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
@@ -427,7 +427,7 @@ done:
        return retval;
 }
 
-/* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
+/* Returns ARM_MODE_ANY or temporary mode to use while reading the
  * specified register ... works around flakiness from ARM core calls.
  * Caller already filtered out SPSR access; mode is never MODE_SYS
  * or MODE_ANY.
@@ -438,10 +438,10 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
        enum armv4_5_mode amode = arm->core_mode;
 
        /* don't switch if the mode is already correct */
-       if (amode == ARMV4_5_MODE_SYS)
-                amode = ARMV4_5_MODE_USR;
+       if (amode == ARM_MODE_SYS)
+                amode = ARM_MODE_USR;
        if (mode == amode)
-               return ARMV4_5_MODE_ANY;
+               return ARM_MODE_ANY;
 
        switch (num) {
        /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
@@ -451,7 +451,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
                break;
        /* r8..r12 aren't shadowed for anything except FIQ */
        case 8 ... 12:
-               if (mode == ARMV4_5_MODE_FIQ)
+               if (mode == ARM_MODE_FIQ)
                        return mode;
                break;
        /* r13/sp, and r14/lr are always shadowed */
@@ -462,7 +462,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
                LOG_WARNING("invalid register #%u", num);
                break;
        }
-       return ARMV4_5_MODE_ANY;
+       return ARM_MODE_ANY;
 }
 
 
@@ -482,7 +482,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
                return ERROR_INVALID_ARGUMENTS;
 
        if (regnum == 16) {
-               if (mode != ARMV4_5_MODE_ANY)
+               if (mode != ARM_MODE_ANY)
                        regnum = 17;
        } else
                mode = dpm_mapmode(dpm->arm, regnum, mode);
@@ -495,7 +495,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
        if (retval != ERROR_OK)
                return retval;
 
-       if (mode != ARMV4_5_MODE_ANY) {
+       if (mode != ARM_MODE_ANY) {
                retval = dpm_modeswitch(dpm, mode);
                if (retval != ERROR_OK)
                        goto fail;
@@ -504,8 +504,8 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
        retval = dpm_read_reg(dpm, r, regnum);
        /* always clean up, regardless of error */
 
-       if (mode != ARMV4_5_MODE_ANY)
-               /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+       if (mode != ARM_MODE_ANY)
+               /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 
 fail:
        /* (void) */ dpm->finish(dpm);
@@ -523,7 +523,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
                return ERROR_INVALID_ARGUMENTS;
 
        if (regnum == 16) {
-               if (mode != ARMV4_5_MODE_ANY)
+               if (mode != ARM_MODE_ANY)
                        regnum = 17;
        } else
                mode = dpm_mapmode(dpm->arm, regnum, mode);
@@ -536,7 +536,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
        if (retval != ERROR_OK)
                return retval;
 
-       if (mode != ARMV4_5_MODE_ANY) {
+       if (mode != ARM_MODE_ANY) {
                retval = dpm_modeswitch(dpm, mode);
                if (retval != ERROR_OK)
                        goto fail;
@@ -545,8 +545,8 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
        retval = dpm_write_reg(dpm, r, regnum);
        /* always clean up, regardless of error */
 
-       if (mode != ARMV4_5_MODE_ANY)
-               /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+       if (mode != ARM_MODE_ANY)
+               /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 
 fail:
        /* (void) */ dpm->finish(dpm);
@@ -566,7 +566,7 @@ static int arm_dpm_full_context(struct target *target)
                goto done;
 
        do {
-               enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
+               enum armv4_5_mode mode = ARM_MODE_ANY;
 
                did_read = false;
 
@@ -593,8 +593,8 @@ static int arm_dpm_full_context(struct target *target)
                                /* For R8..R12 when we've entered debug
                                 * state in FIQ mode... patch mode.
                                 */
-                               if (mode == ARMV4_5_MODE_ANY)
-                                       mode = ARMV4_5_MODE_USR;
+                               if (mode == ARM_MODE_ANY)
+                                       mode = ARM_MODE_USR;
 
                                /* REVISIT error checks */
                                retval = dpm_modeswitch(dpm, mode);
@@ -611,7 +611,7 @@ static int arm_dpm_full_context(struct target *target)
 
        } while (did_read);
 
-       retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
+       retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
        /* (void) */ dpm->finish(dpm);
 done:
        return retval;

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index f4e91993ee8d6363cd2dddcd3b2c62a84777af81..dd6a669597ca827587198de181fa6f17098d42ea 100644 (file)
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -46,7 +46,7 @@ static int do_semihosting(struct target *target)
        struct arm *armv4_5 = target_to_armv4_5(target);
        uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
        uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
-       uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARMV4_5_MODE_SVC, 14).value, 0, 32);
+       uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
        uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
        uint8_t params[16];
        int retval, result;
@@ -410,7 +410,7 @@ int arm_semihosting(struct target *target, int *retval)
        uint32_t lr, spsr;
        struct reg *r;
 
-       if (!arm->is_semihosting || arm->core_mode != ARMV4_5_MODE_SVC)
+       if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
                return 0;
 
        /* Check for PC == 8:  Supervisor Call vector

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index a1ed54c7fc1c7d1b5367d16b4e8931453d809c02..326240bfd15c8c3ecd6a88ecbff4f5104d76f063 100644 (file)
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -673,7 +673,7 @@ int arm_simulate_step_core(struct target *target,
                                if (instruction.info.load_store_multiple.register_list & 0x8000)
                                        update_cpsr = 1;
                                else
-                                       mode = ARMV4_5_MODE_USR;
+                                       mode = ARM_MODE_USR;
                        }
 
                        for (i = 0; i < 16; i++)
@@ -731,7 +731,7 @@ int arm_simulate_step_core(struct target *target,
 
                        if (instruction.info.load_store_multiple.S)
                        {
-                               mode = ARMV4_5_MODE_USR;
+                               mode = ARM_MODE_USR;
                        }
 
                        switch (instruction.info.load_store_multiple.addressing_mode)

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index a893e113d1518bf74f0b126893ac71658133bff5..1a9237499f24715b4b644174bc2ce026e263974d 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -89,43 +89,43 @@ static const struct {
         */
        {
                .name = "User",
-               .psr = ARMV4_5_MODE_USR,
+               .psr = ARM_MODE_USR,
                .n_indices = ARRAY_SIZE(arm_usr_indices),
                .indices = arm_usr_indices,
        },
        {
                .name = "FIQ",
-               .psr = ARMV4_5_MODE_FIQ,
+               .psr = ARM_MODE_FIQ,
                .n_indices = ARRAY_SIZE(arm_fiq_indices),
                .indices = arm_fiq_indices,
        },
        {
                .name = "Supervisor",
-               .psr = ARMV4_5_MODE_SVC,
+               .psr = ARM_MODE_SVC,
                .n_indices = ARRAY_SIZE(arm_svc_indices),
                .indices = arm_svc_indices,
        },
        {
                .name = "Abort",
-               .psr = ARMV4_5_MODE_ABT,
+               .psr = ARM_MODE_ABT,
                .n_indices = ARRAY_SIZE(arm_abt_indices),
                .indices = arm_abt_indices,
        },
        {
                .name = "IRQ",
-               .psr = ARMV4_5_MODE_IRQ,
+               .psr = ARM_MODE_IRQ,
                .n_indices = ARRAY_SIZE(arm_irq_indices),
                .indices = arm_irq_indices,
        },
        {
                .name = "Undefined instruction",
-               .psr = ARMV4_5_MODE_UND,
+               .psr = ARM_MODE_UND,
                .n_indices = ARRAY_SIZE(arm_und_indices),
                .indices = arm_und_indices,
        },
        {
                .name = "System",
-               .psr = ARMV4_5_MODE_SYS,
+               .psr = ARM_MODE_SYS,
                .n_indices = ARRAY_SIZE(arm_usr_indices),
                .indices = arm_usr_indices,
        },
@@ -166,21 +166,21 @@ bool is_arm_mode(unsigned psr_mode)
 int armv4_5_mode_to_number(enum armv4_5_mode mode)
 {
        switch (mode) {
-       case ARMV4_5_MODE_ANY:
+       case ARM_MODE_ANY:
                /* map MODE_ANY to user mode */
-       case ARMV4_5_MODE_USR:
+       case ARM_MODE_USR:
                return 0;
-       case ARMV4_5_MODE_FIQ:
+       case ARM_MODE_FIQ:
                return 1;
-       case ARMV4_5_MODE_IRQ:
+       case ARM_MODE_IRQ:
                return 2;
-       case ARMV4_5_MODE_SVC:
+       case ARM_MODE_SVC:
                return 3;
-       case ARMV4_5_MODE_ABT:
+       case ARM_MODE_ABT:
                return 4;
-       case ARMV4_5_MODE_UND:
+       case ARM_MODE_UND:
                return 5;
-       case ARMV4_5_MODE_SYS:
+       case ARM_MODE_SYS:
                return 6;
        case ARM_MODE_MON:
                return 7;
@@ -195,24 +195,24 @@ enum armv4_5_mode armv4_5_number_to_mode(int number)
 {
        switch (number) {
        case 0:
-               return ARMV4_5_MODE_USR;
+               return ARM_MODE_USR;
        case 1:
-               return ARMV4_5_MODE_FIQ;
+               return ARM_MODE_FIQ;
        case 2:
-               return ARMV4_5_MODE_IRQ;
+               return ARM_MODE_IRQ;
        case 3:
-               return ARMV4_5_MODE_SVC;
+               return ARM_MODE_SVC;
        case 4:
-               return ARMV4_5_MODE_ABT;
+               return ARM_MODE_ABT;
        case 5:
-               return ARMV4_5_MODE_UND;
+               return ARM_MODE_UND;
        case 6:
-               return ARMV4_5_MODE_SYS;
+               return ARM_MODE_SYS;
        case 7:
                return ARM_MODE_MON;
        default:
                LOG_ERROR("mode index out of bounds %d", number);
-               return ARMV4_5_MODE_ANY;
+               return ARM_MODE_ANY;
        }
 }
 
@@ -249,59 +249,59 @@ static const struct {
         * correspond to r0..r7, and the fifteenth to PC, so that callers
         * don't need to map them.
         */
-       { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+       { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
+       { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
+       { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
+       { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
+       { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
+       { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
+       { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
+       { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
 
        /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
         * them as MODE_ANY creates special cases.  (ANY means
         * "not mapped" elsewhere; here it's "everything but FIQ".)
         */
-       { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+       { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
+       { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
+       { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
+       { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
+       { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
 
        /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
-       { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
-       { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+       { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
+       { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
 
        /* guaranteed to be at index 15 */
-       { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+       { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
 
-       { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+       { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
+       { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
+       { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
+       { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
+       { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
 
-       { .name = "sp_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "lr_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+       { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
+       { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
 
-       { .name = "sp_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
-       { .name = "lr_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+       { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
+       { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
 
-       { .name = "sp_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
-       { .name = "lr_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+       { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
+       { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
 
-       { .name = "sp_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
-       { .name = "lr_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+       { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
+       { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
 
-       { .name = "sp_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
-       { .name = "lr_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+       { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
+       { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
 
-       { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
-       { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
-       { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
-       { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
-       { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
-       { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+       { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
+       { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
+       { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
+       { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
+       { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
+       { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
 
        { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
        { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
@@ -364,12 +364,12 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
        /* mode_to_number() warned; set up a somewhat-sane mapping */
        num = armv4_5_mode_to_number(mode);
        if (num < 0) {
-               mode = ARMV4_5_MODE_USR;
+               mode = ARM_MODE_USR;
                num = 0;
        }
 
        arm->map = &armv4_5_core_reg_map[num][0];
-       arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
+       arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
                        ? NULL
                        : arm->core_cache->reg_list + arm->map[16];
 
@@ -517,7 +517,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
                                        arm_mode_name(value & 0x1f));
                        value &= ~((1 << 24) | (1 << 5));
                        armv4_5_target->write_core_reg(target, reg,
-                                       16, ARMV4_5_MODE_ANY, value);
+                                       16, ARM_MODE_ANY, value);
                }
        } else {
                buf_set_u32(reg->value, 0, 32, value);
@@ -646,9 +646,9 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 
                /* label this bank of registers (or shadows) */
                switch (arm_mode_data[mode].psr) {
-               case ARMV4_5_MODE_SYS:
+               case ARM_MODE_SYS:
                        continue;
-               case ARMV4_5_MODE_USR:
+               case ARM_MODE_USR:
                        name = "System and User";
                        sep = "";
                        break;
@@ -1125,7 +1125,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
                return ERROR_INVALID_ARGUMENTS;
        }
 
-       if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
+       if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
        {
                LOG_DEBUG("setting core_mode: 0x%2.2x",
                                armv4_5_algorithm_info->core_mode);
@@ -1274,7 +1274,7 @@ int arm_checksum_memory(struct target *target,
        }
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
@@ -1351,7 +1351,7 @@ int arm_blank_check_memory(struct target *target,
        }
 
        armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-       armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+       armv4_5_info.core_mode = ARM_MODE_SVC;
        armv4_5_info.core_state = ARM_STATE_ARM;
 
        init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
@@ -1425,10 +1425,10 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
        armv4_5->target = target;
 
        armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
-       arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
+       arm_set_cpsr(armv4_5, ARM_MODE_USR);
 
        /* core_type may be overridden by subtype logic */
-       armv4_5->core_type = ARMV4_5_MODE_ANY;
+       armv4_5->core_type = ARM_MODE_ANY;
 
        /* default full_context() has no core-specific optimizations */
        if (!armv4_5->full_context && armv4_5->read_core_reg)

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index de1b9333b552b38bd99bd00ae4cdf278f8faf322..8e2fca2cff03a42343a5f5ab706386884d030a88 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -32,15 +32,15 @@
 
 typedef enum armv4_5_mode
 {
-       ARMV4_5_MODE_USR = 16,
-       ARMV4_5_MODE_FIQ = 17,
-       ARMV4_5_MODE_IRQ = 18,
-       ARMV4_5_MODE_SVC = 19,
-       ARMV4_5_MODE_ABT = 23,
+       ARM_MODE_USR = 16,
+       ARM_MODE_FIQ = 17,
+       ARM_MODE_IRQ = 18,
+       ARM_MODE_SVC = 19,
+       ARM_MODE_ABT = 23,
        ARM_MODE_MON = 26,
-       ARMV4_5_MODE_UND = 27,
-       ARMV4_5_MODE_SYS = 31,
-       ARMV4_5_MODE_ANY = -1
+       ARM_MODE_UND = 27,
+       ARM_MODE_SYS = 31,
+       ARM_MODE_ANY = -1
 } armv4_5_mode_t;
 
 const char *arm_mode_name(unsigned psr_mode);
@@ -91,7 +91,7 @@ struct arm
 
        /**
         * Indicates what registers are in the ARM state core register set.
-        * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+        * ARM_MODE_ANY indicates the standard set of 37 registers,
         * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
         * more registers are shadowed, for "Secure Monitor" mode.
         */

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index e889a8a130003e00b773846d52871103f78fcc59..300ac2835a9867d2dadd736fcee319ce3c7976d0 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -105,7 +105,7 @@ int armv7a_arch_state(struct target *target)
                 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
                 state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
-       if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
+       if (armv4_5->core_mode == ARM_MODE_ABT)
                armv7a_show_fault_registers(target);
        if (target->debug_reason == DBG_REASON_WATCHPOINT)
                LOG_USER("Watchpoint triggered at PC %#08x",

diff --git a/src/target/xscale.c b/src/target/xscale.c
index f52965a34fc64d75690f37fcd15bca3283897290..57b1081f9ffe2775edc9c5f55c86ad1423169589 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1701,7 +1701,7 @@ static int xscale_full_context(struct target *target)
                bool valid = true;
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are invalid registers in the current mode
@@ -1724,7 +1724,7 @@ static int xscale_full_context(struct target *target)
                /* get banked registers:  r8 to r14; and SPSR
                 * except in USR/SYS mode
                 */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        /* SPSR */
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
@@ -1777,7 +1777,7 @@ static int xscale_restore_banked(struct target *target)
                enum armv4_5_mode mode = armv4_5_number_to_mode(i);
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are dirty registers in this mode */
@@ -1789,7 +1789,7 @@ static int xscale_restore_banked(struct target *target)
                }
 
                /* if not USR/SYS, check if the SPSR needs to be written */
-               if (mode != ARMV4_5_MODE_SYS)
+               if (mode != ARM_MODE_SYS)
                {
                        if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16).dirty)
@@ -1817,7 +1817,7 @@ dirty:
                }
 
                /* send spsr if not in USR/SYS mode */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
                        xscale_send_u32(target, buf_get_u32(r->value, 0, 32));