target_free_working_area(target,pworking_area);
- LOG_INFO("Page = 0x%x was written.",page);
+ LOG_INFO("Page = 0x%" PRIx32 " was written.",page);
}
else
target_read_memory(target, target_mem_base+DATA_OFFS, 4, nand->page_size == 2048?512:128, page_buffer);
memcpy(data, page_buffer, data_size);
- LOG_INFO("Page = 0x%x was read.",page);
+ LOG_INFO("Page = 0x%" PRIx32 " was read.",page);
/* check hw generated ECC for each 256 bytes block with the saved ECC in flash spare area*/
int idx = nand->page_size/0x200 ;
target_read_memory(target, target_mem_base+ECC_OFFS, 4, 8, ecc_hw_buffer);
for(i=0;i<idx;i++){
if( (0x00ffffff&*(uint32_t *)(ecc_hw_buffer+i*8)) != (0x00ffffff&*(uint32_t *)(ecc_flash_buffer+8+i*16)) )
- LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%x",i*2+1,page);
+ LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+1,page);
if( (0x00ffffff&*(uint32_t *)(ecc_hw_buffer+4+i*8)) != (0x00ffffff&*(uint32_t *)(ecc_flash_buffer+12+i*16)) )
- LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%x",i*2+2,page);
+ LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,i*2+2,page);
}
}
retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
- LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
+ LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32,
dap->apsel, idreg, romaddr);
xp->control = control;
xp->dirty = true;
- LOG_DEBUG("BPWP: addr %8.8x, control %x, number %d",
+ LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
xp->address, control, xp->number);
/* hardware is updated in write_dirty_registers() */