mflo s6\r
sw s6, 8(s5)\r
\r
- /* Each task maintains its own nesting count. */\r
- la s6, uxCriticalNesting\r
- lw s6, (s6)\r
- sw s6, 4(s5)\r
-\r
/* Update the task stack pointer value if nesting is zero. */\r
la s6, uxInterruptNesting\r
lw s6, (s6)\r
addiu k1, k1, -1\r
sw k1, 0(k0)\r
\r
- /* Restore the critical nesting count. */\r
- la k0, uxCriticalNesting\r
- lw k1, 4(s5)\r
- sw k1, (k0)\r
-\r
- /* If the critical nesting is not zero then set status as if within\r
- a critical section. */\r
lw k0, portSTATUS_STACK_LOCATION(s5)\r
lw k1, portEPC_STACK_LOCATION(s5)\r
\r
#define portIE_BIT ( 0x00000001 )\r
#define portEXL_BIT ( 0x00000002 )\r
#define portSW0_ENABLE ( 0x00000100 )\r
-#define portIPL_SHIFT ( 10 )\r
-#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )\r
\r
/* The EXL bit is set to ensure interrupts do not occur while the context of\r
the first task is being restored. */\r
#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portSW0_ENABLE )\r
\r
-/* Records the nesting depth of calls to portENTER_CRITICAL(). */\r
-unsigned portBASE_TYPE uxCriticalNesting = 0x55555555;\r
-\r
/* Records the interrupt nesting depth. This starts at one as it will be\r
decremented to 0 when the first task starts. */\r
volatile unsigned portBASE_TYPE uxInterruptNesting = 0x01;\r
\r
-/* Used to store the original interrupt mask when the mask level is temporarily\r
-raised during an ISR. */\r
-volatile unsigned portBASE_TYPE uxSavedStatusRegister = 0;\r
-\r
/* Stores the task stack pointer when a switch is made to use the system stack. */\r
unsigned portBASE_TYPE uxSavedTaskStackPointer = 0;\r
\r
*pxTopOfStack = (portSTACK_TYPE) pvParameters; /* Parameters to pass in */\r
pxTopOfStack -= 14;\r
\r
- *pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level */\r
+ *pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level - no longer used. */\r
pxTopOfStack--;\r
\r
return pxTopOfStack;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortEnterCritical(void)\r
-{\r
-unsigned portLONG ulStatus;\r
-\r
- /* Mask interrupts at and below the kernel interrupt priority. */\r
- ulStatus = _CP0_GET_STATUS();\r
- ulStatus |= ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT );\r
- _CP0_SET_STATUS( ulStatus );\r
-\r
- /* Once interrupts are disabled we can access the nesting count directly. */\r
- uxCriticalNesting++;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPortExitCritical(void)\r
-{\r
-unsigned portLONG ulStatus;\r
-\r
- /* If we are in a critical section then we can access the nesting count\r
- directly. */\r
- uxCriticalNesting--;\r
-\r
- /* Has the nesting unwound? */\r
- if( uxCriticalNesting == 0 ) \r
- {\r
- /* Unmask all interrupts. */\r
- ulStatus = _CP0_GET_STATUS();\r
- ulStatus &= ~portALL_IPL_BITS;\r
- _CP0_SET_STATUS( ulStatus );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
portBASE_TYPE xPortStartScheduler( void )\r
{\r
extern void vPortStartFirstTask( void );\r
\r
void vPortIncrementTick( void )\r
{\r
- vPortSetInterruptMaskFromISR();\r
+unsigned portBASE_TYPE uxSavedStatus;\r
+\r
+ uxSavedStatus = uxPortSetInterruptMaskFromISR();\r
vTaskIncrementTick();\r
- vPortClearInterruptMaskFromISR();\r
+ vPortClearInterruptMaskFromISR( uxSavedStatus );\r
\r
/* If we are using the preemptive scheduler then we might want to select\r
a different task to execute. */\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortSetInterruptMaskFromISR( void )\r
+unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void )\r
{\r
+unsigned portBASE_TYPE uxSavedStatusRegister;\r
+\r
asm volatile ( "di" );\r
uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;\r
_CP0_SET_STATUS( ( uxSavedStatusRegister | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );\r
+\r
+ return uxSavedStatusRegister;\r
}\r
/*-----------------------------------------------------------*/\r
\r
-void vPortClearInterruptMaskFromISR( void )\r
+void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE uxSavedStatusRegister )\r
{\r
_CP0_SET_STATUS( uxSavedStatusRegister );\r
}\r
.set noreorder\r
\r
.extern pxCurrentTCB\r
- .extern uxCriticalNesting\r
.extern vTaskSwitchContext\r
.extern vPortIncrementTick\r
.extern xISRStackTop\r
mflo s7\r
sw s7, 8(s5)\r
\r
- /* Each task maintains its own nesting count. */\r
- la s7, uxCriticalNesting\r
- lw s7, (s7)\r
- sw s7, 4(s5)\r
-\r
/* Save the stack pointer to the task. */\r
la s7, pxCurrentTCB\r
lw s7, (s7)\r
/* Switch back to use the real stack pointer. */\r
add sp, zero, s5\r
\r
- /* Restore the critical nesting depth. */\r
- la s5, uxCriticalNesting\r
- lw k0, 4(sp)\r
- sw k0, (s5)\r
+ /* Restore the real s5 value. */\r
+ lw s5, 40(sp)\r
\r
/* If the critical nesting is not zero and a yield is not pended\r
then set status as if within a critical section. */\r
- lw s5, portSTATUS_STACK_LOCATION(sp)\r
- beq k0, zero, .+28\r
- nop\r
- mfc0 k1, _CP0_CAUSE\r
- andi k1, k1, 256\r
- bne k1, zero, .+12\r
- nop\r
- or s5, s5, (configMAX_SYSCALL_INTERRUPT_PRIORITY<<10)\r
-\r
+ lw k1, portSTATUS_STACK_LOCATION(sp)\r
lw k0, portEPC_STACK_LOCATION(sp)\r
\r
- mtc0 s5, _CP0_STATUS\r
- ehb \r
-\r
- /* Restore the real s5 value. */\r
- lw s5, 40(sp)\r
-\r
/* Remove stack frame. */\r
addiu sp, sp, portCONTEXT_SIZE\r
\r
+ mtc0 k1, _CP0_STATUS\r
+ ehb \r
mtc0 k0, _CP0_EPC\r
eret \r
nop\r
/*-----------------------------------------------------------*/\r
\r
/* Critical section management. */\r
-#define portDISABLE_INTERRUPTS() INTDisableInterrupts() \r
-#define portENABLE_INTERRUPTS() INTEnableInterrupts()\r
-\r
-extern void vPortEnterCritical( void );\r
-extern void vPortExitCritical( void );\r
-#define portENTER_CRITICAL() vPortEnterCritical()\r
-#define portEXIT_CRITICAL() vPortExitCritical()\r
-\r
-extern void vPortSetInterruptMaskFromISR();\r
-extern void vPortClearInterruptMaskFromISR();\r
-#define portSET_INTERRUPT_MASK_FROM_ISR() vPortSetInterruptMaskFromISR()\r
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR() vPortClearInterruptMaskFromISR()\r
+#define portIPL_SHIFT ( 10 )\r
+#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )\r
+\r
+#define portDISABLE_INTERRUPTS() \\r
+{ \\r
+unsigned portLONG ulStatus; \\r
+ \\r
+ /* Mask interrupts at and below the kernel interrupt priority. */ \\r
+ ulStatus = _CP0_GET_STATUS(); \\r
+ ulStatus |= ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ); \\r
+ _CP0_SET_STATUS( ulStatus ); \\r
+}\r
+\r
+#define portENABLE_INTERRUPTS() \\r
+{ \\r
+unsigned portLONG ulStatus; \\r
+ \\r
+ /* Unmask all interrupts. */ \\r
+ ulStatus = _CP0_GET_STATUS(); \\r
+ ulStatus &= ~portALL_IPL_BITS; \\r
+ _CP0_SET_STATUS( ulStatus ); \\r
+}\r
+\r
+\r
+extern void vTaskEnterCritical( void );\r
+extern void vTaskExitCritical( void );\r
+#define portCRITICAL_NESTING_IN_TCB 1\r
+#define portENTER_CRITICAL() vTaskEnterCritical()\r
+#define portEXIT_CRITICAL() vTaskExitCritical()\r
+\r
+extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR();\r
+extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )\r
\r
/*-----------------------------------------------------------*/\r
\r
projects / freertos / commitdiff