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Starting point for the STM32L152 demo application added. Very much a work in progress.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 19 Dec 2010 19:20:56 +0000 (19:20 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 19 Dec 2010 19:20:56 +0000 (19:20 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@1173 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

34 files changed:
Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/ParTest.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/RTOSDemo.eww [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/main.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h [new file with mode: 0644] patch | blob
Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c [new file with mode: 0644] patch | blob

diff --git a/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..7d6cf4c
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/FreeRTOSConfig.h
@@ -0,0 +1,110 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION           1\r
+#define configUSE_IDLE_HOOK                    0\r
+#define configUSE_TICK_HOOK                    0\r
+#define configCPU_CLOCK_HZ                     ( 32000000UL )  \r
+#define configTICK_RATE_HZ                     ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE       ( ( unsigned short ) 128 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) ( 10 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                ( 16 )\r
+#define configUSE_TRACE_FACILITY       0\r
+#define configUSE_16_BIT_TICKS         0\r
+#define configIDLE_SHOULD_YIELD                1\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES          0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet               1\r
+#define INCLUDE_uxTaskPriorityGet              1\r
+#define INCLUDE_vTaskDelete                            1\r
+#define INCLUDE_vTaskCleanUpResources  0\r
+#define INCLUDE_vTaskSuspend                   1\r
+#define INCLUDE_vTaskDelayUntil                        1\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+/* This is the raw value as per the Cortex-M3 NVIC.  Values can be 255\r
+(lowest) to 0 (1?) (highest). */\r
+#define configKERNEL_INTERRUPT_PRIORITY                255\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   191 /* equivalent to 0xb0, or priority 11. */\r
+\r
+\r
+/* This is the value being used as per the ST library which permits 16\r
+priority values, 0 to 15.  This must correspond to the\r
+configKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest\r
+NVIC value of 255. */\r
+#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY        15\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/ParTest.c b/Demo/Cortex_STM32L152_IAR/ParTest.c
new file mode 100644 (file)
index 0000000..3009d68
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/ParTest.c
@@ -0,0 +1,147 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* ST library functions. */\r
+#include "stm32l152_eval.h"\r
+\r
+#define partstMAX_OUTPUT_LED 4\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       STM_EVAL_LEDInit( LED1 );\r
+       STM_EVAL_LEDInit( LED2 );\r
+       STM_EVAL_LEDInit( LED3 );\r
+       STM_EVAL_LEDInit( LED4 );\r
+       STM_EVAL_LEDOff( LED1 );\r
+       STM_EVAL_LEDOff( LED2 );\r
+       STM_EVAL_LEDOff( LED3 );\r
+       STM_EVAL_LEDOff( LED4 );        \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+       vTaskSuspendAll();\r
+       {\r
+               if( xValue != pdFALSE )\r
+               {\r
+                       switch( uxLED )\r
+                       {\r
+                               case 0: STM_EVAL_LEDOn( LED1 );\r
+                                               break;\r
+       \r
+                               case 1: STM_EVAL_LEDOn( LED2 );\r
+                                               break;\r
+       \r
+                               case 2: STM_EVAL_LEDOn( LED3 );\r
+                                               break;\r
+       \r
+                               case 3: STM_EVAL_LEDOn( LED4 );\r
+                                               break;                                  \r
+                       }\r
+               }\r
+               else\r
+               {\r
+                       switch( uxLED )\r
+                       {\r
+                               case 0: STM_EVAL_LEDOff( LED1 );\r
+                                               break;\r
+       \r
+                               case 1: STM_EVAL_LEDOff( LED2 );\r
+                                               break;\r
+       \r
+                               case 2: STM_EVAL_LEDOff( LED3 );\r
+                                               break;\r
+       \r
+                               case 3: STM_EVAL_LEDOff( LED4 );\r
+                                               break;                                  \r
+                       }\r
+               }\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+       vTaskSuspendAll();\r
+       {\r
+               switch( uxLED )\r
+               {\r
+                       case 0: STM_EVAL_LEDToggle( LED1 );\r
+                                       break;\r
+\r
+                       case 1: STM_EVAL_LEDToggle( LED2 );\r
+                                       break;\r
+\r
+                       case 2: STM_EVAL_LEDToggle( LED3 );\r
+                                       break;\r
+\r
+                       case 3: STM_EVAL_LEDToggle( LED4 );\r
+                                       break;                                  \r
+               }\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd
new file mode 100644 (file)
index 0000000..8745728
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewd
@@ -0,0 +1,1683 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\ST\iostm32l152xx.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\ST\FlashSTM32L15xxB.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>12</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>4</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>22</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>ARMSIM_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesOffset3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesUse3</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>12</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>4</version>\r
+          <state>5</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCORERESET</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchMMERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchNOCPERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchCHRERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchSTATERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchBUSERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchINTERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchHARDERR</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCatchDummy</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkScriptFile</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>_call_main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>PEMICRO_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCPEMicroAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroInterfaceList</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroJtagSpeed</name>\r
+          <state>#UNINITIALIZED#</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroShowSettings</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroSerialPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroTCPIP</name>\r
+          <state>10.0.0.1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPEMicroCommCmdLineProducer</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSTLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp
new file mode 100644 (file)
index 0000000..3da15ae
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.ewp
@@ -0,0 +1,1807 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>18</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Debug\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Debug\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Debug\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>17</version>\r
+          <state>37</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>6.10.1.52170</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>STM32L152xB   ST STM32L152xB</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>26</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>USE_STM32L152_EVAL</state>\r
+          <state>USE_STDPERIPH_DRIVER</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pa082</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
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+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>18</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Release\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Release\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Release\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>17</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>default       None</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath2</name>\r
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>26</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>NDEBUG</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>1111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRopi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndRwpi</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPosIndNoDynInit</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccLang</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccAllowVLA</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppDialect</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccExceptions</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRTTI</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccStaticDestr</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IccRelaxedFpPrecision</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IccCppInlineSemantics</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>c.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
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+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
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+      <name>BUILDACTION</name>\r
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+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
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+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
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+        <option>\r
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+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
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+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
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+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\generic.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
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+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogAutoLibSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogRedirSymbols</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogUnusedFragments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcReverseByteOrder</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkCrcUseAsInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptInline</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsAllow</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOptExceptionsForce</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>FreeRTOS_Source</name>\r
+    <group>\r
+      <name>Portable</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_spi.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Standard_Demo_Code</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>System_and_ST_Code</name>\r
+    <group>\r
+      <name>Eval_Board_Library</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.c</name>\r
+      </file>\r
+    </group>\r
+    <group>\r
+      <name>Peripheral_Library</name>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\misc.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_exti.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_gpio.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_rcc.c</name>\r
+      </file>\r
+      <file>\r
+        <name>$PROJ_DIR$\system_and_ST_code\STM32L1xx_StdPeriph_Driver\src\stm32l1xx_syscfg.c</name>\r
+      </file>\r
+    </group>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\startup_stm32l1xx_md.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\stm32l1xx_it.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\system_and_ST_code\system_stm32l1xx.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\main.c</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\ParTest.c</name>\r
+  </file>\r
+</project>\r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww b/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww
new file mode 100644 (file)
index 0000000..239a938
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/RTOSDemo.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/main.c b/Demo/Cortex_STM32L152_IAR/main.c
new file mode 100644 (file)
index 0000000..06476f6
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/main.c
@@ -0,0 +1,220 @@
+/*\r
+    FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
+\r
+    ***************************************************************************\r
+    *                                                                         *\r
+    * If you are:                                                             *\r
+    *                                                                         *\r
+    *    + New to FreeRTOS,                                                   *\r
+    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
+    *    + Looking for basic training,                                        *\r
+    *    + Wanting to improve your FreeRTOS skills and productivity           *\r
+    *                                                                         *\r
+    * then take a look at the FreeRTOS books - available as PDF or paperback  *\r
+    *                                                                         *\r
+    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
+    *                  http://www.FreeRTOS.org/Documentation                  *\r
+    *                                                                         *\r
+    * A pdf reference manual is also available.  Both are usually delivered   *\r
+    * to your inbox within 20 minutes to two hours when purchased between 8am *\r
+    * and 8pm GMT (although please allow up to 24 hours in case of            *\r
+    * exceptional circumstances).  Thank you for your support!                *\r
+    *                                                                         *\r
+    ***************************************************************************\r
+\r
+    This file is part of the FreeRTOS distribution.\r
+\r
+    FreeRTOS is free software; you can redistribute it and/or modify it under\r
+    the terms of the GNU General Public License (version 2) as published by the\r
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+    ***NOTE*** The exception to the GPL is included to allow you to distribute\r
+    a combined work that includes FreeRTOS without being obliged to provide the\r
+    source code for proprietary components outside of the FreeRTOS kernel.\r
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
+    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+    more details. You should have received a copy of the GNU General Public\r
+    License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+    by writing to Richard Barry, contact details for whom are available on the\r
+    FreeRTOS WEB site.\r
+\r
+    1 tab == 4 spaces!\r
+\r
+    http://www.FreeRTOS.org - Documentation, latest information, license and\r
+    contact details.\r
+\r
+    http://www.SafeRTOS.com - A version that is certified for use in safety\r
+    critical systems.\r
+\r
+    http://www.OpenRTOS.com - Commercial support, development, porting,\r
+    licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+#include "flash.h"\r
+\r
+/* ST driver includes. */\r
+#include "stm32l1xx_usart.h"\r
+\r
+/* Eval board includes. */\r
+#include "stm32_eval.h"\r
+#include "stm32l152_eval_lcd.h"\r
+\r
+#define mainFLASH_TASK_PRIORITY                        ( tskIDLE_PRIORITY + 1 )\r
+#define mainLCD_TASK_PRIORITY                  ( tskIDLE_PRIORITY + 1 )\r
+\r
+#define mainLCD_TASK_STACK_SIZE                        ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+#define mainQUEUE_LENGTH                               ( 5 )\r
+\r
+#define mainMESSAGE_BUTTON_UP                  ( 1 )\r
+#define mainMESSAGE_BUTTON_DOWN                        ( 2 )\r
+#define mainMESSAGE_BUTTON_LEFT                        ( 3 )\r
+#define mainMESSAGE_BUTTON_RIGHT               ( 4 )\r
+#define mainMESSAGE_BUTTON_SEL                 ( 5 )\r
+\r
+/*\r
+ * System configuration is performed prior to main() being called, this function\r
+ * configures the peripherals used by the demo application.\r
+ */\r
+static void prvSetupHardware( void );\r
+static void prvLCDTask( void *pvParameters );\r
+static void vTempTask( void *pv );\r
+\r
+static xQueueHandle xLCDQueue = NULL;\r
+\r
+typedef struct\r
+{\r
+       char cMessageID;\r
+       long lMessageValue;\r
+} xQueueMessage;\r
+\r
+void main( void )\r
+{\r
+       prvSetupHardware();\r
+       \r
+       /* Create the queue used by tasks and interrupts to send strings to the LCD\r
+       task. */\r
+       xLCDQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( xQueueMessage ) );\r
+       \r
+       if( xLCDQueue != NULL )\r
+       {\r
+               xTaskCreate( prvLCDTask, ( signed char * ) "LCD", mainLCD_TASK_STACK_SIZE, NULL, mainLCD_TASK_PRIORITY, NULL );\r
+               xTaskCreate( vTempTask, ( signed char * ) "Temp", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+       }\r
+       \r
+       vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );\r
+       \r
+       vTaskStartScheduler();\r
+       \r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDTask( void *pvParameters )\r
+{\r
+xQueueMessage xReceivedMessage;\r
+long lLine = Line1;\r
+const long lFontHeight = (((sFONT *)LCD_GetFont())->Height);\r
+static char cBuffer[ 32 ];\r
+\r
+       for( ;; )\r
+       {\r
+               xQueueReceive( xLCDQueue, &xReceivedMessage, portMAX_DELAY );\r
+\r
+               if( lLine >= Line9 )\r
+               {\r
+                       LCD_Clear( Blue );\r
+                       lLine = 0;\r
+               }\r
+               \r
+               switch( xReceivedMessage.cMessageID )\r
+               {\r
+                       case mainMESSAGE_BUTTON_UP              :       sprintf( cBuffer, "Button up = %d", xReceivedMessage.lMessageValue );\r
+                                                                                               break;\r
+                       case mainMESSAGE_BUTTON_DOWN    :\r
+                                                                                               break;\r
+                       case mainMESSAGE_BUTTON_LEFT    :\r
+                                                                                               break;\r
+                       case mainMESSAGE_BUTTON_RIGHT   :\r
+                                                                                               break;\r
+                       case mainMESSAGE_BUTTON_SEL             :\r
+                                                                                               break;\r
+                       default                                                 :       sprintf( cBuffer, "Unknown message" );\r
+                                                                                               break;\r
+               }\r
+               \r
+               LCD_DisplayStringLine( lLine, ( uint8_t * ) cBuffer );\r
+               lLine += lFontHeight;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vTempTask( void *pv )\r
+{\r
+long lLastState = pdFALSE;\r
+long lState;\r
+xQueueMessage xMessage;\r
+\r
+       for( ;; )\r
+       {\r
+               lState = STM_EVAL_PBGetState( BUTTON_UP );\r
+               if( lState != lLastState )\r
+               {\r
+                       xMessage.cMessageID = mainMESSAGE_BUTTON_UP;\r
+                       xMessage.lMessageValue = lState;\r
+                       lLastState = lState;\r
+                       xQueueSend( xLCDQueue, &xMessage, portMAX_DELAY );\r
+                       vTaskDelay( 10 );\r
+               }\r
+       }\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       /* Initialise the LEDs. */\r
+       vParTestInitialise();\r
+\r
+       //BUTTON_MODE_EXTI\r
+       /* Initialise the joystick inputs. */\r
+       STM_EVAL_PBInit( BUTTON_UP, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_DOWN, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_LEFT, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_RIGHT, BUTTON_MODE_GPIO );\r
+       STM_EVAL_PBInit( BUTTON_SEL, BUTTON_MODE_GPIO );\r
+\r
+#if 0  \r
+USART_InitTypeDef USART_InitStructure;\r
+\r
+       USART_InitStructure.USART_BaudRate = 115200;\r
+       USART_InitStructure.USART_WordLength = USART_WordLength_8b;\r
+       USART_InitStructure.USART_StopBits = USART_StopBits_1;\r
+       USART_InitStructure.USART_Parity = USART_Parity_No;\r
+       USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;\r
+       USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+       \r
+       STM_EVAL_COMInit( COM1, &USART_InitStructure );\r
+#endif\r
+       \r
+       /* Initialize the LCD */\r
+       STM32L152_LCD_Init();\r
+       \r
+       LCD_Clear(Blue);\r
+       LCD_SetBackColor(Blue);\r
+       LCD_SetTextColor(White);\r
+       LCD_DisplayStringLine(Line0, "  www.FreeRTOS.org");\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat
new file mode 100644 (file)
index 0000000..1f8369b
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.cspy.bat
@@ -0,0 +1,15 @@
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.0\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\ST\FlashSTM32L15xxB.board" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.0\arm\CONFIG\debugger\ST\iostm32l152xx.ddf" "--semihosting" "--device=STM32L152xB" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--drv_catch_exceptions=0x000" \r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt
new file mode 100644 (file)
index 0000000..8d1124e
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dbgdt
@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+  <Desktop>\r
+    <Static>\r
+      <Debug-Log>\r
+        \r
+        \r
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log>\r
+      <Build>\r
+        <ColumnWidth0>20</ColumnWidth0>\r
+        <ColumnWidth1>1216</ColumnWidth1>\r
+        <ColumnWidth2>324</ColumnWidth2>\r
+        <ColumnWidth3>81</ColumnWidth3>\r
+      </Build>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>295</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Disassembly>\r
+        <PreferedWindows>\r
+          <Position>2</Position>\r
+          <ScreenPosX>0</ScreenPosX>\r
+          <ScreenPosY>0</ScreenPosY>\r
+          <Windows/>\r
+        </PreferedWindows>\r
+        <MixedMode>1</MixedMode>\r
+        <CodeCovShow>1</CodeCovShow>\r
+        <InstrProfShow>1</InstrProfShow>\r
+      </Disassembly>\r
+    <Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Watch><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>208</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QuickWatch></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd1>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-4782-21358</Identity>\r
+            <TabName>Debug Log</TabName>\r
+            <Factory>Debug-Log</Factory>\r
+            <Session/>\r
+          </Tab>\r
+          <Tab>\r
+            <Identity>TabID-4259-21368</Identity>\r
+            <TabName>Build</TabName>\r
+            <Factory>Build</Factory>\r
+            <Session/>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd1><Wnd3>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-15530-21362</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/System_and_ST_Code</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>29</YPos><SelStart>1147</SelStart><SelEnd>1147</SelEnd></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>48</YPos><SelStart>3663</SelStart><SelEnd>3663</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval.c</Filename><XPos>0</XPos><YPos>303</YPos><SelStart>11579</SelStart><SelEnd>11579</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.c</Filename><XPos>0</XPos><YPos>515</YPos><SelStart>17208</SelStart><SelEnd>17208</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\system_and_ST_code\stm32_eval.h</Filename><XPos>0</XPos><YPos>289</YPos><SelStart>10822</SelStart><SelEnd>10832</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\system_and_ST_code\STM32L152_EVAL\stm32l152_eval_lcd.h</Filename><XPos>0</XPos><YPos>260</YPos><SelStart>8641</SelStart><SelEnd>8651</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\system_and_ST_code\Common\fonts.h</Filename><XPos>0</XPos><YPos>50</YPos><SelStart>1617</SelStart><SelEnd>1651</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-012aae80><key>iaridepm.enu1</key></Toolbar-012aae80><Toolbar-06c62ed8><key>debuggergui.enu1</key></Toolbar-06c62ed8></Sizes></Row0><Row1><Sizes><Toolbar-06cfd5f0><key>armjlink.enu1</key></Toolbar-06cfd5f0></Sizes></Row1></Top><Left><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>716</Bottom><Right>369</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>220833</sizeVertCX><sizeVertCY>731161</sizeVertCY></Rect></Wnd3></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Project>\r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni
new file mode 100644 (file)
index 0000000..241c151
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.dni
@@ -0,0 +1,64 @@
+[DebugChecksum]\r
+Checksum=1807629591\r
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[InstructionProfiling]\r
+Enabled=_ 0\r
+[CodeCoverage]\r
+Enabled=_ 0\r
+[Profiling]\r
+Enabled=0\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[StackPlugin]\r
+Enabled=1\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+Base=0\r
+UseAuto=0\r
+TypeViolation=1\r
+UnspecRange=1\r
+ActionState=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=995247177\r
+Graph=0\r
+Symbiont=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt
new file mode 100644 (file)
index 0000000..af87891
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo.wsdt
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>211</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build><TerminalIO/><Debug-Log><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1622</ColumnWidth1></Debug-Log></Static>\r
+    <Windows>\r
+      \r
+    <Wnd2>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-27630-4718</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/System_and_ST_Code</ExpandedNode><ExpandedNode>RTOSDemo/System_and_ST_Code/Eval_Board_Library</ExpandedNode><ExpandedNode>RTOSDemo/System_and_ST_Code/Peripheral_Library</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-10002-7709</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-18437-21512</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>11</YPos><SelStart>3083</SelStart><SelEnd>3083</SelEnd></Tab><ActiveTab>0</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-012aae80><key>iaridepm.enu1</key></Toolbar-012aae80></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>285</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>170833</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r
diff --git a/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
new file mode 100644 (file)
index 0000000..228ff82
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/settings/RTOSDemo_Debug.jlink
@@ -0,0 +1,23 @@
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="ADUC7020X62"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c
new file mode 100644 (file)
index 0000000..d45111b
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.c
@@ -0,0 +1,996 @@
+/**\r
+  ******************************************************************************\r
+  * @file    fonts.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides text fonts for STM32xx-EVAL's LCD driver. \r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "fonts.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup Common\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FONTS\r
+  * @brief      This file includes the Fonts driver of STM32-EVAL boards.\r
+  * @{\r
+  */  \r
+\r
+/** @defgroup FONTS_Private_Types\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Defines\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Macros\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+\r
+/** @defgroup FONTS_Private_Variables\r
+  * @{\r
+  */\r
+const uint16_t ASCII16x24_Table [] = {\r
+/** \r
+  * @brief        Space ' '  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '!'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '"'  \r
+  */ \r
+         0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '#'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,\r
+         0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,\r
+         0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,\r
+/** \r
+  * @brief        '$'  \r
+  */ \r
+         0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,\r
+         0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,\r
+         0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '%'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,\r
+         0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,\r
+         0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '&'  \r
+  */ \r
+         0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,\r
+         0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,\r
+         0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '''  \r
+  */ \r
+         0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '('  \r
+  */ \r
+         0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,\r
+         0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+         0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,\r
+/** \r
+  * @brief        ')'  \r
+  */ \r
+         0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,\r
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+         0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,\r
+/** \r
+  * @brief        '*'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '+'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ','  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '-'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '.'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '/'  \r
+  */ \r
+         0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,\r
+         0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,\r
+         0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '0'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,\r
+         0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '1'  \r
+  */ \r
+         0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '2'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,\r
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '3'  \r
+  */ \r
+         0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,\r
+         0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,\r
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '4'  \r
+  */ \r
+         0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,\r
+         0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,\r
+         0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '5'  \r
+  */ \r
+         0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,\r
+         0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,\r
+         0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '6'  \r
+  */ \r
+         0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,\r
+         0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '7'  \r
+  */ \r
+         0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,\r
+         0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,\r
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '8'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,\r
+         0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,\r
+         0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '9'  \r
+  */ \r
+         0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,\r
+         0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,\r
+         0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ':'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ';'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '<'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,\r
+         0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '='  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '>'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,\r
+         0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '?'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,\r
+         0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '@'  \r
+  */ \r
+         0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,\r
+         0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,\r
+         0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'A'  \r
+  */ \r
+         0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,\r
+         0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,\r
+         0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'B'  \r
+  */ \r
+         0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,\r
+         0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,\r
+         0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'C'  \r
+  */ \r
+         0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,\r
+         0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,\r
+         0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'D'  \r
+  */ \r
+         0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,\r
+         0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,\r
+         0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'E'  \r
+  */ \r
+         0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'F'  \r
+  */ \r
+         0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'G'  \r
+  */ \r
+         0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,\r
+         0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,\r
+         0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'H'  \r
+  */ \r
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'I'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'J'  \r
+  */ \r
+         0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,\r
+         0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,\r
+         0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'K'  \r
+  */ \r
+         0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,\r
+         0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,\r
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'L'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,\r
+         0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'M'  \r
+  */ \r
+         0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,\r
+         0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,\r
+         0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'N'  \r
+  */ \r
+         0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,\r
+         0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,\r
+         0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'O'  \r
+  */ \r
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,\r
+         0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,\r
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'P'  \r
+  */ \r
+         0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,\r
+         0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Q'  \r
+  */ \r
+         0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,\r
+         0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,\r
+         0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'R'  \r
+  */ \r
+         0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,\r
+         0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,\r
+         0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'S'  \r
+  */ \r
+         0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,\r
+         0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,\r
+         0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'T'  \r
+  */ \r
+         0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'U'  \r
+  */ \r
+         0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,\r
+         0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,\r
+         0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'V'  \r
+  */ \r
+         0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,\r
+         0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,\r
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'W'  \r
+  */ \r
+         0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,\r
+         0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,\r
+         0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'X'  \r
+  */ \r
+         0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,\r
+         0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,\r
+         0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Y'  \r
+  */ \r
+         0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,\r
+         0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'Z'  \r
+  */ \r
+         0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,\r
+         0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,\r
+         0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '['  \r
+  */ \r
+         0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,\r
+         0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,\r
+/** \r
+  * @brief        '\'  \r
+  */ \r
+         0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,\r
+         0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,\r
+         0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        ']'  \r
+  */ \r
+         0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,\r
+         0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,\r
+/** \r
+  * @brief        '^'  \r
+  */ \r
+         0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,\r
+         0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '_'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '''  \r
+  */ \r
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'a'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,\r
+         0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,\r
+         0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'b'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,\r
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+         0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'c'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,\r
+         0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,\r
+         0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'd'  \r
+  */ \r
+         0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,\r
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+         0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'e'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+         0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,\r
+         0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'f'  \r
+  */ \r
+         0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'g'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,\r
+         0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,\r
+         0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,\r
+/** \r
+  * @brief        'h'  \r
+  */ \r
+         0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,\r
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'i'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'j'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,\r
+/** \r
+  * @brief        'k'  \r
+  */ \r
+         0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,\r
+         0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,\r
+         0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'l'  \r
+  */ \r
+         0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'm'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,\r
+         0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,\r
+         0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'n'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,\r
+         0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'o'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,\r
+         0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,\r
+         0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'p'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,\r
+         0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,\r
+         0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,\r
+/** \r
+  * @brief        'q'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,\r
+         0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,\r
+         0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,\r
+/** \r
+  * @brief        'r'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,\r
+         0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,\r
+         0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        's'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,\r
+         0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,\r
+         0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        't'  \r
+  */ \r
+         0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'u'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,\r
+         0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,\r
+         0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'v'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,\r
+         0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,\r
+         0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'w'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,\r
+         0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,\r
+         0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'x'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,\r
+         0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,\r
+         0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        'y'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,\r
+         0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,\r
+         0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,\r
+/** \r
+  * @brief        'z'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,\r
+         0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,\r
+         0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '{'  \r
+  */ \r
+         0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,\r
+         0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,\r
+         0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '|'  \r
+  */ \r
+         0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,\r
+/** \r
+  * @brief        '}'  \r
+  */ \r
+         0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,\r
+         0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,\r
+         0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,\r
+/** \r
+  * @brief        '~'  \r
+  */ \r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\r
+         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};\r
+\r
+const uint16_t ASCII12x12_Table [] = {\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x5000,0x5000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0900,0x0900,0x1200,0x7f00,0x1200,0x7f00,0x1200,0x2400,0x2400,0x0000,0x0000,\r
+    0x1000,0x3800,0x5400,0x5000,0x5000,0x3800,0x1400,0x5400,0x5400,0x3800,0x1000,0x0000,\r
+    0x0000,0x3080,0x4900,0x4900,0x4a00,0x32c0,0x0520,0x0920,0x0920,0x10c0,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x1200,0x1400,0x1800,0x2500,0x2300,0x2300,0x1d80,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x4000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0800,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,\r
+    0x0000,0x4000,0x2000,0x2000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x2000,0x2000,\r
+    0x0000,0x2000,0x7000,0x2000,0x5000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0800,0x0800,0x7f00,0x0800,0x0800,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x4400,0x4400,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x1000,0x3000,0x5000,0x1000,0x1000,0x1000,0x1000,0x1000,0x1000,0x0000,0x0000,\r
+    0x0000,0x3000,0x4800,0x4400,0x0400,0x0800,0x1000,0x2000,0x4000,0x7c00,0x0000,0x0000,\r
+    0x0000,0x3000,0x4800,0x0400,0x0800,0x1000,0x0800,0x4400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0800,0x1800,0x1800,0x2800,0x2800,0x4800,0x7c00,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2000,0x4000,0x7000,0x4800,0x0400,0x4400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x1800,0x2400,0x4000,0x5000,0x6800,0x4400,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x7c00,0x0400,0x0800,0x1000,0x1000,0x1000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x2800,0x1000,0x2800,0x4400,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x1000,0x2800,0x4400,0x4400,0x2c00,0x1400,0x0400,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x2000,0x2000,0x4000,\r
+    0x0000,0x0000,0x0400,0x0800,0x3000,0x4000,0x3000,0x0800,0x0400,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x7c00,0x0000,0x0000,0x7c00,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x4000,0x2000,0x1800,0x0400,0x1800,0x2000,0x4000,0x0000,0x0000,0x0000,\r
+    0x0000,0x3800,0x6400,0x4400,0x0400,0x0800,0x1000,0x1000,0x0000,0x1000,0x0000,0x0000,\r
+    0x0000,0x0f80,0x1040,0x2ea0,0x51a0,0x5120,0x5120,0x5120,0x5320,0x4dc0,0x2020,0x1040,\r
+    0x0000,0x0800,0x1400,0x1400,0x1400,0x2200,0x3e00,0x2200,0x4100,0x4100,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x0000,0x0000,\r
+    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2000,0x2000,0x2100,0x1100,0x0e00,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2100,0x2100,0x2100,0x2100,0x2100,0x2200,0x3c00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x2000,0x2000,0x2000,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0e00,0x1100,0x2100,0x2000,0x2700,0x2100,0x2100,0x1100,0x0e00,0x0000,0x0000,\r
+    0x0000,0x2100,0x2100,0x2100,0x2100,0x3f00,0x2100,0x2100,0x2100,0x2100,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x4800,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x2200,0x2400,0x2800,0x2800,0x3800,0x2800,0x2400,0x2400,0x2200,0x0000,0x0000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x3e00,0x0000,0x0000,\r
+    0x0000,0x2080,0x3180,0x3180,0x3180,0x2a80,0x2a80,0x2a80,0x2a80,0x2480,0x0000,0x0000,\r
+    0x0000,0x2100,0x3100,0x3100,0x2900,0x2900,0x2500,0x2300,0x2300,0x2100,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,\r
+    0x0000,0x3c00,0x2200,0x2200,0x2200,0x3c00,0x2000,0x2000,0x2000,0x2000,0x0000,0x0000,\r
+    0x0000,0x0c00,0x1200,0x2100,0x2100,0x2100,0x2100,0x2100,0x1600,0x0d00,0x0100,0x0000,\r
+    0x0000,0x3e00,0x2100,0x2100,0x2100,0x3e00,0x2400,0x2200,0x2100,0x2080,0x0000,0x0000,\r
+    0x0000,0x1c00,0x2200,0x2200,0x2000,0x1c00,0x0200,0x2200,0x2200,0x1c00,0x0000,0x0000,\r
+    0x0000,0x3e00,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x2100,0x1200,0x0c00,0x0000,0x0000,\r
+    0x0000,0x4100,0x4100,0x2200,0x2200,0x2200,0x1400,0x1400,0x1400,0x0800,0x0000,0x0000,\r
+    0x0000,0x4440,0x4a40,0x2a40,0x2a80,0x2a80,0x2a80,0x2a80,0x2a80,0x1100,0x0000,0x0000,\r
+    0x0000,0x4100,0x2200,0x1400,0x1400,0x0800,0x1400,0x1400,0x2200,0x4100,0x0000,0x0000,\r
+    0x0000,0x4100,0x2200,0x2200,0x1400,0x0800,0x0800,0x0800,0x0800,0x0800,0x0000,0x0000,\r
+    0x0000,0x7e00,0x0200,0x0400,0x0800,0x1000,0x1000,0x2000,0x4000,0x7e00,0x0000,0x0000,\r
+    0x0000,0x3000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x4000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,0x1000,0x1000,0x0000,0x0000,\r
+    0x0000,0x6000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x1000,0x2800,0x2800,0x2800,0x4400,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x7e00,\r
+    0x4000,0x2000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x0400,0x3c00,0x4400,0x4400,0x3c00,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x4000,0x4000,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x0400,0x0400,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x7c00,0x4000,0x4400,0x3800,0x0000,0x0000,\r
+    0x0000,0x6000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x4400,\r
+    0x0000,0x4000,0x4000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,\r
+    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x4000,0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,\r
+    0x0000,0x4000,0x4000,0x4800,0x5000,0x6000,0x5000,0x5000,0x4800,0x4800,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5200,0x6d00,0x4900,0x4900,0x4900,0x4900,0x4900,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x4400,0x4400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3800,0x4400,0x4400,0x4400,0x4400,0x4400,0x3800,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x5800,0x6400,0x4400,0x4400,0x4400,0x6400,0x5800,0x4000,0x4000,\r
+    0x0000,0x0000,0x0000,0x3400,0x4c00,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0400,0x0400,\r
+    0x0000,0x0000,0x0000,0x5000,0x6000,0x4000,0x4000,0x4000,0x4000,0x4000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x3000,0x4800,0x4000,0x3000,0x0800,0x4800,0x3000,0x0000,0x0000,\r
+    0x0000,0x4000,0x4000,0xe000,0x4000,0x4000,0x4000,0x4000,0x4000,0x6000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x4400,0x4400,0x4400,0x4c00,0x3400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x2800,0x1000,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4900,0x4900,0x5500,0x5500,0x5500,0x5500,0x2200,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x2800,0x2800,0x1000,0x2800,0x2800,0x4400,0x0000,0x0000,\r
+    0x0000,0x0000,0x0000,0x4400,0x4400,0x2800,0x2800,0x2800,0x1000,0x1000,0x1000,0x1000,\r
+    0x0000,0x0000,0x0000,0x7800,0x0800,0x1000,0x2000,0x2000,0x4000,0x7800,0x0000,0x0000,\r
+    0x0000,0x1000,0x2000,0x2000,0x2000,0x2000,0x4000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x4000,0x2000,0x2000,0x2000,0x2000,0x1000,0x2000,0x2000,0x2000,0x2000,0x2000,\r
+    0x0000,0x0000,0x0000,0x0000,0x7400,0x5800,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,\r
+    0x0000,0x0000,0x7000,0x5000,0x5000,0x5000,0x5000,0x5000,0x5000,0x7000,0x0000,0x0000};\r
+\r
+const uint16_t ASCII8x12_Table [] = {\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x00,\r
+    0x00,0x00,0x00,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x14,0x14,0x3e,0x14,0x28,0x7c,0x28,0x28,0x00,\r
+    0x00,0x00,0x10,0x38,0x54,0x50,0x38,0x14,0x14,0x54,0x38,0x10,\r
+    0x00,0x00,0x00,0x44,0xa8,0xa8,0x50,0x14,0x1a,0x2a,0x24,0x00,\r
+    0x00,0x00,0x00,0x20,0x50,0x50,0x20,0xe8,0x98,0x98,0x60,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x40,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x40,0xe0,0x40,0xa0,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x20,0x20,0xf8,0x20,0x20,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x20,0x20,0x20,0x40,0x40,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x20,0x60,0xa0,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x10,0x20,0x40,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x60,0x10,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x10,0x30,0x50,0x50,0x90,0xf8,0x10,0x10,0x00,\r
+    0x00,0x00,0x00,0x70,0x40,0x80,0xe0,0x10,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x80,0xa0,0xd0,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0xf0,0x10,0x20,0x20,0x20,0x40,0x40,0x40,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0x60,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x90,0xb0,0x50,0x10,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x10,0x60,0x80,0x60,0x10,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0xf0,0x00,0xf0,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x60,0x80,0x00,0x00,\r
+    0x00,0x00,0x00,0x60,0x90,0x10,0x20,0x40,0x40,0x00,0x40,0x00,\r
+    0x00,0x00,0x00,0x1c,0x22,0x5b,0xa5,0xa5,0xa5,0xa5,0x9e,0x41,\r
+    0x00,0x00,0x00,0x20,0x50,0x50,0x50,0x50,0x70,0x88,0x88,0x00,\r
+    0x00,0x00,0x00,0xf0,0x88,0x88,0xf0,0x88,0x88,0x88,0xf0,0x00,\r
+    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x80,0x84,0x44,0x38,0x00,\r
+    0x00,0x00,0x00,0xe0,0x90,0x88,0x88,0x88,0x88,0x90,0xe0,0x00,\r
+    0x00,0x00,0x00,0xf8,0x80,0x80,0xf8,0x80,0x80,0x80,0xf8,0x00,\r
+    0x00,0x00,0x00,0x78,0x40,0x40,0x70,0x40,0x40,0x40,0x40,0x00,\r
+    0x00,0x00,0x00,0x38,0x44,0x84,0x80,0x9c,0x84,0x44,0x38,0x00,\r
+    0x00,0x00,0x00,0x88,0x88,0x88,0xf8,0x88,0x88,0x88,0x88,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x88,0x90,0xa0,0xe0,0xa0,0x90,0x90,0x88,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0x82,0xc6,0xc6,0xaa,0xaa,0xaa,0xaa,0x92,0x00,\r
+    0x00,0x00,0x00,0x84,0xc4,0xa4,0xa4,0x94,0x94,0x8c,0x84,0x00,\r
+    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x48,0x30,0x00,\r
+    0x00,0x00,0x00,0xf0,0x88,0x88,0x88,0xf0,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x30,0x48,0x84,0x84,0x84,0x84,0x58,0x34,0x04,\r
+    0x00,0x00,0x00,0x78,0x44,0x44,0x78,0x50,0x48,0x44,0x42,0x00,\r
+    0x00,0x00,0x00,0x70,0x88,0x80,0x70,0x08,0x88,0x88,0x70,0x00,\r
+    0x00,0x00,0x00,0xf8,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0x84,0x84,0x84,0x84,0x84,0x84,0x48,0x30,0x00,\r
+    0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x50,0x50,0x20,0x00,\r
+    0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0x44,0x00,\r
+    0x00,0x00,0x00,0x84,0x48,0x48,0x30,0x30,0x48,0x48,0x84,0x00,\r
+    0x00,0x00,0x00,0x88,0x50,0x50,0x20,0x20,0x20,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0xf8,0x08,0x10,0x20,0x20,0x40,0x80,0xf8,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x40,0x40,0x40,0x40,0x20,0x20,0x00,\r
+    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x40,0xa0,0xa0,0xa0,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf8,\r
+    0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xe0,0x10,0x70,0x90,0x90,0x70,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x80,0x80,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x10,0x10,0x50,0xb0,0x90,0x90,0xb0,0x50,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0xf0,0x80,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0xc0,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,\r
+    0x00,0x00,0x00,0x80,0x80,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x80,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x90,0xa0,0xc0,0xa0,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa6,0xda,0x92,0x92,0x92,0x92,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0x90,0x90,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x60,0x90,0x90,0x90,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xd0,0x90,0x90,0xd0,0xa0,0x80,\r
+    0x00,0x00,0x00,0x00,0x00,0x50,0xb0,0x90,0x90,0xb0,0x50,0x10,\r
+    0x00,0x00,0x00,0x00,0x00,0xa0,0xc0,0x80,0x80,0x80,0x80,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0xe0,0x90,0x40,0x20,0x90,0x60,0x00,\r
+    0x00,0x00,0x00,0x80,0x80,0xc0,0x80,0x80,0x80,0x80,0xc0,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x90,0x90,0x90,0x90,0xb0,0x50,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x88,0x50,0x50,0x50,0x20,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x92,0xaa,0xaa,0xaa,0xaa,0x44,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x20,0x20,0x50,0x88,0x00,\r
+    0x00,0x00,0x00,0x00,0x00,0x88,0x50,0x50,0x50,0x20,0x20,0x20,\r
+    0x00,0x00,0x00,0x00,0x00,0xf0,0x10,0x20,0x40,0x80,0xf0,0x00,\r
+    0x00,0x00,0x00,0xc0,0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,\r
+    0x00,0x00,0x00,0xc0,0x40,0x40,0x40,0x20,0x40,0x40,0x40,0x40,\r
+    0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0xb0,0x00,0x00,0x00,0x00,\r
+    0x00,0x00,0x00,0x00,0xe0,0xa0,0xa0,0xa0,0xa0,0xa0,0xe0,0x00};\r
+\r
+const uint16_t ASCII8x8_Table [] = {\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x40,\r
+    0xa0, 0xa0, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x24, 0x24, 0xfe, 0x48, 0xfc, 0x48, 0x48,\r
+    0x38, 0x54, 0x50, 0x38, 0x14, 0x14, 0x54, 0x38,\r
+    0x44, 0xa8, 0xa8, 0x50, 0x14, 0x1a, 0x2a, 0x24,\r
+    0x10, 0x28, 0x28, 0x10, 0x74, 0x4c, 0x4c, 0x30,\r
+    0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08,\r
+    0x10, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x24, 0x18, 0x3c, 0x18, 0x24, 0x00,\r
+    0x00, 0x00, 0x10, 0x10, 0x7c, 0x10, 0x10, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18,\r
+    0x08, 0x08, 0x08, 0x10, 0x10, 0x20, 0x20, 0x20,\r
+    0x18, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0x18,\r
+    0x08, 0x18, 0x28, 0x08, 0x08, 0x08, 0x08, 0x08,\r
+    0x38, 0x44, 0x00, 0x04, 0x08, 0x10, 0x20, 0x7c,\r
+    0x18, 0x24, 0x04, 0x18, 0x04, 0x04, 0x24, 0x18,\r
+    0x04, 0x0c, 0x14, 0x24, 0x44, 0x7e, 0x04, 0x04,\r
+    0x3c, 0x20, 0x20, 0x38, 0x04, 0x04, 0x24, 0x18,\r
+    0x18, 0x24, 0x20, 0x38, 0x24, 0x24, 0x24, 0x18,\r
+    0x3c, 0x04, 0x08, 0x08, 0x08, 0x10, 0x10, 0x10,\r
+    0x18, 0x24, 0x24, 0x18, 0x24, 0x24, 0x24, 0x18,\r
+    0x18, 0x24, 0x24, 0x24, 0x1c, 0x04, 0x24, 0x18,\r
+    0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x00, 0x00,\r
+    0x00, 0x00, 0x08, 0x00, 0x00, 0x08, 0x10, 0x00,\r
+    0x00, 0x00, 0x04, 0x18, 0x20, 0x18, 0x04, 0x00,\r
+    0x00, 0x00, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x00,\r
+    0x00, 0x00, 0x20, 0x18, 0x04, 0x18, 0x20, 0x00,\r
+    0x18, 0x24, 0x04, 0x08, 0x10, 0x10, 0x00, 0x10,\r
+    0x3c, 0x42, 0x99, 0xa5, 0xa5, 0x9d, 0x42, 0x38,\r
+    0x38, 0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44,\r
+    0x78, 0x44, 0x44, 0x78, 0x44, 0x44, 0x44, 0x78,\r
+    0x1c, 0x22, 0x42, 0x40, 0x40, 0x42, 0x22, 0x1c,\r
+    0x70, 0x48, 0x44, 0x44, 0x44, 0x44, 0x48, 0x70,\r
+    0x7c, 0x40, 0x40, 0x7c, 0x40, 0x40, 0x40, 0x7c,\r
+    0x3c, 0x20, 0x20, 0x38, 0x20, 0x20, 0x20, 0x20,\r
+    0x1c, 0x22, 0x42, 0x40, 0x4e, 0x42, 0x22, 0x1c,\r
+    0x44, 0x44, 0x44, 0x7c, 0x44, 0x44, 0x44, 0x44,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x04, 0x04, 0x04, 0x04, 0x04, 0x24, 0x24, 0x18,\r
+    0x44, 0x48, 0x50, 0x70, 0x50, 0x48, 0x48, 0x44,\r
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c,\r
+    0x82, 0xc6, 0xc6, 0xaa, 0xaa, 0xaa, 0xaa, 0x92,\r
+    0x42, 0x62, 0x52, 0x52, 0x4a, 0x4a, 0x46, 0x42,\r
+    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,\r
+    0x78, 0x44, 0x44, 0x44, 0x78, 0x40, 0x40, 0x40,\r
+    0x18, 0x24, 0x42, 0x42, 0x42, 0x42, 0x2c, 0x1a,\r
+    0x78, 0x44, 0x44, 0x78, 0x50, 0x48, 0x44, 0x42,\r
+    0x38, 0x44, 0x40, 0x38, 0x04, 0x44, 0x44, 0x38,\r
+    0x7c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x24, 0x18,\r
+    0x44, 0x44, 0x28, 0x28, 0x28, 0x28, 0x28, 0x10,\r
+    0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,\r
+    0x42, 0x24, 0x24, 0x18, 0x18, 0x24, 0x24, 0x42,\r
+    0x44, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x7c, 0x04, 0x08, 0x10, 0x10, 0x20, 0x40, 0x7c,\r
+    0x1c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1c,\r
+    0x10, 0x10, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04,\r
+    0x1c, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1c,\r
+    0x10, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x20, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+    0x00, 0x00, 0x18, 0x04, 0x1c, 0x24, 0x24, 0x1c,\r
+    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x34, 0x28,\r
+    0x00, 0x00, 0x18, 0x24, 0x20, 0x20, 0x24, 0x18,\r
+    0x04, 0x04, 0x14, 0x2c, 0x24, 0x24, 0x2c, 0x14,\r
+    0x00, 0x00, 0x18, 0x24, 0x3c, 0x20, 0x24, 0x18,\r
+    0x00, 0x18, 0x10, 0x10, 0x18, 0x10, 0x10, 0x10,\r
+    0x00, 0x18, 0x24, 0x24, 0x18, 0x04, 0x24, 0x18,\r
+    0x20, 0x20, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,\r
+    0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x28, 0x10,\r
+    0x20, 0x20, 0x24, 0x28, 0x30, 0x28, 0x24, 0x24,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x00, 0xa6, 0xda, 0x92, 0x92, 0x92, 0x92,\r
+    0x00, 0x00, 0x28, 0x34, 0x24, 0x24, 0x24, 0x24,\r
+    0x00, 0x00, 0x18, 0x24, 0x24, 0x24, 0x24, 0x18,\r
+    0x00, 0x28, 0x34, 0x24, 0x38, 0x20, 0x20, 0x20,\r
+    0x00, 0x14, 0x2c, 0x24, 0x1c, 0x04, 0x04, 0x04,\r
+    0x00, 0x00, 0x2c, 0x30, 0x20, 0x20, 0x20, 0x20,\r
+    0x00, 0x00, 0x18, 0x24, 0x10, 0x08, 0x24, 0x18,\r
+    0x00, 0x10, 0x38, 0x10, 0x10, 0x10, 0x10, 0x18,\r
+    0x00, 0x00, 0x24, 0x24, 0x24, 0x24, 0x2c, 0x14,\r
+    0x00, 0x00, 0x44, 0x44, 0x28, 0x28, 0x28, 0x10,\r
+    0x00, 0x00, 0x92, 0xaa, 0xaa, 0xaa, 0xaa, 0x44,\r
+    0x00, 0x00, 0x44, 0x28, 0x10, 0x10, 0x28, 0x44,\r
+    0x00, 0x28, 0x28, 0x28, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x00, 0x3c, 0x04, 0x08, 0x10, 0x20, 0x3c,\r
+    0x00, 0x08, 0x10, 0x10, 0x20, 0x10, 0x10, 0x08,\r
+    0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,\r
+    0x00, 0x10, 0x08, 0x08, 0x04, 0x08, 0x08, 0x10,\r
+    0x00, 0x00, 0x00, 0x60, 0x92, 0x0c, 0x00, 0x00,\r
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\r
+\r
+\r
+sFONT Font16x24 = {\r
+  ASCII16x24_Table,\r
+  16, /* Width */\r
+  24, /* Height */\r
+};\r
+\r
+sFONT Font12x12 = {\r
+  ASCII12x12_Table,\r
+  12, /* Width */\r
+  12, /* Height */\r
+};\r
+\r
+sFONT Font8x12 = {\r
+  ASCII8x12_Table,\r
+  8, /* Width */\r
+  12, /* Height */\r
+};\r
+\r
+\r
+sFONT Font8x8 = {\r
+  ASCII8x8_Table,\r
+  8, /* Width */\r
+  8, /* Height */\r
+};\r
+   \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Function_Prototypes\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup FONTS_Private_Functions\r
+  * @{\r
+  */\r
+    \r
+/**\r
+  * @}\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */  \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h
new file mode 100644 (file)
index 0000000..00fa116
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/Common/fonts.h
@@ -0,0 +1,117 @@
+/**\r
+  ******************************************************************************\r
+  * @file    fonts.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Header for fonts.c\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __FONTS_H\r
+#define __FONTS_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup Common\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup FONTS\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Types\r
+  * @{\r
+  */ \r
+typedef struct _tFont\r
+{    \r
+  const uint16_t *table;\r
+  uint16_t Width;\r
+  uint16_t Height;\r
+  \r
+} sFONT;\r
+\r
+extern sFONT Font16x24;\r
+extern sFONT Font12x12;\r
+extern sFONT Font8x12;\r
+extern sFONT Font8x8;\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Constants\r
+  * @{\r
+  */ \r
+#define LINE(x) ((x) * (((sFONT *)LCD_GetFont())->Height))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup FONTS_Exported_Functions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+  \r
+#endif /* __FONTS_H */\r
+ \r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */      \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
new file mode 100644 (file)
index 0000000..1f087a7
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.c
@@ -0,0 +1,584 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides\r
+  *            - set of firmware functions to manage Leds, push-button and COM ports\r
+  *            - low level initialization functions for SD card (on SPI) and\r
+  *              temperature sensor (LM75)\r
+  *          available on STM32L152-EVAL evaluation board from STMicroelectronics.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l152_eval.h"\r
+#include "stm32l1xx_spi.h"\r
+#include "stm32l1xx_i2c.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */   \r
+    \r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL \r
+  * @brief This file provides firmware functions to manage Leds, push-buttons, \r
+  *        COM ports, SD card on SPI and temperature sensor (LM75) available on \r
+  *        STM32L152-EVAL evaluation board from STMicroelectronics.\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_TypesDefinitions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Defines\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Variables\r
+  * @{\r
+  */ \r
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,\r
+                                 LED4_GPIO_PORT};\r
+const uint16_t GPIO_PIN[LEDn] = {LED1_PIN, LED2_PIN, LED3_PIN,\r
+                                 LED4_PIN};\r
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,\r
+                                 LED4_GPIO_CLK};\r
+\r
+GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_GPIO_PORT, TAMPER_BUTTON_GPIO_PORT,\r
+                                      KEY_BUTTON_GPIO_PORT, RIGHT_BUTTON_GPIO_PORT,\r
+                                      LEFT_BUTTON_GPIO_PORT, UP_BUTTON_GPIO_PORT,\r
+                                      DOWN_BUTTON_GPIO_PORT, SEL_BUTTON_GPIO_PORT}; \r
+\r
+const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,\r
+                                      KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,\r
+                                      LEFT_BUTTON_PIN, UP_BUTTON_PIN,\r
+                                      DOWN_BUTTON_PIN, SEL_BUTTON_PIN}; \r
+\r
+const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_GPIO_CLK, TAMPER_BUTTON_GPIO_CLK,\r
+                                      KEY_BUTTON_GPIO_CLK, RIGHT_BUTTON_GPIO_CLK,\r
+                                      LEFT_BUTTON_GPIO_CLK, UP_BUTTON_GPIO_CLK,\r
+                                      DOWN_BUTTON_GPIO_CLK, SEL_BUTTON_GPIO_CLK};\r
+\r
+const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,\r
+                                            TAMPER_BUTTON_EXTI_LINE, \r
+                                            KEY_BUTTON_EXTI_LINE,\r
+                                            RIGHT_BUTTON_EXTI_LINE,\r
+                                            LEFT_BUTTON_EXTI_LINE,\r
+                                            UP_BUTTON_EXTI_LINE,\r
+                                            DOWN_BUTTON_EXTI_LINE,\r
+                                            SEL_BUTTON_EXTI_LINE};\r
+\r
+const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PORT_SOURCE,\r
+                                              TAMPER_BUTTON_EXTI_PORT_SOURCE, \r
+                                              KEY_BUTTON_EXTI_PORT_SOURCE,\r
+                                              RIGHT_BUTTON_EXTI_PORT_SOURCE,\r
+                                              LEFT_BUTTON_EXTI_PORT_SOURCE,\r
+                                              UP_BUTTON_EXTI_PORT_SOURCE,\r
+                                              DOWN_BUTTON_EXTI_PORT_SOURCE,\r
+                                              SEL_BUTTON_EXTI_PORT_SOURCE};\r
+                                                                \r
+const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_EXTI_PIN_SOURCE,\r
+                                             TAMPER_BUTTON_EXTI_PIN_SOURCE, \r
+                                             KEY_BUTTON_EXTI_PIN_SOURCE,\r
+                                             RIGHT_BUTTON_EXTI_PIN_SOURCE,\r
+                                             LEFT_BUTTON_EXTI_PIN_SOURCE,\r
+                                             UP_BUTTON_EXTI_PIN_SOURCE,\r
+                                             DOWN_BUTTON_EXTI_PIN_SOURCE,\r
+                                             SEL_BUTTON_EXTI_PIN_SOURCE}; \r
+                                             \r
+const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_EXTI_IRQn, TAMPER_BUTTON_EXTI_IRQn,\r
+                                       KEY_BUTTON_EXTI_IRQn, RIGHT_BUTTON_EXTI_IRQn,\r
+                                       LEFT_BUTTON_EXTI_IRQn, UP_BUTTON_EXTI_IRQn,\r
+                                       DOWN_BUTTON_EXTI_IRQn, SEL_BUTTON_EXTI_IRQn};\r
+\r
+USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2}; \r
+\r
+GPIO_TypeDef* COM_TX_PORT[COMn] = {EVAL_COM1_TX_GPIO_PORT, EVAL_COM2_TX_GPIO_PORT};\r
+ \r
+GPIO_TypeDef* COM_RX_PORT[COMn] = {EVAL_COM1_RX_GPIO_PORT, EVAL_COM2_RX_GPIO_PORT};\r
+\r
+const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};\r
+\r
+const uint32_t COM_TX_PORT_CLK[COMn] = {EVAL_COM1_TX_GPIO_CLK, EVAL_COM2_TX_GPIO_CLK};\r
+ \r
+const uint32_t COM_RX_PORT_CLK[COMn] = {EVAL_COM1_RX_GPIO_CLK, EVAL_COM2_RX_GPIO_CLK};\r
+\r
+const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN};\r
+\r
+const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};\r
+ \r
+const uint16_t COM_TX_PIN_SOURCE[COMn] = {EVAL_COM1_TX_SOURCE, EVAL_COM2_TX_SOURCE};\r
+\r
+const uint16_t COM_RX_PIN_SOURCE[COMn] = {EVAL_COM1_RX_SOURCE, EVAL_COM2_RX_SOURCE};\r
+ \r
+const uint16_t COM_TX_AF[COMn] = {EVAL_COM1_TX_AF, EVAL_COM2_TX_AF};\r
+ \r
+const uint16_t COM_RX_AF[COMn] = {EVAL_COM1_RX_AF, EVAL_COM2_RX_AF};\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_FunctionPrototypes\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Private_Functions\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @brief  Configures LED GPIO.\r
+  * @param  Led: Specifies the Led to be configured. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4\r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  \r
+  /* Enable the GPIO_LED Clock */\r
+  RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);\r
+\r
+  /* Configure the GPIO_LED pin */\r
+  GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);\r
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Turns selected LED On.\r
+  * @param  Led: Specifies the Led to be set on. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDOn(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Turns selected LED Off.\r
+  * @param  Led: Specifies the Led to be set off. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4 \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDOff(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led];  \r
+}\r
+\r
+/**\r
+  * @brief  Toggles the selected LED.\r
+  * @param  Led: Specifies the Led to be toggled. \r
+  *   This parameter can be one of following parameters:\r
+  *     @arg LED1\r
+  *     @arg LED2\r
+  *     @arg LED3\r
+  *     @arg LED4  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led)\r
+{\r
+  GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];\r
+}\r
+\r
+/**\r
+  * @brief  Configures Button GPIO and EXTI Line.\r
+  * @param  Button: Specifies the Button to be configured.\r
+  *   This parameter can be one of following parameters:   \r
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button\r
+  *     @arg BUTTON_TAMPER: Tamper Push Button  \r
+  *     @arg BUTTON_KEY: Key Push Button \r
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button \r
+  *     @arg BUTTON_LEFT: Joystick Left Push Button \r
+  *     @arg BUTTON_UP: Joystick Up Push Button \r
+  *     @arg BUTTON_DOWN: Joystick Down Push Button\r
+  *     @arg BUTTON_SEL: Joystick Sel Push Button\r
+  * @param  Button_Mode: Specifies Button mode.\r
+  *   This parameter can be one of following parameters:   \r
+  *     @arg BUTTON_MODE_GPIO: Button will be used as simple IO \r
+  *     @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt\r
+  *                     generation capability  \r
+  * @retval None\r
+  */\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+  EXTI_InitTypeDef EXTI_InitStructure;\r
+  NVIC_InitTypeDef NVIC_InitStructure;\r
+\r
+  /* Enable the BUTTON Clock */\r
+  RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);\r
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+  /* Configure Button pin as input */\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];\r
+  GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);\r
+\r
+\r
+  if (Button_Mode == BUTTON_MODE_EXTI)\r
+  {\r
+    /* Connect Button EXTI Line to Button GPIO Pin */\r
+    SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);\r
+\r
+    /* Configure Button EXTI line */\r
+    EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];\r
+    EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;\r
+    \r
+    if((Button != BUTTON_WAKEUP) && (Button != BUTTON_KEY) && (Button != BUTTON_TAMPER))\r
+    {\r
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;  \r
+    }\r
+    else\r
+    {\r
+      EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;  \r
+    }\r
+    EXTI_InitStructure.EXTI_LineCmd = ENABLE;\r
+    EXTI_Init(&EXTI_InitStructure);\r
+\r
+    /* Enable and set Button EXTI Interrupt to the lowest priority */\r
+    NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];\r
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;\r
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;\r
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
+\r
+    NVIC_Init(&NVIC_InitStructure); \r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Returns the selected Button state.\r
+  * @param  Button: Specifies the Button to be checked.\r
+  *   This parameter can be one of following parameters:    \r
+  *     @arg BUTTON_WAKEUP: Wakeup Push Button\r
+  *     @arg BUTTON_TAMPER: Tamper Push Button  \r
+  *     @arg BUTTON_KEY: Key Push Button \r
+  *     @arg BUTTON_RIGHT: Joystick Right Push Button \r
+  *     @arg BUTTON_LEFT: Joystick Left Push Button \r
+  *     @arg BUTTON_UP: Joystick Up Push Button \r
+  *     @arg BUTTON_DOWN: Joystick Down Push Button\r
+  *     @arg BUTTON_SEL: Joystick Sel Push Button    \r
+  * @retval The Button GPIO pin value.\r
+  */\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)\r
+{\r
+  return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures COM port.\r
+  * @param  COM: Specifies the COM port to be configured.\r
+  *   This parameter can be one of following parameters:    \r
+  *     @arg COM1\r
+  *     @arg COM2  \r
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that\r
+  *   contains the configuration information for the specified USART peripheral.\r
+  * @retval None\r
+  */\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  /* Enable GPIO clock */\r
+  RCC_AHBPeriphClockCmd(COM_TX_PORT_CLK[COM] | COM_RX_PORT_CLK[COM], ENABLE);\r
+\r
+  /* Enable UART clock */\r
+  RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);\r
+\r
+  /* Connect PXx to USARTx_Tx*/\r
+  GPIO_PinAFConfig(COM_TX_PORT[COM], COM_TX_PIN_SOURCE[COM], COM_TX_AF[COM]);\r
+\r
+  /* Connect PXx to USARTx_Rx*/\r
+  GPIO_PinAFConfig(COM_RX_PORT[COM], COM_RX_PIN_SOURCE[COM], COM_RX_AF[COM]);\r
+  \r
+  /* Configure USART Tx as alternate function push-pull */\r
+  GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_Init(COM_TX_PORT[COM], &GPIO_InitStructure);\r
+    \r
+  /* Configure USART Rx as input floating */\r
+  GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];\r
+  GPIO_Init(COM_RX_PORT[COM], &GPIO_InitStructure);\r
+\r
+  /* USART configuration */\r
+  USART_Init(COM_USART[COM], USART_InitStruct);\r
+    \r
+  /* Enable USART */\r
+  USART_Cmd(COM_USART[COM], ENABLE);\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the SPI interface.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SD_LowLevel_DeInit(void)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  \r
+  SPI_Cmd(SD_SPI, DISABLE); /*!< SD_SPI disable */\r
+  SPI_DeInit(SD_SPI);   /*!< DeInitializes the SD_SPI */\r
+  \r
+  /*!< SD_SPI Periph clock disable */\r
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, DISABLE); \r
+\r
+  /*!< Configure SD_SPI pins: SCK */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MISO */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the SD Card and put it into StandBy State (Ready for \r
+  *         data transfer).\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SD_LowLevel_Init(void)\r
+{\r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+  SPI_InitTypeDef   SPI_InitStructure;\r
+\r
+  /*!< SD_SPI_CS_GPIO, SD_SPI_MOSI_GPIO, SD_SPI_MISO_GPIO, SD_SPI_DETECT_GPIO \r
+       and SD_SPI_SCK_GPIO Periph clock enable */\r
+  RCC_AHBPeriphClockCmd(SD_CS_GPIO_CLK | SD_SPI_MOSI_GPIO_CLK | SD_SPI_MISO_GPIO_CLK |\r
+                        SD_SPI_SCK_GPIO_CLK | SD_DETECT_GPIO_CLK, ENABLE);\r
+\r
+  /*!< SD_SPI Periph clock enable */\r
+  RCC_APB1PeriphClockCmd(SD_SPI_CLK, ENABLE); \r
+\r
+  /*!< Configure SD_SPI pins: SCK */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;\r
+  GPIO_Init(SD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MISO */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MISO_PIN;\r
+  GPIO_Init(SD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI pins: MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = SD_SPI_MOSI_PIN;\r
+  GPIO_Init(SD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_CS_PIN pin: SD Card CS pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_CS_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_Init(SD_CS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure SD_SPI_DETECT_PIN pin: SD Card detect pin */\r
+  GPIO_InitStructure.GPIO_Pin = SD_DETECT_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;\r
+  GPIO_Init(SD_DETECT_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Connect PXx to SD_SPI_SCK */\r
+  GPIO_PinAFConfig(SD_SPI_SCK_GPIO_PORT, SD_SPI_SCK_SOURCE, SD_SPI_SCK_AF);\r
+\r
+  /* Connect PXx to SD_SPI_MISO */\r
+  GPIO_PinAFConfig(SD_SPI_MISO_GPIO_PORT, SD_SPI_MISO_SOURCE, SD_SPI_MISO_AF); \r
+\r
+  /* Connect PXx to SD_SPI_MOSI */\r
+  GPIO_PinAFConfig(SD_SPI_MOSI_GPIO_PORT, SD_SPI_MOSI_SOURCE, SD_SPI_MOSI_AF);  \r
+  \r
+  /*!< SD_SPI Config */\r
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;\r
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;\r
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+\r
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+  SPI_InitStructure.SPI_CRCPolynomial = 7;\r
+  SPI_Init(SD_SPI, &SPI_InitStructure);\r
+  \r
+  SPI_Cmd(SD_SPI, ENABLE); /*!< SD_SPI enable */\r
+}\r
+\r
+/**\r
+  * @brief  DeInitializes the LM75_I2C.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LM75_LowLevel_DeInit(void)\r
+{ \r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+\r
+  /*!< Disable LM75_I2C */\r
+  I2C_Cmd(LM75_I2C, DISABLE);\r
+  \r
+  /*!< DeInitializes the LM75_I2C */\r
+  I2C_DeInit(LM75_I2C);\r
+  \r
+  /*!< LM75_I2C Periph clock disable */\r
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, DISABLE);\r
+    \r
+  /*!< Configure LM75_I2C pins: SCL */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pins: SDA */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the LM75_I2C.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LM75_LowLevel_Init(void)\r
+{ \r
+  GPIO_InitTypeDef  GPIO_InitStructure;\r
+\r
+  /*!< LM75_I2C Periph clock enable */\r
+  RCC_APB1PeriphClockCmd(LM75_I2C_CLK, ENABLE);\r
+    \r
+  /*!< LM75_I2C_SCL_GPIO_CLK, LM75_I2C_SDA_GPIO_CLK \r
+       and LM75_I2C_SMBUSALERT_GPIO_CLK Periph clock enable */\r
+  RCC_AHBPeriphClockCmd(LM75_I2C_SCL_GPIO_CLK | LM75_I2C_SDA_GPIO_CLK |\r
+                        LM75_I2C_SMBUSALERT_GPIO_CLK, ENABLE);\r
+  \r
+  /*!< Configure LM75_I2C pins: SCL */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SCL_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;\r
+  GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LM75_I2C_SCL_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pins: SDA */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SDA_PIN;\r
+  GPIO_Init(LM75_I2C_SDA_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /*!< Configure LM75_I2C pin: SMBUS ALERT */\r
+  GPIO_InitStructure.GPIO_Pin = LM75_I2C_SMBUSALERT_PIN;\r
+  GPIO_Init(LM75_I2C_SMBUSALERT_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+\r
+  /* Connect PXx to I2C_SCL */\r
+  GPIO_PinAFConfig(LM75_I2C_SCL_GPIO_PORT, LM75_I2C_SCL_SOURCE, LM75_I2C_SCL_AF);\r
+\r
+  /* Connect PXx to I2C_SDA */\r
+  GPIO_PinAFConfig(LM75_I2C_SDA_GPIO_PORT, LM75_I2C_SDA_SOURCE, LM75_I2C_SDA_AF); \r
+\r
+  /* Connect PXx to I2C_SMBUSALER */\r
+  GPIO_PinAFConfig(LM75_I2C_SMBUSALERT_GPIO_PORT, LM75_I2C_SMBUSALERT_SOURCE, LM75_I2C_SMBUSALERT_AF);     \r
+}\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */    \r
+\r
+/**\r
+  * @}\r
+  */ \r
+    \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
new file mode 100644 (file)
index 0000000..56df0fb
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval.h
@@ -0,0 +1,337 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains definitions for STM32L152_EVAL's Leds, push-buttons\r
+  *          and COM ports hardware resources.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L152_EVAL_H\r
+#define __STM32L152_EVAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32_eval.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+      \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Types\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Constants\r
+  * @{\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_LED\r
+  * @{\r
+  */\r
+#define LEDn                             4\r
+\r
+#define LED1_PIN                         GPIO_Pin_0\r
+#define LED1_GPIO_PORT                   GPIOD\r
+#define LED1_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED2_PIN                         GPIO_Pin_1\r
+#define LED2_GPIO_PORT                   GPIOD\r
+#define LED2_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED3_PIN                         GPIO_Pin_4\r
+#define LED3_GPIO_PORT                   GPIOD\r
+#define LED3_GPIO_CLK                    RCC_AHBPeriph_GPIOD  \r
+  \r
+#define LED4_PIN                         GPIO_Pin_5\r
+#define LED4_GPIO_PORT                   GPIOD\r
+#define LED4_GPIO_CLK                    RCC_AHBPeriph_GPIOD\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_BUTTON\r
+  * @{\r
+  */  \r
+#define BUTTONn                          8 \r
+\r
+/**\r
+ * @brief Wakeup push-button\r
+ */\r
+#define WAKEUP_BUTTON_PIN                GPIO_Pin_13\r
+#define WAKEUP_BUTTON_GPIO_PORT          GPIOC\r
+#define WAKEUP_BUTTON_GPIO_CLK           RCC_AHBPeriph_GPIOC\r
+#define WAKEUP_BUTTON_EXTI_LINE          EXTI_Line13\r
+#define WAKEUP_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOC\r
+#define WAKEUP_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource13\r
+#define WAKEUP_BUTTON_EXTI_IRQn          EXTI15_10_IRQn \r
+\r
+/**\r
+ * @brief Tamper push-button\r
+ */\r
+#define TAMPER_BUTTON_PIN                GPIO_Pin_13\r
+#define TAMPER_BUTTON_GPIO_PORT          GPIOC\r
+#define TAMPER_BUTTON_GPIO_CLK           RCC_AHBPeriph_GPIOC\r
+#define TAMPER_BUTTON_EXTI_LINE          EXTI_Line13\r
+#define TAMPER_BUTTON_EXTI_PORT_SOURCE   EXTI_PortSourceGPIOC\r
+#define TAMPER_BUTTON_EXTI_PIN_SOURCE    EXTI_PinSource13\r
+#define TAMPER_BUTTON_EXTI_IRQn          EXTI15_10_IRQn \r
+\r
+/**\r
+ * @brief Key push-button\r
+ */\r
+#define KEY_BUTTON_PIN                   GPIO_Pin_13\r
+#define KEY_BUTTON_GPIO_PORT             GPIOC\r
+#define KEY_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOC\r
+#define KEY_BUTTON_EXTI_LINE             EXTI_Line13\r
+#define KEY_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOC\r
+#define KEY_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource13\r
+#define KEY_BUTTON_EXTI_IRQn             EXTI15_10_IRQn\r
+\r
+/**\r
+ * @brief Joystick Right push-button\r
+ */\r
+#define RIGHT_BUTTON_PIN                 GPIO_Pin_11\r
+#define RIGHT_BUTTON_GPIO_PORT           GPIOE\r
+#define RIGHT_BUTTON_GPIO_CLK            RCC_AHBPeriph_GPIOE\r
+#define RIGHT_BUTTON_EXTI_LINE           EXTI_Line11\r
+#define RIGHT_BUTTON_EXTI_PORT_SOURCE    EXTI_PortSourceGPIOE\r
+#define RIGHT_BUTTON_EXTI_PIN_SOURCE     EXTI_PinSource11\r
+#define RIGHT_BUTTON_EXTI_IRQn           EXTI15_10_IRQn\r
+\r
+/**\r
+ * @brief Joystick Left push-button\r
+ */\r
+#define LEFT_BUTTON_PIN                  GPIO_Pin_12\r
+#define LEFT_BUTTON_GPIO_PORT            GPIOE\r
+#define LEFT_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE\r
+#define LEFT_BUTTON_EXTI_LINE            EXTI_Line12\r
+#define LEFT_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE\r
+#define LEFT_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource12\r
+#define LEFT_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Up push-button\r
+ */\r
+#define UP_BUTTON_PIN                    GPIO_Pin_9\r
+#define UP_BUTTON_GPIO_PORT              GPIOE\r
+#define UP_BUTTON_GPIO_CLK               RCC_AHBPeriph_GPIOE\r
+#define UP_BUTTON_EXTI_LINE              EXTI_Line9\r
+#define UP_BUTTON_EXTI_PORT_SOURCE       EXTI_PortSourceGPIOE\r
+#define UP_BUTTON_EXTI_PIN_SOURCE        EXTI_PinSource9\r
+#define UP_BUTTON_EXTI_IRQn              EXTI9_5_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Down push-button\r
+ */  \r
+#define DOWN_BUTTON_PIN                  GPIO_Pin_10\r
+#define DOWN_BUTTON_GPIO_PORT            GPIOE\r
+#define DOWN_BUTTON_GPIO_CLK             RCC_AHBPeriph_GPIOE\r
+#define DOWN_BUTTON_EXTI_LINE            EXTI_Line10\r
+#define DOWN_BUTTON_EXTI_PORT_SOURCE     EXTI_PortSourceGPIOE\r
+#define DOWN_BUTTON_EXTI_PIN_SOURCE      EXTI_PinSource10\r
+#define DOWN_BUTTON_EXTI_IRQn            EXTI15_10_IRQn  \r
+\r
+/**\r
+ * @brief Joystick Sel push-button\r
+ */\r
+#define SEL_BUTTON_PIN                   GPIO_Pin_8\r
+#define SEL_BUTTON_GPIO_PORT             GPIOE\r
+#define SEL_BUTTON_GPIO_CLK              RCC_AHBPeriph_GPIOE\r
+#define SEL_BUTTON_EXTI_LINE             EXTI_Line8\r
+#define SEL_BUTTON_EXTI_PORT_SOURCE      EXTI_PortSourceGPIOE\r
+#define SEL_BUTTON_EXTI_PIN_SOURCE       EXTI_PinSource8\r
+#define SEL_BUTTON_EXTI_IRQn             EXTI9_5_IRQn \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_COM\r
+  * @{\r
+  */\r
+#define COMn                             2\r
+\r
+/**\r
+ * @brief Definition for COM port1, connected to USART2\r
+ */ \r
+#define EVAL_COM1                        USART2\r
+#define EVAL_COM1_CLK                    RCC_APB1Periph_USART2\r
+#define EVAL_COM1_TX_PIN                 GPIO_Pin_5\r
+#define EVAL_COM1_TX_GPIO_PORT           GPIOD\r
+#define EVAL_COM1_TX_GPIO_CLK            RCC_AHBPeriph_GPIOD\r
+#define EVAL_COM1_TX_SOURCE              GPIO_PinSource5\r
+#define EVAL_COM1_TX_AF                  GPIO_AF_USART2\r
+#define EVAL_COM1_RX_PIN                 GPIO_Pin_6\r
+#define EVAL_COM1_RX_GPIO_PORT           GPIOD\r
+#define EVAL_COM1_RX_GPIO_CLK            RCC_AHBPeriph_GPIOD\r
+#define EVAL_COM1_RX_SOURCE              GPIO_PinSource6\r
+#define EVAL_COM1_RX_AF                  GPIO_AF_USART2\r
+#define EVAL_COM1_IRQn                   USART2_IRQn\r
+\r
+/**\r
+ * @brief Definition for COM port2, connected to USART3\r
+ */ \r
+#define EVAL_COM2                        USART3\r
+#define EVAL_COM2_CLK                    RCC_APB1Periph_USART3\r
+\r
+#define EVAL_COM2_TX_PIN                 GPIO_Pin_10\r
+#define EVAL_COM2_TX_GPIO_PORT           GPIOC\r
+#define EVAL_COM2_TX_GPIO_CLK            RCC_AHBPeriph_GPIOC\r
+#define EVAL_COM2_TX_SOURCE              GPIO_PinSource10\r
+#define EVAL_COM2_TX_AF                  GPIO_AF_USART3\r
+\r
+#define EVAL_COM2_RX_PIN                 GPIO_Pin_11\r
+#define EVAL_COM2_RX_GPIO_PORT           GPIOC\r
+#define EVAL_COM2_RX_GPIO_CLK            RCC_AHBPeriph_GPIOC\r
+#define EVAL_COM2_RX_SOURCE              GPIO_PinSource11\r
+#define EVAL_COM2_RX_AF                  GPIO_AF_USART3\r
+#define EVAL_COM2_IRQn                   USART3_IRQn\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_SD_FLASH\r
+  * @{\r
+  */ \r
+/**\r
+  * @brief  SD Card SPI Interface\r
+  */  \r
+#define SD_SPI                           SPI2\r
+#define SD_SPI_CLK                       RCC_APB1Periph_SPI2\r
+#define SD_SPI_SCK_PIN                   GPIO_Pin_13                 /* PB.13 */\r
+#define SD_SPI_SCK_GPIO_PORT             GPIOB                       /* GPIOB */\r
+#define SD_SPI_SCK_GPIO_CLK              RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_SCK_SOURCE                GPIO_PinSource13\r
+#define SD_SPI_SCK_AF                    GPIO_AF_SPI2\r
+#define SD_SPI_MISO_PIN                  GPIO_Pin_14                 /* PB.14 */\r
+#define SD_SPI_MISO_GPIO_PORT            GPIOB                       /* GPIOB */\r
+#define SD_SPI_MISO_GPIO_CLK             RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_MISO_SOURCE               GPIO_PinSource14\r
+#define SD_SPI_MISO_AF                   GPIO_AF_SPI2\r
+#define SD_SPI_MOSI_PIN                  GPIO_Pin_15                 /* PB.15 */\r
+#define SD_SPI_MOSI_GPIO_PORT            GPIOB                       /* GPIOB */\r
+#define SD_SPI_MOSI_GPIO_CLK             RCC_AHBPeriph_GPIOB\r
+#define SD_SPI_MOSI_SOURCE               GPIO_PinSource15\r
+#define SD_SPI_MOSI_AF                   GPIO_AF_SPI2\r
+#define SD_CS_PIN                        GPIO_Pin_7                  /* PD.07 */\r
+#define SD_CS_GPIO_PORT                  GPIOD                       /* GPIOD */\r
+#define SD_CS_GPIO_CLK                   RCC_AHBPeriph_GPIOD\r
+#define SD_DETECT_PIN                    GPIO_Pin_7                  /* PE.07 */\r
+#define SD_DETECT_GPIO_PORT              GPIOE                       /* GPIOE */\r
+#define SD_DETECT_GPIO_CLK               RCC_AHBPeriph_GPIOE\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @addtogroup STM32L152_EVAL_LOW_LEVEL_TSENSOR_I2C\r
+  * @{\r
+  */\r
+/**\r
+  * @brief  LM75 Temperature Sensor I2C Interface pins\r
+  */  \r
+#define LM75_I2C                         I2C1\r
+#define LM75_I2C_CLK                     RCC_APB1Periph_I2C1\r
+#define LM75_I2C_SCL_PIN                 GPIO_Pin_6                  /* PB.06 */\r
+#define LM75_I2C_SCL_GPIO_PORT           GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SCL_GPIO_CLK            RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SCL_SOURCE              GPIO_PinSource6\r
+#define LM75_I2C_SCL_AF                  GPIO_AF_I2C1\r
+#define LM75_I2C_SDA_PIN                 GPIO_Pin_7                  /* PB.07 */\r
+#define LM75_I2C_SDA_GPIO_PORT           GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SDA_GPIO_CLK            RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SDA_SOURCE              GPIO_PinSource7\r
+#define LM75_I2C_SDA_AF                  GPIO_AF_I2C1\r
+#define LM75_I2C_SMBUSALERT_PIN          GPIO_Pin_5                  /* PB.05 */\r
+#define LM75_I2C_SMBUSALERT_GPIO_PORT    GPIOB                       /* GPIOB */\r
+#define LM75_I2C_SMBUSALERT_GPIO_CLK     RCC_AHBPeriph_GPIOB\r
+#define LM75_I2C_SMBUSALERT_SOURCE       GPIO_PinSource5\r
+#define LM75_I2C_SMBUSALERT_AF           GPIO_AF_I2C1\r
+/**\r
+  * @}\r
+  */  \r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Macros\r
+  * @{\r
+  */  \r
+/**\r
+  * @}\r
+  */ \r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LOW_LEVEL_Exported_Functions\r
+  * @{\r
+  */\r
+void STM_EVAL_LEDInit(Led_TypeDef Led);\r
+void STM_EVAL_LEDOn(Led_TypeDef Led);\r
+void STM_EVAL_LEDOff(Led_TypeDef Led);\r
+void STM_EVAL_LEDToggle(Led_TypeDef Led);\r
+void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);\r
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);\r
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct); \r
+void SD_LowLevel_DeInit(void);\r
+void SD_LowLevel_Init(void); \r
+void LM75_LowLevel_DeInit(void);\r
+void LM75_LowLevel_Init(void);  \r
+/**\r
+  * @}\r
+  */\r
+  \r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L152_EVAL_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */  \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
new file mode 100644 (file)
index 0000000..8c3f05a
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.c
@@ -0,0 +1,1528 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval_lcd.c\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),\r
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module\r
+  *          of STM32L152-EVAL board.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l152_eval_lcd.h"\r
+#include "../Common/fonts.c"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD\r
+  * @brief   This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320),\r
+  *          AM-240320LDTNQW00H (LCD_SPFD5408B) Liquid Crystal Display Module\r
+  *          of STM32L152-EVAL board.\r
+  * @{\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Types\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Defines\r
+  * @{\r
+  */\r
+#define LCD_ILI9320        0x9320\r
+#define LCD_SPFD5408       0x5408\r
+#define START_BYTE         0x70\r
+#define SET_INDEX          0x00\r
+#define READ_STATUS        0x01\r
+#define LCD_WRITE_REG      0x02\r
+#define LCD_READ_REG       0x03\r
+#define MAX_POLY_CORNERS   200\r
+#define POLY_Y(Z)          ((int32_t)((Points + Z)->X))\r
+#define POLY_X(Z)          ((int32_t)((Points + Z)->Y))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Macros\r
+  * @{\r
+  */\r
+#define ABS(X)  ((X) > 0 ? (X) : -(X))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Variables\r
+  * @{\r
+  */\r
+static sFONT *LCD_Currentfonts;\r
+/* Global variables to set the written text color */\r
+static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;\r
+static __IO uint32_t LCDType = LCD_SPFD5408;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Function_Prototypes\r
+  * @{\r
+  */\r
+#ifndef USE_Delay\r
+static void delay(__IO uint32_t nCount);\r
+#endif /* USE_Delay*/\r
+\r
+static void PutPixel(int16_t x, int16_t y);\r
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  DeInitializes the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void STM32L152_LCD_DeInit(void)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  /*!< LCD Display Off */\r
+  LCD_DisplayOff();\r
+\r
+  /*!< LCD_SPI disable */\r
+  SPI_Cmd(LCD_SPI, DISABLE);\r
+\r
+  /*!< LCD_SPI DeInit */\r
+  SPI_DeInit(LCD_SPI);\r
+\r
+  /*!< Disable SPI clock  */\r
+  RCC_APB1PeriphClockCmd(LCD_SPI_CLK, DISABLE);\r
+\r
+  /* Configure NCS in Output Push-Pull mode */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure SPI pins: SCK, MISO and MOSI */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;\r
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;\r
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;\r
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+}\r
+\r
+/**\r
+  * @brief  Setups the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_Setup(void)\r
+{\r
+/* Configure the LCD Control pins --------------------------------------------*/\r
+  LCD_CtrlLinesConfig();\r
+\r
+/* Configure the LCD_SPI interface ----------------------------------------------*/\r
+  LCD_SPIConfig();\r
+\r
+  if(LCDType == LCD_SPFD5408)\r
+  {\r
+    /* Start Initial Sequence --------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_227, 0x3008); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_231, 0x0012); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_239, 0x1231); /* Set internal timing */\r
+    LCD_WriteReg(LCD_REG_1, 0x0100);   /* Set SS and SM bit */\r
+    LCD_WriteReg(LCD_REG_2, 0x0700);   /* Set 1 line inversion */\r
+    LCD_WriteReg(LCD_REG_3, 0x1030);   /* Set GRAM write direction and BGR=1. */\r
+    LCD_WriteReg(LCD_REG_4, 0x0000);   /* Resize register */\r
+    LCD_WriteReg(LCD_REG_8, 0x0202);   /* Set the back porch and front porch */\r
+    LCD_WriteReg(LCD_REG_9, 0x0000);   /* Set non-display area refresh cycle ISC[3:0] */\r
+    LCD_WriteReg(LCD_REG_10, 0x0000);  /* FMARK function */\r
+    LCD_WriteReg(LCD_REG_12, 0x0000);  /* RGB interface setting */\r
+    LCD_WriteReg(LCD_REG_13, 0x0000);  /* Frame marker Position */\r
+    LCD_WriteReg(LCD_REG_15, 0x0000);  /* RGB interface polarity */\r
+    /* Power On sequence -------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_16, 0x0000);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0000);  /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    LCD_WriteReg(LCD_REG_18, 0x0000);  /* VREG1OUT voltage */\r
+    LCD_WriteReg(LCD_REG_19, 0x0000);  /* VDV[4:0] for VCOM amplitude */\r
+    _delay_(20);                /* Dis-charge capacitor power voltage (200ms) */\r
+    LCD_WriteReg(LCD_REG_17, 0x0007);  /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_16, 0x12B0);  /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    _delay_(5);                  /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_18, 0x01BD);  /* External reference voltage= Vci */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_19, 0x1400);       /* VDV[4:0] for VCOM amplitude */\r
+    LCD_WriteReg(LCD_REG_41, 0x000E);  /* VCM[4:0] for VCOMH */\r
+    _delay_(5);                 /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_32, 0x0000);  /* GRAM horizontal Address */\r
+    LCD_WriteReg(LCD_REG_33, 0x013F);  /* GRAM Vertical Address */\r
+    /* Adjust the Gamma Curve --------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_48, 0x0007);\r
+    LCD_WriteReg(LCD_REG_49, 0x0302);\r
+    LCD_WriteReg(LCD_REG_50, 0x0105);\r
+    LCD_WriteReg(LCD_REG_53, 0x0206);\r
+    LCD_WriteReg(LCD_REG_54, 0x0808);\r
+    LCD_WriteReg(LCD_REG_55, 0x0206);\r
+    LCD_WriteReg(LCD_REG_56, 0x0504);\r
+    LCD_WriteReg(LCD_REG_57, 0x0007);\r
+    LCD_WriteReg(LCD_REG_60, 0x0105);\r
+    LCD_WriteReg(LCD_REG_61, 0x0808);\r
+    /* Set GRAM area -----------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_80, 0x0000);  /* Horizontal GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_81, 0x00EF);  /* Horizontal GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_82, 0x0000);  /* Vertical GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_83, 0x013F);  /* Vertical GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_96,  0xA700); /* Gate Scan Line */\r
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */\r
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* Set scrolling line */\r
+    /* Partial Display Control -------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_128, 0x0000);\r
+    LCD_WriteReg(LCD_REG_129, 0x0000);\r
+    LCD_WriteReg(LCD_REG_130, 0x0000);\r
+    LCD_WriteReg(LCD_REG_131, 0x0000);\r
+    LCD_WriteReg(LCD_REG_132, 0x0000);\r
+    LCD_WriteReg(LCD_REG_133, 0x0000);\r
+    /* Panel Control -----------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_144, 0x0010);\r
+    LCD_WriteReg(LCD_REG_146, 0x0000);\r
+    LCD_WriteReg(LCD_REG_147, 0x0003);\r
+    LCD_WriteReg(LCD_REG_149, 0x0110);\r
+    LCD_WriteReg(LCD_REG_151, 0x0000);\r
+    LCD_WriteReg(LCD_REG_152, 0x0000);\r
+    /* Set GRAM write direction and BGR = 1\r
+       I/D=01 (Horizontal : increment, Vertical : decrement)\r
+       AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+    LCD_WriteReg(LCD_REG_7, 0x0112);   /* 262K color and display ON */\r
+  }\r
+  else if(LCDType == LCD_ILI9320)\r
+  {\r
+    _delay_(5); /* Delay 50 ms */\r
+    /* Start Initial Sequence ------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */\r
+    LCD_WriteReg(LCD_REG_0,  0x0001); /* Start internal OSC. */\r
+    LCD_WriteReg(LCD_REG_1,  0x0100); /* set SS and SM bit */\r
+    LCD_WriteReg(LCD_REG_2,  0x0700); /* set 1 line inversion */\r
+    LCD_WriteReg(LCD_REG_3,  0x1030); /* set GRAM write direction and BGR=1. */\r
+    LCD_WriteReg(LCD_REG_4,  0x0000); /* Resize register */\r
+    LCD_WriteReg(LCD_REG_8,  0x0202); /* set the back porch and front porch */\r
+    LCD_WriteReg(LCD_REG_9,  0x0000); /* set non-display area refresh cycle ISC[3:0] */\r
+    LCD_WriteReg(LCD_REG_10, 0x0000); /* FMARK function */\r
+    LCD_WriteReg(LCD_REG_12, 0x0000); /* RGB interface setting */\r
+    LCD_WriteReg(LCD_REG_13, 0x0000); /* Frame marker Position */\r
+    LCD_WriteReg(LCD_REG_15, 0x0000); /* RGB interface polarity */\r
+    /* Power On sequence -----------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */\r
+    LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */\r
+    _delay_(20);                      /* Dis-charge capacitor power voltage (200ms) */\r
+    LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+    LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */\r
+    LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */\r
+    _delay_(5);                       /* Delay 50 ms */\r
+    LCD_WriteReg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */\r
+    LCD_WriteReg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */\r
+    /* Adjust the Gamma Curve ------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_48, 0x0006);\r
+    LCD_WriteReg(LCD_REG_49, 0x0101);\r
+    LCD_WriteReg(LCD_REG_50, 0x0003);\r
+    LCD_WriteReg(LCD_REG_53, 0x0106);\r
+    LCD_WriteReg(LCD_REG_54, 0x0b02);\r
+    LCD_WriteReg(LCD_REG_55, 0x0302);\r
+    LCD_WriteReg(LCD_REG_56, 0x0707);\r
+    LCD_WriteReg(LCD_REG_57, 0x0007);\r
+    LCD_WriteReg(LCD_REG_60, 0x0600);\r
+    LCD_WriteReg(LCD_REG_61, 0x020b);\r
+\r
+    /* Set GRAM area ---------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_81, 0x00EF); /* Horizontal GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */\r
+    LCD_WriteReg(LCD_REG_83, 0x013F); /* Vertical GRAM End Address */\r
+    LCD_WriteReg(LCD_REG_96,  0x2700); /* Gate Scan Line */\r
+    LCD_WriteReg(LCD_REG_97,  0x0001); /* NDL,VLE, REV */\r
+    LCD_WriteReg(LCD_REG_106, 0x0000); /* set scrolling line */\r
+    /* Partial Display Control -----------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_128, 0x0000);\r
+    LCD_WriteReg(LCD_REG_129, 0x0000);\r
+    LCD_WriteReg(LCD_REG_130, 0x0000);\r
+    LCD_WriteReg(LCD_REG_131, 0x0000);\r
+    LCD_WriteReg(LCD_REG_132, 0x0000);\r
+    LCD_WriteReg(LCD_REG_133, 0x0000);\r
+    /* Panel Control ---------------------------------------------------------*/\r
+    LCD_WriteReg(LCD_REG_144, 0x0010);\r
+    LCD_WriteReg(LCD_REG_146, 0x0000);\r
+    LCD_WriteReg(LCD_REG_147, 0x0003);\r
+    LCD_WriteReg(LCD_REG_149, 0x0110);\r
+    LCD_WriteReg(LCD_REG_151, 0x0000);\r
+    LCD_WriteReg(LCD_REG_152, 0x0000);\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D=01 (Horizontal : increment, Vertical : decrement) */\r
+    /* AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+    LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Initializes the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void STM32L152_LCD_Init(void)\r
+{\r
+  /* Setups the LCD */\r
+  LCD_Setup();\r
+\r
+  /* Try to read new LCD controller ID 0x5408 */\r
+  if (LCD_ReadReg(LCD_REG_0) == LCD_SPFD5408)\r
+  {\r
+    LCDType = LCD_SPFD5408;\r
+  }\r
+  else\r
+  {\r
+    LCDType = LCD_ILI9320;\r
+    /* Setups the LCD */\r
+    LCD_Setup();\r
+  }\r
+\r
+  LCD_SetFont(&LCD_DEFAULT_FONT);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the LCD Text and Background colors.\r
+  * @param  _TextColor: specifies the Text Color.\r
+  * @param  _BackColor: specifies the Background Color.\r
+  * @retval None\r
+  */\r
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor)\r
+{\r
+  TextColor = _TextColor;\r
+  BackColor = _BackColor;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the LCD Text and Background colors.\r
+  * @param  _TextColor: pointer to the variable that will contain the Text\r
+            Color.\r
+  * @param  _BackColor: pointer to the variable that will contain the Background\r
+            Color.\r
+  * @retval None\r
+  */\r
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor)\r
+{\r
+  *_TextColor = TextColor; *_BackColor = BackColor;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the Text color.\r
+  * @param  Color: specifies the Text color code RGB(5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_SetTextColor(__IO uint16_t Color)\r
+{\r
+  TextColor = Color;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets the Background color.\r
+  * @param  Color: specifies the Background color code RGB(5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_SetBackColor(__IO uint16_t Color)\r
+{\r
+  BackColor = Color;\r
+}\r
+\r
+/**\r
+  * @brief  Sets the Text Font.\r
+  * @param  fonts: specifies the font to be used.\r
+  * @retval None\r
+  */\r
+void LCD_SetFont(sFONT *fonts)\r
+{\r
+  LCD_Currentfonts = fonts;\r
+}\r
+\r
+/**\r
+  * @brief  Gets the Text Font.\r
+  * @param  None.\r
+  * @retval the used font.\r
+  */\r
+sFONT *LCD_GetFont(void)\r
+{\r
+  return LCD_Currentfonts;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the selected line.\r
+  * @param  Line: the Line to be cleared.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..n\r
+  * @retval None\r
+  */\r
+void LCD_ClearLine(uint8_t Line)\r
+{\r
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;\r
+\r
+  /* Send the string character by character on lCD */\r
+  while (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width)\r
+  {\r
+    /* Display one character on LCD */\r
+    LCD_DisplayChar(Line, refcolumn, ' ');\r
+    /* Decrement the column position by 16 */\r
+    refcolumn -= LCD_Currentfonts->Width;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Clears the hole LCD.\r
+  * @param  Color: the color of the background.\r
+  * @retval None\r
+  */\r
+void LCD_Clear(uint16_t Color)\r
+{\r
+  uint32_t index = 0;\r
+\r
+  LCD_SetCursor(0x00, 0x013F);\r
+\r
+  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+  for(index = 0; index < 76800; index++)\r
+  {\r
+    LCD_WriteRAM(Color);\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets the cursor position.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @retval None\r
+  */\r
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)\r
+{\r
+  LCD_WriteReg(LCD_REG_32, Xpos);\r
+  LCD_WriteReg(LCD_REG_33, Ypos);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Draws a character on LCD.\r
+  * @param  Xpos: the Line where to display the character shape.\r
+  * @param  Ypos: start column address.\r
+  * @param  c: pointer to the character data.\r
+  * @retval None\r
+  */\r
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)\r
+{\r
+  uint32_t index = 0, i = 0;\r
+  uint8_t Xaddress = 0;\r
+\r
+  Xaddress = Xpos;\r
+\r
+  LCD_SetCursor(Xaddress, Ypos);\r
+\r
+  for(index = 0; index < LCD_Currentfonts->Height; index++)\r
+  {\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+    for(i = 0; i < LCD_Currentfonts->Width; i++)\r
+    {\r
+      if((((c[index] & ((0x80 << ((LCD_Currentfonts->Width / 12 ) * 8 ) ) >> i)) == 0x00) &&(LCD_Currentfonts->Width <= 12))||\r
+        (((c[index] & (0x1 << i)) == 0x00)&&(LCD_Currentfonts->Width > 12 )))\r
+\r
+      {\r
+        LCD_WriteRAM(BackColor);\r
+      }\r
+      else\r
+      {\r
+        LCD_WriteRAM(TextColor);\r
+      }\r
+    }\r
+\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+    Xaddress++;\r
+    LCD_SetCursor(Xaddress, Ypos);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays one character (16dots width, 24dots height).\r
+  * @param  Line: the Line where to display the character shape .\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..9\r
+  * @param  Column: start column address.\r
+  * @param  Ascii: character ascii code, must be between 0x20 and 0x7E.\r
+  * @retval None\r
+  */\r
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)\r
+{\r
+  Ascii -= 32;\r
+  LCD_DrawChar(Line, Column, &LCD_Currentfonts->table[Ascii * LCD_Currentfonts->Height]);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a maximum of 20 char on the LCD.\r
+  * @param  Line: the Line where to display the character shape .\r
+  *   This parameter can be one of the following values:\r
+  *     @arg Linex: where x can be 0..9\r
+  * @param  *ptr: pointer to string to display on LCD.\r
+  * @retval None\r
+  */\r
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)\r
+{\r
+  uint16_t refcolumn = LCD_PIXEL_WIDTH - 1;\r
+\r
+  /* Send the string character by character on lCD */\r
+  while ((*ptr != 0) & (((refcolumn + 1) & 0xFFFF) >= LCD_Currentfonts->Width))\r
+  {\r
+    /* Display one character on LCD */\r
+    LCD_DisplayChar(Line, refcolumn, *ptr);\r
+    /* Decrement the column position by 16 */\r
+    refcolumn -= LCD_Currentfonts->Width;\r
+    /* Point on the next character */\r
+    ptr++;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets a display window\r
+  * @param  Xpos: specifies the X buttom left position.\r
+  * @param  Ypos: specifies the Y buttom left position.\r
+  * @param  Height: display window height.\r
+  * @param  Width: display window width.\r
+  * @retval None\r
+  */\r
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)\r
+{\r
+  /* Horizontal GRAM Start Address */\r
+  if(Xpos >= Height)\r
+  {\r
+    LCD_WriteReg(LCD_REG_80, (Xpos - Height + 1));\r
+  }\r
+  else\r
+  {\r
+    LCD_WriteReg(LCD_REG_80, 0);\r
+  }\r
+  /* Horizontal GRAM End Address */\r
+  LCD_WriteReg(LCD_REG_81, Xpos);\r
+  /* Vertical GRAM Start Address */\r
+  if(Ypos >= Width)\r
+  {\r
+    LCD_WriteReg(LCD_REG_82, (Ypos - Width + 1));\r
+  }\r
+  else\r
+  {\r
+    LCD_WriteReg(LCD_REG_82, 0);\r
+  }\r
+  /* Vertical GRAM End Address */\r
+  LCD_WriteReg(LCD_REG_83, Ypos);\r
+\r
+  LCD_SetCursor(Xpos, Ypos);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Disables LCD Window mode.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_WindowModeDisable(void)\r
+{\r
+  LCD_SetDisplayWindow(239, 0x13F, 240, 320);\r
+  LCD_WriteReg(LCD_REG_3, 0x1018);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a line.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Length: line length.\r
+  * @param  Direction: line direction.\r
+  *   This parameter can be one of the following values: Vertical or Horizontal.\r
+  * @retval None\r
+  */\r
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)\r
+{\r
+  uint32_t i = 0;\r
+\r
+  LCD_SetCursor(Xpos, Ypos);\r
+\r
+  if(Direction == LCD_DIR_HORIZONTAL)\r
+  {\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+    for(i = 0; i < Length; i++)\r
+    {\r
+      LCD_WriteRAM(TextColor);\r
+    }\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+  }\r
+  else\r
+  {\r
+    for(i = 0; i < Length; i++)\r
+    {\r
+      LCD_WriteRAMWord(TextColor);\r
+      Xpos++;\r
+      LCD_SetCursor(Xpos, Ypos);\r
+    }\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a rectangle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Height: display rectangle height.\r
+  * @param  Width: display rectangle width.\r
+  * @retval None\r
+  */\r
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)\r
+{\r
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);\r
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a circle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Radius\r
+  * @retval None\r
+  */\r
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+  int32_t  D;/* Decision Variable */\r
+  uint32_t  CurX;/* Current X Value */\r
+  uint32_t  CurY;/* Current Y Value */\r
+\r
+  D = 3 - (Radius << 1);\r
+  CurX = 0;\r
+  CurY = Radius;\r
+\r
+  while (CurX <= CurY)\r
+  {\r
+    LCD_SetCursor(Xpos + CurX, Ypos + CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+    LCD_SetCursor(Xpos + CurX, Ypos - CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurX, Ypos + CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurX, Ypos - CurY);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos + CurY, Ypos + CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos + CurY, Ypos - CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurY, Ypos + CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    LCD_SetCursor(Xpos - CurY, Ypos - CurX);\r
+    LCD_WriteRAMWord(TextColor);\r
+\r
+    if (D < 0)\r
+    {\r
+      D += (CurX << 2) + 6;\r
+    }\r
+    else\r
+    {\r
+      D += ((CurX - CurY) << 2) + 10;\r
+      CurY--;\r
+    }\r
+    CurX++;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a monocolor picture.\r
+  * @param  Pict: pointer to the picture array.\r
+  * @retval None\r
+  */\r
+void LCD_DrawMonoPict(const uint32_t *Pict)\r
+{\r
+  uint32_t index = 0, i = 0;\r
+  LCD_SetCursor(0, (LCD_PIXEL_WIDTH - 1));\r
+\r
+  LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+\r
+  for(index = 0; index < 2400; index++)\r
+  {\r
+    for(i = 0; i < 32; i++)\r
+    {\r
+      if((Pict[index] & (1 << i)) == 0x00)\r
+      {\r
+        LCD_WriteRAM(BackColor);\r
+      }\r
+      else\r
+      {\r
+        LCD_WriteRAM(TextColor);\r
+      }\r
+    }\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+#ifdef USE_LCD_DrawBMP\r
+/**\r
+  * @brief  Displays a bitmap picture loaded in the SPI Flash.\r
+  * @param  BmpAddress: Bmp picture address in the SPI Flash.\r
+  * @retval None\r
+  */\r
+void LCD_DrawBMP(uint32_t BmpAddress)\r
+{\r
+  uint32_t i = 0, size = 0;\r
+  /* Read bitmap size */\r
+  SPI_FLASH_BufferRead((uint8_t*)&size, BmpAddress + 2, 4);\r
+  /* get bitmap data address offset */\r
+  SPI_FLASH_BufferRead((uint8_t*)&i, BmpAddress + 10, 4);\r
+\r
+  size = (size - i)/2;\r
+  SPI_FLASH_StartReadSequence(BmpAddress + i);\r
+  /* Disable SPI1  */\r
+  SPI_Cmd(SPI1, DISABLE);\r
+  /* SPI in 16-bit mode */\r
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);\r
+  /* Enable SPI1  */\r
+  SPI_Cmd(SPI1, ENABLE);\r
+\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D=00 (Horizontal : decrement, Vertical : decrement) */\r
+    /* AM=1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1008);\r
+    LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */\r
+  }\r
+\r
+  /* Read bitmap data from SPI Flash and send them to LCD */\r
+  for(i = 0; i < size; i++)\r
+  {\r
+    LCD_WriteRAM(__REV16(SPI_FLASH_SendHalfWord(0xA5A5)));\r
+  }\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+  }\r
+\r
+  /* Deselect the FLASH: Chip Select high */\r
+  SPI_FLASH_CS_HIGH();\r
+  /* Disable SPI1  */\r
+  SPI_Cmd(SPI1, DISABLE);\r
+  /* SPI in 8-bit mode */\r
+  SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);\r
+  /* Enable SPI1  */\r
+  SPI_Cmd(SPI1, ENABLE);\r
+\r
+  if((LCDType == LCD_ILI9320) || (LCDType == LCD_SPFD5408))\r
+  {\r
+    /* Set GRAM write direction and BGR = 1 */\r
+    /* I/D = 01 (Horizontal : increment, Vertical : decrement) */\r
+    /* AM = 1 (address is updated in vertical writing direction) */\r
+    LCD_WriteReg(LCD_REG_3, 0x1018);\r
+  }\r
+}\r
+#endif /* USE_LCD_DrawBMP */\r
+\r
+/**\r
+  * @brief  Displays a full rectangle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Height: rectangle height.\r
+  * @param  Width: rectangle width.\r
+  * @retval None\r
+  */\r
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)\r
+{\r
+  LCD_SetTextColor(TextColor);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  LCD_DrawLine((Xpos + Height), Ypos, Width, LCD_DIR_HORIZONTAL);\r
+\r
+  LCD_DrawLine(Xpos, Ypos, Height, LCD_DIR_VERTICAL);\r
+  LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, LCD_DIR_VERTICAL);\r
+\r
+  Width -= 2;\r
+  Height--;\r
+  Ypos--;\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  while(Height--)\r
+  {\r
+    LCD_DrawLine(++Xpos, Ypos, Width, LCD_DIR_HORIZONTAL);\r
+  }\r
+\r
+  LCD_SetTextColor(TextColor);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a full circle.\r
+  * @param  Xpos: specifies the X position.\r
+  * @param  Ypos: specifies the Y position.\r
+  * @param  Radius\r
+  * @retval None\r
+  */\r
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)\r
+{\r
+  int32_t  D;    /* Decision Variable */\r
+  uint32_t  CurX;/* Current X Value */\r
+  uint32_t  CurY;/* Current Y Value */\r
+\r
+  D = 3 - (Radius << 1);\r
+\r
+  CurX = 0;\r
+  CurY = Radius;\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  while (CurX <= CurY)\r
+  {\r
+    if(CurY > 0)\r
+    {\r
+      LCD_DrawLine(Xpos - CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);\r
+      LCD_DrawLine(Xpos + CurX, Ypos + CurY, 2*CurY, LCD_DIR_HORIZONTAL);\r
+    }\r
+\r
+    if(CurX > 0)\r
+    {\r
+      LCD_DrawLine(Xpos - CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);\r
+      LCD_DrawLine(Xpos + CurY, Ypos + CurX, 2*CurX, LCD_DIR_HORIZONTAL);\r
+    }\r
+    if (D < 0)\r
+    {\r
+      D += (CurX << 2) + 6;\r
+    }\r
+    else\r
+    {\r
+      D += ((CurX - CurY) << 2) + 10;\r
+      CurY--;\r
+    }\r
+    CurX++;\r
+  }\r
+\r
+  LCD_SetTextColor(TextColor);\r
+  LCD_DrawCircle(Xpos, Ypos, Radius);\r
+}\r
+\r
+/**\r
+  * @brief  Displays an uni line (between two points).\r
+  * @param  x1: specifies the point 1 x position.\r
+  * @param  y1: specifies the point 1 y position.\r
+  * @param  x2: specifies the point 2 x position.\r
+  * @param  y2: specifies the point 2 y position.\r
+  * @retval None\r
+  */\r
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)\r
+{\r
+  int16_t deltax = 0, deltay = 0, x = 0, y = 0, xinc1 = 0, xinc2 = 0,\r
+  yinc1 = 0, yinc2 = 0, den = 0, num = 0, numadd = 0, numpixels = 0,\r
+  curpixel = 0;\r
+\r
+  deltax = ABS(x2 - x1);        /* The difference between the x's */\r
+  deltay = ABS(y2 - y1);        /* The difference between the y's */\r
+  x = x1;                       /* Start x off at the first pixel */\r
+  y = y1;                       /* Start y off at the first pixel */\r
+\r
+  if (x2 >= x1)                 /* The x-values are increasing */\r
+  {\r
+    xinc1 = 1;\r
+    xinc2 = 1;\r
+  }\r
+  else                          /* The x-values are decreasing */\r
+  {\r
+    xinc1 = -1;\r
+    xinc2 = -1;\r
+  }\r
+\r
+  if (y2 >= y1)                 /* The y-values are increasing */\r
+  {\r
+    yinc1 = 1;\r
+    yinc2 = 1;\r
+  }\r
+  else                          /* The y-values are decreasing */\r
+  {\r
+    yinc1 = -1;\r
+    yinc2 = -1;\r
+  }\r
+\r
+  if (deltax >= deltay)         /* There is at least one x-value for every y-value */\r
+  {\r
+    xinc1 = 0;                  /* Don't change the x when numerator >= denominator */\r
+    yinc2 = 0;                  /* Don't change the y for every iteration */\r
+    den = deltax;\r
+    num = deltax / 2;\r
+    numadd = deltay;\r
+    numpixels = deltax;         /* There are more x-values than y-values */\r
+  }\r
+  else                          /* There is at least one y-value for every x-value */\r
+  {\r
+    xinc2 = 0;                  /* Don't change the x for every iteration */\r
+    yinc1 = 0;                  /* Don't change the y when numerator >= denominator */\r
+    den = deltay;\r
+    num = deltay / 2;\r
+    numadd = deltax;\r
+    numpixels = deltay;         /* There are more y-values than x-values */\r
+  }\r
+\r
+  for (curpixel = 0; curpixel <= numpixels; curpixel++)\r
+  {\r
+    PutPixel(x, y);             /* Draw the current pixel */\r
+    num += numadd;              /* Increase the numerator by the top of the fraction */\r
+    if (num >= den)             /* Check if numerator >= denominator */\r
+    {\r
+      num -= den;               /* Calculate the new numerator value */\r
+      x += xinc1;               /* Change the x as appropriate */\r
+      y += yinc1;               /* Change the y as appropriate */\r
+    }\r
+    x += xinc2;                 /* Change the x as appropriate */\r
+    y += yinc2;                 /* Change the y as appropriate */\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays an polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_PolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  int16_t X = 0, Y = 0;\r
+\r
+  if(PointCount < 2)\r
+  {\r
+    return;\r
+  }\r
+\r
+  while(--PointCount)\r
+  {\r
+    X = Points->X;\r
+    Y = Points->Y;\r
+    Points++;\r
+    LCD_DrawUniLine(X, Y, Points->X, Points->Y);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays an relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @param  Closed: specifies if the draw is closed or not.\r
+  *           1: closed, 0 : not closed.\r
+  * @retval None\r
+  */\r
+static void LCD_PolyLineRelativeClosed(pPoint Points, uint16_t PointCount, uint16_t Closed)\r
+{\r
+  int16_t X = 0, Y = 0;\r
+  pPoint First = Points;\r
+\r
+  if(PointCount < 2)\r
+  {\r
+    return;\r
+  }\r
+  X = Points->X;\r
+  Y = Points->Y;\r
+  while(--PointCount)\r
+  {\r
+    Points++;\r
+    LCD_DrawUniLine(X, Y, X + Points->X, Y + Points->Y);\r
+    X = X + Points->X;\r
+    Y = Y + Points->Y;\r
+  }\r
+  if(Closed)\r
+  {\r
+    LCD_DrawUniLine(First->X, First->Y, X, Y);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Displays a closed polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLine(Points, PointCount);\r
+  LCD_DrawUniLine(Points->X, Points->Y, (Points+PointCount-1)->X, (Points+PointCount-1)->Y);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLineRelativeClosed(Points, PointCount, 0);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a closed relative polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount)\r
+{\r
+  LCD_PolyLineRelativeClosed(Points, PointCount, 1);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Displays a  full polyline (between many points).\r
+  * @param  Points: pointer to the points array.\r
+  * @param  PointCount: Number of points.\r
+  * @retval None\r
+  */\r
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount)\r
+{\r
+  /*  public-domain code by Darel Rex Finley, 2007 */\r
+  uint16_t  nodes = 0, nodeX[MAX_POLY_CORNERS], pixelX = 0, pixelY = 0, i = 0,\r
+  j = 0, swap = 0;\r
+  uint16_t  IMAGE_LEFT = 0, IMAGE_RIGHT = 0, IMAGE_TOP = 0, IMAGE_BOTTOM = 0;\r
+\r
+  IMAGE_LEFT = IMAGE_RIGHT = Points->X;\r
+  IMAGE_TOP= IMAGE_BOTTOM = Points->Y;\r
+\r
+  for(i = 1; i < PointCount; i++)\r
+  {\r
+    pixelX = POLY_X(i);\r
+    if(pixelX < IMAGE_LEFT)\r
+    {\r
+      IMAGE_LEFT = pixelX;\r
+    }\r
+    if(pixelX > IMAGE_RIGHT)\r
+    {\r
+      IMAGE_RIGHT = pixelX;\r
+    }\r
+\r
+    pixelY = POLY_Y(i);\r
+    if(pixelY < IMAGE_TOP)\r
+    {\r
+      IMAGE_TOP = pixelY;\r
+    }\r
+    if(pixelY > IMAGE_BOTTOM)\r
+    {\r
+      IMAGE_BOTTOM = pixelY;\r
+    }\r
+  }\r
+\r
+  LCD_SetTextColor(BackColor);\r
+\r
+  /*  Loop through the rows of the image. */\r
+  for (pixelY = IMAGE_TOP; pixelY < IMAGE_BOTTOM; pixelY++)\r
+  {\r
+    /* Build a list of nodes. */\r
+    nodes = 0; j = PointCount-1;\r
+\r
+    for (i = 0; i < PointCount; i++)\r
+    {\r
+      if (POLY_Y(i)<(double) pixelY && POLY_Y(j)>=(double) pixelY || POLY_Y(j)<(double) pixelY && POLY_Y(i)>=(double) pixelY)\r
+      {\r
+        nodeX[nodes++]=(int) (POLY_X(i)+((pixelY-POLY_Y(i))*(POLY_X(j)-POLY_X(i)))/(POLY_Y(j)-POLY_Y(i)));\r
+      }\r
+      j = i;\r
+    }\r
+\r
+    /* Sort the nodes, via a simple \93Bubble\94 sort. */\r
+    i = 0;\r
+    while (i < nodes-1)\r
+    {\r
+      if (nodeX[i]>nodeX[i+1])\r
+      {\r
+        swap = nodeX[i];\r
+        nodeX[i] = nodeX[i+1];\r
+        nodeX[i+1] = swap;\r
+        if(i)\r
+        {\r
+          i--;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        i++;\r
+      }\r
+    }\r
+\r
+    /*  Fill the pixels between node pairs. */\r
+    for (i = 0; i < nodes; i+=2)\r
+    {\r
+      if(nodeX[i] >= IMAGE_RIGHT)\r
+      {\r
+        break;\r
+      }\r
+      if(nodeX[i+1] > IMAGE_LEFT)\r
+      {\r
+        if (nodeX[i] < IMAGE_LEFT)\r
+        {\r
+          nodeX[i]=IMAGE_LEFT;\r
+        }\r
+        if(nodeX[i+1] > IMAGE_RIGHT)\r
+        {\r
+          nodeX[i+1] = IMAGE_RIGHT;\r
+        }\r
+        LCD_SetTextColor(BackColor);\r
+        LCD_DrawLine(pixelY, nodeX[i+1], nodeX[i+1] - nodeX[i], LCD_DIR_HORIZONTAL);\r
+        LCD_SetTextColor(TextColor);\r
+        PutPixel(pixelY, nodeX[i+1]);\r
+        PutPixel(pixelY, nodeX[i]);\r
+        /* for (j=nodeX[i]; j<nodeX[i+1]; j++) PutPixel(j,pixelY); */\r
+      }\r
+    }\r
+  }\r
+\r
+  /* draw the edges */\r
+  LCD_SetTextColor(TextColor);\r
+}\r
+\r
+/**\r
+  * @brief  Reset LCD control line(/CS) and Send Start-Byte\r
+  * @param  Start_Byte: the Start-Byte to be sent\r
+  * @retval None\r
+  */\r
+void LCD_nCS_StartByte(uint8_t Start_Byte)\r
+{\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);\r
+\r
+  SPI_SendData(LCD_SPI, Start_Byte);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes index to select the LCD register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @retval None\r
+  */\r
+void LCD_WriteRegIndex(uint8_t LCD_Reg)\r
+{\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | SET_INDEX);\r
+\r
+  /* Write 16-bit Reg Index (High Byte is 0) */\r
+  SPI_SendData(LCD_SPI, 0x00);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, LCD_Reg);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes to the selected LCD ILI9320 register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @param  LCD_RegValue: value to write to the selected register.\r
+  * @retval None\r
+  */\r
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)\r
+{\r
+  /* Write 16-bit Index (then Write Reg) */\r
+  LCD_WriteRegIndex(LCD_Reg);\r
+\r
+  /* Write 16-bit Reg */\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);\r
+\r
+  SPI_SendData(LCD_SPI, LCD_RegValue >> 8);\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, (LCD_RegValue & 0xFF));\r
+\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Reads the selected LCD Register.\r
+  * @param  LCD_Reg: address of the selected register.\r
+  * @retval LCD Register Value.\r
+  */\r
+uint16_t LCD_ReadReg(uint8_t LCD_Reg)\r
+{\r
+  uint16_t tmp = 0;\r
+  uint8_t i = 0;\r
+\r
+  /* LCD_SPI prescaler: 4 */\r
+  LCD_SPI->CR1 &= 0xFFC7;\r
+  LCD_SPI->CR1 |= 0x0008;\r
+  /* Write 16-bit Index (then Read Reg) */\r
+  LCD_WriteRegIndex(LCD_Reg);\r
+  /* Read 16-bit Reg */\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);\r
+\r
+  for(i = 0; i < 5; i++)\r
+  {\r
+    SPI_SendData(LCD_SPI, 0xFF);\r
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+    {\r
+    }\r
+    /* One byte of invalid dummy data read after the start byte */\r
+    while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+    {\r
+    }\r
+    SPI_ReceiveData(LCD_SPI);\r
+  }\r
+\r
+  SPI_SendData(LCD_SPI, 0xFF);\r
+\r
+  /* Read upper byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  /* Read lower byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+  {\r
+  }\r
+  tmp = SPI_ReceiveData(LCD_SPI);\r
+\r
+\r
+  SPI_SendData(LCD_SPI, 0xFF);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+\r
+  /* Read lower byte */\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_RXNE) == RESET)\r
+  {\r
+  }\r
+\r
+  tmp = ((tmp & 0xFF) << 8) | SPI_ReceiveData(LCD_SPI);\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+\r
+  /* LCD_SPI prescaler: 2 */\r
+  LCD_SPI->CR1 &= 0xFFC7;\r
+\r
+  return tmp;\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Prepare to write to the LCD RAM.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAM_Prepare(void)\r
+{\r
+  LCD_WriteRegIndex(LCD_REG_34); /* Select GRAM Reg */\r
+\r
+  /* Reset LCD control line(/CS) and Send Start-Byte */\r
+  LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Writes 1 word to the LCD RAM.\r
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAMWord(uint16_t RGB_Code)\r
+{\r
+  LCD_WriteRAM_Prepare();\r
+\r
+  LCD_WriteRAM(RGB_Code);\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+/**\r
+  * @brief  Writes to the LCD RAM.\r
+  * @param  RGB_Code: the pixel color in RGB mode (5-6-5).\r
+  * @retval None\r
+  */\r
+void LCD_WriteRAM(uint16_t RGB_Code)\r
+{\r
+  SPI_SendData(LCD_SPI, RGB_Code >> 8);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+  SPI_SendData(LCD_SPI, RGB_Code & 0xFF);\r
+  while(SPI_GetFlagStatus(LCD_SPI, SPI_FLAG_BSY) != RESET)\r
+  {\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Power on the LCD.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_PowerOn(void)\r
+{\r
+  /* Power On sequence ---------------------------------------------------------*/\r
+  LCD_WriteReg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+  LCD_WriteReg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+  LCD_WriteReg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */\r
+  LCD_WriteReg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */\r
+  _delay_(20);                 /* Dis-charge capacitor power voltage (200ms) */\r
+  LCD_WriteReg(LCD_REG_16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */\r
+  LCD_WriteReg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */\r
+  _delay_(5);                /* Delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */\r
+  _delay_(5);                /* delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */\r
+  LCD_WriteReg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */\r
+  _delay_(5);                /* delay 50 ms */\r
+  LCD_WriteReg(LCD_REG_7, 0x0173);  /* 262K color and display ON */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Enables the Display.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_DisplayOn(void)\r
+{\r
+  /* Display On */\r
+  LCD_WriteReg(LCD_REG_7, 0x0173); /* 262K color and display ON */\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Disables the Display.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_DisplayOff(void)\r
+{\r
+  /* Display Off */\r
+  LCD_WriteReg(LCD_REG_7, 0x0);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures LCD control lines in Output Push-Pull mode.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_CtrlLinesConfig(void)\r
+{\r
+  GPIO_InitTypeDef GPIO_InitStructure;\r
+\r
+  RCC_AHBPeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);\r
+\r
+  /* Configure NCS (PF.02) in Output Push-Pull mode */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Sets or reset LCD control lines.\r
+  * @param  GPIOx: where x can be B or D to select the GPIO peripheral.\r
+  * @param  CtrlPins: the Control line.\r
+  *   This parameter can be:\r
+  *     @arg LCD_NCS_PIN: Chip Select pin\r
+  *     @arg LCD_NWR_PIN: Read/Write Selection pin\r
+  *     @arg LCD_RS_PIN: Register/RAM Selection pin\r
+  * @param  BitVal: specifies the value to be written to the selected bit.\r
+  *   This parameter can be:\r
+  *     @arg Bit_RESET: to clear the port pin\r
+  *     @arg Bit_SET: to set the port pin\r
+  * @retval None\r
+  */\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)\r
+{\r
+  /* Set or Reset the control line */\r
+  GPIO_WriteBit(GPIOx, CtrlPins, BitVal);\r
+}\r
+\r
+\r
+/**\r
+  * @brief  Configures the LCD_SPI interface.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void LCD_SPIConfig(void)\r
+{\r
+  SPI_InitTypeDef    SPI_InitStructure;\r
+  GPIO_InitTypeDef   GPIO_InitStructure;\r
+\r
+  /* Enable LCD_SPI_SCK_GPIO_CLK, LCD_SPI_MISO_GPIO_CLK and LCD_SPI_MOSI_GPIO_CLK clock */\r
+  RCC_AHBPeriphClockCmd(LCD_SPI_SCK_GPIO_CLK | LCD_SPI_MISO_GPIO_CLK | LCD_SPI_MOSI_GPIO_CLK, ENABLE);\r
+\r
+  /* Enable LCD_SPI and SYSCFG clock  */\r
+  RCC_APB2PeriphClockCmd(LCD_SPI_CLK | RCC_APB2Periph_SYSCFG, ENABLE);\r
+\r
+  /* Configure LCD_SPI SCK pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN;\r
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;\r
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;\r
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+  GPIO_Init(LCD_SPI_SCK_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure LCD_SPI MISO pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MISO_PIN;\r
+  GPIO_Init(LCD_SPI_MISO_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Configure LCD_SPI MOSI pin */\r
+  GPIO_InitStructure.GPIO_Pin = LCD_SPI_MOSI_PIN;\r
+  GPIO_Init(LCD_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure);\r
+\r
+  /* Connect PE.13 to SPI SCK */\r
+  GPIO_PinAFConfig(LCD_SPI_SCK_GPIO_PORT, LCD_SPI_SCK_SOURCE, LCD_SPI_SCK_AF);\r
+\r
+  /* Connect PE.14 to SPI MISO */\r
+  GPIO_PinAFConfig(LCD_SPI_MISO_GPIO_PORT, LCD_SPI_MISO_SOURCE, LCD_SPI_MISO_AF);\r
+\r
+  /* Connect PE.15 to SPI MOSI */\r
+  GPIO_PinAFConfig(LCD_SPI_MOSI_GPIO_PORT, LCD_SPI_MOSI_SOURCE, LCD_SPI_MOSI_AF);\r
+\r
+  SPI_DeInit(LCD_SPI);\r
+\r
+  /* SPI Config */\r
+  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;\r
+  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;\r
+  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;\r
+  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;\r
+  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;\r
+  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;\r
+  SPI_InitStructure.SPI_CRCPolynomial = 7;\r
+  SPI_Init(LCD_SPI, &SPI_InitStructure);\r
+\r
+  /* SPI enable */\r
+  SPI_Cmd(LCD_SPI, ENABLE);\r
+}\r
+\r
+/**\r
+  * @brief  Displays a pixel.\r
+  * @param  x: pixel x.\r
+  * @param  y: pixel y.\r
+  * @retval None\r
+  */\r
+static void PutPixel(int16_t x, int16_t y)\r
+{\r
+  if(x < 0 || x > 239 || y < 0 || y > 319)\r
+  {\r
+    return;\r
+  }\r
+  LCD_DrawLine(x, y, 1, LCD_DIR_HORIZONTAL);\r
+}\r
+\r
+#ifndef USE_Delay\r
+/**\r
+  * @brief  Inserts a delay time.\r
+  * @param  nCount: specifies the delay time length.\r
+  * @retval None\r
+  */\r
+static void delay(__IO uint32_t nCount)\r
+{\r
+  __IO uint32_t index = 0;\r
+  for(index = (34000 * nCount); index != 0; index--)\r
+  {\r
+  }\r
+}\r
+#endif /* USE_Delay*/\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
new file mode 100644 (file)
index 0000000..e3c06a1
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L152_EVAL/stm32l152_eval_lcd.h
@@ -0,0 +1,391 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l152_eval_lcd.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the stm32l152_eval_lcd\r
+  *          firmware driver.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L152_EVAL_LCD_H\r
+#define __STM32L152_EVAL_LCD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+#include "../Common/fonts.h"\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L152_EVAL_LCD\r
+  * @{\r
+  */\r
+\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Types\r
+  * @{\r
+  */\r
+typedef struct\r
+{\r
+  int16_t X;\r
+  int16_t Y;\r
+} Point, * pPoint;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use LCD_DrawBMP function to\r
+ *        display a bitmap picture on the LCD. This function assumes that the bitmap\r
+ *        file is loaded in the SPI Flash (mounted on STM32L152-EVAL board), however\r
+ *        user can tailor it according to his application hardware requirement.\r
+ */\r
+/*#define USE_LCD_DrawBMP*/\r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use user defined Delay function\r
+ *        (for precise timing), otherwise default _delay_ function defined within\r
+ *         this driver is used (less precise timing).\r
+ */\r
+/* #define USE_Delay */\r
+\r
+#ifdef USE_Delay\r
+#include "main.h"\r
+\r
+  #define _delay_     Delay  /* !< User can provide more timing precise _delay_ function\r
+                                   (with 10ms time base), using SysTick for example */\r
+#else\r
+  #define _delay_     delay      /* !< Default _delay_ function with less precise timing */\r
+#endif\r
+\r
+\r
+/**\r
+  * @brief  LCD Control pins\r
+  */\r
+#define LCD_NCS_PIN             GPIO_Pin_2\r
+#define LCD_NCS_GPIO_PORT       GPIOH\r
+#define LCD_NCS_GPIO_CLK        RCC_AHBPeriph_GPIOH\r
+\r
+/**\r
+  * @brief  LCD SPI Interface pins\r
+  */\r
+#define LCD_SPI_SCK_PIN               GPIO_Pin_13                    /* PE.13 */\r
+#define LCD_SPI_SCK_GPIO_PORT         GPIOE                          /* GPIOE */\r
+#define LCD_SPI_SCK_GPIO_CLK          RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_SCK_SOURCE            GPIO_PinSource13\r
+#define LCD_SPI_SCK_AF                GPIO_AF_SPI1\r
+#define LCD_SPI_MISO_PIN              GPIO_Pin_14                    /* PE.14 */\r
+#define LCD_SPI_MISO_GPIO_PORT        GPIOE                          /* GPIOE */\r
+#define LCD_SPI_MISO_GPIO_CLK         RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_MISO_SOURCE           GPIO_PinSource14\r
+#define LCD_SPI_MISO_AF               GPIO_AF_SPI1\r
+#define LCD_SPI_MOSI_PIN              GPIO_Pin_15                    /* PE.15 */\r
+#define LCD_SPI_MOSI_GPIO_PORT        GPIOE                          /* GPIOE */\r
+#define LCD_SPI_MOSI_GPIO_CLK         RCC_AHBPeriph_GPIOE\r
+#define LCD_SPI_MOSI_SOURCE           GPIO_PinSource15\r
+#define LCD_SPI_MOSI_AF               GPIO_AF_SPI1\r
+#define LCD_SPI                       SPI1\r
+#define LCD_SPI_CLK                   RCC_APB2Periph_SPI1\r
+\r
+\r
+/**\r
+  * @brief  LCD Registers\r
+  */\r
+#define LCD_REG_0             0x00\r
+#define LCD_REG_1             0x01\r
+#define LCD_REG_2             0x02\r
+#define LCD_REG_3             0x03\r
+#define LCD_REG_4             0x04\r
+#define LCD_REG_5             0x05\r
+#define LCD_REG_6             0x06\r
+#define LCD_REG_7             0x07\r
+#define LCD_REG_8             0x08\r
+#define LCD_REG_9             0x09\r
+#define LCD_REG_10            0x0A\r
+#define LCD_REG_12            0x0C\r
+#define LCD_REG_13            0x0D\r
+#define LCD_REG_14            0x0E\r
+#define LCD_REG_15            0x0F\r
+#define LCD_REG_16            0x10\r
+#define LCD_REG_17            0x11\r
+#define LCD_REG_18            0x12\r
+#define LCD_REG_19            0x13\r
+#define LCD_REG_20            0x14\r
+#define LCD_REG_21            0x15\r
+#define LCD_REG_22            0x16\r
+#define LCD_REG_23            0x17\r
+#define LCD_REG_24            0x18\r
+#define LCD_REG_25            0x19\r
+#define LCD_REG_26            0x1A\r
+#define LCD_REG_27            0x1B\r
+#define LCD_REG_28            0x1C\r
+#define LCD_REG_29            0x1D\r
+#define LCD_REG_30            0x1E\r
+#define LCD_REG_31            0x1F\r
+#define LCD_REG_32            0x20\r
+#define LCD_REG_33            0x21\r
+#define LCD_REG_34            0x22\r
+#define LCD_REG_36            0x24\r
+#define LCD_REG_37            0x25\r
+#define LCD_REG_40            0x28\r
+#define LCD_REG_41            0x29\r
+#define LCD_REG_43            0x2B\r
+#define LCD_REG_45            0x2D\r
+#define LCD_REG_48            0x30\r
+#define LCD_REG_49            0x31\r
+#define LCD_REG_50            0x32\r
+#define LCD_REG_51            0x33\r
+#define LCD_REG_52            0x34\r
+#define LCD_REG_53            0x35\r
+#define LCD_REG_54            0x36\r
+#define LCD_REG_55            0x37\r
+#define LCD_REG_56            0x38\r
+#define LCD_REG_57            0x39\r
+#define LCD_REG_59            0x3B\r
+#define LCD_REG_60            0x3C\r
+#define LCD_REG_61            0x3D\r
+#define LCD_REG_62            0x3E\r
+#define LCD_REG_63            0x3F\r
+#define LCD_REG_64            0x40\r
+#define LCD_REG_65            0x41\r
+#define LCD_REG_66            0x42\r
+#define LCD_REG_67            0x43\r
+#define LCD_REG_68            0x44\r
+#define LCD_REG_69            0x45\r
+#define LCD_REG_70            0x46\r
+#define LCD_REG_71            0x47\r
+#define LCD_REG_72            0x48\r
+#define LCD_REG_73            0x49\r
+#define LCD_REG_74            0x4A\r
+#define LCD_REG_75            0x4B\r
+#define LCD_REG_76            0x4C\r
+#define LCD_REG_77            0x4D\r
+#define LCD_REG_78            0x4E\r
+#define LCD_REG_79            0x4F\r
+#define LCD_REG_80            0x50\r
+#define LCD_REG_81            0x51\r
+#define LCD_REG_82            0x52\r
+#define LCD_REG_83            0x53\r
+#define LCD_REG_96            0x60\r
+#define LCD_REG_97            0x61\r
+#define LCD_REG_106           0x6A\r
+#define LCD_REG_118           0x76\r
+#define LCD_REG_128           0x80\r
+#define LCD_REG_129           0x81\r
+#define LCD_REG_130           0x82\r
+#define LCD_REG_131           0x83\r
+#define LCD_REG_132           0x84\r
+#define LCD_REG_133           0x85\r
+#define LCD_REG_134           0x86\r
+#define LCD_REG_135           0x87\r
+#define LCD_REG_136           0x88\r
+#define LCD_REG_137           0x89\r
+#define LCD_REG_139           0x8B\r
+#define LCD_REG_140           0x8C\r
+#define LCD_REG_141           0x8D\r
+#define LCD_REG_143           0x8F\r
+#define LCD_REG_144           0x90\r
+#define LCD_REG_145           0x91\r
+#define LCD_REG_146           0x92\r
+#define LCD_REG_147           0x93\r
+#define LCD_REG_148           0x94\r
+#define LCD_REG_149           0x95\r
+#define LCD_REG_150           0x96\r
+#define LCD_REG_151           0x97\r
+#define LCD_REG_152           0x98\r
+#define LCD_REG_153           0x99\r
+#define LCD_REG_154           0x9A\r
+#define LCD_REG_157           0x9D\r
+#define LCD_REG_192           0xC0\r
+#define LCD_REG_193           0xC1\r
+#define LCD_REG_227           0xE3\r
+#define LCD_REG_229           0xE5\r
+#define LCD_REG_231           0xE7\r
+#define LCD_REG_239           0xEF\r
+\r
+\r
+/**\r
+  * @brief  LCD color\r
+  */\r
+#define LCD_COLOR_WHITE          0xFFFF\r
+#define LCD_COLOR_BLACK          0x0000\r
+#define LCD_COLOR_GREY           0xF7DE\r
+#define LCD_COLOR_BLUE           0x001F\r
+#define LCD_COLOR_BLUE2          0x051F\r
+#define LCD_COLOR_RED            0xF800\r
+#define LCD_COLOR_MAGENTA        0xF81F\r
+#define LCD_COLOR_GREEN          0x07E0\r
+#define LCD_COLOR_CYAN           0x7FFF\r
+#define LCD_COLOR_YELLOW         0xFFE0\r
+\r
+/**\r
+  * @brief  LCD Lines depending on the chosen fonts.\r
+  */\r
+#define LCD_LINE_0               LINE(0)\r
+#define LCD_LINE_1               LINE(1)\r
+#define LCD_LINE_2               LINE(2)\r
+#define LCD_LINE_3               LINE(3)\r
+#define LCD_LINE_4               LINE(4)\r
+#define LCD_LINE_5               LINE(5)\r
+#define LCD_LINE_6               LINE(6)\r
+#define LCD_LINE_7               LINE(7)\r
+#define LCD_LINE_8               LINE(8)\r
+#define LCD_LINE_9               LINE(9)\r
+#define LCD_LINE_10              LINE(10)\r
+#define LCD_LINE_11              LINE(11)\r
+#define LCD_LINE_12              LINE(12)\r
+#define LCD_LINE_13              LINE(13)\r
+#define LCD_LINE_14              LINE(14)\r
+#define LCD_LINE_15              LINE(15)\r
+#define LCD_LINE_16              LINE(16)\r
+#define LCD_LINE_17              LINE(17)\r
+#define LCD_LINE_18              LINE(18)\r
+#define LCD_LINE_19              LINE(19)\r
+#define LCD_LINE_20              LINE(20)\r
+#define LCD_LINE_21              LINE(21)\r
+#define LCD_LINE_22              LINE(22)\r
+#define LCD_LINE_23              LINE(23)\r
+#define LCD_LINE_24              LINE(24)\r
+#define LCD_LINE_25              LINE(25)\r
+#define LCD_LINE_26              LINE(26)\r
+#define LCD_LINE_27              LINE(27)\r
+#define LCD_LINE_28              LINE(28)\r
+#define LCD_LINE_29              LINE(29)\r
+\r
+\r
+/**\r
+  * @brief LCD default font\r
+  */\r
+#define LCD_DEFAULT_FONT         Font16x24\r
+\r
+/**\r
+  * @brief  LCD Direction\r
+  */\r
+#define LCD_DIR_HORIZONTAL       0x0000\r
+#define LCD_DIR_VERTICAL         0x0001\r
+\r
+/**\r
+  * @brief  LCD Size (Width and Height)\r
+  */\r
+#define LCD_PIXEL_WIDTH          0x0140\r
+#define LCD_PIXEL_HEIGHT         0x00F0\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Macros\r
+  * @{\r
+  */\r
+#define ASSEMBLE_RGB(R, G, B)    ((((R)& 0xF8) << 8) | (((G) & 0xFC) << 3) | (((B) & 0xF8) >> 3))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup STM32L152_EVAL_LCD_Exported_Functions\r
+  * @{\r
+  */\r
+void STM32L152_LCD_DeInit(void);\r
+void LCD_Setup(void);\r
+void STM32L152_LCD_Init(void);\r
+void LCD_SetColors(__IO uint16_t _TextColor, __IO uint16_t _BackColor);\r
+void LCD_GetColors(__IO uint16_t *_TextColor, __IO uint16_t *_BackColor);\r
+void LCD_SetTextColor(__IO uint16_t Color);\r
+void LCD_SetBackColor(__IO uint16_t Color);\r
+void LCD_ClearLine(uint8_t Line);\r
+void LCD_Clear(uint16_t Color);\r
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);\r
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);\r
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);\r
+void LCD_SetFont(sFONT *fonts);\r
+sFONT *LCD_GetFont(void);\r
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);\r
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);\r
+void LCD_WindowModeDisable(void);\r
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);\r
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);\r
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void LCD_DrawMonoPict(const uint32_t *Pict);\r
+void LCD_DrawBMP(uint32_t BmpAddress);\r
+void LCD_DrawUniLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2);\r
+void LCD_DrawFullRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height);\r
+void LCD_DrawFullCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius);\r
+void LCD_PolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_PolyLineRelative(pPoint Points, uint16_t PointCount);\r
+void LCD_ClosedPolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_ClosedPolyLineRelative(pPoint Points, uint16_t PointCount);\r
+void LCD_FillPolyLine(pPoint Points, uint16_t PointCount);\r
+void LCD_nCS_StartByte(uint8_t Start_Byte);\r
+void LCD_WriteRegIndex(uint8_t LCD_Reg);\r
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);\r
+void LCD_WriteRAM_Prepare(void);\r
+void LCD_WriteRAMWord(uint16_t RGB_Code);\r
+uint16_t LCD_ReadReg(uint8_t LCD_Reg);\r
+void LCD_WriteRAM(uint16_t RGB_Code);\r
+void LCD_PowerOn(void);\r
+void LCD_DisplayOn(void);\r
+void LCD_DisplayOff(void);\r
+\r
+void LCD_CtrlLinesConfig(void);\r
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);\r
+void LCD_SPIConfig(void);\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L152_EVAL_LCD_H */\r
+\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
new file mode 100644 (file)
index 0000000..6ae338d
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/misc.h
@@ -0,0 +1,219 @@
+/**\r
+  ******************************************************************************\r
+  * @file    misc.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the miscellaneous\r
+  *          firmware library functions (add-on to CMSIS functions).\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup MISC\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  NVIC Init Structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.\r
+                                                   This parameter can be a value of @ref IRQn_Type \r
+                                                   (For the complete STM32 Devices IRQ Channels list, please\r
+                                                    refer to stm32l1xx.h file) */\r
+\r
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel\r
+                                                   specified in NVIC_IRQChannel. This parameter can be a value\r
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified\r
+                                                   in NVIC_IRQChannel. This parameter can be a value\r
+                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+                                                   will be enabled or disabled. \r
+                                                   This parameter can be set either to ENABLE or DISABLE */   \r
+} NVIC_InitTypeDef;\r
+ \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup NVIC_Priority_Table \r
+  * @{\r
+  */\r
+\r
+/**\r
+@code  \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+  ============================================================================================================================\r
+    NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description\r
+  ============================================================================================================================\r
+   NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority\r
+                         |                                   |                             |   4 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------\r
+   NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority\r
+                         |                                   |                             |   3 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority\r
+                         |                                   |                             |   2 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority\r
+                         |                                   |                             |   1 bits for subpriority\r
+  ----------------------------------------------------------------------------------------------------------------------------    \r
+   NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority\r
+                         |                                   |                             |   0 bits for subpriority                       \r
+  ============================================================================================================================\r
+@endcode\r
+*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup Vector_Table_Base \r
+  * @{\r
+  */\r
+\r
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup System_Low_Power \r
+  * @{\r
+  */\r
+\r
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+                        ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+  * @{\r
+  */\r
+\r
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+                                                            4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+                                                            3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+                                                            2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+                                                            1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+                                                            0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \\r
+                                       ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0001FFFF)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SysTick_clock_source \r
+  * @{\r
+  */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
new file mode 100644 (file)
index 0000000..769e4fc
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_exti.h
@@ -0,0 +1,201 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_exti.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the EXTI firmware\r
+  *          library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_EXTI_H\r
+#define __STM32L1xx_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup EXTI\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  EXTI mode enumeration  \r
+  */\r
+\r
+typedef enum\r
+{\r
+  EXTI_Mode_Interrupt = 0x00,\r
+  EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+  * @brief  EXTI Trigger enumeration  \r
+  */\r
+\r
+typedef enum\r
+{\r
+  EXTI_Trigger_Rising = 0x08,\r
+  EXTI_Trigger_Falling = 0x0C,  \r
+  EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+  * @brief  EXTI Init Structure definition  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.\r
+                                         This parameter can be any combination of @ref EXTI_Lines */\r
+   \r
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.\r
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.\r
+                                         This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Lines \r
+  * @{\r
+  */\r
+\r
+#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0 */\r
+#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1 */\r
+#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2 */\r
+#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3 */\r
+#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4 */\r
+#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5 */\r
+#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6 */\r
+#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7 */\r
+#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8 */\r
+#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9 */\r
+#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */\r
+#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */\r
+#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */\r
+#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */\r
+#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */\r
+#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */\r
+#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 \r
+                                                      Connected to the PVD Output */\r
+#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< External interrupt line 17 \r
+                                                      Connected to the RTC Alarm \r
+                                                      event */\r
+#define EXTI_Line18      ((uint32_t)0x00040000)  /*!< External interrupt line 18 \r
+                                                      Connected to the USB Device \r
+                                                      FS Wakeup from suspend event */\r
+#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< External interrupt line 19 \r
+                                                      Connected to the RTC Tamper \r
+                                                      and Time Stamp events */ \r
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 \r
+                                                      Connected to the RTC Wakeup \r
+                                                      event */\r
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 \r
+                                                      Connected to the Comparator 1 \r
+                                                      event */\r
+\r
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 \r
+                                                      Connected to the Comparator 2\r
+                                                      event */\r
+                                                                                                  \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \\r
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \\r
+                                ((LINE) == EXTI_Line22))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_EXTI_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
new file mode 100644 (file)
index 0000000..189be5a
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_gpio.h
@@ -0,0 +1,369 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_gpio.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the GPIO \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_GPIO_H\r
+#define __STM32L1xx_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup GPIO\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Types\r
+  * @{\r
+  */ \r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+                                    ((PERIPH) == GPIOB) || \\r
+                                    ((PERIPH) == GPIOC) || \\r
+                                    ((PERIPH) == GPIOD) || \\r
+                                    ((PERIPH) == GPIOE) || \\r
+                                    ((PERIPH) == GPIOH))\r
+\r
+/** @defgroup Configuration_Mode_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ \r
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */\r
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */\r
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */\r
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */\r
+}GPIOMode_TypeDef;\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \\r
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Output_type_enumeration\r
+  * @{\r
+  */ \r
+typedef enum\r
+{ GPIO_OType_PP = 0x00,\r
+  GPIO_OType_OD = 0x01\r
+}GPIOOType_TypeDef;\r
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Output_Maximum_frequency_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ \r
+  GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */\r
+  GPIO_Speed_2MHz   = 0x01, /*!< Low Speed */\r
+  GPIO_Speed_10MHz  = 0x02, /*!< Medium Speed */\r
+  GPIO_Speed_40MHz  = 0x03  /*!< High Speed */\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+                              ((SPEED) == GPIO_Speed_10MHz)||  ((SPEED) == GPIO_Speed_40MHz))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration \r
+  * @{\r
+  */ \r
+typedef enum\r
+{ GPIO_PuPd_NOPULL = 0x00,\r
+  GPIO_PuPd_UP     = 0x01,\r
+  GPIO_PuPd_DOWN   = 0x02\r
+}GPIOPuPd_TypeDef;\r
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \\r
+                            ((PUPD) == GPIO_PuPd_DOWN))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration\r
+  * @{\r
+  */\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+  Bit_SET\r
+}BitAction;\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** \r
+  * @brief  GPIO Init structure definition\r
+  */ \r
+typedef struct\r
+{\r
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.\r
+                                       This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */\r
+\r
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */\r
+\r
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.\r
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */\r
+}GPIO_InitTypeDef;\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+  * @{\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_pins_define \r
+  * @{\r
+  */\r
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */\r
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */\r
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */\r
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */\r
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */\r
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */\r
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */\r
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */\r
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */\r
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */\r
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */\r
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */\r
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */\r
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */\r
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */\r
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */\r
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+                              ((PIN) == GPIO_Pin_1) || \\r
+                              ((PIN) == GPIO_Pin_2) || \\r
+                              ((PIN) == GPIO_Pin_3) || \\r
+                              ((PIN) == GPIO_Pin_4) || \\r
+                              ((PIN) == GPIO_Pin_5) || \\r
+                              ((PIN) == GPIO_Pin_6) || \\r
+                              ((PIN) == GPIO_Pin_7) || \\r
+                              ((PIN) == GPIO_Pin_8) || \\r
+                              ((PIN) == GPIO_Pin_9) || \\r
+                              ((PIN) == GPIO_Pin_10) || \\r
+                              ((PIN) == GPIO_Pin_11) || \\r
+                              ((PIN) == GPIO_Pin_12) || \\r
+                              ((PIN) == GPIO_Pin_13) || \\r
+                              ((PIN) == GPIO_Pin_14) || \\r
+                              ((PIN) == GPIO_Pin_15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+  * @{\r
+  */ \r
+#define GPIO_PinSource0            ((uint8_t)0x00)\r
+#define GPIO_PinSource1            ((uint8_t)0x01)\r
+#define GPIO_PinSource2            ((uint8_t)0x02)\r
+#define GPIO_PinSource3            ((uint8_t)0x03)\r
+#define GPIO_PinSource4            ((uint8_t)0x04)\r
+#define GPIO_PinSource5            ((uint8_t)0x05)\r
+#define GPIO_PinSource6            ((uint8_t)0x06)\r
+#define GPIO_PinSource7            ((uint8_t)0x07)\r
+#define GPIO_PinSource8            ((uint8_t)0x08)\r
+#define GPIO_PinSource9            ((uint8_t)0x09)\r
+#define GPIO_PinSource10           ((uint8_t)0x0A)\r
+#define GPIO_PinSource11           ((uint8_t)0x0B)\r
+#define GPIO_PinSource12           ((uint8_t)0x0C)\r
+#define GPIO_PinSource13           ((uint8_t)0x0D)\r
+#define GPIO_PinSource14           ((uint8_t)0x0E)\r
+#define GPIO_PinSource15           ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource1) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource2) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource3) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource4) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource5) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource6) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource7) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource8) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource9) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource10) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource11) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource12) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource13) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource14) || \\r
+                                       ((PINSOURCE) == GPIO_PinSource15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Alternat_function_selection_define \r
+  * @{\r
+  */\r
+\r
+/** \r
+  * @brief  AF 0 selection  \r
+  */ \r
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /*!< RTC 50/60 Hz Alternate Function mapping */\r
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /*!< MCO Alternate Function mapping */\r
+#define GPIO_AF_RTC_AF1       ((uint8_t)0x00)  /*!< RTC_AF1 Alternate Function mapping */\r
+#define GPIO_AF_WKUP          ((uint8_t)0x00)  /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */\r
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /*!< SWJ (SW and JTAG) Alternate Function mapping */\r
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /*!< TRACE Alternate Function mapping */\r
+\r
+/** \r
+  * @brief  AF 1 selection  \r
+  */ \r
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 2 selection  \r
+  */ \r
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /*!< TIM3 Alternate Function mapping */\r
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /*!< TIM4 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 3 selection  \r
+  */ \r
+#define GPIO_AF_TIM9           ((uint8_t)0x03)  /*!< TIM9 Alternate Function mapping */\r
+#define GPIO_AF_TIM10          ((uint8_t)0x03)  /*!< TIM10 Alternate Function mapping */\r
+#define GPIO_AF_TIM11          ((uint8_t)0x03)  /*!< TIM11 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 4 selection  \r
+  */ \r
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /*!< I2C2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 5 selection  \r
+  */ \r
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 7 selection  \r
+  */ \r
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /*!< USART1 Alternate Function mapping */\r
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /*!< USART2 Alternate Function mapping */\r
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /*!< USART3 Alternate Function mapping */\r
+/** \r
+  * @brief  AF 10 selection  \r
+  */ \r
+#define GPIO_AF_USB           ((uint8_t)0xA)  /*!< USB Full speed device  Alternate Function mapping */\r
+/** \r
+  * @brief  AF 11 selection  \r
+  */ \r
+#define GPIO_AF_LCD           ((uint8_t)0x0B)  /*!< LCD Alternate Function mapping */\r
+/** \r
+  * @brief  AF 14 selection  \r
+  */ \r
+#define GPIO_AF_RI            ((uint8_t)0x0E)  /*!< RI Alternate Function mapping */\r
+\r
+/** \r
+  * @brief  AF 15 selection  \r
+  */ \r
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /*!< EVENTOUT Alternate Function mapping */\r
+\r
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \\r
+                          ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \\r
+                          ((AF) == GPIO_AF_SWJ)    || ((AF) == GPIO_AF_TRACE) || \\r
+                          ((AF) == GPIO_AF_TIM2)   || ((AF)== GPIO_AF_TIM3) || \\r
+                          ((AF) == GPIO_AF_TIM4)   || ((AF)== GPIO_AF_TIM9) || \\r
+                          ((AF) == GPIO_AF_TIM10)  || ((AF)== GPIO_AF_TIM11) || \\r
+                          ((AF) == GPIO_AF_I2C1)   || ((AF) == GPIO_AF_I2C2) || \\r
+                          ((AF) == GPIO_AF_SPI1)   || ((AF) == GPIO_AF_SPI2) || \\r
+                          ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \\r
+                          ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \\r
+                          ((AF) == GPIO_AF_LCD)    || ((AF) == GPIO_AF_RI) || \\r
+                          ((AF) == GPIO_AF_EVENTOUT))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Legacy \r
+  * @{\r
+  */\r
+    \r
+#define GPIO_Mode_AIN GPIO_Mode_AN\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup GPIO_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Exported_Functions\r
+  * @{\r
+  */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_GPIO_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
new file mode 100644 (file)
index 0000000..a9b949c
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_rcc.h
@@ -0,0 +1,471 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_rcc.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the RCC \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_RCC_H\r
+#define __STM32L1xx_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup RCC\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Types\r
+  * @{\r
+  */\r
+\r
+typedef struct\r
+{\r
+  uint32_t SYSCLK_Frequency;\r
+  uint32_t HCLK_Frequency;\r
+  uint32_t PCLK1_Frequency;\r
+  uint32_t PCLK2_Frequency;\r
+}RCC_ClocksTypeDef;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+  * @{\r
+  */\r
+\r
+/** @defgroup HSE_configuration \r
+  * @{\r
+  */\r
+\r
+#define RCC_HSE_OFF                      ((uint8_t)0x00)\r
+#define RCC_HSE_ON                       ((uint8_t)0x01)\r
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+                         ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup MSI_Clock_Range \r
+  * @{\r
+  */\r
+\r
+#define RCC_MSIRange_64KHz               RCC_ICSCR_MSIRANGE_64KHz\r
+#define RCC_MSIRange_128KHz              RCC_ICSCR_MSIRANGE_128KHz\r
+#define RCC_MSIRange_256KHz              RCC_ICSCR_MSIRANGE_256KHz\r
+#define RCC_MSIRange_512KHz              RCC_ICSCR_MSIRANGE_512KHz\r
+#define RCC_MSIRange_1MHz                RCC_ICSCR_MSIRANGE_1MHz\r
+#define RCC_MSIRange_2MHz                RCC_ICSCR_MSIRANGE_2MHz\r
+#define RCC_MSIRange_4MHz                RCC_ICSCR_MSIRANGE_4MHz\r
+\r
+#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_64KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_128KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_256KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_512KHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_1MHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_2MHz) || \\r
+                                       ((RANGE) == RCC_MSIRange_4MHz))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup PLL_Clock_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLSource_HSI                ((uint8_t)0x00)\r
+#define RCC_PLLSource_HSE                ((uint8_t)0x01)\r
+\r
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \\r
+                                   ((SOURCE) == RCC_PLLSource_HSE))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup PLL_Multiplication_Factor \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLMul_3                     ((uint8_t)0x00)\r
+#define RCC_PLLMul_4                     ((uint8_t)0x04)\r
+#define RCC_PLLMul_6                     ((uint8_t)0x08)\r
+#define RCC_PLLMul_8                     ((uint8_t)0x0C)\r
+#define RCC_PLLMul_12                    ((uint8_t)0x10)\r
+#define RCC_PLLMul_16                    ((uint8_t)0x14)\r
+#define RCC_PLLMul_24                    ((uint8_t)0x18)\r
+#define RCC_PLLMul_32                    ((uint8_t)0x1C)\r
+#define RCC_PLLMul_48                    ((uint8_t)0x20)\r
+\r
+\r
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \\r
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \\r
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \\r
+                             ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \\r
+                             ((MUL) == RCC_PLLMul_48))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup PLL_Divider_Factor \r
+  * @{\r
+  */\r
+\r
+#define RCC_PLLDiv_2                     ((uint8_t)0x40)\r
+#define RCC_PLLDiv_3                     ((uint8_t)0x80)\r
+#define RCC_PLLDiv_4                     ((uint8_t)0xC0)\r
+\r
+\r
+#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \\r
+                             ((DIV) == RCC_PLLDiv_4))\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup System_Clock_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_SYSCLKSource_MSI             RCC_CFGR_SW_MSI\r
+#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI\r
+#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE\r
+#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup AHB_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1\r
+#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2\r
+#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4\r
+#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8\r
+#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16\r
+#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64\r
+#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128\r
+#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256\r
+#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+                           ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup APB1_APB2_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_HCLK_Div1                    RCC_CFGR_PPRE1_DIV1\r
+#define RCC_HCLK_Div2                    RCC_CFGR_PPRE1_DIV2\r
+#define RCC_HCLK_Div4                    RCC_CFGR_PPRE1_DIV4\r
+#define RCC_HCLK_Div8                    RCC_CFGR_PPRE1_DIV8\r
+#define RCC_HCLK_Div16                   RCC_CFGR_PPRE1_DIV16\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+                           ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+  * @}\r
+  */\r
+  \r
+\r
+/** @defgroup RCC_Interrupt_Source \r
+  * @{\r
+  */\r
+\r
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)\r
+#define RCC_IT_MSIRDY                    ((uint8_t)0x20)\r
+#define RCC_IT_CSS                       ((uint8_t)0x80)\r
+\r
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \\r
+                           ((IT) == RCC_IT_CSS))\r
+\r
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup LSE_Configuration \r
+  * @{\r
+  */\r
+\r
+#define RCC_LSE_OFF                      ((uint8_t)0x00)\r
+#define RCC_LSE_ON                       ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass                   ((uint8_t)0x05)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+                         ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RTC_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_RTCCLKSource_LSE             RCC_CSR_RTCSEL_LSE\r
+#define RCC_RTCCLKSource_LSI             RCC_CSR_RTCSEL_LSI\r
+#define RCC_RTCCLKSource_HSE_Div2        RCC_CSR_RTCSEL_HSE\r
+#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)\r
+#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)\r
+#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \\r
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup AHB_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN\r
+#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN\r
+#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN\r
+#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN\r
+#define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN\r
+#define RCC_AHBPeriph_GPIOH               RCC_AHBENR_GPIOHEN\r
+#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN\r
+#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN\r
+#define RCC_AHBPeriph_SRAM                RCC_AHBLPENR_SRAMLPEN\r
+#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN\r
+\r
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup APB2_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN\r
+#define RCC_APB2Periph_TIM9              RCC_APB2ENR_TIM9EN\r
+#define RCC_APB2Periph_TIM10             RCC_APB2ENR_TIM10EN\r
+#define RCC_APB2Periph_TIM11             RCC_APB2ENR_TIM11EN\r
+#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN\r
+#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN\r
+#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup APB1_Peripherals \r
+  * @{\r
+  */\r
+\r
+#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN\r
+#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN\r
+#define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN\r
+#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN\r
+#define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN\r
+#define RCC_APB1Periph_LCD               RCC_APB1ENR_LCDEN\r
+#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN\r
+#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN\r
+#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN\r
+#define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN\r
+#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN\r
+#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN\r
+#define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN\r
+#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN\r
+#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN\r
+#define RCC_APB1Periph_COMP              RCC_APB1ENR_COMPEN\r
+\r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MCO_Clock_Source\r
+  * @{\r
+  */\r
+\r
+#define RCC_MCOSource_NoClock            ((uint8_t)0x00)\r
+#define RCC_MCOSource_SYSCLK             ((uint8_t)0x01)\r
+#define RCC_MCOSource_HSI                ((uint8_t)0x02)\r
+#define RCC_MCOSource_MSI                ((uint8_t)0x03)\r
+#define RCC_MCOSource_HSE                ((uint8_t)0x04)\r
+#define RCC_MCOSource_PLLCLK             ((uint8_t)0x05)\r
+#define RCC_MCOSource_LSI                ((uint8_t)0x06)\r
+#define RCC_MCOSource_LSE                ((uint8_t)0x07)\r
+\r
+#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \\r
+                                   ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_MSI) || \\r
+                                   ((SOURCE) == RCC_MCOSource_HSE)  || ((SOURCE) == RCC_MCOSource_PLLCLK) || \\r
+                                   ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MCO_Output_Divider \r
+  * @{\r
+  */\r
+\r
+#define RCC_MCODiv_1                     ((uint8_t)0x00)\r
+#define RCC_MCODiv_2                     ((uint8_t)0x10)\r
+#define RCC_MCODiv_4                     ((uint8_t)0x20)\r
+#define RCC_MCODiv_8                     ((uint8_t)0x30)\r
+#define RCC_MCODiv_16                    ((uint8_t)0x40)\r
+\r
+#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \\r
+                             ((DIV) == RCC_MCODiv_4)  || ((DIV) == RCC_MCODiv_8) || \\r
+                             ((DIV) == RCC_MCODiv_16))\r
+/**\r
+  * @}\r
+  */  \r
+\r
+/** @defgroup RCC_Flag \r
+  * @{\r
+  */\r
+\r
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)\r
+#define RCC_FLAG_MSIRDY                  ((uint8_t)0x29)\r
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x49)\r
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)\r
+#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)\r
+#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)\r
+#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)\r
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)\r
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)\r
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)\r
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)\r
+\r
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+                           ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \\r
+                           ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \\r
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \\r
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \\r
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \\r
+                           ((FLAG) == RCC_FLAG_WWDGRST))\r
+\r
+#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Exported_Functions\r
+  * @{\r
+  */\r
+\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(uint8_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);\r
+void RCC_MSICmd(FunctionalState NewState);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_RTCResetCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_RCC_H */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
new file mode 100644 (file)
index 0000000..cd51e92
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/inc/stm32l1xx_syscfg.h
@@ -0,0 +1,381 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_syscfg.h\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains all the functions prototypes for the SYSCFG \r
+  *          firmware library.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/*!< Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_SYSCFG_H\r
+#define __STM32L1xx_SYSCFG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/*!< Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup SYSCFG\r
+  * @{\r
+  */ \r
+  \r
+/** @defgroup SYSCFG_Exported_Types\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Port_Sources \r
+  * @{\r
+  */ \r
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)\r
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)\r
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)\r
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)\r
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)\r
+#define EXTI_PortSourceGPIOH       ((uint8_t)0x05)\r
+                                      \r
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \\r
+                                         ((PORTSOURCE) == EXTI_PortSourceGPIOH)) \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Pin_sources \r
+  * @{\r
+  */ \r
+#define EXTI_PinSource0            ((uint8_t)0x00)\r
+#define EXTI_PinSource1            ((uint8_t)0x01)\r
+#define EXTI_PinSource2            ((uint8_t)0x02)\r
+#define EXTI_PinSource3            ((uint8_t)0x03)\r
+#define EXTI_PinSource4            ((uint8_t)0x04)\r
+#define EXTI_PinSource5            ((uint8_t)0x05)\r
+#define EXTI_PinSource6            ((uint8_t)0x06)\r
+#define EXTI_PinSource7            ((uint8_t)0x07)\r
+#define EXTI_PinSource8            ((uint8_t)0x08)\r
+#define EXTI_PinSource9            ((uint8_t)0x09)\r
+#define EXTI_PinSource10           ((uint8_t)0x0A)\r
+#define EXTI_PinSource11           ((uint8_t)0x0B)\r
+#define EXTI_PinSource12           ((uint8_t)0x0C)\r
+#define EXTI_PinSource13           ((uint8_t)0x0D)\r
+#define EXTI_PinSource14           ((uint8_t)0x0E)\r
+#define EXTI_PinSource15           ((uint8_t)0x0F)\r
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource1) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource2) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource3) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource4) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource5) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource6) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource7) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource8) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource9) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource10) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource11) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource12) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource13) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource14) || \\r
+                                       ((PINSOURCE) == EXTI_PinSource15))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Memory_Remap_Config \r
+  * @{\r
+  */ \r
+#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)\r
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)\r
+#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)\r
+   \r
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \\r
+                                               ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \\r
+                                               ((REMAP) == SYSCFG_MemoryRemap_SRAM))\r
+\r
+\r
+/** @defgroup RI_Resistor\r
+  * @{\r
+  */\r
+\r
+#define RI_Resistor_10KPU          COMP_CSR_10KPU\r
+#define RI_Resistor_400KPU         COMP_CSR_400KPU\r
+#define RI_Resistor_10KPD          COMP_CSR_10KPD\r
+#define RI_Resistor_400KPD         COMP_CSR_400KPD\r
+\r
+#define IS_RI_RESISTOR(RESISTOR)  (((RESISTOR) == COMP_CSR_10KPU) || \\r
+                                   ((RESISTOR) == COMP_CSR_400KPU) || \\r
+                                   ((RESISTOR) == COMP_CSR_10KPD) || \\r
+                                   ((RESISTOR) == COMP_CSR_400KPD))\r
+ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RI_InputCapture\r
+  * @{\r
+  */ \r
+  \r
+#define RI_InputCapture_IC1  RI_ICR_IC1    /*!< Input Capture 1 */\r
+#define RI_InputCapture_IC2  RI_ICR_IC2    /*!< Input Capture 2 */\r
+#define RI_InputCapture_IC3  RI_ICR_IC3    /*!< Input Capture 3 */\r
+#define RI_InputCapture_IC4  RI_ICR_IC4    /*!< Input Capture 4 */\r
+\r
+#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup TIM_Select\r
+  * @{\r
+  */ \r
+  \r
+#define TIM_Select_None  ((uint32_t)0x00000000)    /*!< None selected */\r
+#define TIM_Select_TIM2  ((uint32_t)0x00010000)    /*!< Timer 2 selected */\r
+#define TIM_Select_TIM3  ((uint32_t)0x00020000)    /*!< Timer 3 selected */\r
+#define TIM_Select_TIM4  ((uint32_t)0x00030000)    /*!< Timer 4 selected */\r
+\r
+#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \\r
+                        ((TIM) == TIM_Select_TIM2) || \\r
+                        ((TIM) == TIM_Select_TIM3) || \\r
+                        ((TIM) == TIM_Select_TIM4))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup RI_InputCaptureRouting\r
+  * @{\r
+  */ \r
+                                                          /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */  \r
+#define RI_InputCaptureRouting_0   ((uint32_t)0x00000000) /* PA0       PA1      PA2       PA3      */\r
+#define RI_InputCaptureRouting_1   ((uint32_t)0x00000001) /* PA4       PA5      PA6       PA7      */\r
+#define RI_InputCaptureRouting_2   ((uint32_t)0x00000002) /* PA8       PA9      PA10      PA11     */\r
+#define RI_InputCaptureRouting_3   ((uint32_t)0x00000003) /* PA12      PA13     PA14      PA15     */\r
+#define RI_InputCaptureRouting_4   ((uint32_t)0x00000004) /* PC0       PC1      PC2       PC3      */\r
+#define RI_InputCaptureRouting_5   ((uint32_t)0x00000005) /* PC4       PC5      PC6       PC7      */\r
+#define RI_InputCaptureRouting_6   ((uint32_t)0x00000006) /* PC8       PC9      PC10      PC11     */\r
+#define RI_InputCaptureRouting_7   ((uint32_t)0x00000007) /* PC12      PC13     PC14      PC15     */\r
+#define RI_InputCaptureRouting_8   ((uint32_t)0x00000008) /* PD0       PD1      PD2       PD3      */\r
+#define RI_InputCaptureRouting_9   ((uint32_t)0x00000009) /* PD4       PD5      PD6       PD7      */\r
+#define RI_InputCaptureRouting_10  ((uint32_t)0x0000000A) /* PD8       PD9      PD10      PD11     */\r
+#define RI_InputCaptureRouting_11  ((uint32_t)0x0000000B) /* PD12      PD13     PD14      PD15     */\r
+#define RI_InputCaptureRouting_12  ((uint32_t)0x0000000C) /* PE0       PE1      PE2       PE3      */\r
+#define RI_InputCaptureRouting_13  ((uint32_t)0x0000000D) /* PE4       PE5      PE6       PE7      */\r
+#define RI_InputCaptureRouting_14  ((uint32_t)0x0000000E) /* PE8       PE9      PE10      PE11     */\r
+#define RI_InputCaptureRouting_15  ((uint32_t)0x0000000F) /* PE12      PE13     PE14      PE15     */\r
+\r
+#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_1) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_2) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_3) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_4) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_5) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_6) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_7) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_8) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_9) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_10) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_11) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_12) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_13) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_14) || \\r
+                                             ((ROUTING) == RI_InputCaptureRouting_15))\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RI_IOSwitch\r
+  * @{\r
+  */ \r
+  \r
+/* ASCR1 I/O switch: bit 28 is set to '1' to indicate that the mask is in ASCR1 register */\r
+#define RI_IOSwitch_CH0        ((uint32_t)0x10000001)\r
+#define RI_IOSwitch_CH1        ((uint32_t)0x10000002)\r
+#define RI_IOSwitch_CH2        ((uint32_t)0x10000004)\r
+#define RI_IOSwitch_CH3        ((uint32_t)0x10000008)\r
+#define RI_IOSwitch_CH4        ((uint32_t)0x10000010)\r
+#define RI_IOSwitch_CH5        ((uint32_t)0x10000020)\r
+#define RI_IOSwitch_CH6        ((uint32_t)0x10000040)\r
+#define RI_IOSwitch_CH7        ((uint32_t)0x10000080)\r
+#define RI_IOSwitch_CH8        ((uint32_t)0x10000100)\r
+#define RI_IOSwitch_CH9        ((uint32_t)0x10000200)\r
+#define RI_IOSwitch_CH10       ((uint32_t)0x10000400)\r
+#define RI_IOSwitch_CH11       ((uint32_t)0x10000800)\r
+#define RI_IOSwitch_CH12       ((uint32_t)0x10001000)\r
+#define RI_IOSwitch_CH13       ((uint32_t)0x10002000)\r
+#define RI_IOSwitch_CH14       ((uint32_t)0x10004000)\r
+#define RI_IOSwitch_CH15       ((uint32_t)0x10008000)\r
+#define RI_IOSwitch_CH18       ((uint32_t)0x10040000)\r
+#define RI_IOSwitch_CH19       ((uint32_t)0x10080000)\r
+#define RI_IOSwitch_CH20       ((uint32_t)0x10100000)\r
+#define RI_IOSwitch_CH21       ((uint32_t)0x10200000)\r
+#define RI_IOSwitch_CH22       ((uint32_t)0x10400000)\r
+#define RI_IOSwitch_CH23       ((uint32_t)0x10800000)\r
+#define RI_IOSwitch_CH24       ((uint32_t)0x11000000)\r
+#define RI_IOSwitch_CH25       ((uint32_t)0x12000000)\r
+#define RI_IOSwitch_VCOMP      ((uint32_t)0x14000000) /* VCOMP is an internal switch used to connect \r
+                                                         selected channel to COMP1 non inverting input */\r
+\r
+/* ASCR2 IO switch: : bit 28 is set to '0' to indicate that the mask is in ASCR2 register */  \r
+#define RI_IOSwitch_GR10_1     ((uint32_t)0x00000001)\r
+#define RI_IOSwitch_GR10_2     ((uint32_t)0x00000002)\r
+#define RI_IOSwitch_GR10_3     ((uint32_t)0x00000004)\r
+#define RI_IOSwitch_GR10_4     ((uint32_t)0x00000008)\r
+#define RI_IOSwitch_GR6_1      ((uint32_t)0x00000010)\r
+#define RI_IOSwitch_GR6_2      ((uint32_t)0x00000020)\r
+#define RI_IOSwitch_GR5_1      ((uint32_t)0x00000040)\r
+#define RI_IOSwitch_GR5_2      ((uint32_t)0x00000080)\r
+#define RI_IOSwitch_GR5_3      ((uint32_t)0x00000100)\r
+#define RI_IOSwitch_GR4_1      ((uint32_t)0x00000200)\r
+#define RI_IOSwitch_GR4_2      ((uint32_t)0x00000400)\r
+#define RI_IOSwitch_GR4_3      ((uint32_t)0x00000800)\r
+\r
+#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH4) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH5) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH6) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH7) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH8) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH9) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH10) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH11) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH12) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH13) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH14) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH15) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH18) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH19) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH20) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH21) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH22) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH23) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH24) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_CH25) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_VCOMP) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR10_4) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR6_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR6_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR5_3) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_1) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_2) || \\r
+                                  ((IOSWITCH) == RI_IOSwitch_GR4_3))\r
+\r
+/** @defgroup RI_Port\r
+  * @{\r
+  */\r
+\r
+#define RI_PortA                 ((uint8_t)0x01)   /*!< GPIOA selected */\r
+#define RI_PortB                 ((uint8_t)0x02)   /*!< GPIOB selected */\r
+#define RI_PortC                 ((uint8_t)0x03)   /*!< GPIOC selected */\r
+#define RI_PortD                 ((uint8_t)0x04)   /*!< GPIOD selected */\r
+#define RI_PortE                 ((uint8_t)0x05)   /*!< GPIOE selected */\r
+\r
+#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \\r
+                          ((PORT) == RI_PortB) || \\r
+                          ((PORT) == RI_PortC) || \\r
+                          ((PORT) == RI_PortD) || \\r
+                          ((PORT) == RI_PortE))\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RI_Pin define \r
+  * @{\r
+  */\r
+#define RI_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */\r
+#define RI_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */\r
+#define RI_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */\r
+#define RI_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */\r
+#define RI_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */\r
+#define RI_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */\r
+#define RI_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */\r
+#define RI_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */\r
+#define RI_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */\r
+#define RI_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */\r
+#define RI_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */\r
+#define RI_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */\r
+#define RI_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */\r
+#define RI_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */\r
+#define RI_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */\r
+#define RI_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */\r
+#define RI_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */\r
+\r
+#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup SYSCFG_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Exported_Functions\r
+  * @{\r
+  */ \r
+void SYSCFG_DeInit(void);\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);\r
+void SYSCFG_USBPuCmd(FunctionalState NewState);\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);\r
+void SYSCFG_RIDeInit(void);\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select);\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+                               FunctionalState NewState);\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32L1xx_SYSCFG_H */\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
new file mode 100644 (file)
index 0000000..e7648ab
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,223 @@
+/**\r
+  ******************************************************************************\r
+  * @file    misc.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the miscellaneous firmware functions (add-on\r
+  *          to CMSIS functions).\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC \r
+  * @brief MISC driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup MISC_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup MISC_Private_Defines\r
+  * @{\r
+  */\r
+\r
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup MISC_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.\r
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+  *                                4 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+  *                                3 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+  *                                2 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+  *                                1 bits for subpriority\r
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+  *                                0 bits for subpriority\r
+  * @retval None\r
+  */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+  \r
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the NVIC peripheral according to the specified\r
+  *   parameters in the NVIC_InitStruct.\r
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+  *   the configuration information for the specified NVIC peripheral.\r
+  * @retval None\r
+  */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  \r
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+    \r
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+  {\r
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    \r
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+    tmppre = (0x4 - tmppriority);\r
+    tmpsub = tmpsub >> tmppriority;\r
+\r
+    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+    tmppriority = tmppriority << 0x04;\r
+        \r
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+    \r
+    /* Enable the Selected IRQ Channels --------------------------------------*/\r
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Selected IRQ Channels -------------------------------------*/\r
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Sets the vector table location and Offset.\r
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_VectTab_RAM\r
+  *     @arg NVIC_VectTab_FLASH\r
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
+  * @retval None\r
+  */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+  assert_param(IS_NVIC_OFFSET(Offset));  \r
+   \r
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+  * @brief  Selects the condition for the system to enter low power mode.\r
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg NVIC_LP_SEVONPEND\r
+  *     @arg NVIC_LP_SLEEPDEEP\r
+  *     @arg NVIC_LP_SLEEPONEXIT\r
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_NVIC_LP(LowPowerMode));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  \r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    SCB->SCR |= LowPowerMode;\r
+  }\r
+  else\r
+  {\r
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the SysTick clock source.\r
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+  * @retval None\r
+  */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+  {\r
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+  }\r
+  else\r
+  {\r
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+  }\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
new file mode 100644 (file)
index 0000000..348f33c
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_exti.c
@@ -0,0 +1,268 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_exti.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the EXTI firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_exti.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI \r
+  * @brief EXTI driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup EXTI_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Defines\r
+  * @{\r
+  */\r
+\r
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void EXTI_DeInit(void)\r
+{\r
+  EXTI->IMR = 0x00000000;\r
+  EXTI->EMR = 0x00000000;\r
+  EXTI->RTSR = 0x00000000; \r
+  EXTI->FTSR = 0x00000000; \r
+  EXTI->PR = 0x007FFFFF;\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the EXTI peripheral according to the specified\r
+  *   parameters in the EXTI_InitStruct.\r
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+  *   that contains the configuration information for the EXTI peripheral.\r
+  * @retval None\r
+  */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+  uint32_t tmp = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  \r
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+  tmp = (uint32_t)EXTI_BASE;\r
+     \r
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+  {\r
+    /* Clear EXTI line configuration */\r
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+    \r
+    tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+    /* Clear Rising Falling edge configuration */\r
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+    \r
+    /* Select the trigger for the selected external interrupts */\r
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+    {\r
+      /* Rising Falling edge */\r
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+    }\r
+    else\r
+    {\r
+      tmp = (uint32_t)EXTI_BASE;\r
+      tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+    /* Disable the selected external lines */\r
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Fills each EXTI_InitStruct member with its reset value.\r
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+  *   be initialized.\r
+  * @retval None\r
+  */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+  * @brief  Generates a Software interrupt.\r
+  * @param  EXTI_Line: specifies the EXTI lines to be enabled or disabled.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified EXTI line flag is set or not.\r
+  * @param  EXTI_Line: specifies the EXTI line flag to check.\r
+  *   This parameter can be:\r
+  *     @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+  * @retval The new state of EXTI_Line (SET or RESET).\r
+  */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+  FlagStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+  \r
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the EXTI\92s line pending flags.\r
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified EXTI line is asserted or not.\r
+  * @param  EXTI_Line: specifies the EXTI line to check.\r
+  *   This parameter can be:\r
+  *     @arg EXTI_Linex: External interrupt line x where x(0..22)\r
+  * @retval The new state of EXTI_Line (SET or RESET).\r
+  */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+  ITStatus bitstatus = RESET;\r
+  uint32_t enablestatus = 0;\r
+  /* Check the parameters */\r
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+  \r
+  enablestatus =  EXTI->IMR & EXTI_Line;\r
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the EXTI\92s line pending bits.\r
+  * @param  EXTI_Line: specifies the EXTI lines to clear.\r
+  *   This parameter can be any combination of EXTI_Linex where x can be (0..22).\r
+  * @retval None\r
+  */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_LINE(EXTI_Line));\r
+  \r
+  EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
new file mode 100644 (file)
index 0000000..6c45f16
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_gpio.c
@@ -0,0 +1,437 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_gpio.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the GPIO firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO \r
+  * @brief GPIO driver modules\r
+  * @{\r
+  */\r
+\r
+/** @defgroup GPIO_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Defines\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Macros\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Variables\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset \r
+  *         values.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval None\r
+  */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+\r
+  if(GPIOx == GPIOA)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);  \r
+  }\r
+  else if(GPIOx == GPIOB)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOC)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOD)\r
+  {\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);\r
+    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);\r
+  }\r
+  else if(GPIOx == GPIOE)\r
+  {\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);\r
+  }\r
+  else\r
+  {\r
+    if(GPIOx == GPIOH)\r
+    {\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);\r
+      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Initializes the GPIOx peripheral according to the specified \r
+  *         parameters in the GPIO_InitStruct.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that \r
+  *         contains the configuration information for the specified GPIO\r
+  *         peripheral.\r
+  * @retval None\r
+  */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));\r
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));\r
+\r
+  /* -------------------------Configure the port pins---------------- */\r
+  /*-- GPIO Mode Configuration --*/\r
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)\r
+  {\r
+    pos = ((uint32_t)0x01) << pinpos;\r
+\r
+    /* Get the port pins position */\r
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+\r
+    if (currentpin == pos)\r
+    {\r
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));\r
+\r
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));\r
+\r
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))\r
+      {\r
+        /*Check Speed mode parameters */\r
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+\r
+        /*Speed mode configuration */\r
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));\r
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));\r
+\r
+        /*Check Output mode parameters */\r
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));\r
+\r
+        /* Output mode configuartion*/\r
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;\r
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));\r
+      }\r
+\r
+      /*Pull-up Pull down resistor configuration*/\r
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));\r
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Fills each GPIO_InitStruct member with its default value.\r
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will \r
+  *         be initialized.\r
+  * @retval None\r
+  */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+  /* Reset GPIO init structure parameters values */\r
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;\r
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;\r
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;\r
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;\r
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified input port pin.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to read.\r
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).\r
+  * @retval The input port pin value.\r
+  */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint8_t bitstatus = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+\r
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+  {\r
+    bitstatus = (uint8_t)Bit_SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = (uint8_t)Bit_RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified GPIO input data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval GPIO input data port value.\r
+  */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified output data port bit.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: Specifies the port bit to read.\r
+  *   This parameter can be GPIO_Pin_x where x can be (0..15).\r
+  * @retval The output port pin value.\r
+  */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint8_t bitstatus = 0x00;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+  \r
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+  {\r
+    bitstatus = (uint8_t)Bit_SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = (uint8_t)Bit_RESET;\r
+  }\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Reads the specified GPIO output data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @retval GPIO output data port value.\r
+  */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+  * @brief  Sets the selected data port bits.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bits to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  GPIOx->BSRRL = GPIO_Pin;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the selected data port bits.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bits to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  GPIOx->BSRRH = GPIO_Pin;\r
+}\r
+\r
+/**\r
+  * @brief  Sets or clears the selected data port bit.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to be written.\r
+  *   This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+  * @param  BitVal: specifies the value to be written to the selected bit.\r
+  *   This parameter can be one of the BitAction enum values:\r
+  *     @arg Bit_RESET: to clear the port pin\r
+  *     @arg Bit_SET: to set the port pin\r
+  * @retval None\r
+  */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));\r
+  \r
+  if (BitVal != Bit_RESET)\r
+  {\r
+    GPIOx->BSRRL = GPIO_Pin;\r
+  }\r
+  else\r
+  {\r
+    GPIOx->BSRRH = GPIO_Pin ;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Writes data to the specified GPIO data port.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  PortVal: specifies the value to be written to the port output data \r
+  *                  register.\r
+  * @retval None\r
+  */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  \r
+  GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+  * @brief  Locks GPIO Pins configuration registers.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_Pin: specifies the port bit to be written.\r
+  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+  * @retval None\r
+  */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+  uint32_t tmp = 0x00010000;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+  \r
+  tmp |= GPIO_Pin;\r
+  /* Set LCKK bit */\r
+  GPIOx->LCKR = tmp;\r
+  /* Reset LCKK bit */\r
+  GPIOx->LCKR =  GPIO_Pin;\r
+  /* Set LCKK bit */\r
+  GPIOx->LCKR = tmp;\r
+  /* Read LCKK bit*/\r
+  tmp = GPIOx->LCKR;\r
+  /* Read LCKK bit*/\r
+  tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+  * @brief  Changes the mapping of the specified pin.\r
+  * @param  GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral.\r
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.\r
+  *   This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+  * @param  GPIO_AFSelection: selects the pin to used as Alternat function.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg GPIO_AF_RTC_50Hz\r
+  *     @arg GPIO_AF_MCO\r
+  *     @arg GPIO_AF_TAMPER\r
+  *     @arg GPIO_AF_WKUP\r
+  *     @arg GPIO_AF_SWJ\r
+  *     @arg GPIO_AF_TRACE\r
+  *     @arg GPIO_AF_TIMESTAMP\r
+  *     @arg GPIO_AF_CALIB\r
+  *     @arg GPIO_AF_TIM2\r
+  *     @arg GPIO_AF_TIM3\r
+  *     @arg GPIO_AF_TIM4\r
+  *     @arg GPIO_AF_TIM9\r
+  *     @arg GPIO_AF_TIM10\r
+  *     @arg GPIO_AF_TIM11\r
+  *     @arg GPIO_AF_I2C1\r
+  *     @arg GPIO_AF_I2C2\r
+  *     @arg GPIO_AF_SPI1\r
+  *     @arg GPIO_AF_SPI2\r
+  *     @arg GPIO_AF_USART1\r
+  *     @arg GPIO_AF_USART2\r
+  *     @arg GPIO_AF_USART3\r
+  *     @arg GPIO_AF_USB\r
+  *     @arg GPIO_AF_LCD\r
+  *     @arg GPIO_AF_RI\r
+  *     @arg GPIO_AF_EVENTOUT\r
+  * @retval None\r
+  */\r
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)\r
+{\r
+  uint32_t temp = 0x00;\r
+  uint32_t temp_2 = 0x00;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+  assert_param(IS_GPIO_AF(GPIO_AF));\r
+  \r
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;\r
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;\r
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
new file mode 100644 (file)
index 0000000..f7bdb49
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_rcc.c
@@ -0,0 +1,1225 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_rcc.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the RCC firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup RCC \r
+  * @brief RCC driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup RCC_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber           0x00\r
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of MSION bit */\r
+#define MSION_BitNumber           0x08\r
+#define CR_MSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber           0x18\r
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber           0x1C\r
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET                (RCC_OFFSET + 0x34)\r
+#define LSION_BitNumber           0x00\r
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define RTCEN_BitNumber           0x16\r
+#define CSR_RTCEN_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of RTCRST bit */\r
+#define RTCRST_BitNumber          0x17\r
+#define CSR_RTCRST_BB             (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))\r
+\r
+\r
+/* ---------------------- RCC registers mask -------------------------------- */\r
+/* RCC Flag Mask */\r
+#define FLAG_MASK                 ((uint8_t)0x1F)\r
+\r
+/* CR register byte 3 (Bits[23:16]) base address */\r
+#define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)\r
+\r
+/* ICSCR register byte 4 (Bits[31:24]) base address */\r
+#define ICSCR_BYTE4_ADDRESS       ((uint32_t)0x40023807)\r
+\r
+/* CFGR register byte 3 (Bits[23:16]) base address */\r
+#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x4002380A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x4002380B)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002380D)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002380E)\r
+\r
+/* CSR register byte 2 (Bits[15:8]) base address */\r
+#define CSR_BYTE2_ADDRESS         ((uint32_t)0x40023835)\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RCC_Private_Macros\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup RCC_Private_Variables\r
+  * @{\r
+  */ \r
+\r
+static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static __I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @defgroup RCC_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Resets the RCC clock configuration to the default reset state.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void RCC_DeInit(void)\r
+{\r
+  \r
+  /* Set MSION bit */\r
+  RCC->CR |= (uint32_t)0x00000100;\r
+\r
+  /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+  RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+  \r
+  /* Reset HSION, HSEON, CSSON and PLLON bits */\r
+  RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+  /* Reset HSEBYP bit */\r
+  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+  /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+  /* Disable all interrupts */\r
+  RCC->CIR = 0x00000000;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External High Speed oscillator (HSE).\r
+  * @note   HSE can not be stopped if it is used directly or through the PLL as system clock.\r
+  * @param RCC_HSE: specifies the new state of the HSE.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HSE_OFF: HSE oscillator OFF\r
+  *     @arg RCC_HSE_ON: HSE oscillator ON\r
+  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+  * @retval None\r
+  */\r
+void RCC_HSEConfig(uint8_t RCC_HSE)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HSE(RCC_HSE));\r
+\r
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;\r
+\r
+  /* Set the new HSE configuration -------------------------------------------*/\r
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;\r
+\r
+}\r
+\r
+/**\r
+  * @brief  Waits for HSE start-up.\r
+  * @param  None\r
+  * @retval An ErrorStatus enumuration value:\r
+  *          - SUCCESS: HSE oscillator is stable and ready to use\r
+  *          - ERROR: HSE oscillator not yet ready\r
+  */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0;\r
+  ErrorStatus status = ERROR;\r
+  FlagStatus HSEStatus = RESET;\r
+  \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+    StartUpCounter++;  \r
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+  \r
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+  {\r
+    status = SUCCESS;\r
+  }\r
+  else\r
+  {\r
+    status = ERROR;\r
+  }  \r
+  return (status);\r
+}\r
+\r
+/**\r
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.\r
+  *   This parameter must be a number between 0 and 0x1F.\r
+  * @retval None\r
+  */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));\r
+  \r
+  tmpreg = RCC->ICSCR;\r
+  \r
+  /* Clear HSITRIM[4:0] bits */\r
+  tmpreg &= ~RCC_ICSCR_HSITRIM;\r
+  \r
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+  tmpreg |= (uint32_t)HSICalibrationValue << 8;\r
+\r
+  /* Store the new value */\r
+  RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Adjusts the Internal Multi Speed oscillator (MSI) calibration value.\r
+  * @param  MSICalibrationValue: specifies the MSI calibration trimming value.\r
+  *   This parameter must be a number between 0 and 0xFF.\r
+  * @retval None\r
+  */\r
+void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue)\r
+{\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue));\r
+\r
+  *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue;  \r
+}\r
+\r
+/**\r
+  * @brief  Configures the Internal Multi Speed oscillator (MSI) clock range.\r
+  * @param  RCC_MSIRange: specifies the MSI Clcok range.\r
+  *   This parameter must be one of the following values:\r
+  *     @arg RCC_MSIRange_64KHz:  MSI clock is around 64 KHz\r
+  *     @arg RCC_MSIRange_128KHz: MSI clock is around 128 KHz\r
+  *     @arg RCC_MSIRange_256KHz: MSI clock is around 256 KHz\r
+  *     @arg RCC_MSIRange_512KHz: MSI clock is around 512 KHz\r
+  *     @arg RCC_MSIRange_1MHz:   MSI clock is around 1 MHz\r
+  *     @arg RCC_MSIRange_2MHz:   MSI clock is around 2 MHz\r
+  *     @arg RCC_MSIRange_4MHz:   MSI clock is around 4 MHz             \r
+  * @retval None\r
+  */\r
+void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));\r
+  \r
+  tmpreg = RCC->ICSCR;\r
+  \r
+  /* Clear MSIRANGE[2:0] bits */\r
+  tmpreg &= ~RCC_ICSCR_MSIRANGE;\r
+  \r
+  /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */\r
+  tmpreg |= (uint32_t)RCC_MSIRange;\r
+\r
+  /* Store the new value */\r
+  RCC->ICSCR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal Multi Speed oscillator (MSI).\r
+  * @note   MSI can not be stopped if it is used directly as system clock.\r
+  * @param  NewState: new state of the MSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_MSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).\r
+  * @note   HSI can not be stopped if it is used directly or through the PLL as system clock.\r
+  * @param  NewState: new state of the HSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the PLL clock source and multiplication factor.\r
+  * @note   This function must be used only when the PLL is disabled.\r
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry\r
+  *     @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry\r
+  * @param  RCC_PLLMul: specifies the PLL multiplication factor.\r
+  *   This parameter can be:\r
+  *     @arg RCC_PLLMul_3: PLL Clock entry multiplied by 3\r
+  *     @arg RCC_PLLMul_4: PLL Clock entry multiplied by 4\r
+  *     @arg RCC_PLLMul_6: PLL Clock entry multiplied by 6\r
+  *     @arg RCC_PLLMul_8: PLL Clock entry multiplied by 8\r
+  *     @arg RCC_PLLMul_12: PLL Clock entry multiplied by 12\r
+  *     @arg RCC_PLLMul_16: PLL Clock entry multiplied by 16  \r
+  *     @arg RCC_PLLMul_24: PLL Clock entry multiplied by 24\r
+  *     @arg RCC_PLLMul_32: PLL Clock entry multiplied by 32\r
+  *     @arg RCC_PLLMul_48: PLL Clock entry multiplied by 48             \r
+  * @param  RCC_PLLDiv: specifies the PLL division factor.\r
+  *   This parameter can be:\r
+  *     @arg RCC_PLLDiv_2: PLL Clock output divided by 2  \r
+  *     @arg RCC_PLLDiv_3: PLL Clock output divided by 3         \r
+  *     @arg RCC_PLLDiv_4: PLL Clock output divided by 4   \r
+  * @retval None\r
+  */\r
+void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+  assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));\r
+  \r
+  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the PLL.\r
+  * @note   The PLL can not be disabled if it is used as system clock.\r
+  * @param  NewState: new state of the PLL.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the system clock (SYSCLK).\r
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock. \r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_SYSCLKSource_MSI:    MSI selected as system clock\r
+  *     @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock\r
+  *     @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock\r
+  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+  * @retval None\r
+  */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear SW[1:0] bits */\r
+  tmpreg &= ~RCC_CFGR_SW;\r
+  \r
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+  tmpreg |= RCC_SYSCLKSource;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the clock source used as system clock.\r
+  * @param  None\r
+  * @retval The clock source used as system clock. The returned value can be one \r
+  *         of the following values:\r
+  *              - 0x00: MSI used as system clock\r
+  *              - 0x04: HSI used as system clock  \r
+  *              - 0x08: HSE used as system clock\r
+  *              - 0x0C: PLL used as system clock\r
+  */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));\r
+}\r
+\r
+/**\r
+  * @brief  Configures the AHB clock (HCLK).\r
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+  *                     the system clock (SYSCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK\r
+  *     @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2\r
+  *     @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4\r
+  *     @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8\r
+  *     @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16\r
+  *     @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64\r
+  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+  * @retval None\r
+  */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear HPRE[3:0] bits */\r
+  tmpreg &= ~RCC_CFGR_HPRE;\r
+  \r
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+  tmpreg |= RCC_SYSCLK;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the Low Speed APB clock (PCLK1).\r
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+  *                   the AHB clock (HCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HCLK_Div1:  APB1 clock = HCLK\r
+  *     @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2\r
+  *     @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4\r
+  *     @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8\r
+  *     @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+  * @retval None\r
+  */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear PPRE1[2:0] bits */\r
+  tmpreg &= ~RCC_CFGR_PPRE1;\r
+  \r
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+  tmpreg |= RCC_HCLK;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the High Speed APB clock (PCLK2).\r
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+  *                   the AHB clock (HCLK).\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_HCLK_Div1:  APB2 clock = HCLK\r
+  *     @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2\r
+  *     @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4\r
+  *     @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8\r
+  *     @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+  * @retval None\r
+  */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+  uint32_t tmpreg = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+  \r
+  tmpreg = RCC->CFGR;\r
+  \r
+  /* Clear PPRE2[2:0] bits */\r
+  tmpreg &= ~RCC_CFGR_PPRE2;\r
+  \r
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+  tmpreg |= RCC_HCLK << 3;\r
+  \r
+  /* Store the new value */\r
+  RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the specified RCC interrupts.\r
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt\r
+  * @param  NewState: new state of the specified RCC interrupts.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_IT(RCC_IT));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */\r
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+  }\r
+  else\r
+  {\r
+    /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */\r
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Configures the External Low Speed oscillator (LSE).\r
+  * @param  RCC_LSE: specifies the new state of the LSE.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_LSE_OFF: LSE oscillator OFF\r
+  *     @arg RCC_LSE_ON: LSE oscillator ON\r
+  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+  * @retval None\r
+  */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_LSE(RCC_LSE));\r
+  \r
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;\r
+\r
+  /* Set the new LSE configuration -------------------------------------------*/\r
+  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;  \r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).\r
+  * @note   LSI can not be disabled if the IWDG is running.\r
+  * @param  NewState: new state of the LSI.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the RTC and LCD clock (RTCCLK / LCDCLK).\r
+  * @note   \r
+  *   - Once the RTC clock is selected it can't be changed unless the RTC is\r
+  *     reset using RCC_RTCResetCmd function.\r
+  *   - This RTC clock (RTCCLK) is used to clock the LCD (LCDCLK).  \r
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock\r
+  *     @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock      \r
+  * @retval None\r
+  */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+  uint32_t     tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+  \r
+  if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)\r
+  { \r
+    /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */\r
+    tmpreg = RCC->CR;\r
+\r
+    /* Clear RTCPRE[1:0] bits */\r
+    tmpreg &= ~RCC_CR_RTCPRE;\r
+\r
+    /* Configure HSE division factor for RTC clock */\r
+    tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE);\r
+\r
+    /* Store the new value */\r
+    RCC->CR = tmpreg;\r
+  }\r
+         \r
+  RCC->CSR &= ~RCC_CSR_RTCSEL;\r
+  \r
+  /* Select the RTC clock source */\r
+  RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL);\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the RTC clock.\r
+  * @note   This function must be used only after the RTC clock was selected using the \r
+  *   RCC_RTCCLKConfig function.\r
+  * @param  NewState: new state of the RTC clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases the RTC peripheral reset.\r
+  * @param  NewState: new state of the RTC reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_RTCResetCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Returns the frequencies of different on chip clocks.\r
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold \r
+  *   the clocks frequencies.\r
+  * @retval None\r
+  */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0;\r
+\r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+  \r
+  switch (tmp)\r
+  {\r
+    case 0x00:  /* MSI used as system clock */\r
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;\r
+      RCC_Clocks->SYSCLK_Frequency = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));\r
+      break;\r
+    case 0x04:  /* HSI used as system clock */\r
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+      break;\r
+    case 0x08:  /* HSE used as system clock */\r
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+      break;\r
+    case 0x0C:  /* PLL used as system clock */\r
+      /* Get PLL clock source and multiplication factor ----------------------*/\r
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+      pllmul = PLLMulTable[(pllmul >> 18)];\r
+      plldiv = (plldiv >> 22) + 1;\r
+      \r
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock selected as PLL clock entry */\r
+        RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv);\r
+      }\r
+      else\r
+      {\r
+        /* HSE selected as PLL clock entry */\r
+        RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv);\r
+      }\r
+      break;\r
+    default:\r
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+      break;\r
+  }\r
+  /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;\r
+  tmp = tmp >> 4;\r
+  presc = APBAHBPrescTable[tmp]; \r
+  /* HCLK clock frequency */\r
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+\r
+  /* Get PCLK1 prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_PPRE1;\r
+  tmp = tmp >> 8;\r
+  presc = APBAHBPrescTable[tmp];\r
+  /* PCLK1 clock frequency */\r
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+\r
+  /* Get PCLK2 prescaler */\r
+  tmp = RCC->CFGR & RCC_CFGR_PPRE2;\r
+  tmp = tmp >> 11;\r
+  presc = APBAHBPrescTable[tmp];\r
+  /* PCLK2 clock frequency */\r
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the AHB peripheral clock.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_DMA1\r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBENR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBENR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1            \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2ENR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2ENR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP                                \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1ENR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1ENR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases AHB peripheral reset.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_DMA1   \r
+  * @param  NewState: new state of the specified peripheral reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBRSTR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1  \r
+  * @param  NewState: new state of the specified peripheral reset.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2RSTR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP    \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1RSTR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the AHB peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_AHBPeriph_GPIOA\r
+  *     @arg RCC_AHBPeriph_GPIOB\r
+  *     @arg RCC_AHBPeriph_GPIOC  \r
+  *     @arg RCC_AHBPeriph_GPIOD\r
+  *     @arg RCC_AHBPeriph_GPIOE\r
+  *     @arg RCC_AHBPeriph_GPIOH\r
+  *     @arg RCC_AHBPeriph_CRC\r
+  *     @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)  \r
+  *     @arg RCC_AHBPeriph_SRAM     \r
+  *     @arg RCC_AHBPeriph_DMA1\r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->AHBLPENR |= RCC_AHBPeriph;\r
+  }\r
+  else\r
+  {\r
+    RCC->AHBLPENR &= ~RCC_AHBPeriph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the APB2 peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB2Periph_SYSCFG\r
+  *     @arg RCC_APB2Periph_TIM9\r
+  *     @arg RCC_APB2Periph_TIM10\r
+  *     @arg RCC_APB2Periph_TIM11\r
+  *     @arg RCC_APB2Periph_ADC1\r
+  *     @arg RCC_APB2Periph_SPI1\r
+  *     @arg RCC_APB2Periph_USART1            \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB2LPENR |= RCC_APB2Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB2LPENR &= ~RCC_APB2Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the APB1 peripheral clock during Low Power (SLEEP) mode.\r
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_APB1Periph_TIM2\r
+  *     @arg RCC_APB1Periph_TIM3\r
+  *     @arg RCC_APB1Periph_TIM4\r
+  *     @arg RCC_APB1Periph_TIM6\r
+  *     @arg RCC_APB1Periph_TIM7\r
+  *     @arg RCC_APB1Periph_LCD\r
+  *     @arg RCC_APB1Periph_WWDG\r
+  *     @arg RCC_APB1Periph_SPI2\r
+  *     @arg RCC_APB1Periph_USART2\r
+  *     @arg RCC_APB1Periph_USART3\r
+  *     @arg RCC_APB1Periph_I2C1\r
+  *     @arg RCC_APB1Periph_I2C2\r
+  *     @arg RCC_APB1Periph_USB\r
+  *     @arg RCC_APB1Periph_PWR\r
+  *     @arg RCC_APB1Periph_DAC\r
+  *     @arg RCC_APB1Periph_COMP                                \r
+  * @param  NewState: new state of the specified peripheral clock.\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    RCC->APB1LPENR |= RCC_APB1Periph;\r
+  }\r
+  else\r
+  {\r
+    RCC->APB1LPENR &= ~RCC_APB1Periph;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enables or disables the Clock Security System.\r
+  * @param  NewState: new state of the Clock Security System..\r
+  *   This parameter can be: ENABLE or DISABLE.\r
+  * @retval None\r
+  */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+  * @brief  Selects the clock source to output on MCO pin.\r
+  * @param  RCC_MCOSource: specifies the clock source to output.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_MCOSource_NoClock: No clock selected\r
+  *     @arg RCC_MCOSource_SYSCLK: System clock selected\r
+  *     @arg RCC_MCOSource_HSI: HSI oscillator clock selected\r
+  *     @arg RCC_MCOSource_MSI: MSI oscillator clock selected  \r
+  *     @arg RCC_MCOSource_HSE: HSE oscillator clock selected\r
+  *     @arg RCC_MCOSource_PLLCLK: PLL clock selected\r
+  *     @arg RCC_MCOSource_LSI: LSI clock selected\r
+  *     @arg RCC_MCOSource_LSE: LSE clock selected    \r
+  * @param  RCC_MCODiv: specifies the MCO prescaler.\r
+  *   This parameter can be one of the following values: \r
+  *     @arg RCC_MCODiv_1: no division applied to MCO clock \r
+  *     @arg RCC_MCODiv_2: division by 2 applied to MCO clock\r
+  *     @arg RCC_MCODiv_4: division by 4 applied to MCO clock\r
+  *     @arg RCC_MCODiv_8: division by 8 applied to MCO clock\r
+  *     @arg RCC_MCODiv_16: division by 16 applied to MCO clock             \r
+  * @retval None\r
+  */\r
+void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));\r
+  assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));\r
+    \r
+  /* Select MCO clock source and prescaler */\r
+  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS =  RCC_MCOSource | RCC_MCODiv; \r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified RCC flag is set or not.\r
+  * @param  RCC_FLAG: specifies the flag to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+  *     @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready  \r
+  *     @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+  *     @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+  *     @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+  *     @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+  *     @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset \r
+  *     @arg RCC_FLAG_PINRST: Pin reset\r
+  *     @arg RCC_FLAG_PORRST: POR/PDR reset\r
+  *     @arg RCC_FLAG_SFTRST: Software reset\r
+  *     @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+  *     @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+  *     @arg RCC_FLAG_LPWRRST: Low Power reset\r
+  * @retval The new state of RCC_FLAG (SET or RESET).\r
+  */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+  uint32_t tmp = 0;\r
+  uint32_t statusreg = 0;\r
+  FlagStatus bitstatus = RESET;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+  /* Get the RCC register index */\r
+  tmp = RCC_FLAG >> 5;\r
+\r
+  if (tmp == 1)               /* The flag to check is in CR register */\r
+  {\r
+    statusreg = RCC->CR;\r
+  }\r
+  else          /* The flag to check is in CSR register (tmp == 2) */\r
+  {\r
+    statusreg = RCC->CSR;\r
+  }\r
+\r
+  /* Get the flag position */\r
+  tmp = RCC_FLAG & FLAG_MASK;\r
+\r
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the flag status */\r
+  return bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the RCC reset flags.\r
+  *   The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, \r
+  *   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void RCC_ClearFlag(void)\r
+{\r
+  /* Set RMVF bit to clear the reset flags */\r
+  RCC->CSR |= RCC_CSR_RMVF;\r
+}\r
+\r
+/**\r
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.\r
+  * @param  RCC_IT: specifies the RCC interrupt source to check.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt \r
+  *     @arg RCC_IT_CSS: Clock Security System interrupt\r
+  * @retval The new state of RCC_IT (SET or RESET).\r
+  */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+  ITStatus bitstatus = RESET;\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_GET_IT(RCC_IT));\r
+  \r
+  /* Check the status of the specified RCC interrupt */\r
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+  {\r
+    bitstatus = SET;\r
+  }\r
+  else\r
+  {\r
+    bitstatus = RESET;\r
+  }\r
+  /* Return the RCC_IT status */\r
+  return  bitstatus;\r
+}\r
+\r
+/**\r
+  * @brief  Clears the RCC's interrupt pending bits.\r
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.\r
+  *   This parameter can be any combination of the following values:\r
+  *     @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+  *     @arg RCC_IT_LSERDY: LSE ready interrupt\r
+  *     @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+  *     @arg RCC_IT_HSERDY: HSE ready interrupt\r
+  *     @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+  *     @arg RCC_IT_MSIRDY: MSI ready interrupt  \r
+  *     @arg RCC_IT_CSS: Clock Security System interrupt\r
+  * @retval None\r
+  */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+  \r
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+     pending bits */\r
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
new file mode 100644 (file)
index 0000000..0d9bef1
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/STM32L1xx_StdPeriph_Driver/src/stm32l1xx_syscfg.c
@@ -0,0 +1,494 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32l1xx_syscfg.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file provides all the SYSCFG and RI firmware functions.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_syscfg.h"\r
+#include "stm32l1xx_rcc.h"\r
+\r
+/** @addtogroup STM32L1xx_StdPeriph_Driver\r
+  * @{\r
+  */\r
+\r
+/** @defgroup SYSCFG \r
+  * @brief SYSCFG driver modules\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_TypesDefinitions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Defines\r
+  * @{\r
+  */ \r
+  \r
+#define RI_ICR_RESET_VALUE          ((uint32_t)0x00000000) /*!< ICR Reset value */\r
+#define RI_ASCR1_RESET_VALUE        ((uint32_t)0x00000000) /*!< ASCR1 Reset value */\r
+#define RI_ASCR2_RESET_VALUE        ((uint32_t)0x00000000) /*!< ASCR2 Reset value */\r
+#define RI_HYSCR1_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR1 Reset value */\r
+#define RI_HYSCR2_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR2 Reset value */\r
+#define RI_HYSCR3_RESET_VALUE       ((uint32_t)0x00000000) /*!< HYSCR3 Reset value */\r
+\r
+#define TIM_SELECT_MASK             ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */\r
+#define IC_ROUTING_MASK             ((uint32_t)0x0000000F) /*!< Input Capture routing mask */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Variables\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_FunctionPrototypes\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup SYSCFG_Private_Functions\r
+  * @{\r
+  */ \r
+\r
+/**\r
+  * @brief  Deinitializes the syscfg registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  * @ Note: MEMRMP bits are not reset by APB2 reset.\r
+  */\r
+void SYSCFG_DeInit(void)\r
+{\r
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);\r
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);\r
+}\r
+\r
+/**\r
+  * @brief  Changes the mapping of the specified pin.\r
+  * @param  SYSCFG_Memory: selects the memory remapping.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  \r
+  *     @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000\r
+  *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000     \r
+  * @retval None\r
+  */\r
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));\r
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;\r
+}\r
+\r
+/**\r
+  * @brief  Control the internal pull-up on USB DP line.\r
+  * @param  NewState: New state of the switch control mode. \r
+  *   This parameter can be ENABLE: Connect internal pull-up on USB DP line.\r
+  *                      or DISABLE: Disconnect internal pull-up on USB DP line.\r
+  * @retval None\r
+  */\r
+void SYSCFG_USBPuCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+  if (NewState != DISABLE)\r
+  { \r
+    /* Connect internal pull-up on USB DP line */\r
+    SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;\r
+  }\r
+  else\r
+  {\r
+    /* Disconnect internal pull-up on USB DP line */\r
+    SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Selects the GPIO pin used as EXTI Line.\r
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source \r
+  *                                for EXTI lines where x can be (A, B, C, D, E or H).\r
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.\r
+  *   This parameter can be EXTI_PinSourcex where x can be (0..15)\r
+  * @retval None\r
+  */\r
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)\r
+{\r
+  uint32_t tmp = 0x00;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));\r
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));\r
+  \r
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));\r
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;\r
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+  * @brief Deinitializes the RI registers to their default reset values.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIDeInit(void)\r
+{\r
+  RI->ICR     = RI_ICR_RESET_VALUE;         /*!< Set RI->ICR to reset value */\r
+  RI->ASCR1   = RI_ASCR1_RESET_VALUE;       /*!< Set RI->ASCR1 to reset value */  \r
+  RI->ASCR2   = RI_ASCR2_RESET_VALUE;       /*!< Set RI->ASCR2 to reset value */  \r
+  RI->HYSCR1  = RI_HYSCR1_RESET_VALUE;      /*!< Set RI->HYSCR1 to reset value */\r
+  RI->HYSCR2  = RI_HYSCR2_RESET_VALUE;      /*!< Set RI->HYSCR2 to reset value */\r
+  RI->HYSCR3  = RI_HYSCR3_RESET_VALUE;      /*!< Set RI->HYSCR3 to reset value */\r
+}\r
+\r
+/**\r
+  * @brief  Configures the routing interface to select which Timer to be routed.\r
+  * @param  TIM_Select: Timer select.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg TIM_Select_None : No timer selected\r
+  *     @arg TIM_Select_TIM2 : Timer 2 selected \r
+  *     @arg TIM_Select_TIM3 : Timer 3 selected \r
+  *     @arg TIM_Select_TIM4 : Timer 4 selected \r
+  * @retval None.\r
+  */\r
+void SYSCFG_RITIMSelect(uint32_t TIM_Select)\r
+{\r
+  uint32_t tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_TIM(TIM_Select));\r
+\r
+  /* Get the old register value */\r
+  tmpreg = RI->ICR;\r
+\r
+  /* Clear the TIMx select bits */\r
+  tmpreg &= TIM_SELECT_MASK;\r
+\r
+  /* Select the Timer */\r
+  tmpreg |= (TIM_Select);\r
+\r
+  /* Write to RI->ICR register */\r
+  RI->ICR = tmpreg;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the routing interface to select which Timer Input Capture\r
+  *         to be routed to a selected pin.\r
+  * @param  RI_InputCapture selects which input capture to be routed.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg  RI_InputCapture_IC1: Input capture 1 is slected.\r
+  *     @arg  RI_InputCapture_IC2: Input capture 2 is slected.\r
+  *     @arg  RI_InputCapture_IC3: Input capture 3 is slected.\r
+  *     @arg  RI_InputCapture_IC4: Input capture 4 is slected.\r
+  * @param  RI_InputCaptureRouting: selects which pin to be routed to Input Capture.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg  RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15\r
+  * @Note Input capture selection bits are not reset by this function.\r
+  * @retval None.\r
+  */\r
+void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)\r
+{\r
+  uint32_t tmpreg = 0;\r
+\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));\r
+  assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));\r
+\r
+  /* Get the old register value */\r
+  tmpreg = RI->ICR;\r
+\r
+  /* Select input captures to be routed */\r
+  tmpreg |= (RI_InputCapture);\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~IC_ROUTING_MASK);\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( RI_InputCaptureRouting);\r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); \r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));  \r
+  }\r
+\r
+  if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)\r
+  {\r
+    /* Clear the input capture select bits */\r
+    tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));\r
+\r
+    /* Set RI_InputCaptureRouting bits  */\r
+    tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));  \r
+  }\r
+\r
+  /* Write to RI->ICR register */\r
+  RI->ICR = tmpreg;\r
+}\r
+/**\r
+  * @brief  Configures the Pull-up and Pull-down Resistors \r
+  * @param  RI_Resistor selects the resistor to connect. \r
+  *   This parameter can be  one of the following values:\r
+  *     @arg RI_Resistor_10KPU : 10K pull-up resistor\r
+  *     @arg RI_Resistor_400KPU : 400K pull-up resistor \r
+  *     @arg RI_Resistor_10KPD : 10K pull-down resistor \r
+  *     @arg RI_Resistor_400KPD : 400K pull-down resistor\r
+  * @param  NewState: New state of the analog switch associated to the selected resistor.\r
+  *   This parameter can be:\r
+  *      ENABLE so the selected resistor is connected\r
+  *   or DISABLE so the selected resistor is disconnected\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_RESISTOR(RI_Resistor));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if (NewState != DISABLE)\r
+  {\r
+    /* Enable the resistor */\r
+    COMP->CSR |= (uint32_t) RI_Resistor;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Resistor */\r
+    COMP->CSR &= (uint32_t) (~RI_Resistor);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Close or Open the routing interface Input Output switches.\r
+  * @param  RI_IOSwitch: selects the I/O analog switch number.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15\r
+  *     @argRI_IOSwitch_CH18 --> RI_IOSwitch_CH25\r
+  *     @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4\r
+  *     @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2\r
+  *     @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3\r
+  *     @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3\r
+  *     @arg  RI_IOSwitch_VCOMP\r
+  * @param  NewState: New state of the analog switch. \r
+  *   This parameter can be \r
+  *     ENABLE so the Input Output switch is closed\r
+  *     or DISABLE so the Input Output switch is open\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)\r
+{\r
+  uint32_t IOSwitchmask = 0;\r
+  \r
+  /* Check the parameters */\r
+  assert_param(IS_RI_IOSWITCH(RI_IOSwitch));\r
+  \r
+  /* Read Analog switch register index*/\r
+  IOSwitchmask = RI_IOSwitch >> 28;\r
+  \r
+  /** Get Bits[27:0] of the IO switch */\r
+  RI_IOSwitch  &= 0x0FFFFFFF;\r
+  \r
+  \r
+  if (NewState != DISABLE)\r
+  { \r
+    if (IOSwitchmask != 0)\r
+    {\r
+      /* Close the analog switches */\r
+      RI->ASCR1 |= RI_IOSwitch;\r
+    }\r
+    else\r
+    {\r
+      /* Open the analog switches */\r
+      RI->ASCR2 |= RI_IOSwitch;\r
+    }\r
+  }\r
+  else\r
+  {\r
+    if (IOSwitchmask != 0)\r
+    {\r
+      /* Close the analog switches */\r
+      RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);\r
+    }\r
+    else\r
+    {\r
+      /* Open the analog switches */\r
+      RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable or disable the switch control mode.\r
+  * @param  NewState: New state of the switch control mode. This parameter can\r
+  *         be ENABLE: ADC analog switches closed if the corresponding \r
+  *                    I/O switch is also closed. \r
+  *         or DISABLE: ADC analog switches open or controlled by the ADC interface.\r
+  * @retval None\r
+  */\r
+void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  \r
+  \r
+  if (NewState != DISABLE)\r
+  { \r
+    /* Enable the Switch control mode */  \r
+    RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;\r
+  }\r
+  else\r
+  {\r
+    /* Disable the Switch control mode */  \r
+    RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A..E \r
+  * @param  RI_Port: selects the GPIO Port.\r
+  *   This parameter can be one of the following values:\r
+  *     @arg RI_PortA : Port A is selected\r
+  *     @arg RI_PortB : Port B is selected\r
+  *     @arg RI_PortC : Port C is selected\r
+  *     @arg RI_PortD : Port D is selected\r
+  *     @arg RI_PortE : Port E is selected\r
+  *  @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.\r
+  *    This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.\r
+  *  @param  NewState new state of the Hysteresis.\r
+  *   This parameter can be:\r
+  *      ENABLE so the Hysteresis is on\r
+  *   or DISABLE so the Hysteresis is off\r
+  * @retval None\r
+  */\r
+void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,\r
+                             FunctionalState NewState)\r
+{\r
+  /* Check the parameters */\r
+  assert_param(IS_RI_PORT(RI_Port));\r
+  assert_param(IS_RI_PIN(RI_Pin));\r
+  assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+  \r
+  if(RI_Port == RI_PortA)\r
+  {  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR1 |= (uint32_t) RI_Pin;\r
+    }\r
+  }\r
+  \r
+  else if(RI_Port == RI_PortB)\r
+  {\r
+  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+    }\r
+  }  \r
+ \r
+  else if(RI_Port == RI_PortC)\r
+  {\r
+  \r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR2 |= (uint32_t) (RI_Pin );\r
+    }\r
+  } \r
+  else if(RI_Port == RI_PortD)\r
+  {\r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);\r
+\r
+    }\r
+  }   \r
+  else /* RI_Port == RI_PortE */\r
+  {\r
+    if (NewState != DISABLE)\r
+    {\r
+      /* Hysteresis on */\r
+      RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));\r
+    }\r
+    else\r
+    {\r
+      /* Hysteresis off */\r
+      RI->HYSCR3 |= (uint32_t) (RI_Pin );\r
+    }\r
+  }   \r
+}\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/   \r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
new file mode 100644 (file)
index 0000000..8ede05b
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/startup_stm32l1xx_md.s
@@ -0,0 +1,459 @@
+;/******************** (C) COPYRIGHT 2010 STMicroelectronics ********************\r
+;* File Name          : startup_stm32l15x_lp.s\r
+;* Author             : MCD Application Team\r
+;* Version            : V1.0.0RC1\r
+;* Date               : 07/02/2010\r
+;* Description        : STM32L15x Low Power Devices vector table for EWARM5.x toolchain.\r
+;*                      This module performs:\r
+;*                      - Set the initial SP\r
+;*                      - Set the initial PC == __iar_program_start,\r
+;*                      - Set the vector table entries with the exceptions ISR\r
+;*                        address.\r
+;*                      After Reset the Cortex-M3 processor is in Thread mode,\r
+;*                      priority is Privileged, and the Stack is set to Main.\r
+;********************************************************************************\r
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.\r
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,\r
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE\r
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING\r
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+;*******************************************************************************/\r
+;\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+        MODULE  ?cstartup\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+        EXTERN  SystemInit\r
+        EXTERN vPortSVCHandler\r
+        EXTERN xPortPendSVHandler\r
+        EXTERN xPortSysTickHandler             \r
+               \r
+        PUBLIC  __vector_table\r
+\r
+        DATA\r
+__vector_table\r
+        DCD     sfe(CSTACK)\r
+        DCD     Reset_Handler             ; Reset Handler\r
+\r
+        DCD     NMI_Handler               ; NMI Handler\r
+        DCD     HardFault_Handler         ; Hard Fault Handler\r
+        DCD     MemManage_Handler         ; MPU Fault Handler\r
+        DCD     BusFault_Handler          ; Bus Fault Handler\r
+        DCD     UsageFault_Handler        ; Usage Fault Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     0                         ; Reserved\r
+        DCD     vPortSVCHandler           ; SVCall Handler\r
+        DCD     DebugMon_Handler          ; Debug Monitor Handler\r
+        DCD     0                         ; Reserved\r
+        DCD     xPortPendSVHandler        ; PendSV Handler\r
+        DCD     xPortSysTickHandler       ; SysTick Handler\r
+\r
+         ; External Interrupts\r
+        DCD     WWDG_IRQHandler           ; Window Watchdog\r
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\r
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp\r
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup\r
+        DCD     FLASH_IRQHandler          ; FLASH\r
+        DCD     RCC_IRQHandler            ; RCC\r
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0\r
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1\r
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2\r
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3\r
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4\r
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1\r
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2\r
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3\r
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4\r
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5\r
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6\r
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7\r
+        DCD     ADC1_IRQHandler           ; ADC1\r
+        DCD     USB_HP_IRQHandler         ; USB High Priority\r
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority\r
+        DCD     DAC_IRQHandler            ; DAC\r
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line\r
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5\r
+        DCD     LCD_IRQHandler            ; LCD\r
+        DCD     TIM9_IRQHandler           ; TIM9\r
+        DCD     TIM10_IRQHandler          ; TIM10\r
+        DCD     TIM11_IRQHandler          ; TIM11\r
+        DCD     TIM2_IRQHandler           ; TIM2\r
+        DCD     TIM3_IRQHandler           ; TIM3\r
+        DCD     TIM4_IRQHandler           ; TIM4\r
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event\r
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error\r
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event\r
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error\r
+        DCD     SPI1_IRQHandler           ; SPI1\r
+        DCD     SPI2_IRQHandler           ; SPI2\r
+        DCD     USART1_IRQHandler         ; USART1\r
+        DCD     USART2_IRQHandler         ; USART2\r
+        DCD     USART3_IRQHandler         ; USART3\r
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10\r
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line\r
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend\r
+        DCD     TIM6_IRQHandler           ; TIM6\r
+        DCD     TIM7_IRQHandler           ; TIM7\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+\r
+        PUBWEAK Reset_Handler\r
+        SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+        LDR     R0, =SystemInit\r
+        BLX     R0\r
+        LDR     R0, =__iar_program_start\r
+        BX      R0\r
+\r
+        PUBWEAK NMI_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+        B NMI_Handler\r
+\r
+\r
+        PUBWEAK HardFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+        B HardFault_Handler\r
+\r
+\r
+        PUBWEAK MemManage_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+        B MemManage_Handler\r
+\r
+\r
+        PUBWEAK BusFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+        B BusFault_Handler\r
+\r
+\r
+        PUBWEAK UsageFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+        B UsageFault_Handler\r
+\r
+\r
+        PUBWEAK SVC_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+        B SVC_Handler\r
+\r
+\r
+        PUBWEAK DebugMon_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+        B DebugMon_Handler\r
+\r
+\r
+        PUBWEAK PendSV_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+        B PendSV_Handler\r
+\r
+\r
+        PUBWEAK SysTick_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+        B SysTick_Handler\r
+\r
+\r
+        PUBWEAK WWDG_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+WWDG_IRQHandler\r
+        B WWDG_IRQHandler\r
+\r
+\r
+        PUBWEAK PVD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PVD_IRQHandler\r
+        B PVD_IRQHandler\r
+\r
+\r
+        PUBWEAK TAMPER_STAMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TAMPER_STAMP_IRQHandler\r
+        B TAMPER_STAMP_IRQHandler\r
+\r
+\r
+        PUBWEAK RTC_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_WKUP_IRQHandler\r
+        B RTC_WKUP_IRQHandler\r
+\r
+\r
+        PUBWEAK FLASH_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+FLASH_IRQHandler\r
+        B FLASH_IRQHandler\r
+\r
+\r
+        PUBWEAK RCC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RCC_IRQHandler\r
+        B RCC_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI0_IRQHandler\r
+        B EXTI0_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI1_IRQHandler\r
+        B EXTI1_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI2_IRQHandler\r
+        B EXTI2_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI3_IRQHandler\r
+        B EXTI3_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI4_IRQHandler\r
+        B EXTI4_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel1_IRQHandler\r
+        B DMA1_Channel1_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel2_IRQHandler\r
+        B DMA1_Channel2_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel3_IRQHandler\r
+        B DMA1_Channel3_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel4_IRQHandler\r
+        B DMA1_Channel4_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel5_IRQHandler\r
+        B DMA1_Channel5_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel6_IRQHandler\r
+        B DMA1_Channel6_IRQHandler\r
+\r
+\r
+        PUBWEAK DMA1_Channel7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DMA1_Channel7_IRQHandler\r
+        B DMA1_Channel7_IRQHandler\r
+\r
+\r
+        PUBWEAK ADC1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+ADC1_IRQHandler\r
+        B ADC1_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_HP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_HP_IRQHandler\r
+        B USB_HP_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_LP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_LP_IRQHandler\r
+        B USB_LP_IRQHandler\r
+\r
+\r
+        PUBWEAK DAC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+DAC_IRQHandler\r
+        B DAC_IRQHandler\r
+\r
+\r
+        PUBWEAK COMP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+COMP_IRQHandler\r
+        B COMP_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI9_5_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI9_5_IRQHandler\r
+        B EXTI9_5_IRQHandler\r
+\r
+\r
+        PUBWEAK LCD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+LCD_IRQHandler\r
+        B LCD_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM9_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM9_IRQHandler\r
+        B TIM9_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM10_IRQHandler\r
+        B TIM10_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM11_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM11_IRQHandler\r
+        B TIM11_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM2_IRQHandler\r
+        B TIM2_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM3_IRQHandler\r
+        B TIM3_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM4_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM4_IRQHandler\r
+        B TIM4_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C1_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_EV_IRQHandler\r
+        B I2C1_EV_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C1_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_ER_IRQHandler\r
+        B I2C1_ER_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C2_EV_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_EV_IRQHandler\r
+        B I2C2_EV_IRQHandler\r
+\r
+\r
+        PUBWEAK I2C2_ER_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_ER_IRQHandler\r
+        B I2C2_ER_IRQHandler\r
+\r
+\r
+        PUBWEAK SPI1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI1_IRQHandler\r
+        B SPI1_IRQHandler\r
+\r
+\r
+        PUBWEAK SPI2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI2_IRQHandler\r
+        B SPI2_IRQHandler\r
+\r
+\r
+        PUBWEAK USART1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART1_IRQHandler\r
+        B USART1_IRQHandler\r
+\r
+\r
+        PUBWEAK USART2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART2_IRQHandler\r
+        B USART2_IRQHandler\r
+\r
+\r
+        PUBWEAK USART3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USART3_IRQHandler\r
+        B USART3_IRQHandler\r
+\r
+\r
+        PUBWEAK EXTI15_10_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EXTI15_10_IRQHandler\r
+        B EXTI15_10_IRQHandler\r
+\r
+\r
+        PUBWEAK RTC_Alarm_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_Alarm_IRQHandler\r
+        B RTC_Alarm_IRQHandler\r
+\r
+\r
+        PUBWEAK USB_FS_WKUP_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_FS_WKUP_IRQHandler\r
+        B USB_FS_WKUP_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM6_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM6_IRQHandler\r
+        B TIM6_IRQHandler\r
+\r
+\r
+        PUBWEAK TIM7_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TIM7_IRQHandler\r
+        B TIM7_IRQHandler\r
+\r
+        END\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h
new file mode 100644 (file)
index 0000000..7d1cabd
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32_eval.h
@@ -0,0 +1,360 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32_eval.h\r
+  * @author  MCD Application Team\r
+  * @version V4.4.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Header file for stm32_eval.c module.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+  \r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_EVAL_H\r
+#define __STM32_EVAL_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+\r
+/** @addtogroup Utilities\r
+  * @{\r
+  */ \r
+  \r
+/** @addtogroup STM32_EVAL\r
+  * @{\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Abstraction_Layer\r
+  * @{\r
+  */\r
+  \r
+/** @defgroup STM32_EVAL_HARDWARE_RESOURCES\r
+  * @{\r
+  */\r
+\r
+/**\r
+@code  \r
+ The table below gives an overview of the hardware resources supported by each \r
+ STM32 EVAL board.\r
+     - LCD: TFT Color LCD (Parallel (FSMC) and Serial (SPI))\r
+     - IOE: IO Expander on I2C\r
+     - sFLASH: serial SPI FLASH (M25Pxxx)\r
+     - sEE: serial I2C EEPROM (M24C08, M24C32, M24C64)\r
+     - TSENSOR: Temperature Sensor (LM75)\r
+     - SD: SD Card memory (SPI and SDIO (SD Card MODE)) \r
+  =================================================================================================================+\r
+    STM32 EVAL     | LED | Buttons  | Com Ports |    LCD    | IOE  | sFLASH | sEE | TSENSOR | SD (SPI) | SD(SDIO)  |\r
+  =================================================================================================================+\r
+   STM3210B-EVAL   |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM3210E-EVAL   |  4  |    8     |     2     | YES (FSMC)| NO   |  YES   | NO  |   YES   |    NO    |    YES    |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM3210C-EVAL   |  4  |    3     |     1     | YES (SPI) | YES  |  NO    | YES |   NO    |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM32100B-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  YES   | NO  |   YES   |    YES   |    NO     |\r
+  -----------------------------------------------------------------------------------------------------------------+\r
+   STM32L152-EVAL  |  4  |    8     |     2     | YES (SPI) | NO   |  NO    | NO  |   YES   |    YES   |    NO     |\r
+  =================================================================================================================+\r
+@endcode\r
+*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @defgroup STM32_EVAL_Exported_Types\r
+  * @{\r
+  */\r
+typedef enum \r
+{\r
+  LED1 = 0,\r
+  LED2 = 1,\r
+  LED3 = 2,\r
+  LED4 = 3\r
+} Led_TypeDef;\r
+\r
+typedef enum \r
+{  \r
+  BUTTON_WAKEUP = 0,\r
+  BUTTON_TAMPER = 1,\r
+  BUTTON_KEY = 2,\r
+  BUTTON_RIGHT = 3,\r
+  BUTTON_LEFT = 4,\r
+  BUTTON_UP = 5,\r
+  BUTTON_DOWN = 6,\r
+  BUTTON_SEL = 7\r
+} Button_TypeDef;\r
+\r
+typedef enum \r
+{  \r
+  BUTTON_MODE_GPIO = 0,\r
+  BUTTON_MODE_EXTI = 1\r
+} ButtonMode_TypeDef;\r
+\r
+typedef enum \r
+{ \r
+  JOY_NONE = 0,\r
+  JOY_SEL = 1,\r
+  JOY_DOWN = 2,\r
+  JOY_LEFT = 3,\r
+  JOY_RIGHT = 4,\r
+  JOY_UP = 5\r
+} JOYState_TypeDef\r
+;\r
+\r
+typedef enum \r
+{\r
+  COM1 = 0,\r
+  COM2 = 1\r
+} COM_TypeDef;   \r
+/**\r
+  * @}\r
+  */ \r
+  \r
+/** @defgroup STM32_EVAL_Exported_Constants\r
+  * @{\r
+  */ \r
+\r
+/** \r
+  * @brief  Uncomment the line corresponding to the STMicroelectronics evaluation\r
+  *   board used in your application.\r
+  *   \r
+  *  Tip: To avoid modifying this file each time you need to switch between these\r
+  *       boards, you can define the board in your toolchain compiler preprocessor.    \r
+  */ \r
+#if !defined (USE_STM32100B_EVAL) && !defined (USE_STM3210B_EVAL) &&  !defined (USE_STM3210E_EVAL)\\r
+   &&  !defined (USE_STM3210C_EVAL) &&  !defined (USE_STM32L152_EVAL)\r
+ //#define USE_STM32100B_EVAL\r
+ //#define USE_STM3210B_EVAL\r
+ //#define USE_STM3210E_EVAL\r
+ //#define USE_STM3210C_EVAL\r
+ //#define USE_STM32L152_EVAL\r
+#endif\r
+\r
+#ifdef USE_STM32100B_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm32100b_eval/stm32100b_eval.h"\r
+#elif defined USE_STM3210B_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210b_eval/stm3210b_eval.h" \r
+#elif defined USE_STM3210E_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210e_eval/stm3210e_eval.h"\r
+#elif defined USE_STM3210C_EVAL\r
+ #include "stm32f10x.h"\r
+ #include "stm3210c_eval/stm3210c_eval.h"\r
+#elif defined USE_STM32L152_EVAL\r
+ #include "stm32l1xx.h"\r
+ #include "stm32l152_eval/stm32l152_eval.h" \r
+#else \r
+ #error "Please select first the STM32 EVAL board to be used (in stm32_eval.h)"\r
+#endif                      \r
+\r
+\r
+/** \r
+  * @brief  STM32 Button Defines Legacy  \r
+  */ \r
+#define Button_WAKEUP        BUTTON_WAKEUP\r
+#define Button_TAMPER        BUTTON_TAMPER\r
+#define Button_KEY           BUTTON_KEY\r
+#define Button_RIGHT         BUTTON_RIGHT\r
+#define Button_LEFT          BUTTON_LEFT\r
+#define Button_UP            BUTTON_UP\r
+#define Button_DOWN          BUTTON_DOWN\r
+#define Button_SEL           BUTTON_SEL\r
+#define Mode_GPIO            BUTTON_MODE_GPIO\r
+#define Mode_EXTI            BUTTON_MODE_EXTI\r
+#define Button_Mode_TypeDef  ButtonMode_TypeDef\r
+#define JOY_CENTER           JOY_SEL\r
+#define JOY_State_TypeDef    JOYState_TypeDef \r
+\r
+/** \r
+  * @brief  LCD Defines Legacy  \r
+  */ \r
+#define LCD_RSNWR_GPIO_CLK  LCD_NWR_GPIO_CLK\r
+#define LCD_SPI_GPIO_PORT   LCD_SPI_SCK_GPIO_PORT\r
+#define LCD_SPI_GPIO_CLK    LCD_SPI_SCK_GPIO_CLK\r
+#define R0                  LCD_REG_0\r
+#define R1                  LCD_REG_1\r
+#define R2                  LCD_REG_2\r
+#define R3                  LCD_REG_3\r
+#define R4                  LCD_REG_4\r
+#define R5                  LCD_REG_5\r
+#define R6                  LCD_REG_6\r
+#define R7                  LCD_REG_7\r
+#define R8                  LCD_REG_8\r
+#define R9                  LCD_REG_9\r
+#define R10                 LCD_REG_10\r
+#define R12                 LCD_REG_12\r
+#define R13                 LCD_REG_13\r
+#define R14                 LCD_REG_14\r
+#define R15                 LCD_REG_15\r
+#define R16                 LCD_REG_16\r
+#define R17                 LCD_REG_17\r
+#define R18                 LCD_REG_18\r
+#define R19                 LCD_REG_19\r
+#define R20                 LCD_REG_20\r
+#define R21                 LCD_REG_21\r
+#define R22                 LCD_REG_22\r
+#define R23                 LCD_REG_23\r
+#define R24                 LCD_REG_24\r
+#define R25                 LCD_REG_25\r
+#define R26                 LCD_REG_26\r
+#define R27                 LCD_REG_27\r
+#define R28                 LCD_REG_28\r
+#define R29                 LCD_REG_29\r
+#define R30                 LCD_REG_30\r
+#define R31                 LCD_REG_31\r
+#define R32                 LCD_REG_32\r
+#define R33                 LCD_REG_33\r
+#define R34                 LCD_REG_34\r
+#define R36                 LCD_REG_36\r
+#define R37                 LCD_REG_37\r
+#define R40                 LCD_REG_40\r
+#define R41                 LCD_REG_41\r
+#define R43                 LCD_REG_43\r
+#define R45                 LCD_REG_45\r
+#define R48                 LCD_REG_48\r
+#define R49                 LCD_REG_49\r
+#define R50                 LCD_REG_50\r
+#define R51                 LCD_REG_51\r
+#define R52                 LCD_REG_52\r
+#define R53                 LCD_REG_53\r
+#define R54                 LCD_REG_54\r
+#define R55                 LCD_REG_55\r
+#define R56                 LCD_REG_56\r
+#define R57                 LCD_REG_57\r
+#define R59                 LCD_REG_59\r
+#define R60                 LCD_REG_60\r
+#define R61                 LCD_REG_61\r
+#define R62                 LCD_REG_62\r
+#define R63                 LCD_REG_63\r
+#define R64                 LCD_REG_64\r
+#define R65                 LCD_REG_65\r
+#define R66                 LCD_REG_66\r
+#define R67                 LCD_REG_67\r
+#define R68                 LCD_REG_68\r
+#define R69                 LCD_REG_69\r
+#define R70                 LCD_REG_70\r
+#define R71                 LCD_REG_71\r
+#define R72                 LCD_REG_72\r
+#define R73                 LCD_REG_73\r
+#define R74                 LCD_REG_74\r
+#define R75                 LCD_REG_75\r
+#define R76                 LCD_REG_76\r
+#define R77                 LCD_REG_77\r
+#define R78                 LCD_REG_78\r
+#define R79                 LCD_REG_79\r
+#define R80                 LCD_REG_80\r
+#define R81                 LCD_REG_81\r
+#define R82                 LCD_REG_82\r
+#define R83                 LCD_REG_83\r
+#define R96                 LCD_REG_96\r
+#define R97                 LCD_REG_97\r
+#define R106                LCD_REG_106\r
+#define R118                LCD_REG_118\r
+#define R128                LCD_REG_128\r
+#define R129                LCD_REG_129\r
+#define R130                LCD_REG_130\r
+#define R131                LCD_REG_131\r
+#define R132                LCD_REG_132\r
+#define R133                LCD_REG_133\r
+#define R134                LCD_REG_134\r
+#define R135                LCD_REG_135\r
+#define R136                LCD_REG_136\r
+#define R137                LCD_REG_137\r
+#define R139                LCD_REG_139\r
+#define R140                LCD_REG_140\r
+#define R141                LCD_REG_141\r
+#define R143                LCD_REG_143\r
+#define R144                LCD_REG_144\r
+#define R145                LCD_REG_145\r
+#define R146                LCD_REG_146\r
+#define R147                LCD_REG_147\r
+#define R148                LCD_REG_148\r
+#define R149                LCD_REG_149\r
+#define R150                LCD_REG_150\r
+#define R151                LCD_REG_151\r
+#define R152                LCD_REG_152\r
+#define R153                LCD_REG_153\r
+#define R154                LCD_REG_154\r
+#define R157                LCD_REG_157\r
+#define R192                LCD_REG_192\r
+#define R193                LCD_REG_193\r
+#define R227                LCD_REG_227\r
+#define R229                LCD_REG_229\r
+#define R231                LCD_REG_231\r
+#define R239                LCD_REG_239\r
+#define White               LCD_COLOR_WHITE\r
+#define Black               LCD_COLOR_BLACK\r
+#define Grey                LCD_COLOR_GREY\r
+#define Blue                LCD_COLOR_BLUE\r
+#define Blue2               LCD_COLOR_BLUE2\r
+#define Red                 LCD_COLOR_RED\r
+#define Magenta             LCD_COLOR_MAGENTA\r
+#define Green               LCD_COLOR_GREEN\r
+#define Cyan                LCD_COLOR_CYAN\r
+#define Yellow              LCD_COLOR_YELLOW\r
+#define Line0               LCD_LINE_0\r
+#define Line1               LCD_LINE_1\r
+#define Line2               LCD_LINE_2\r
+#define Line3               LCD_LINE_3\r
+#define Line4               LCD_LINE_4\r
+#define Line5               LCD_LINE_5\r
+#define Line6               LCD_LINE_6\r
+#define Line7               LCD_LINE_7\r
+#define Line8               LCD_LINE_8\r
+#define Line9               LCD_LINE_9\r
+#define Horizontal          LCD_DIR_HORIZONTAL\r
+#define Vertical            LCD_DIR_VERTICAL\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Exported_Macros\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+/** @defgroup STM32_EVAL_Exported_Functions\r
+  * @{\r
+  */ \r
+/**\r
+  * @}\r
+  */ \r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __STM32_EVAL_H */\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/**\r
+  * @}\r
+  */   \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
new file mode 100644 (file)
index 0000000..84dc285
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_conf.h
@@ -0,0 +1,74 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_conf.h \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Library configuration file.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_CONF_H\r
+#define __STM32L1xx_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Uncomment the line below to enable peripheral header file inclusion */\r
+/* #include "stm32l1xx_adc.h" */\r
+/* #include "stm32l1xx_crc.h" */\r
+/* #include "stm32l1xx_comp.h" */\r
+/* #include "stm32l1xx_dac.h" */\r
+/* #include "stm32l1xx_dbgmcu.h" */\r
+/* #include "stm32l1xx_dma.h" */\r
+#include "stm32l1xx_exti.h"\r
+/* #include "stm32l1xx_flash.h" */\r
+#include "stm32l1xx_gpio.h"\r
+#include "stm32l1xx_syscfg.h"\r
+/* #include "stm32l1xx_i2c.h" */\r
+/* #include "stm32l1xx_iwdg.h" */\r
+/* #include "stm32l1xx_lcd.h" */\r
+/* #include "stm32l1xx_pwr.h" */\r
+#include "stm32l1xx_rcc.h"\r
+/* #include "stm32l1xx_rtc.h" */\r
+#include "stm32l1xx_spi.h"\r
+/* #include "stm32l1xx_tim.h" */\r
+#include "stm32l1xx_usart.h"\r
+/* #include "stm32l1xx_wwdg.h" */\r
+#include "misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to expanse the "assert_param" macro in the \r
+   Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT    1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef  USE_FULL_ASSERT\r
+\r
+/**\r
+  * @brief  The assert_param macro is used for function's parameters check.\r
+  * @param  expr: If expr is false, it calls assert_failed function which reports \r
+  *         the name of the source file and the source line number of the call \r
+  *         that failed. If expr is true, it returns no value.\r
+  * @retval None\r
+  */\r
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+  void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+  #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32L1xx_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
new file mode 100644 (file)
index 0000000..ebca1e6
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;\r
+define symbol __ICFEDIT_region_ROM_end__   = 0x0801FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;\r
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x200;\r
+define symbol __ICFEDIT_size_heap__   = 0x0;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+\r
+place in ROM_region   { readonly };\r
+place in RAM_region   { readwrite,\r
+                        block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
new file mode 100644 (file)
index 0000000..5afcd2a
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.c
@@ -0,0 +1,160 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   Main Interrupt Service Routines.\r
+  *          This file provides template for all exceptions handler and\r
+  *          peripherals interrupt service routine.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx_it.h"\r
+\r
+\r
+/** @addtogroup Template_Project\r
+  * @{\r
+  */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/*            Cortex-M3 Processor Exceptions Handlers                         */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles NMI exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Hard Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void HardFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Hard Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Memory Manage exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void MemManage_Handler(void)\r
+{\r
+  /* Go to infinite loop when Memory Manage exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Bus Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void BusFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Bus Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Usage Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void UsageFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Usage Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SVCall exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Debug Monitor exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles PendSVC exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SysTick Handler.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SysTick_Handler(void)\r
+{\r
+}\r
+\r
+/******************************************************************************/\r
+/*                 STM32L1xx Peripherals Interrupt Handlers                   */\r
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */\r
+/*  available peripheral interrupt handler's name please refer to the startup */\r
+/*  file (startup_stm32l1xx_md.s).                                            */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles PPP interrupt request.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
new file mode 100644 (file)
index 0000000..7eabc16
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/stm32l1xx_it.h
@@ -0,0 +1,53 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Project/STM32L1xx_StdPeriph_Template/stm32l1xx_it.h \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   This file contains the headers of the interrupt handlers.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32L1xx_IT_H\r
+#define __STM32L1xx_IT_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32l1xx.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32L1xx_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
diff --git a/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
new file mode 100644 (file)
index 0000000..e3881c1
--- /dev/null
+++ b/Demo/Cortex_STM32L152_IAR/system_and_ST_code/system_stm32l1xx.c
@@ -0,0 +1,934 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32l1xx.c\r
+  * @author  MCD Application Team\r
+  * @version V1.0.0RC1\r
+  * @date    07/02/2010\r
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+  ******************************************************************************\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32l1xx_system\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Includes\r
+  * @{\r
+  */\r
+\r
+#include "stm32l1xx.h"\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
+   frequency (after reset the MSI is used as SYSCLK source)\r
+\r
+   IMPORTANT NOTE:\r
+   ==============\r
+   1. After each device reset the MSI is used as System clock source.\r
+\r
+   2. Please make sure that the selected System clock doesn't exceed your device's\r
+      maximum frequency.\r
+\r
+   3. If none of the define below is enabled, the MSI (2MHz default) is used as\r
+      System clock source.\r
+\r
+   4. The System clock configuration functions provided within this file assume that:\r
+        - For Ultra Low Power Medium Mensity devices an external 8MHz crystal is\r
+          used to drive the System clock.\r
+     If you are using different crystal you have to adapt those functions accordingly.\r
+    */\r
+\r
+/* #define SYSCLK_FREQ_MSI */\r
+\r
+#ifndef SYSCLK_FREQ_MSI\r
+/* #define SYSCLK_FREQ_HSI    HSI_VALUE */\r
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */\r
+/* #define SYSCLK_FREQ_4MHz   4000000 */\r
+/* #define SYSCLK_FREQ_8MHz   8000000 */\r
+/* #define SYSCLK_FREQ_16MHz  16000000 */\r
+#define SYSCLK_FREQ_32MHz  32000000\r
+#else\r
+/* #define SYSCLK_FREQ_MSI_64KHz     64000 */\r
+/* #define SYSCLK_FREQ_MSI_128KHz    128000 */\r
+/* #define SYSCLK_FREQ_MSI_256KHz    256000 */\r
+/* #define SYSCLK_FREQ_MSI_512KHz    512000 */\r
+/* #define SYSCLK_FREQ_MSI_1MHz      1000000 */\r
+/* #define SYSCLK_FREQ_MSI_2MHz      2000000 */\r
+/* #define SYSCLK_FREQ_MSI_4MHz      4000000 */\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/*******************************************************************************\r
+*  Clock Definitions\r
+*******************************************************************************/\r
+#ifndef SYSCLK_FREQ_MSI\r
+#ifdef SYSCLK_FREQ_HSI\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSI;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_HSE\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_4MHz;       /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_8MHz;       /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_16MHz;      /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_32MHz;      /*!< System Clock Frequency (Core Clock) */\r
+#else /*!< MSI Selected as System Clock source */\r
+  uint32_t SystemCoreClock         = MSI_VALUE;              /*!< System Clock Frequency (Core Clock) */\r
+#endif\r
+#else\r
+#ifdef SYSCLK_FREQ_MSI_64KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_64KHz;  /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_128KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_128KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_256KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_256KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_512KHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_512KHz; /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_1MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_1MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_2MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_2MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_MSI_4MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_MSI_4MHz;   /*!< System Clock Frequency (Core Clock) */\r
+#else\r
+  uint32_t SystemCoreClock         = MSI_VALUE;              /*!< System Clock Frequency (Core Clock) */\r
+#endif\r
+#endif\r
+\r
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};\r
+__I uint8_t MSITable[7] = {0, 0, 0, 0, 1, 2, 4};\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+static void SetSysClock(void);\r
+\r
+#ifdef SYSCLK_FREQ_HSI\r
+  static void SetSysClockToHSI(void);\r
+#elif defined SYSCLK_FREQ_HSE\r
+  static void SetSysClockToHSE(void);\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  static void SetSysClockTo4(void);\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  static void SetSysClockTo8(void);\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  static void SetSysClockTo16(void);\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  static void SetSysClockTo32(void);\r
+#else\r
+  static void SetSysClockToMSI(void);\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32L1xx_System_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system\r
+  *         Initialize the Embedded Flash Interface, the PLL and update the\r
+  *         SystemCoreClock variable\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit (void)\r
+{\r
+  /*!< Set MSION bit */\r
+  RCC->CR |= (uint32_t)0x00000100;\r
+\r
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */\r
+  RCC->CFGR &= (uint32_t)0x88FFC00C;\r
+\r
+  /*!< Reset HSION, HSEON, CSSON and PLLON bits */\r
+  RCC->CR &= (uint32_t)0xEEFEFFFE;\r
+\r
+  /*!< Reset HSEBYP bit */\r
+  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */\r
+  RCC->CFGR &= (uint32_t)0xFF02FFFF;\r
+\r
+  /*!< Disable all interrupts */\r
+  RCC->CIR = 0x00000000;\r
+\r
+  /*!< Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+  /*!< Configure the Flash Latency cycles and enable prefetch buffer */\r
+  SetSysClock();\r
+\r
+}\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   None\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;\r
+\r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+\r
+  switch (tmp)\r
+  {\r
+    case 0x00:  /* MSI used as system clock */\r
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;\r
+      SystemCoreClock = (((1 << msirange) * 64000) - (MSITable[msirange] * 24000));\r
+      break;\r
+    case 0x04:  /* HSI used as system clock */\r
+      SystemCoreClock = HSI_VALUE;\r
+      break;\r
+    case 0x08:  /* HSE used as system clock */\r
+      SystemCoreClock = HSE_VALUE;\r
+      break;\r
+    case 0x0C:  /* PLL used as system clock */\r
+      /* Get PLL clock source and multiplication factor ----------------------*/\r
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;\r
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;\r
+      pllmul = PLLMulTable[(pllmul >> 18)];\r
+      plldiv = (plldiv >> 22) + 1;\r
+\r
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+\r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock selected as PLL clock entry */\r
+        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);\r
+      }\r
+      else\r
+      {\r
+        /* HSE selected as PLL clock entry */\r
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);\r
+      }\r
+      break;\r
+    default:\r
+      SystemCoreClock = MSI_VALUE;\r
+      break;\r
+  }\r
+  /* Compute HCLK clock frequency --------------------------------------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+  /* HCLK clock frequency */\r
+  SystemCoreClock >>= tmp;\r
+}\r
+\r
+/**\r
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClock(void)\r
+{\r
+#ifdef SYSCLK_FREQ_HSI\r
+  SetSysClockToHSI();\r
+#elif defined SYSCLK_FREQ_HSE\r
+  SetSysClockToHSE();\r
+#elif defined SYSCLK_FREQ_4MHz\r
+  SetSysClockTo4();\r
+#elif defined SYSCLK_FREQ_8MHz\r
+  SetSysClockTo8();\r
+#elif defined SYSCLK_FREQ_16MHz\r
+  SetSysClockTo16();\r
+#elif defined SYSCLK_FREQ_32MHz\r
+  SetSysClockTo32();\r
+#else\r
+  SetSysClockToMSI();\r
+#endif\r
+\r
+ /* If none of the define above is enabled, the MSI (2MHz default) is used as\r
+    System clock source (default after reset) */\r
+}\r
+\r
+#ifdef SYSCLK_FREQ_HSI\r
+/**\r
+  * @brief  Selects HSI as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToHSI(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSIStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSI */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSION);\r
+\r
+  /* Wait till HSI is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSIStatus = RCC->CR & RCC_CR_HSIRDY;\r
+    StartUpCounter++;\r
+  } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSIRDY) != RESET)\r
+  {\r
+    HSIStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSIStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSIStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 1 (1.8V) */\r
+    PWR->CR = PWR_CR_VOS_0;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSI as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;\r
+\r
+    /* Wait till HSI is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSI fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_HSE\r
+/**\r
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToHSE(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+#elif defined SYSCLK_FREQ_4MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 4MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo4(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_8MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 8MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo8(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;\r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_16MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 16MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo16(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 2 (1.5V) */\r
+    PWR->CR = PWR_CR_VOS_1;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV2;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /*  PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |\r
+                                        RCC_CFGR_PLLDIV));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#elif defined SYSCLK_FREQ_32MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 32MHz and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo32(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable HSE */\r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;\r
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 1 (1.8V) */\r
+    PWR->CR = PWR_CR_VOS_0;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+    /*  PLL configuration: PLLCLK = (HSE * 12) / 3 = 32MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |\r
+                                        RCC_CFGR_PLLDIV));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If HSE fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+\r
+#else\r
+/**\r
+  * @brief  Selects MSI as System clock source and configure HCLK, PCLK2\r
+  *         and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToMSI(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, MSIStatus = 0;\r
+\r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+  /* Enable MSI */\r
+  RCC->CR |= ((uint32_t)RCC_CR_MSION);\r
+\r
+  /* Wait till MSI is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    MSIStatus = RCC->CR & RCC_CR_MSIRDY;\r
+    StartUpCounter++;\r
+  } while((MSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));\r
+\r
+  if ((RCC->CR & RCC_CR_MSIRDY) != RESET)\r
+  {\r
+    MSIStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    MSIStatus = (uint32_t)0x00;\r
+  }\r
+\r
+  if (MSIStatus == (uint32_t)0x01)\r
+  {\r
+#ifdef SYSCLK_FREQ_MSI\r
+#ifdef SYSCLK_FREQ_MSI_4MHz\r
+    /* Enable 64-bit access */\r
+    FLASH->ACR |= FLASH_ACR_ACC64;\r
+\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTEN;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR |= FLASH_ACR_LATENCY;\r
+#else\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;\r
+\r
+    /* Disable Prefetch Buffer */\r
+    FLASH->ACR &= ~FLASH_ACR_PRFTEN;\r
+\r
+    /* Disable 64-bit access */\r
+    FLASH->ACR &= ~FLASH_ACR_ACC64;\r
+#endif\r
+#endif\r
+    /* Enable the PWR APB1 Clock */\r
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;\r
+\r
+    /* Select the Voltage Range 3 (1.2V) */\r
+    PWR->CR = PWR_CR_VOS;\r
+\r
+    /* Wait Until the Voltage Regulator is ready */\r
+    while((PWR->CSR & PWR_CSR_VOSF) != RESET)\r
+    {\r
+    }\r
+\r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+\r
+#ifdef SYSCLK_FREQ_MSI\r
+  #ifdef SYSCLK_FREQ_MSI_64KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_64KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_128KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_128KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_256KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_256KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_512KHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_512KHz;\r
+  #elif defined SYSCLK_FREQ_MSI_1MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_1MHz;\r
+  #elif defined SYSCLK_FREQ_MSI_2MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_2MHz;\r
+  #elif defined SYSCLK_FREQ_MSI_4MHz\r
+    /* Set MSI clock range */\r
+    RCC->ICSCR &= (uint32_t)((uint32_t)~(RCC_ICSCR_MSIRANGE));\r
+    RCC->ICSCR |= (uint32_t)RCC_ICSCR_MSIRANGE_4MHz;\r
+  #endif\r
+#endif\r
+\r
+    /* Select MSI as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_MSI;\r
+\r
+    /* Wait till MSI is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x00)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  {\r
+    /* If MSI fails to start-up, the application will have wrong clock\r
+       configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
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