aarch64: remove mrs/msr functions from struct arm

No longer needed, no users.

Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3983
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

diff --git a/src/target/arm.h b/src/target/arm.h
index e5e336dff7f3094432be3fd3d77eb00b90b02f0f..d63ead215159d5e430d0a6de75b2e0e5a44c8275 100644 (file)
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -189,18 +189,6 @@ struct arm {
                        uint32_t CRn, uint32_t CRm,
                        uint32_t value);
 
-       /** Read coprocessor register.  */
-       int (*mrs)(struct target *target, uint32_t op0,
-                       uint32_t op1, uint32_t op2,
-                       uint32_t CRn, uint32_t CRm,
-                       uint32_t *value);
-
-       /** Write coprocessor register.  */
-       int (*msr)(struct target *target, uint32_t cpnum,
-                       uint32_t op1, uint32_t op2,
-                       uint32_t CRn, uint32_t CRm,
-                       uint32_t value);
-
        void *arch_info;
 
        /** For targets conforming to ARM Debug Interface v5,

diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index b06e456b59907a8df53f2a8a14d00e4ab0a407ff..acfd1bcdf8d510b8d73f9d3a3ff1284de80925e6 100644 (file)
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -551,62 +551,6 @@ static int dpmv8_mcr(struct target *target, int cpnum,
        return retval;
 }
 
-static int dpmv8_mrs(struct target *target, uint32_t op0,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
-       uint32_t *value)
-{
-       struct arm *arm = target_to_arm(target);
-       struct arm_dpm *dpm = arm->dpm;
-       int retval;
-       uint32_t op_code;
-
-       retval = dpm->prepare(dpm);
-       if (retval != ERROR_OK)
-               return retval;
-       op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
-                               (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
-       op_code >>= 5;
-       LOG_DEBUG("MRS p%d, %d, r0, c%d, c%d, %d", (int)op0,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
-       /* read coprocessor register into R0; return via DCC */
-       retval = dpm->instr_read_data_r0(dpm,
-                       ARMV8_MRS(op_code, 0),
-                       value);
-
-       /* (void) */ dpm->finish(dpm);
-       return retval;
-}
-
-static int dpmv8_msr(struct target *target, uint32_t op0,
-       uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
-       uint32_t value)
-{
-       struct arm *arm = target_to_arm(target);
-       struct arm_dpm *dpm = arm->dpm;
-       int retval;
-       uint32_t op_code;
-
-       retval = dpm->prepare(dpm);
-       if (retval != ERROR_OK)
-               return retval;
-
-       op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
-                               (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
-       op_code >>= 5;
-       LOG_DEBUG("MSR p%d, %d, r0, c%d, c%d, %d", (int)op0,
-               (int) op1, (int) CRn,
-               (int) CRm, (int) op2);
-
-       /* read DCC into r0; then write coprocessor register from R0 */
-       retval = dpm->instr_write_data_r0(dpm,
-                       ARMV8_MSR_GP(op_code, 0),
-                       value);
-
-       /* (void) */ dpm->finish(dpm);
-       return retval;
-}
-
 /*----------------------------------------------------------------------*/
 
 /*
@@ -1449,8 +1393,6 @@ int armv8_dpm_setup(struct arm_dpm *dpm)
        /* coprocessor access setup */
        arm->mrc = dpmv8_mrc;
        arm->mcr = dpmv8_mcr;
-       arm->mrs = dpmv8_mrs;
-       arm->msr = dpmv8_msr;
 
        dpm->prepare = dpmv8_dpm_prepare;
        dpm->finish = dpmv8_dpm_finish;