--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 59 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 7000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 3 )\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+#ifndef DRIVER_LIB_H\r
+#define DRIVER_LIB_H\r
+\r
+#include "DriverLib.h"\r
+#include "hw_adc.h"\r
+#include "hw_comp.h"\r
+#include "hw_flash.h"\r
+#include "hw_gpio.h"\r
+#include "hw_i2c.h"\r
+#include "hw_ints.h"\r
+#include "hw_memmap.h"\r
+#include "hw_nvic.h"\r
+#include "hw_pwm.h"\r
+#include "hw_qei.h"\r
+#include "hw_ssi.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_timer.h"\r
+#include "hw_types.h"\r
+#include "hw_uart.h"\r
+#include "hw_watchdog.h"\r
+#include "osram96x16.h"\r
+#include "src\adc.h"\r
+#include "src\comp.h"\r
+#include "src\cpu.h"\r
+#include "src\debug.h"\r
+#include "src\flash.h"\r
+#include "src\gpio.h"\r
+#include "src\i2c.h"\r
+#include "src\interrupt.h"\r
+#include "src\pwm.h"\r
+#include "src\qei.h"\r
+#include "src\ssi.h"\r
+#include "src\sysctl.h"\r
+#include "src\systick.h"\r
+#include "src\timer.h"\r
+#include "src\uart.h"\r
+#include "src\watchdog.h"\r
+\r
+#endif\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS 0x00000000 // Active sample register\r
+#define ADC_O_RIS 0x00000004 // Raw interrupt status register\r
+#define ADC_O_IM 0x00000008 // Interrupt mask register\r
+#define ADC_O_ISC 0x0000000C // Interrupt status/clear register\r
+#define ADC_O_OSTAT 0x00000010 // Overflow status register\r
+#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg.\r
+#define ADC_O_USTAT 0x00000018 // Underflow status register\r
+#define ADC_O_SSPRI 0x00000020 // Channel priority register\r
+#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg.\r
+#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register\r
+#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register\r
+#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register\r
+#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register\r
+#define ADC_O_TMLB 0x00000100 // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
+#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask\r
+#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask\r
+#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event\r
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event\r
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event\r
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event\r
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event\r
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event\r
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event\r
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event\r
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT 28\r
+#define ADC_SSMUX_MUX6_SHIFT 24\r
+#define ADC_SSMUX_MUX5_SHIFT 20\r
+#define ADC_SSMUX_MUX4_SHIFT 16\r
+#define ADC_SSMUX_MUX3_SHIFT 12\r
+#define ADC_SSMUX_MUX2_SHIFT 8\r
+#define ADC_SSMUX_MUX1_SHIFT 4\r
+#define ADC_SSMUX_MUX0_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable\r
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select\r
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select\r
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable\r
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select\r
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select\r
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable\r
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select\r
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select\r
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable\r
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select\r
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select\r
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable\r
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select\r
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select\r
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable\r
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select\r
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select\r
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable\r
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select\r
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select\r
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable\r
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select\r
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
+#define ADC_LB_CONT 0x00000020 // Continuation sample\r
+#define ADC_LB_DIFF 0x00000010 // Differential sample\r
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
+#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
+#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
+#define COMP_O_ACCTL1 0x00000044 // Comp1 control register\r
+#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register\r
+#define COMP_O_ACCTL2 0x00000064 // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
+#define COMP_INT_1 0x00000002 // Comp1 interrupt\r
+#define COMP_INT_0 0x00000001 // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved\r
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable\r
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges\r
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA 0x400FD000 // Memory address register\r
+#define FLASH_FMD 0x400FD004 // Memory data register\r
+#define FLASH_FMC 0x400FD008 // Memory control register\r
+#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
+#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
+#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
+#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
+#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
+#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
+#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
+#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+#define FLASH_PROTECT_SIZE 0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA 0x00000000 // Data register.\r
+#define GPIO_O_DIR 0x00000400 // Data direction register.\r
+#define GPIO_O_IS 0x00000404 // Interrupt sense register.\r
+#define GPIO_O_IBE 0x00000408 // Interrupt both edges register.\r
+#define GPIO_O_IEV 0x0000040C // Intterupt event register.\r
+#define GPIO_O_IM 0x00000410 // Interrupt mask register.\r
+#define GPIO_O_RIS 0x00000414 // Raw interrupt status register.\r
+#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg.\r
+#define GPIO_O_ICR 0x0000041C // Interrupt clear register.\r
+#define GPIO_O_AFSEL 0x00000420 // Mode control select register.\r
+#define GPIO_O_DR2R 0x00000500 // 2ma drive select register.\r
+#define GPIO_O_DR4R 0x00000504 // 4ma drive select register.\r
+#define GPIO_O_DR8R 0x00000508 // 8ma drive select register.\r
+#define GPIO_O_ODR 0x0000050C // Open drain select register.\r
+#define GPIO_O_PUR 0x00000510 // Pull up select register.\r
+#define GPIO_O_PDR 0x00000514 // Pull down select register.\r
+#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg.\r
+#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
+#define GPIO_O_PeriphID4 0x00000FD0 //\r
+#define GPIO_O_PeriphID5 0x00000FD4 //\r
+#define GPIO_O_PeriphID6 0x00000FD8 //\r
+#define GPIO_O_PeriphID7 0x00000FDC //\r
+#define GPIO_O_PeriphID0 0x00000FE0 //\r
+#define GPIO_O_PeriphID1 0x00000FE4 //\r
+#define GPIO_O_PeriphID2 0x00000FE8 //\r
+#define GPIO_O_PeriphID3 0x00000FEC //\r
+#define GPIO_O_PCellID0 0x00000FF0 //\r
+#define GPIO_O_PCellID1 0x00000FF4 //\r
+#define GPIO_O_PCellID2 0x00000FF8 //\r
+#define GPIO_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_PeriphID4 0x00000000 //\r
+#define GPIO_RV_PeriphID5 0x00000000 //\r
+#define GPIO_RV_PeriphID6 0x00000000 //\r
+#define GPIO_RV_PeriphID7 0x00000000 //\r
+#define GPIO_RV_PeriphID0 0x00000061 //\r
+#define GPIO_RV_PeriphID1 0x00000010 //\r
+#define GPIO_RV_PeriphID2 0x00000004 //\r
+#define GPIO_RV_PeriphID3 0x00000000 //\r
+#define GPIO_RV_PCellID0 0x0000000D //\r
+#define GPIO_RV_PCellID1 0x000000F0 //\r
+#define GPIO_RV_PCellID2 0x00000005 //\r
+#define GPIO_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the offset between the I2C master and slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register\r
+#define I2C_MASTER_O_DR 0x00000008 // Data register\r
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register\r
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
+#define I2C_MASTER_CS_START 0x00000002 // Start\r
+#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable\r
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI 2 // NMI fault\r
+#define FAULT_HARD 3 // Hard fault\r
+#define FAULT_MPU 4 // MPU fault\r
+#define FAULT_BUS 5 // Bus fault\r
+#define FAULT_USAGE 6 // Usage fault\r
+#define FAULT_SVCALL 11 // SVCall\r
+#define FAULT_DEBUG 12 // Debug monitor\r
+#define FAULT_PENDSV 14 // PendSV\r
+#define FAULT_SYSTICK 15 // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA 16 // GPIO Port A\r
+#define INT_GPIOB 17 // GPIO Port B\r
+#define INT_GPIOC 18 // GPIO Port C\r
+#define INT_GPIOD 19 // GPIO Port D\r
+#define INT_GPIOE 20 // GPIO Port E\r
+#define INT_UART0 21 // UART0 Rx and Tx\r
+#define INT_UART1 22 // UART1 Rx and Tx\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_PWM_FAULT 25 // PWM Fault\r
+#define INT_PWM0 26 // PWM Generator 0\r
+#define INT_PWM1 27 // PWM Generator 1\r
+#define INT_PWM2 28 // PWM Generator 2\r
+#define INT_QEI 29 // Quadrature Encoder\r
+#define INT_ADC0 30 // ADC Sequence 0\r
+#define INT_ADC1 31 // ADC Sequence 1\r
+#define INT_ADC2 32 // ADC Sequence 2\r
+#define INT_ADC3 33 // ADC Sequence 3\r
+#define INT_WATCHDOG 34 // Watchdog timer\r
+#define INT_TIMER0A 35 // Timer 0 subtimer A\r
+#define INT_TIMER0B 36 // Timer 0 subtimer B\r
+#define INT_TIMER1A 37 // Timer 1 subtimer A\r
+#define INT_TIMER1B 38 // Timer 1 subtimer B\r
+#define INT_TIMER2A 39 // Timer 2 subtimer A\r
+#define INT_TIMER2B 40 // Timer 2 subtimer B\r
+#define INT_COMP0 41 // Analog Comparator 0\r
+#define INT_COMP1 42 // Analog Comparator 1\r
+#define INT_COMP2 43 // Analog Comparator 2\r
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)\r
+#define INT_FLASH 45 // FLASH Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS 46\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY 8\r
+#define NUM_PRIORITY_BITS 3\r
+\r
+#endif // __HW_INTS_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE 0x00000000 // FLASH memory\r
+#define SRAM_BASE 0x20000000 // SRAM memory\r
+#define WATCHDOG_BASE 0x40000000 // Watchdog\r
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A\r
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define UART0_BASE 0x4000C000 // UART0\r
+#define UART1_BASE 0x4000D000 // UART1\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E\r
+#define PWM_BASE 0x40028000 // PWM\r
+#define QEI_BASE 0x4002C000 // QEI\r
+#define TIMER0_BASE 0x40030000 // Timer0\r
+#define TIMER1_BASE 0x40031000 // Timer1\r
+#define TIMER2_BASE 0x40032000 // Timer2\r
+#define ADC_BASE 0x40038000 // ADC\r
+#define COMP_BASE 0x4003C000 // Analog comparators\r
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
+#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register\r
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg.\r
+#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register\r
+#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register\r
+#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
+#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register\r
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register\r
+#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State\r
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register\r
+#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register\r
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register\r
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register\r
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data\r
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source\r
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
+#define NVIC_ST_RELOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
+#define NVIC_ST_CURRENT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable\r
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable\r
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable\r
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable\r
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable\r
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable\r
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable\r
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable\r
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable\r
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable\r
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable\r
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable\r
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable\r
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable\r
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable\r
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable\r
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable\r
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable\r
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable\r
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable\r
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable\r
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable\r
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable\r
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable\r
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable\r
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable\r
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable\r
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable\r
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable\r
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable\r
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S 24\r
+#define NVIC_PRI0_INT2_S 16\r
+#define NVIC_PRI0_INT1_S 8\r
+#define NVIC_PRI0_INT0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S 24\r
+#define NVIC_PRI1_INT6_S 16\r
+#define NVIC_PRI1_INT5_S 8\r
+#define NVIC_PRI1_INT4_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S 24\r
+#define NVIC_PRI2_INT10_S 16\r
+#define NVIC_PRI2_INT9_S 8\r
+#define NVIC_PRI2_INT8_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S 24\r
+#define NVIC_PRI3_INT14_S 16\r
+#define NVIC_PRI3_INT13_S 8\r
+#define NVIC_PRI3_INT12_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S 24\r
+#define NVIC_PRI4_INT18_S 16\r
+#define NVIC_PRI4_INT17_S 8\r
+#define NVIC_PRI4_INT16_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S 24\r
+#define NVIC_PRI5_INT22_S 16\r
+#define NVIC_PRI5_INT21_S 8\r
+#define NVIC_PRI5_INT20_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S 24\r
+#define NVIC_PRI6_INT26_S 16\r
+#define NVIC_PRI6_INT25_S 8\r
+#define NVIC_PRI6_INT24_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S 24\r
+#define NVIC_PRI7_INT30_S 16\r
+#define NVIC_PRI7_INT29_S 8\r
+#define NVIC_PRI7_INT28_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant\r
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number\r
+#define NVIC_CPUID_REV_M 0x0000000F // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S 16\r
+#define NVIC_SYS_PRI1_BUS_S 8\r
+#define NVIC_SYS_PRI1_MEM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S 24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S 24\r
+#define NVIC_SYS_PRI3_PENDSV_S 16\r
+#define NVIC_SYS_PRI3_DEBUG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation\r
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
+#define NVIC_MM_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
+#define NVIC_EXC_NUM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
+#define NVIC_MPU_NUMBER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
+#define NVIC_MPU_BASE_ADDR_S 8\r
+#define NVIC_MPU_BASE_REGION_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
+#define NVIC_DBG_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S 0\r
+\r
+#endif // __HW_NVIC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register\r
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register\r
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register\r
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault register\r
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register\r
+#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
+#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+\r
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg\r
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg\r
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg\r
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg\r
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg\r
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
+#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
+ // output pins\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
+ // PWM output pins\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
+ // generator block\r
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
+ // count\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
+\r
+#endif // __HW_PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_qei.h - Macros used when accessing the QEI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_QEI_H__\r
+#define __HW_QEI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_O_STAT 0x00000004 // Status register\r
+#define QEI_O_POS 0x00000008 // Current position register\r
+#define QEI_O_MAXPOS 0x0000000C // Maximum position register\r
+#define QEI_O_LOAD 0x00000010 // Velocity timer load register\r
+#define QEI_O_TIME 0x00000014 // Velocity timer register\r
+#define QEI_O_COUNT 0x00000018 // Velocity pulse count register\r
+#define QEI_O_SPEED 0x0000001C // Velocity speed register\r
+#define QEI_O_INTEN 0x00000020 // Interrupt enable register\r
+#define QEI_O_RIS 0x00000024 // Raw interrupt status register\r
+#define QEI_O_ISC 0x00000028 // Interrupt status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
+#define QEI_CTL_INVI 0x00000800 // Invert Index input\r
+#define QEI_CTL_INVB 0x00000400 // Invert PhB input\r
+#define QEI_CTL_INVA 0x00000200 // Invert PhA input\r
+#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask\r
+#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128\r
+#define QEI_CTL_VELEN 0x00000020 // Velocity enable\r
+#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode\r
+#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode\r
+#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode\r
+#define QEI_CTL_SWAP 0x00000002 // Swap input signals\r
+#define QEI_CTL_ENABLE 0x00000001 // QEI enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
+#define QEI_STAT_ERROR 0x00000001 // Signalling error detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_POS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
+#define QEI_POS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_MAXPOS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
+#define QEI_MAXPOS_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
+#define QEI_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_TIME register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
+#define QEI_TIME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
+#define QEI_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_SPEED register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
+#define QEI_SPEED_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INTEN_DIR 0x00000004 // Direction change\r
+#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
+#define QEI_RIS_DIR 0x00000004 // Direction change\r
+#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_RIS_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the QEI_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
+#define QEI_INT_DIR 0x00000004 // Direction change\r
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the QEI registers.\r
+//\r
+//*****************************************************************************\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_POS 0x00000000 // Current position register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+\r
+#endif // __HW_QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0 0x00000000 // Control register 0\r
+#define SSI_O_CR1 0x00000004 // Control register 1\r
+#define SSI_O_DR 0x00000008 // Data register\r
+#define SSI_O_SR 0x0000000C // Status register\r
+#define SSI_O_CPSR 0x00000010 // Clock prescale register\r
+#define SSI_O_IM 0x00000014 // Int mask set and clear register\r
+#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
+#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
+#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
+#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
+#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
+#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
+#define SSI_CR0_DSS_7 0x00000006 // 7 bit data\r
+#define SSI_CR0_DSS_8 0x00000007 // 8 bit data\r
+#define SSI_CR0_DSS_9 0x00000008 // 9 bit data\r
+#define SSI_CR0_DSS_10 0x00000009 // 10 bit data\r
+#define SSI_CR0_DSS_11 0x0000000A // 11 bit data\r
+#define SSI_CR0_DSS_12 0x0000000B // 12 bit data\r
+#define SSI_CR0_DSS_13 0x0000000C // 13 bit data\r
+#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
+#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
+#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
+#define SSI_CR1_MS 0x00000004 // Master or slave mode select\r
+#define SSI_CR1_SSE 0x00000002 // Sync serial port enable\r
+#define SSI_CR1_LBM 0x00000001 // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY 0x00000010 // SSI busy\r
+#define SSI_SR_RFF 0x00000008 // RX FIFO full\r
+#define SSI_SR_RNE 0x00000004 // RX FIFO not empty\r
+#define SSI_SR_TNF 0x00000002 // TX FIFO not full\r
+#define SSI_SR_TFE 0x00000001 // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt\r
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
+#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
+#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
+#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613\r
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615\r
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2kB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4kB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8kB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64kB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
+#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
+#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
+#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
+#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
+#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present\r
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present\r
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present\r
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present\r
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present\r
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
+#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
+#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present\r
+#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present\r
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
+#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG 0x00000000 // Configuration register\r
+#define TIMER_O_TAMR 0x00000004 // TimerA mode register\r
+#define TIMER_O_TBMR 0x00000008 // TimerB mode register\r
+#define TIMER_O_CTL 0x0000000C // Control register\r
+#define TIMER_O_IMR 0x00000018 // Interrupt mask register\r
+#define TIMER_O_RIS 0x0000001C // Interrupt status register\r
+#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg.\r
+#define TIMER_O_ICR 0x00000024 // Interrupt clear register\r
+#define TIMER_O_TAILR 0x00000028 // TimerA interval load register\r
+#define TIMER_O_TBILR 0x0000002C // TimerB interval load register\r
+#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register\r
+#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register\r
+#define TIMER_O_TAPR 0x00000038 // TimerA prescale register\r
+#define TIMER_O_TBPR 0x0000003C // TimerB prescale register\r
+#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register\r
+#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register\r
+#define TIMER_O_TAR 0x00000048 // TimerA register\r
+#define TIMER_O_TBR 0x0000004C // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
+#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
+#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
+#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status\r
+#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR 0x00000000 // Data Register\r
+#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
+#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
+#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_CTL 0x00000030 // Control Register\r
+#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
+#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
+#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
+#define UART_O_PeriphID4 0x00000FD0 //\r
+#define UART_O_PeriphID5 0x00000FD4 //\r
+#define UART_O_PeriphID6 0x00000FD8 //\r
+#define UART_O_PeriphID7 0x00000FDC //\r
+#define UART_O_PeriphID0 0x00000FE0 //\r
+#define UART_O_PeriphID1 0x00000FE4 //\r
+#define UART_O_PeriphID2 0x00000FE8 //\r
+#define UART_O_PeriphID3 0x00000FEC //\r
+#define UART_O_PCellID0 0x00000FF0 //\r
+#define UART_O_PCellID1 0x00000FF4 //\r
+#define UART_O_PCellID2 0x00000FF8 //\r
+#define UART_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE 0x00000800 // Overrun Error\r
+#define UART_DR_BE 0x00000400 // Break Error\r
+#define UART_DR_PE 0x00000200 // Parity Error\r
+#define UART_DR_FE 0x00000100 // Framing Error\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE 0x00000008 // Overrun Error\r
+#define UART_RSR_BE 0x00000004 // Break Error\r
+#define UART_RSR_PE 0x00000002 // Parity Error\r
+#define UART_RSR_FE 0x00000001 // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
+#define UART_FR_RXFF 0x00000040 // RX FIFO Full\r
+#define UART_FR_TXFF 0x00000020 // TX FIFO Full\r
+#define UART_FR_RXFE 0x00000010 // RX FIFO Empty\r
+#define UART_FR_BUSY 0x00000008 // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE 0x00000200 // Receive Enable\r
+#define UART_CTL_TXE 0x00000100 // Transmit Enable\r
+#define UART_CTL_LBE 0x00000080 // Loopback Enable\r
+#define UART_CTL_UARTEN 0x00000001 // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_RX2_8 0x00000010 // 1/4 Full\r
+#define UART_IFLS_RX4_8 0x00000020 // 1/2 Full\r
+#define UART_IFLS_RX6_8 0x00000030 // 3/4 Full\r
+#define UART_IFLS_RX7_8 0x00000040 // 7/8 Full\r
+#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
+#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
+#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
+#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full\r
+#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask\r
+#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask\r
+#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY (UART_RSR_OE | \\r
+ UART_RSR_BE | \\r
+ UART_RSR_PE | \\r
+ UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR 0x00000000\r
+#define UART_RV_RSR 0x00000000\r
+#define UART_RV_ECR 0x00000000\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_FBRD 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_IM 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
+#define UART_RV_MIS 0x00000000\r
+#define UART_RV_ICR 0x00000000\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PeriphID1 0x00000000\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PCellID3 0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD 0x00000000 // Load register\r
+#define WDT_O_VALUE 0x00000004 // Current value register\r
+#define WDT_O_CTL 0x00000008 // Control register\r
+#define WDT_O_ICR 0x0000000C // Interrupt clear register\r
+#define WDT_O_RIS 0x00000010 // Raw interrupt status register\r
+#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
+#define WDT_O_TEST 0x00000418 // Test register\r
+#define WDT_O_LOCK 0x00000C00 // Lock register\r
+#define WDT_O_PeriphID4 0x00000FD0 //\r
+#define WDT_O_PeriphID5 0x00000FD4 //\r
+#define WDT_O_PeriphID6 0x00000FD8 //\r
+#define WDT_O_PeriphID7 0x00000FDC //\r
+#define WDT_O_PeriphID0 0x00000FE0 //\r
+#define WDT_O_PeriphID1 0x00000FE4 //\r
+#define WDT_O_PeriphID2 0x00000FE8 //\r
+#define WDT_O_PeriphID3 0x00000FEC //\r
+#define WDT_O_PCellID0 0x00000FF0 //\r
+#define WDT_O_PCellID1 0x00000FF4 //\r
+#define WDT_O_PCellID2 0x00000FF8 //\r
+#define WDT_O_PCellID3 0x00000FFC //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
+#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_LOCK 0x00000000 // Lock register\r
+#define WDT_RV_PeriphID4 0x00000000 //\r
+#define WDT_RV_PeriphID5 0x00000000 //\r
+#define WDT_RV_PeriphID6 0x00000000 //\r
+#define WDT_RV_PeriphID7 0x00000000 //\r
+#define WDT_RV_PeriphID0 0x00000005 //\r
+#define WDT_RV_PeriphID1 0x00000018 //\r
+#define WDT_RV_PeriphID2 0x00000018 //\r
+#define WDT_RV_PeriphID3 0x00000001 //\r
+#define WDT_RV_PCellID0 0x0000000D //\r
+#define WDT_RV_PCellID1 0x000000F0 //\r
+#define WDT_RV_PCellID2 0x00000005 //\r
+#define WDT_RV_PCellID3 0x000000B1 //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram96x16.c - Driver for the OSRAM 96x16 graphical OLED display.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup ev_lm3s811_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_i2c.h"\r
+#include "hw_memmap.h"\r
+#include "hw_sysctl.h"\r
+#include "hw_types.h"\r
+#include "src/debug.h"\r
+#include "src/gpio.h"\r
+#include "src/i2c.h"\r
+#include "src/sysctl.h"\r
+#include "osram96x16.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// The I2C slave address of the SSD0303 controller on the OLED display.\r
+//\r
+//*****************************************************************************\r
+#define SSD0303_ADDR 0x3d\r
+\r
+//*****************************************************************************\r
+//\r
+// A 5x7 font (in a 6x8 cell, where the sixth column is omitted from this\r
+// table) for displaying text on the OLED display. The data is organized as\r
+// bytes from the left column to the right column, with each byte containing\r
+// the top row in the LSB and the bottom row in the MSB.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucFont[95][5] =\r
+{\r
+ { 0x00, 0x00, 0x00, 0x00, 0x00 }, // " "\r
+ { 0x00, 0x00, 0x4f, 0x00, 0x00 }, // !\r
+ { 0x00, 0x07, 0x00, 0x07, 0x00 }, // "\r
+ { 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // #\r
+ { 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $\r
+ { 0x23, 0x13, 0x08, 0x64, 0x62 }, // %\r
+ { 0x36, 0x49, 0x55, 0x22, 0x50 }, // &\r
+ { 0x00, 0x05, 0x03, 0x00, 0x00 }, // '\r
+ { 0x00, 0x1c, 0x22, 0x41, 0x00 }, // (\r
+ { 0x00, 0x41, 0x22, 0x1c, 0x00 }, // )\r
+ { 0x14, 0x08, 0x3e, 0x08, 0x14 }, // *\r
+ { 0x08, 0x08, 0x3e, 0x08, 0x08 }, // +\r
+ { 0x00, 0x50, 0x30, 0x00, 0x00 }, // ,\r
+ { 0x08, 0x08, 0x08, 0x08, 0x08 }, // -\r
+ { 0x00, 0x60, 0x60, 0x00, 0x00 }, // .\r
+ { 0x20, 0x10, 0x08, 0x04, 0x02 }, // /\r
+ { 0x3e, 0x51, 0x49, 0x45, 0x3e }, // 0\r
+ { 0x00, 0x42, 0x7f, 0x40, 0x00 }, // 1\r
+ { 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2\r
+ { 0x21, 0x41, 0x45, 0x4b, 0x31 }, // 3\r
+ { 0x18, 0x14, 0x12, 0x7f, 0x10 }, // 4\r
+ { 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5\r
+ { 0x3c, 0x4a, 0x49, 0x49, 0x30 }, // 6\r
+ { 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7\r
+ { 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8\r
+ { 0x06, 0x49, 0x49, 0x29, 0x1e }, // 9\r
+ { 0x00, 0x36, 0x36, 0x00, 0x00 }, // :\r
+ { 0x00, 0x56, 0x36, 0x00, 0x00 }, // ;\r
+ { 0x08, 0x14, 0x22, 0x41, 0x00 }, // <\r
+ { 0x14, 0x14, 0x14, 0x14, 0x14 }, // =\r
+ { 0x00, 0x41, 0x22, 0x14, 0x08 }, // >\r
+ { 0x02, 0x01, 0x51, 0x09, 0x06 }, // ?\r
+ { 0x32, 0x49, 0x79, 0x41, 0x3e }, // @\r
+ { 0x7e, 0x11, 0x11, 0x11, 0x7e }, // A\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x36 }, // B\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x22 }, // C\r
+ { 0x7f, 0x41, 0x41, 0x22, 0x1c }, // D\r
+ { 0x7f, 0x49, 0x49, 0x49, 0x41 }, // E\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x01 }, // F\r
+ { 0x3e, 0x41, 0x49, 0x49, 0x7a }, // G\r
+ { 0x7f, 0x08, 0x08, 0x08, 0x7f }, // H\r
+ { 0x00, 0x41, 0x7f, 0x41, 0x00 }, // I\r
+ { 0x20, 0x40, 0x41, 0x3f, 0x01 }, // J\r
+ { 0x7f, 0x08, 0x14, 0x22, 0x41 }, // K\r
+ { 0x7f, 0x40, 0x40, 0x40, 0x40 }, // L\r
+ { 0x7f, 0x02, 0x0c, 0x02, 0x7f }, // M\r
+ { 0x7f, 0x04, 0x08, 0x10, 0x7f }, // N\r
+ { 0x3e, 0x41, 0x41, 0x41, 0x3e }, // O\r
+ { 0x7f, 0x09, 0x09, 0x09, 0x06 }, // P\r
+ { 0x3e, 0x41, 0x51, 0x21, 0x5e }, // Q\r
+ { 0x7f, 0x09, 0x19, 0x29, 0x46 }, // R\r
+ { 0x46, 0x49, 0x49, 0x49, 0x31 }, // S\r
+ { 0x01, 0x01, 0x7f, 0x01, 0x01 }, // T\r
+ { 0x3f, 0x40, 0x40, 0x40, 0x3f }, // U\r
+ { 0x1f, 0x20, 0x40, 0x20, 0x1f }, // V\r
+ { 0x3f, 0x40, 0x38, 0x40, 0x3f }, // W\r
+ { 0x63, 0x14, 0x08, 0x14, 0x63 }, // X\r
+ { 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y\r
+ { 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z\r
+ { 0x00, 0x7f, 0x41, 0x41, 0x00 }, // [\r
+ { 0x02, 0x04, 0x08, 0x10, 0x20 }, // "\"\r
+ { 0x00, 0x41, 0x41, 0x7f, 0x00 }, // ]\r
+ { 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^\r
+ { 0x40, 0x40, 0x40, 0x40, 0x40 }, // _\r
+ { 0x00, 0x01, 0x02, 0x04, 0x00 }, // `\r
+ { 0x20, 0x54, 0x54, 0x54, 0x78 }, // a\r
+ { 0x7f, 0x48, 0x44, 0x44, 0x38 }, // b\r
+ { 0x38, 0x44, 0x44, 0x44, 0x20 }, // c\r
+ { 0x38, 0x44, 0x44, 0x48, 0x7f }, // d\r
+ { 0x38, 0x54, 0x54, 0x54, 0x18 }, // e\r
+ { 0x08, 0x7e, 0x09, 0x01, 0x02 }, // f\r
+ { 0x0c, 0x52, 0x52, 0x52, 0x3e }, // g\r
+ { 0x7f, 0x08, 0x04, 0x04, 0x78 }, // h\r
+ { 0x00, 0x44, 0x7d, 0x40, 0x00 }, // i\r
+ { 0x20, 0x40, 0x44, 0x3d, 0x00 }, // j\r
+ { 0x7f, 0x10, 0x28, 0x44, 0x00 }, // k\r
+ { 0x00, 0x41, 0x7f, 0x40, 0x00 }, // l\r
+ { 0x7c, 0x04, 0x18, 0x04, 0x78 }, // m\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x78 }, // n\r
+ { 0x38, 0x44, 0x44, 0x44, 0x38 }, // o\r
+ { 0x7c, 0x14, 0x14, 0x14, 0x08 }, // p\r
+ { 0x08, 0x14, 0x14, 0x18, 0x7c }, // q\r
+ { 0x7c, 0x08, 0x04, 0x04, 0x08 }, // r\r
+ { 0x48, 0x54, 0x54, 0x54, 0x20 }, // s\r
+ { 0x04, 0x3f, 0x44, 0x40, 0x20 }, // t\r
+ { 0x3c, 0x40, 0x40, 0x20, 0x7c }, // u\r
+ { 0x1c, 0x20, 0x40, 0x20, 0x1c }, // v\r
+ { 0x3c, 0x40, 0x30, 0x40, 0x3c }, // w\r
+ { 0x44, 0x28, 0x10, 0x28, 0x44 }, // x\r
+ { 0x0c, 0x50, 0x50, 0x50, 0x3c }, // y\r
+ { 0x44, 0x64, 0x54, 0x4c, 0x44 }, // z\r
+ { 0x00, 0x08, 0x36, 0x41, 0x00 }, // {\r
+ { 0x00, 0x00, 0x7f, 0x00, 0x00 }, // |\r
+ { 0x00, 0x41, 0x36, 0x08, 0x00 }, // }\r
+ { 0x02, 0x01, 0x02, 0x04, 0x02 }, // ~\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The sequence of commands used to initialize the SSD0303 controller.\r
+//\r
+//*****************************************************************************\r
+static const unsigned char g_pucOSRAMInit[] =\r
+{\r
+ //\r
+ // Turn off the panel\r
+ //\r
+ 0x80, 0xae,\r
+\r
+ //\r
+ // Set lower column address\r
+ //\r
+ 0x80, 0x04,\r
+\r
+ //\r
+ // Set higher column address\r
+ //\r
+ 0x80, 0x12,\r
+\r
+ //\r
+ // Set contrast control register\r
+ //\r
+ 0x80, 0x81, 0x80, 0x2b,\r
+\r
+ //\r
+ // Set segment re-map\r
+ //\r
+ 0x80, 0xa1,\r
+\r
+ //\r
+ // Set display start line\r
+ //\r
+ 0x80, 0x40,\r
+\r
+ //\r
+ // Set display offset\r
+ //\r
+ 0x80, 0xd3, 0x80, 0x00,\r
+\r
+ //\r
+ // Set multiplex ratio\r
+ //\r
+ 0x80, 0xa8, 0x80, 0x0f,\r
+\r
+ //\r
+ // Set the display to normal mode\r
+ //\r
+ 0x80, 0xa4,\r
+\r
+ //\r
+ // Non-inverted display\r
+ //\r
+ 0x80, 0xa6,\r
+\r
+ //\r
+ // Set the page address\r
+ //\r
+ 0x80, 0xb0,\r
+\r
+ //\r
+ // Set COM output scan direction\r
+ //\r
+ 0x80, 0xc8,\r
+\r
+ //\r
+ // Set display clock divide ratio/oscillator frequency\r
+ //\r
+ 0x80, 0xd5, 0x80, 0x72,\r
+\r
+ //\r
+ // Enable mono mode\r
+ //\r
+ 0x80, 0xd8, 0x80, 0x00,\r
+\r
+ //\r
+ // Set pre-charge period\r
+ //\r
+ 0x80, 0xd9, 0x80, 0x22,\r
+\r
+ //\r
+ // Set COM pins hardware configuration\r
+ //\r
+ 0x80, 0xda, 0x80, 0x12,\r
+\r
+ //\r
+ // Set VCOM deslect level\r
+ //\r
+ 0x80, 0xdb, 0x80, 0x0f,\r
+\r
+ //\r
+ // Set DC-DC on\r
+ //\r
+ 0x80, 0xad, 0x80, 0x8b,\r
+\r
+ //\r
+ // Turn on the panel\r
+ //\r
+ 0x80, 0xaf,\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The inter-byte delay required by the SSD0303 OLED controller.\r
+//\r
+//*****************************************************************************\r
+static unsigned long g_ulDelay;\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Provide a small delay.\r
+//!\r
+//! \param ulCount is the number of delay loop iterations to perform.\r
+//!\r
+//! Since the SSD0303 controller needs a delay between bytes written to it over\r
+//! the I2C bus, this function provides a means of generating that delay. It\r
+//! is written in assembly to keep the delay consistent across tool chains,\r
+//! avoiding the need to tune the delay based on the tool chain in use.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#if defined(ewarm)\r
+static void\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ __asm(" subs r0, #1\n"\r
+ " bne OSRAMDelay\n"\r
+ " bx lr");\r
+}\r
+#endif\r
+#if defined(gcc)\r
+static void __attribute__((naked))\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ __asm(" subs r0, #1\n"\r
+ " bne OSRAMDelay\n"\r
+ " bx lr");\r
+}\r
+#endif\r
+#if defined(rvmdk) || defined(__ARMCC_VERSION)\r
+__asm void\r
+OSRAMDelay(unsigned long ulCount)\r
+{\r
+ subs r0, #1;\r
+ bne OSRAMDelay;\r
+ bx lr;\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Start a transfer to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the first byte to be written to the controller.\r
+//!\r
+//! This function will start a transfer to the SSD0303 controller via the I2C\r
+//! bus.\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteFirst(unsigned char ucChar)\r
+{\r
+ //\r
+ // Set the slave address.\r
+ //\r
+ I2CMasterSlaveAddrSet(I2C_MASTER_BASE, SSD0303_ADDR, false);\r
+\r
+ //\r
+ // Write the first byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Start the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a byte to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the byte to be transmitted to the controller.\r
+//!\r
+//! This function continues a transfer to the SSD0303 controller by writing\r
+//! another byte over the I2C bus. This must only be called after calling\r
+//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().\r
+//!\r
+//! The data is written in a polled faashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteByte(unsigned char ucChar)\r
+{\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Continue the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Write a sequence of bytes to the SSD0303 controller.\r
+//!\r
+//! This function continues a transfer to the SSD0303 controller by writing a\r
+//! sequence of bytes over the I2C bus. This must only be called after calling\r
+//! OSRAMWriteFirst(), but before calling OSRAMWriteFinal().\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the entire byte sequence has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteArray(const unsigned char *pucBuffer, unsigned long ulCount)\r
+{\r
+ //\r
+ // Loop while there are more bytes left to be transferred.\r
+ //\r
+ while(ulCount != 0)\r
+ {\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the next byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, *pucBuffer++);\r
+ ulCount--;\r
+\r
+ //\r
+ // Continue the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! \internal\r
+//!\r
+//! Finish a transfer to the SSD0303 controller.\r
+//!\r
+//! \param ucChar is the final byte to be written to the controller.\r
+//!\r
+//! This function will finish a transfer to the SSD0303 controller via the I2C\r
+//! bus. This must only be called after calling OSRAMWriteFirst().\r
+//!\r
+//! The data is written in a polled fashion; this function will not return\r
+//! until the byte has been written to the controller.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+static void\r
+OSRAMWriteFinal(unsigned char ucChar)\r
+{\r
+ //\r
+ // Wait until the current byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+\r
+ //\r
+ // Write the final byte to the controller.\r
+ //\r
+ I2CMasterDataPut(I2C_MASTER_BASE, ucChar);\r
+\r
+ //\r
+ // Finish the transfer.\r
+ //\r
+ I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);\r
+\r
+ //\r
+ // Wait until the final byte has been transferred.\r
+ //\r
+ while(I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0)\r
+ {\r
+ }\r
+\r
+ //\r
+ // Provide the required inter-byte delay.\r
+ //\r
+ OSRAMDelay(g_ulDelay);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clears the OLED display.\r
+//!\r
+//! This function will clear the display. All pixels in the display will be\r
+//! turned off.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMClear(void)\r
+{\r
+ static const unsigned char pucRow1[] =\r
+ {\r
+ 0xb0, 0x80, 0x04, 0x80, 0x12, 0x40\r
+ };\r
+ static const unsigned char pucRow2[] =\r
+ {\r
+ 0xb1, 0x80, 0x04, 0x80, 0x12, 0x40\r
+ };\r
+ unsigned long ulIdx;\r
+\r
+ //\r
+ // Move the display cursor to the first column of the first row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteArray(pucRow1, sizeof(pucRow1));\r
+\r
+ //\r
+ // Fill this row with zeros.\r
+ //\r
+ for(ulIdx = 0; ulIdx < 95; ulIdx++)\r
+ {\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ OSRAMWriteFinal(0x00);\r
+\r
+ //\r
+ // Move the display cursor to the first column of the second row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteArray(pucRow2, sizeof(pucRow2));\r
+\r
+ //\r
+ // Fill this row with zeros.\r
+ //\r
+ for(ulIdx = 0; ulIdx < 95; ulIdx++)\r
+ {\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ OSRAMWriteFinal(0x00);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays a string on the OLED display.\r
+//!\r
+//! \param pcStr is a pointer to the string to display.\r
+//! \param ulX is the horizontal position to display the string, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display the string, specified in\r
+//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are\r
+//! valid).\r
+//!\r
+//! This function will draw a string on the display. Only the ASCII characters\r
+//! between 32 (space) and 126 (tilde) are supported; other characters will\r
+//! result in random data being draw on the display (based on whatever appears\r
+//! before/after the font in memory). The font is mono-spaced, so characters\r
+//! such as "i" and "l" have more white space around them than characters such\r
+//! as "m" or "w".\r
+//!\r
+//! If the drawing of the string reaches the right edge of the display, no more\r
+//! characters will be drawn. Therefore, special care is not required to avoid\r
+//! supplying a string that is "too long" to display.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMStringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 96);\r
+ ASSERT(ulY < 2);\r
+\r
+ //\r
+ // Move the display cursor to the requested position on the display.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte((ulX + 36) & 0x0f);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x10 | (((ulX + 36) >> 4) & 0x0f));\r
+ OSRAMWriteByte(0x40);\r
+\r
+ //\r
+ // Loop while there are more characters in the string.\r
+ //\r
+ while(*pcStr != 0)\r
+ {\r
+ //\r
+ // See if there is enough space on the display for this entire\r
+ // character.\r
+ //\r
+ if(ulX <= 90)\r
+ {\r
+ //\r
+ // Write the contents of this character to the display.\r
+ //\r
+ OSRAMWriteArray(g_pucFont[*pcStr - ' '], 5);\r
+\r
+ //\r
+ // See if this is the last character to display (either because the\r
+ // right edge has been reached or because there are no more\r
+ // characters).\r
+ //\r
+ if((ulX == 90) || (pcStr[1] == 0))\r
+ {\r
+ //\r
+ // Write the final column of the display.\r
+ //\r
+ OSRAMWriteFinal(0x00);\r
+\r
+ //\r
+ // The string has been displayed.\r
+ //\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Write the inter-character padding column.\r
+ //\r
+ OSRAMWriteByte(0x00);\r
+ }\r
+ else\r
+ {\r
+ //\r
+ // Write the portion of the character that will fit onto the\r
+ // display.\r
+ //\r
+ OSRAMWriteArray(g_pucFont[*pcStr - ' '], 95 - ulX);\r
+ OSRAMWriteFinal(g_pucFont[*pcStr - ' '][95 - ulX]);\r
+\r
+ //\r
+ // The string has been displayed.\r
+ //\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Advance to the next character.\r
+ //\r
+ pcStr++;\r
+\r
+ //\r
+ // Increment the X coordinate by the six columns that were just\r
+ // written.\r
+ //\r
+ ulX += 6;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Displays an image on the OLED display.\r
+//!\r
+//! \param pucImage is a pointer to the image data.\r
+//! \param ulX is the horizontal position to display this image, specified in\r
+//! columns from the left edge of the display.\r
+//! \param ulY is the vertical position to display this image, specified in\r
+//! eight scan line blocks from the top of the display (i.e. only 0 and 1 are\r
+//! valid).\r
+//! \param ulWidth is the width of the image, specified in columns.\r
+//! \param ulHeight is the height of the image, specified in eight row blocks\r
+//! (i.e. only 1 and 2 are valid).\r
+//!\r
+//! This function will display a bitmap graphic on the display. The image to\r
+//! be displayed must be a multiple of eight scan lines high (i.e. one row) and\r
+//! will be drawn at a vertical position that is a multiple of eight scan lines\r
+//! (i.e. scan line zero or scan line eight, corresponding to row zero or row\r
+//! one).\r
+//!\r
+//! The image data is organized with the first row of image data appearing left\r
+//! to right, followed immediately by the second row of image data. Each byte\r
+//! contains the data for the eight scan lines of the column, with the top scan\r
+//! line being in the least significant bit of the byte and the bottom scan\r
+//! line being in the most significat bit of the byte.\r
+//!\r
+//! For example, an image four columns wide and sixteen scan lines tall would\r
+//! be arranged as follows (showing how the eight bytes of the image would\r
+//! appear on the display):\r
+//!\r
+//! \verbatim\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! | | 0 | | | 0 | | | 0 | | | 0 |\r
+//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |\r
+//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |\r
+//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |\r
+//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |\r
+//! | | 5 | | | 5 | | | 5 | | | 5 |\r
+//! | 0 | 6 | | 1 | 6 | | 2 | 6 | | 3 | 6 |\r
+//! | | 7 | | | 7 | | | 7 | | | 7 |\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//!\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! | | 0 | | | 0 | | | 0 | | | 0 |\r
+//! | B | 1 | | B | 1 | | B | 1 | | B | 1 |\r
+//! | y | 2 | | y | 2 | | y | 2 | | y | 2 |\r
+//! | t | 3 | | t | 3 | | t | 3 | | t | 3 |\r
+//! | e | 4 | | e | 4 | | e | 4 | | e | 4 |\r
+//! | | 5 | | | 5 | | | 5 | | | 5 |\r
+//! | 4 | 6 | | 5 | 6 | | 6 | 6 | | 7 | 6 |\r
+//! | | 7 | | | 7 | | | 7 | | | 7 |\r
+//! +-------+ +-------+ +-------+ +-------+\r
+//! \endverbatim\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight)\r
+{\r
+ //\r
+ // Check the arguments.\r
+ //\r
+ ASSERT(ulX < 96);\r
+ ASSERT(ulY < 2);\r
+ ASSERT((ulX + ulWidth) <= 96);\r
+ ASSERT((ulY + ulHeight) <= 2);\r
+\r
+ //\r
+ // The first 36 columns of the LCD buffer are not displayed, so increment\r
+ // the X coorddinate by 36 to account for the non-displayed frame buffer\r
+ // memory.\r
+ //\r
+ ulX += 36;\r
+\r
+ //\r
+ // Loop while there are more rows to display.\r
+ //\r
+ while(ulHeight--)\r
+ {\r
+ //\r
+ // Write the starting address within this row.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte((ulY == 0) ? 0xb0 : 0xb1);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(ulX & 0x0f);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x10 | ((ulX >> 4) & 0x0f));\r
+ OSRAMWriteByte(0x40);\r
+\r
+ //\r
+ // Write this row of image data.\r
+ //\r
+ OSRAMWriteArray(pucImage, ulWidth - 1);\r
+ OSRAMWriteFinal(pucImage[ulWidth - 1]);\r
+\r
+ //\r
+ // Advance to the next row of the image.\r
+ //\r
+ pucImage += ulWidth;\r
+ ulY++;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initialize the OLED display.\r
+//!\r
+//! \param bFast is a boolean that is \e true if the I2C interface should be\r
+//! run at 400 kbps and \e false if it should be run at 100 kbps.\r
+//!\r
+//! This function initializes the I2C interface to the OLED display and\r
+//! configures the SSD0303 controller on the panel.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMInit(tBoolean bFast)\r
+{\r
+ //\r
+ // Enable the I2C and GPIO port B blocks as they are needed by this driver.\r
+ //\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);\r
+\r
+ //\r
+ // Configure the I2C SCL and SDA pins for I2C operation.\r
+ //\r
+ GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);\r
+\r
+ //\r
+ // Initialize the I2C master.\r
+ //\r
+ I2CMasterInit(I2C_MASTER_BASE, bFast);\r
+\r
+ //\r
+ // Compute the inter-byte delay for the SSD0303 controller. This delay is\r
+ // dependent upon the I2C bus clock rate; the slower the clock the longer\r
+ // the delay required.\r
+ //\r
+ // The derivation of this formula is based on a measured delay of\r
+ // OSRAMDelay(1640) for a 100 kHz I2C bus with the CPU running at 50 MHz\r
+ // (referred to as C). To scale this to the delay for a different CPU\r
+ // speed (since this is just a CPU-based delay loop) is:\r
+ //\r
+ // f(CPU)\r
+ // C * ----------\r
+ // 50,000,000\r
+ //\r
+ // To then scale this to the actual I2C rate (since it won't always be\r
+ // precisely 100 kHz):\r
+ //\r
+ // f(CPU) 100,000\r
+ // C * ---------- * -------\r
+ // 50,000,000 f(I2C)\r
+ //\r
+ // This equation will give the inter-byte delay required for any\r
+ // configuration of the I2C master. But, as arranged it is impossible to\r
+ // directly compute in 32-bit arithmetic (without loosing a lot of\r
+ // accuracy). So, the equation is simplified.\r
+ //\r
+ // Since f(I2C) is generated by dividing down from f(CPU), replace it with\r
+ // the equivalent (where TPR is the value programmed into the Master Timer\r
+ // Period Register of the I2C master, with the 1 added back):\r
+ //\r
+ // 100,000\r
+ // f(CPU) -------\r
+ // C * ---------- * f(CPU)\r
+ // 50,000,000 ------------\r
+ // 2 * 10 * TPR\r
+ //\r
+ // Inverting the dividend in the last term:\r
+ //\r
+ // f(CPU) 100,000 * 2 * 10 * TPR\r
+ // C * ---------- * ----------------------\r
+ // 50,000,000 f(CPU)\r
+ //\r
+ // The f(CPU) now cancels out.\r
+ //\r
+ // 100,000 * 2 * 10 * TPR\r
+ // C * ----------------------\r
+ // 50,000,000\r
+ //\r
+ // Since there are no clock frequencies left in the equation, this equation\r
+ // also works for 400 kHz bus operation as well, since the 100,000 in the\r
+ // numerator becomes 400,000 but C is 1/4, which cancel out each other.\r
+ // Reducing the constants gives:\r
+ //\r
+ // TPR TPR TPR\r
+ // C * --- = 1640 * --- = 328 * ---\r
+ // 25 25 5\r
+ //\r
+ // Note that the constant C is actually a bit larger than it needs to be in\r
+ // order to provide some safety margin.\r
+ //\r
+ g_ulDelay = (328 * (HWREG(I2C_MASTER_BASE + I2C_MASTER_O_TPR) + 1)) / 5;\r
+\r
+ //\r
+ // Initialize the SSD0303 controller.\r
+ //\r
+ OSRAMWriteFirst(g_pucOSRAMInit[0]);\r
+ OSRAMWriteArray(g_pucOSRAMInit + 1, sizeof(g_pucOSRAMInit) - 2);\r
+ OSRAMWriteFinal(g_pucOSRAMInit[sizeof(g_pucOSRAMInit) - 1]);\r
+\r
+ //\r
+ // Clear the frame buffer.\r
+ //\r
+ OSRAMClear();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the OLED display.\r
+//!\r
+//! This function will turn on the OLED display, causing it to display the\r
+//! contents of its internal frame buffer.\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMDisplayOn(void)\r
+{\r
+ //\r
+ // Turn on the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte(0xad);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x8b);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteFinal(0xaf);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns off the OLED display.\r
+//!\r
+//! This function will turn off the OLED display. This will stop the scanning\r
+//! of the panel and turn off the on-chip DC-DC converter, preventing damage to\r
+//! the panel due to burn-in (it has similar characters to a CRT in this\r
+//! respect).\r
+//!\r
+//! This function is contained in <tt>osram96x16.c</tt>, with\r
+//! <tt>osram96x16.h</tt> containing the API definition for use by\r
+//! applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+OSRAMDisplayOff(void)\r
+{\r
+ //\r
+ // Turn off the DC-DC converter and the display.\r
+ //\r
+ OSRAMWriteFirst(0x80);\r
+ OSRAMWriteByte(0xad);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteByte(0x8a);\r
+ OSRAMWriteByte(0x80);\r
+ OSRAMWriteFinal(0xae);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// osram96x16.h - Prototypes for the driver for the OSRAM 96x16 graphical OLED\r
+// display.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __OSRAM96X16_H__\r
+#define __OSRAM96X16_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the driver APIs.\r
+//\r
+//*****************************************************************************\r
+extern void OSRAMClear(void);\r
+extern void OSRAMStringDraw(const char *pcStr, unsigned long ulX,\r
+ unsigned long ulY);\r
+extern void OSRAMImageDraw(const unsigned char *pucImage, unsigned long ulX,\r
+ unsigned long ulY, unsigned long ulWidth,\r
+ unsigned long ulHeight);\r
+extern void OSRAMInit(tBoolean bFast);\r
+extern void OSRAMDisplayOn(void);\r
+extern void OSRAMDisplayOff(void);\r
+\r
+#endif // __OSRAM96X16_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event\r
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event\r
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event\r
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event\r
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event\r
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select\r
+#define ADC_CTL_IE 0x00000040 // Interrupt enable\r
+#define ADC_CTL_END 0x00000020 // Sequence end select\r
+#define ADC_CTL_D 0x00000010 // Differential select\r
+#define ADC_CTL_CH0 0x00000000 // Input channel 0\r
+#define ADC_CTL_CH1 0x00000001 // Input channel 1\r
+#define ADC_CTL_CH2 0x00000002 // Input channel 2\r
+#define ADC_CTL_CH3 0x00000003 // Input channel 3\r
+#define ADC_CTL_CH4 0x00000004 // Input channel 4\r
+#define ADC_CTL_CH5 0x00000005 // Input channel 5\r
+#define ADC_CTL_CH6 0x00000006 // Input channel 6\r
+#define ADC_CTL_CH7 0x00000007 // Input channel 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+ void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulTrigger,\r
+ unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+ unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long ulStep,\r
+ unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+ unsigned long ulSequenceNum,\r
+ unsigned long *pulBuffer,\r
+ unsigned long ulCount);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high\r
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low\r
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge\r
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge\r
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges\r
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high\r
+#define COMP_INT_LOW 0x00000000 // Interrupt when low\r
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge\r
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge\r
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges\r
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin\r
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output\r
+#define COMP_OUTPUT_NORMAL 0x00000100 // Comparator output normal\r
+#define COMP_OUTPUT_INVERT 0x00000102 // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference\r
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V\r
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+ unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+ void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+ unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+ tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API. This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+ FlashReadWrite, // Flash can be read and written\r
+ FlashReadOnly, // Flash can only be read\r
+ FlashExecuteOnly // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+ unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+ tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0\r
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1\r
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2\r
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3\r
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4\r
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5\r
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6\r
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned long ulStrength,\r
+ unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+ unsigned long *pulStrength,\r
+ unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+ void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+ unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __GPIO_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER 0x00000001\r
+#define I2C_INT_SLAVE 0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START \\r
+ (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT \\r
+ (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \\r
+ (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \\r
+ (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE 0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE 0\r
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+ unsigned char ucSlaveAddr,\r
+ tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+ unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0\r
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1\r
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2\r
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+ unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+ unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+ unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+ tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+ void (*pfIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+ void (*pfIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+ tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// qei.h - Prototypes for the Quadrature Encoder Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __QEI_H__\r
+#define __QEI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIConfigure as the ulConfig paramater.\r
+//\r
+//*****************************************************************************\r
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only\r
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges\r
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse\r
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse\r
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature\r
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir\r
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB\r
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.\r
+//\r
+//*****************************************************************************\r
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1\r
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2\r
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4\r
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8\r
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16\r
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32\r
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64\r
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts\r
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define QEI_INTERROR 0x00000008 // Phase error detected\r
+#define QEI_INTDIR 0x00000004 // Direction change\r
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired\r
+#define QEI_INTINDEX 0x00000001 // Index pulse detected\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void QEIEnable(unsigned long ulBase);\r
+extern void QEIDisable(unsigned long ulBase);\r
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,\r
+ unsigned long ulMaxPosition);\r
+extern unsigned long QEIPositionGet(unsigned long ulBase);\r
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);\r
+extern long QEIDirectionGet(unsigned long ulBase);\r
+extern tBoolean QEIErrorGet(unsigned long ulBase);\r
+extern void QEIVelocityEnable(unsigned long ulBase);\r
+extern void QEIVelocityDisable(unsigned long ulBase);\r
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,\r
+ unsigned long ulPeriod);\r
+extern unsigned long QEIVelocityGet(unsigned long ulBase);\r
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void QEIIntUnregister(unsigned long ulBase);\r
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __QEI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF 0x00000008 // TX FIFO half empty or less\r
+#define SSI_RXFF 0x00000004 // RX FIFO half full or less\r
+#define SSI_RXTO 0x00000002 // RX timeout\r
+#define SSI_RXOR 0x00000001 // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI 0x00000010 // TI frame format\r
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER 0x00000000 // SSI master\r
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+ unsigned long ulMode, unsigned long ulBitRate,\r
+ unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM 0x00100000 // PWM\r
+#define SYSCTL_PERIPH_ADC 0x00010000 // ADC\r
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#define SYSCTL_PERIPH_TIMER0 0x10010000 // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1 0x10020000 // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2 0x10040000 // Timer 2\r
+#define SYSCTL_PERIPH_COMP0 0x11000000 // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1 0x12000000 // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2 0x14000000 // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin\r
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin\r
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin\r
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin\r
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin\r
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin\r
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin\r
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin\r
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin\r
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin\r
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin\r
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin\r
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin\r
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin\r
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin\r
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin\r
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin\r
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin\r
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin\r
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin\r
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin\r
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin\r
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset\r
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset\r
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset\r
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlADCSpeedSet() API\r
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second\r
+#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second\r
+#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second\r
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+ unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);\r
+extern unsigned long SysCtlADCSpeedGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer\r
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer\r
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A 0x000000ff // Timer A\r
+#define TIMER_B 0x0000ff00 // Timer B\r
+#define TIMER_BOTH 0x0000ffff // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+ tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+ unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+ unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+ void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask\r
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask\r
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask\r
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask\r
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask\r
+#define UART_INT_RX 0x010 // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter. Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
+#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+ unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+ unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+ unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 816 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+ cExt (*.c)\r
+ aExt (*.s*; *.src; *.a*)\r
+ oExt (*.obj)\r
+ lExt (*.lib)\r
+ tExt (*.txt; *.h; *.inc)\r
+ pExt (*.plm)\r
+ CppX (*.cpp)\r
+ DaveTm { 0,0,0,0,0,0,0,0 }\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+GRPOPT 1,(Demo_Source),1,0,0\r
+GRPOPT 2,(Libraries),1,0,0\r
+GRPOPT 3,(RTOS_Source),0,0,0\r
+GRPOPT 4,(Documentation),1,0,0\r
+\r
+OPTFFF 1,1,2,0,0,0,0,0,<.\startup_rvmdk.S><startup_rvmdk.S> \r
+OPTFFF 1,2,1,167772160,0,0,0,0,<.\LuminaryCode\osram96x16.c><osram96x16.c> \r
+OPTFFF 1,3,1,0,0,0,0,0,<.\main.c><main.c> \r
+OPTFFF 1,4,1,0,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c> \r
+OPTFFF 1,5,1,989855744,0,0,0,0,<..\Common\Minimal\integer.c><integer.c> \r
+OPTFFF 1,6,1,939524096,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c> \r
+OPTFFF 1,7,1,201326592,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c> \r
+OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> \r
+OPTFFF 2,9,4,0,0,0,0,0,<C:\Devtools\Keil\ARM\RV30\LIB\Luminary\driverlib.lib><driverlib.lib> \r
+OPTFFF 3,10,1,503316481,0,0,0,0,<..\..\Source\tasks.c><tasks.c> \r
+OPTFFF 3,11,1,0,0,0,0,0,<..\..\Source\list.c><list.c> \r
+OPTFFF 3,12,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c> \r
+OPTFFF 3,13,1,0,0,0,0,0,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> \r
+OPTFFF 4,14,5,2,0,1,1,0,<.\readme.txt><readme.txt> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 }\r
+\r
+ExtF <.\readme.txt> 1,1,0,{ 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,66,0,0,0,99,0,0,0,22,4,0,0,64,2,0,0 }\r
+\r
+TARGOPT 1, (FreeRTOS_Demo)\r
+ ADSCLK=50000000\r
+ OPTTT 1,1,1,0\r
+ OPTHX 1,65535,0,0,0\r
+ OPTLX 79,66,8,<.\rvmdk\>\r
+ OPTOX 16\r
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0\r
+ OPTXL 1,1,1,1,1,1,1,0,0\r
+ OPTFL 1,0,1\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811)\r
+ OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ OPTKEY 0,(DLGTARM)()\r
+ OPTKEY 0,(ARMDBGFLAGS)(-T5F)\r
+ OPTKEY 0,(LMIDK-AGDI)(-B0 -O1792)\r
+ OPTBB 0,0,106,1,3002,0,0,0,0,1,<main.c>()()\r
+ OPTDF 0x84\r
+ OPTLE <>\r
+ OPTLC <>\r
+EndOpt\r
+\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (FreeRTOS_Demo), 0x0004 // Tools: 'ARM-ADS'\r
+\r
+Group (Demo_Source)\r
+Group (Libraries)\r
+Group (RTOS_Source)\r
+Group (Documentation)\r
+\r
+File 1,2,<.\startup_rvmdk.S><startup_rvmdk.S> 0x44FB12E0 \r
+File 1,1,<.\LuminaryCode\osram96x16.c><osram96x16.c> 0x44F9AFC1 \r
+File 1,1,<.\main.c><main.c> 0x44FC00B0 \r
+File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x44F30401 \r
+File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x44F30401 \r
+File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x44F30401 \r
+File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x44F30403 \r
+File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x44F30418 \r
+File 2,4,<C:\Devtools\Keil\ARM\RV30\LIB\Luminary\driverlib.lib><driverlib.lib> 0x44F892D1 \r
+File 3,1,<..\..\Source\tasks.c><tasks.c> 0x44F303D7 \r
+File 3,1,<..\..\Source\list.c><list.c> 0x44F303E1 \r
+File 3,1,<..\..\Source\queue.c><queue.c> 0x44F303E0 \r
+File 3,1,<..\..\Source\portable\RVDS\ARM_CM3\port.c><port.c> 0x44F30423 \r
+File 4,5,<.\readme.txt><readme.txt> 0x44FC00DA \r
+\r
+\r
+Options 1,0,0 // Target 'FreeRTOS_Demo'\r
+ Device (LM3S811)\r
+ Vendor (Luminary Micro)\r
+ Cpu (IRAM(0x20000000-0x20001fff) IROM(0-0xffff) CLOCK(50000000) CPUTYPE("Cortex-M3"))\r
+ FlashUt ()\r
+ StupF ("STARTUP\Luminary\Startup.s" ("Luminary Startup Code"))\r
+ FlashDR (LMIDK-AGDI(-U40296420 -O7 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_8 -FS00 -FL02000))\r
+ DevID (4079)\r
+ Rgf (LM3Sxxx.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿLuminary\)\r
+ OrgReg (ÿLuminary\)\r
+ TgStat=16\r
+ OutDir (.\rvmdk\)\r
+ OutName (RTOSDemo)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=0\r
+ Debug=1\r
+ Browse=1\r
+ LstDir (.\rvmdk\)\r
+ HexSel=1\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ SVCSID <>\r
+ GLFLAGS=1790\r
+ ADSFLGA { 16,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ACPUTYP (Cortex-M3)\r
+ ADSTFLGA { 0,12,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCMADSIRAM { 0,0,0,0,32,0,32,0,0 }\r
+ OCMADSIROM { 1,0,0,0,0,0,0,1,0 }\r
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }\r
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,32,0,0,0,0,0,0,0,0,0,0,0 }\r
+ RV_STAVEC ()\r
+ ADSCCFLG { 9,32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSCMISC ()\r
+ ADSCDEFN (RVDS_ARMCM3_LM3S102)\r
+ ADSCUDEF ()\r
+ ADSCINCD (.;./LuminaryCode;..\..\Source\portable\RVDS\ARM_CM3;..\..\Source\include;..\Common\include)\r
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSAMISC ()\r
+ ADSADEFN ()\r
+ ADSAUDEF ()\r
+ ADSAINCD ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ ADSLDTA (0x00000000)\r
+ ADSLDDA (0x20000000)\r
+ ADSLDSC ()\r
+ ADSLDIB ()\r
+ ADSLDIC ()\r
+ ADSLDMC (--entry Reset_Handler)\r
+ ADSLDIF ()\r
+ ADSLDDW ()\r
+ OPTDL (SARMCM3.DLL)()(DLM.DLL)(-pLM3S811)(SARMCM3.DLL)()(TLM.DLL)(-pLM3S811)\r
+ OPTDBG 48126,4,()()()()()()()()()() (BIN\lmidk-agdi.dll)()()()\r
+ FLASH1 { 1,0,0,0,1,0,0,0,3,0,0,0,0,0,0,0,0,0,0,0 }\r
+ FLASH2 (BIN\LMIDK-AGDI.DLL)\r
+ FLASH3 ("" ())\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section \r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ See http://www.FreeRTOS.org for documentation, latest information, license \r
+ and contact details. Please ensure to read the configuration and relevant \r
+ port sections of the online documentation.\r
+ ***************************************************************************\r
+*/\r
+\r
+\r
+/*\r
+ * This project contains an application demonstrating the use of the \r
+ * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval\r
+ * board. See http://www.FreeRTOS.org for more information.\r
+ *\r
+ * main() simply sets up the hardware, creates all the demo application tasks, \r
+ * then starts the scheduler. http://www.freertos.org/a00102.html provides\r
+ * more information on the standard demo tasks. \r
+ *\r
+ * In addition to a subset of the standard demo application tasks, main.c also\r
+ * defines the following tasks: \r
+ *\r
+ * + A 'Print' task. The print task is the only task permitted to access the\r
+ * LCD - thus ensuring mutual exclusion and consistent access to the resource.\r
+ * Other tasks do not access the LCD directly, but instead send the text they\r
+ * wish to display to the print task. The print task spends most of its time\r
+ * blocked - only waking when a message is queued for display.\r
+ *\r
+ * + A 'Button handler' task. The eval board contains a user push button that\r
+ * is configured to generate interrupts. The interrupt handler uses a \r
+ * semaphore to wake the button handler task - demonstrating how the priority \r
+ * mechanism can be used to defer interrupt processing to the task level. The\r
+ * button handler task sends a message both to the LCD (via the print task) and\r
+ * the UART where it can be viewed using a dumb terminal (via the UART to USB\r
+ * converter on the eval board). NOTES: The dumb terminal must be closed in \r
+ * order to reflash the microcontroller. A very basic interrupt driven UART\r
+ * driver is used that does not use the FIFO. 19200 baud is used.\r
+ *\r
+ * + A 'check' task. The check task only executes every five seconds but has a\r
+ * high priority so is guaranteed to get processor time. Its function is to\r
+ * check that all the other tasks are still operational and that no errors have\r
+ * been detected at any time. If no errors have every been detected 'PASS' is\r
+ * written to the display (via the print task) - if an error has ever been\r
+ * detected the message is changed to 'FAIL'. The position of the message is\r
+ * changed for each write.\r
+ */\r
+\r
+\r
+\r
+/* Environment includes. */\r
+#include "DriverLib.h"\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "BlockQ.h"\r
+\r
+/* Delay between cycles of the 'check' task. */\r
+#define mainCHECK_DELAY ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* UART configuration - note this does not use the FIFO so is not very \r
+efficient. */\r
+#define mainBAUD_RATE ( 19200 )\r
+#define mainFIFO_SET ( 0x10 )\r
+\r
+/* Demo task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/* Demo board specifics. */\r
+#define mainPUSH_BUTTON GPIO_PIN_4\r
+\r
+/* Misc. */\r
+#define mainQUEUE_SIZE ( 3 )\r
+#define mainDEBOUNCE_DELAY ( ( portTickType ) 150 / portTICK_RATE_MS )\r
+#define mainNO_DELAY ( ( portTickType ) 0 )\r
+/*\r
+ * Configure the processor and peripherals for this demo. \r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The 'check' task, as described at the top of this file.\r
+ */\r
+static void vCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that is woken by the ISR that processes GPIO interrupts originating\r
+ * from the push button.\r
+ */\r
+static void vButtonHandlerTask( void *pvParameters );\r
+\r
+/*\r
+ * The task that controls access to the LCD.\r
+ */\r
+static void vPrintTask( void *pvParameter );\r
+\r
+/* String that is transmitted on the UART. */\r
+static portCHAR *cMessage = "Task woken by button interrupt! --- ";\r
+static volatile portCHAR *pcNextChar;\r
+\r
+/* The semaphore used to wake the button handler task from within the GPIO\r
+interrupt handler. */\r
+xSemaphoreHandle xButtonSemaphore;\r
+\r
+/* The queue used to send strings to the print task for display on the LCD. */\r
+xQueueHandle xPrintQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Configure the clocks, UART and GPIO. */\r
+ prvSetupHardware();\r
+\r
+ /* Create the semaphore used to wake the button handler task from the GPIO\r
+ ISR. */\r
+ vSemaphoreCreateBinary( xButtonSemaphore );\r
+ xSemaphoreTake( xButtonSemaphore, 0 );\r
+\r
+ /* Create the queue used to pass message to vPrintTask. */\r
+ xPrintQueue = xQueueCreate( mainQUEUE_SIZE, sizeof( portCHAR * ) );\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the tasks defined within the file. */\r
+ xTaskCreate( vCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+ xTaskCreate( vButtonHandlerTask, "Status", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY + 1, NULL );\r
+ xTaskCreate( vPrintTask, "Print", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY - 1, NULL );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient heap to start the \r
+ scheduler. */\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vCheckTask( void *pvParameters )\r
+{\r
+portBASE_TYPE xErrorOccurred = pdFALSE;\r
+portTickType xLastExecutionTime;\r
+const portCHAR *pcPassMessage = "PASS";\r
+const portCHAR *pcFailMessage = "FAIL";\r
+\r
+ /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil()\r
+ works correctly. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Perform this check every mainCHECK_DELAY milliseconds. */\r
+ vTaskDelayUntil( &xLastExecutionTime, mainCHECK_DELAY );\r
+\r
+ /* Has an error been found in any task? */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ \r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ \r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Send either a pass or fail message. If an error is found it is\r
+ never cleared again. We do not write directly to the LCD, but instead\r
+ queue a message for display by the print task. */\r
+ if( xErrorOccurred == pdTRUE )\r
+ {\r
+ xQueueSend( xPrintQueue, &pcFailMessage, portMAX_DELAY );\r
+ }\r
+ else\r
+ {\r
+ xQueueSend( xPrintQueue, &pcPassMessage, portMAX_DELAY );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ /* Setup the PLL. */\r
+ SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+\r
+ /* Setup the push button. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);\r
+ GPIODirModeSet(GPIO_PORTC_BASE, mainPUSH_BUTTON, GPIO_DIR_MODE_IN);\r
+ GPIOIntTypeSet( GPIO_PORTC_BASE, mainPUSH_BUTTON,GPIO_FALLING_EDGE );\r
+ GPIOPinIntEnable( GPIO_PORTC_BASE, mainPUSH_BUTTON );\r
+ IntEnable( INT_GPIOC );\r
+\r
+\r
+\r
+ /* Enable the UART. */\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+ /* Set GPIO A0 and A1 as peripheral function. They are used to output the\r
+ UART signals. */\r
+ GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+ /* Configure the UART for 8-N-1 operation. */\r
+ UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+ /* We don't want to use the fifo. This is for test purposes to generate\r
+ as many interrupts as possible. */\r
+ HWREG( UART0_BASE + UART_O_LCR_H ) &= ~mainFIFO_SET;\r
+\r
+ /* Enable Tx interrupts. */\r
+ HWREG( UART0_BASE + UART_O_IM ) |= UART_INT_TX;\r
+ IntEnable( INT_UART0 );\r
+\r
+\r
+ /* Initialise the LCD> */\r
+ OSRAMInit( false );\r
+ OSRAMStringDraw("www.FreeRTOS.org", 0, 0);\r
+ OSRAMStringDraw("LM3S811 demo", 16, 1);\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vButtonHandlerTask( void *pvParameters )\r
+{\r
+const portCHAR *pcInterruptMessage = "Int";\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a GPIO interrupt to wake this task. */\r
+ while( xSemaphoreTake( xButtonSemaphore, portMAX_DELAY ) != pdPASS );\r
+\r
+ /* Start the Tx of the message on the UART. */\r
+ UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+ {\r
+ pcNextChar = cMessage;\r
+\r
+ /* Send the first character. */\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;\r
+ }\r
+\r
+ pcNextChar++;\r
+ }\r
+ UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+ /* Queue a message for the print task to display on the LCD. */\r
+ xQueueSend( xPrintQueue, &pcInterruptMessage, portMAX_DELAY );\r
+\r
+ /* Make sure we don't process bounces. */\r
+ vTaskDelay( mainDEBOUNCE_DELAY );\r
+ xSemaphoreTake( xButtonSemaphore, mainNO_DELAY );\r
+ }\r
+}\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR(void)\r
+{\r
+unsigned portLONG ulStatus;\r
+\r
+ /* What caused the interrupt. */\r
+ ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+ /* Clear the interrupt. */\r
+ UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+ /* Was a Tx interrupt pending? */\r
+ if( ulStatus & UART_INT_TX )\r
+ {\r
+ /* Send the next character in the string. We are not using the FIFO. */\r
+ if( *pcNextChar != NULL )\r
+ {\r
+ if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+ {\r
+ HWREG( UART0_BASE + UART_O_DR ) = *pcNextChar;\r
+ }\r
+ pcNextChar++;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vGPIO_ISR( void )\r
+{\r
+ /* Clear the interrupt. */\r
+ GPIOPinIntClear(GPIO_PORTC_BASE, mainPUSH_BUTTON);\r
+\r
+ /* Wake the button handler task. */\r
+ if( xSemaphoreGiveFromISR( xButtonSemaphore, pdFALSE ) )\r
+ {\r
+ portEND_SWITCHING_ISR( pdTRUE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPrintTask( void *pvParameters )\r
+{\r
+portCHAR *pcMessage;\r
+unsigned portBASE_TYPE uxLine = 0, uxRow = 0;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait for a message to arrive. */\r
+ xQueueReceive( xPrintQueue, &pcMessage, portMAX_DELAY );\r
+\r
+ /* Write the message to the LCD. */\r
+ uxRow++;\r
+ uxLine++;\r
+ OSRAMClear();\r
+ OSRAMStringDraw( pcMessage, uxLine & 0x3f, uxRow & 0x01);\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ * This project contains an application demonstrating the use of the \r
+ * FreeRTOS.org mini real time scheduler on the Luminary Micro LM3S811 Eval\r
+ * board. See http://www.FreeRTOS.org for more information.\r
+ *\r
+ * main() simply sets up the hardware, creates all the demo application tasks, \r
+ * then starts the scheduler. http://www.freertos.org/a00102.html provides\r
+ * more information on the standard demo tasks. \r
+ *\r
+ * In addition to a subset of the standard demo application tasks, main.c also\r
+ * defines the following tasks: \r
+ *\r
+ * + A 'Print' task. The print task is the only task permitted to access the\r
+ * LCD - thus ensuring mutual exclusion and consistent access to the resource.\r
+ * Other tasks do not access the LCD directly, but instead send the text they\r
+ * wish to display to the print task. The print task spends most of its time\r
+ * blocked - only waking when a message is queued for display.\r
+ *\r
+ * + A 'Button handler' task. The eval board contains a user push button that\r
+ * is configured to generate interrupts. The interrupt handler uses a \r
+ * semaphore to wake the button handler task - demonstrating how the priority \r
+ * mechanism can be used to defer interrupt processing to the task level. The\r
+ * button handler task sends a message both to the LCD (via the print task) and\r
+ * the UART where it can be viewed using a dumb terminal (via the UART to USB\r
+ * converter on the eval board). NOTES: The dumb terminal must be closed in \r
+ * order to reflash the microcontroller. A very basic interrupt driven UART\r
+ * driver is used that does not use the FIFO. 19200 baud is used.\r
+ *\r
+ * + A 'check' task. The check task only executes every five seconds but has a\r
+ * high priority so is guaranteed to get processor time. Its function is to\r
+ * check that all the other tasks are still operational and that no errors have\r
+ * been detected at any time. If no errors have every been detected 'PASS' is\r
+ * written to the display (via the print task) - if an error has ever been\r
+ * detected the message is changed to 'FAIL'. The position of the message is\r
+ * changed for each write.\r
+ */
\ No newline at end of file
--- /dev/null
+; <<< Use Configuration Wizard in Context Menu >>>\r
+;******************************************************************************\r
+;\r
+; startup_rvmdk.S - Startup code for Stellaris.\r
+;\r
+; Copyright (c) 2006 Luminary Micro, Inc. All rights reserved.\r
+;\r
+; Software License Agreement\r
+;\r
+; Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+; exclusively on LMI's Stellaris Family of microcontroller products.\r
+;\r
+; The software is owned by LMI and/or its suppliers, and is protected under\r
+; applicable copyright laws. All rights are reserved. Any use in violation of\r
+; the foregoing restrictions may subject the user to criminal sanctions under\r
+; applicable laws, as well as to civil liability for the breach of the terms\r
+; and conditions of this license.\r
+;\r
+; THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+;\r
+; This is part of revision 816 of the Stellaris Driver Library.\r
+;\r
+;******************************************************************************\r
+\r
+;******************************************************************************\r
+;\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+;\r
+;******************************************************************************\r
+Stack EQU 0x00000100\r
+\r
+;******************************************************************************\r
+;\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+;\r
+;******************************************************************************\r
+Heap EQU 0x00000000\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the stack.\r
+;\r
+;******************************************************************************\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+StackMem\r
+ SPACE Stack\r
+\r
+;******************************************************************************\r
+;\r
+; Allocate space for the heap.\r
+;\r
+;******************************************************************************\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+HeapMem\r
+ SPACE Heap\r
+\r
+;******************************************************************************\r
+;\r
+; Indicate that the code in this file preserves 8-byte alignment of the stack.\r
+;\r
+;******************************************************************************\r
+ PRESERVE8\r
+\r
+;******************************************************************************\r
+;\r
+; Place code into the reset code section.\r
+;\r
+;******************************************************************************\r
+ AREA RESET, CODE, READONLY\r
+ THUMB\r
+\r
+;******************************************************************************\r
+;\r
+; The vector table.\r
+;\r
+;******************************************************************************\r
+Vectors\r
+ DCD StackMem + Stack ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NmiSR ; NMI Handler\r
+ DCD FaultISR ; Hard Fault Handler\r
+ DCD IntDefaultHandler ; MPU Fault Handler\r
+ DCD IntDefaultHandler ; Bus Fault Handler\r
+ DCD IntDefaultHandler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD IntDefaultHandler ; SVCall Handler\r
+ DCD IntDefaultHandler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD xPortPendSVHandler ; PendSV Handler\r
+ DCD xPortSysTickHandler ; SysTick Handler\r
+ DCD IntDefaultHandler ; GPIO Port A\r
+ DCD IntDefaultHandler ; GPIO Port B\r
+ DCD vGPIO_ISR ; GPIO Port C\r
+ DCD IntDefaultHandler ; GPIO Port D\r
+ DCD IntDefaultHandler ; GPIO Port E\r
+ DCD vUART_ISR ; UART0\r
+ DCD IntDefaultHandler ; UART1\r
+ DCD IntDefaultHandler ; SSI\r
+ DCD IntDefaultHandler ; I2C\r
+ DCD IntDefaultHandler ; PWM Fault\r
+ DCD IntDefaultHandler ; PWM Generator 0\r
+ DCD IntDefaultHandler ; PWM Generator 1\r
+ DCD IntDefaultHandler ; PWM Generator 2\r
+ DCD IntDefaultHandler ; Quadrature Encoder\r
+ DCD IntDefaultHandler ; ADC Sequence 0\r
+ DCD IntDefaultHandler ; ADC Sequence 1\r
+ DCD IntDefaultHandler ; ADC Sequence 2\r
+ DCD IntDefaultHandler ; ADC Sequence 3\r
+ DCD IntDefaultHandler ; Watchdog\r
+ DCD IntDefaultHandler ; Timer 0A\r
+ DCD IntDefaultHandler ; Timer 0B\r
+ DCD IntDefaultHandler ; Timer 1A\r
+ DCD IntDefaultHandler ; Timer 1B\r
+ DCD IntDefaultHandler ; Timer 2A\r
+ DCD IntDefaultHandler ; Timer 2B\r
+ DCD IntDefaultHandler ; Comp 0\r
+ DCD IntDefaultHandler ; Comp 1\r
+ DCD IntDefaultHandler ; Comp 2\r
+ DCD IntDefaultHandler ; System Control\r
+ DCD IntDefaultHandler ; Flash Control\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor first starts execution\r
+; following a reset event.\r
+;\r
+;******************************************************************************\r
+ EXPORT Reset_Handler\r
+Reset_Handler\r
+ ;\r
+ ; Call __main() in the C library, which will call the application\r
+ ; supplied main().\r
+ ;\r
+ IMPORT __main\r
+ IMPORT vGPIO_ISR\r
+ IMPORT vUART_ISR\r
+ IMPORT xPortPendSVHandler\r
+ IMPORT xPortSysTickHandler\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a NMI. This\r
+; simply enters an infinite loop, preserving the system state for examination\r
+; by a debugger.\r
+;\r
+;******************************************************************************\r
+NmiSR\r
+ B NmiSR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives a fault\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+FaultISR\r
+ B FaultISR\r
+\r
+;******************************************************************************\r
+;\r
+; This is the code that gets called when the processor receives an unexpected\r
+; interrupt. This simply enters an infinite loop, preserving the system state\r
+; for examination by a debugger.\r
+;\r
+;******************************************************************************\r
+IntDefaultHandler\r
+ B IntDefaultHandler\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Some code in the normal code section for initializing the heap and stack.\r
+;\r
+;******************************************************************************\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;******************************************************************************\r
+;\r
+; The function expected of the C library startup code for defining the stack\r
+; and heap memory locations.\r
+;\r
+;******************************************************************************\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+ LDR R0, =HeapMem\r
+ LDR R1, =(StackMem + Stack)\r
+ LDR R2, =(HeapMem + Heap)\r
+ LDR R3, =StackMem\r
+ BX LR\r
+\r
+;******************************************************************************\r
+;\r
+; Make sure the end of this section is aligned.\r
+;\r
+;******************************************************************************\r
+ ALIGN\r
+\r
+;******************************************************************************\r
+;\r
+; Tell the assembler that we're done.\r
+;\r
+;******************************************************************************\r
+ END\r
projects / freertos / commitdiff