--- /dev/null
+S0030000FC\r
+S3210000000020003FFC00000A5200000CD600000CD600000CD600000CD600000CD6BD\r
+S3210000001C00000CD600000CD600000CD600000CD600000CD600000CD600000CD694\r
+S3210000003800000CD600000CD600000CD600000CD600000CD600000CD600000CD678\r
+S3210000005400000CD600000CD600000CD600000CD600000CD600000CD600000CD65C\r
+S3210000007000000CD600000CD600000CD600000CD600000CD600000CD600000CD640\r
+S3210000008C00000CD600000CD600000CD600000CD600000CD600000CD600000CD624\r
+S321000000A800000CD600000CD600000CD600000CD600000CD600000CD600000CD608\r
+S321000000C400000CD600000CD600000CD600000CD600000CD600000CD600000CD6EC\r
+S321000000E000000CD600000CD600000CD600000CD600000CD600000CD600000CD6D0\r
+S321000000FC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6B4\r
+S3210000011800000CD600000CD600000CD600000CD600000CD600000CD600000CD697\r
+S3210000013400000CD600000CD600000CD600000CD600000CD600000CD600000CD67B\r
+S3210000015000000CD600000CD600000CD600000CD600000CD600000CD600000CD65F\r
+S3210000016C00000CD600000CD600000CD600000CD600000CD600000CD600000CD643\r
+S3210000018800000CD600000CD600000CD600000CD600000CD600000CD600000CD627\r
+S321000001A400000CD600000CD600000CD600000CD600000CD600000CD600000CD60B\r
+S321000001C000000CD600000CD600000CD600000CD600000CD600000CD600000CD6EF\r
+S321000001DC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6D3\r
+S321000001F800000CD600000CD600000CD600000CD600000CD600000CD600000CD6B7\r
+S3210000021400000CD600000CD600000CD600000CD600000CD600000CD600000CD69A\r
+S3210000023000000CD600000CD600000CD600000CD600000CD600000CD600000CD67E\r
+S3210000024C00000CD600000CD600000CD600000CD600000CD600000CD600000CD662\r
+S3210000026800000CD600000CD600000CD600000CD600000CD600000CD600000CD646\r
+S3210000028400000CD600000CD600000CD600000CD600000CD600000CD600000CD62A\r
+S321000002A000000CD600000CD600000CD600000CD600000CD600000CD600000CD60E\r
+S321000002BC00000CD600000CD600000CD600000CD600000CD600000CD600000CD6F2\r
+S321000002D800000CD600000CD600000CD600000CD600000CD600000CD600000CD6D6\r
+S321000002F400000CD600000CD600000CD600000CD600000CD600000CD600000CD6BA\r
+S3210000031000000CD600000CD600000CD600000CD600000CD600000CD600000CD69D\r
+S3210000032C00000CD600000CD600000CD600000CD600000CD600000CD600000CD681\r
+S3210000034800000CD600000CD600000CD600000CD600000CD600000CD600000CD665\r
+S3210000036400000CD600000CD600000CD600000CD600000CD600000CD600000CD649\r
+S3210000038000000CD600000CD600000CD600000CD600000CD600000CD600000CD62D\r
+S3210000039C00000CD600000CD600000CD600000CD600000CD600000CD600000CD611\r
+S321000003B800000CD600000CD600000CD600000CD600000CD600000CD600000CD6F5\r
+S321000003D400000CD600000CD600000CD600000CD600000CD600000CD600000CD6D9\r
+S315000003F000000CD600000CD600000CD600000CD66F\r
+S31D00000400000000000000000000000000000000000000000000000000DE\r
+S321000005004E5600004FEFFFE84EB9000006CE42974EB90000140670012E804EB915\r
+S3210000051C0000250A70022E804EB900001B9242974EB9000014CE4EB900001D3A9A\r
+S321000005384EB90000221E70022E804EB900000F1042AF001442AF001041F92000B4\r
+S3210000055404042F48000A303C00A03F40000841F9000041302F4800042EBC000059\r
+S3210000057006F24EB900002FB042AF001442AF001041F9200004082F48000A303C32\r
+S3210000058C00A03F40000841F9000041352F4800042EBC000007EA4EB900002FB03A\r
+S321000005A842AF001470032F40001042AF000A303C00A03F40000841F90000413AF7\r
+S321000005C42F4800042EBC000005EA4EB900002FB070022E804EB90000124C4EB94F\r
+S321000005E00000358C51FC6000FFFC4E5600004FEFFFE448EF00F0000C2E3C00002E\r
+S321000005FC01F47C007A0078004EB9000037182D40FFEC2F47000441EEFFEC2E8882\r
+S321000006184EB9000031884EB900001B347201B08157C049C044804A80660408C620\r
+S3210000063400004EB9000021E47201B081670408C600014EB9000011CE7201B08130\r
+S32100000650670408C600024EB90000277C7201B081670408C600054EB900001D0E8F\r
+S3210000066C7201B081670408C600064EB9000013AA7201B081670408C600074EB9DA\r
+S32100000688000024867201B081670408C60009BAB920000404660408C6000CB8B970\r
+S321000006A420000408660408C6000C2A39200004042839200004084A8667027E32C3\r
+S321000006C070032E804EB900000EBC6000FF424E560000598F70042E804EB90000D0\r
+S321000006DC3FDC4EB900000EA04E5E4E754E56000051FC6000FFFC4E560000226E3D\r
+S321000006F8000841F9200004042008B3C0670651FC6000FFFC7001720274037604F0\r
+S3210000071478057A067C077E08207C00000009227C0000000A247C0000000B267C23\r
+S321000007300000000C287C0000000D2A7C0000000E2C7C0000000F0C8000000001F2\r
+S3210000074C660000960C81000000026600008C0C8200000003660000820C83000006\r
+S32100000768000466780C840000000566700C850000000666680C860000000766605E\r
+S321000007840C8700000008665820080C8000000009664E20090C800000000A664420\r
+S321000007A0200A0C800000000B663A200B0C800000000C6630200C0C800000000DB8\r
+S321000007BC6626200D0C800000000E661C200E0C800000000F661220392000040484\r
+S321000007D8528023C0200004046000FF2A60FE4E5E4E754E560000226E000841F956\r
+S321000007F4200004082008B3C0670651FC6000FFFC700A7214741E762878327A3C77\r
+S321000008107C467E50207C0000005A227C00000064247C0000006E267C0000007816\r
+S3210000082C287C000000822A7C0000008C2C7C000000960C800000000A6600009682\r
+S321000008480C81000000146600008C0C820000001E660000820C83000000286678D2\r
+S321000008640C840000003266700C850000003C66680C860000004666600C8700000E\r
+S321000008800050665820080C800000005A664E20090C80000000646644200A0C800D\r
+S3210000089C0000006E663A200B0C80000000786630200C0C80000000826626200D74\r
+S321000008B80C800000008C661C200E0C80000000966612203920000404528023C086\r
+S321000008D4200004086000FF2A60FE4E5E4E754E56000051FC6000FFFC4E56000090\r
+S321000008F0700513C040120008303C300733C04012000010394012000208000003B4\r
+S3210000090C67F44E5E4E754E560000203C400000000280C0000000528023C0400088\r
+S321000009280000203C000000000280FFF800000680000000614E7B0C04203C02DCDE\r
+S321000009446C0023C04012000C4EB9000008EC41F92000000020080280FFFF0000E7\r
+S3210000096008C0000923C0400000084EB900000D064E5E4E754E5600004E5E4E75DD\r
+S3210000097C4E5600004E5E4E754E5600002F0C2F0B2209B1C1670C600210D92200B0\r
+S3210000099853804A8166F6265F285F4E5E4E754E5600002F0C49F9000042304A9457\r
+S321000009B4671A202C000822142241222C000420414EB900000984508C588C60E26A\r
+S321000009D04AAC000466E04AAC000866DA285F4E5E4E754E5600002F0C7220B081EF\r
+S321000009EC6514240844827203C481671690824218538266FA600C4A806746421869\r
+S32100000A08538066FA603E2400EA8A671C22482202EB89D1C14299429942994299E0\r
+S32100000A244299429942994299538266EC721F2400C481E48A670C224841F02C007B\r
+S32100000A404299538266FA7203C08160B6285F4E5E4E7546FC27004FF920003FFCB6\r
+S32100000A5C203C200000214E7B0C054EB9000009124FF9200026042C7C00000000A5\r
+S32100000A784E5600004BF92000041841F92000060443F92000041891C92008670C67\r
+S32100000A9441F9200004184EB9000009E241F92000041843F92000041891C9200868\r
+S32100000AB0670C41F9200004184EB9000009E241F900004230200867064EB9000001\r
+S32100000ACC09A64EB90000097C4EB900000974487A001C42A74EB900000500508F97\r
+S32100000AE84E5E42A74EB9000008E2588F4AFC4E75000000004E5600002F074FEF5E\r
+S32100000B04FFE8206E00082D50FFF83D680002FFE63D50FFE47200322EFFE4700CB1\r
+S32100000B20E0A12E3C000000FFC2872D41FFEC7400342EFFE4028200000C00E0827C\r
+S32100000B3C7200322EFFE47003C28084812D42FFF07000302EFFE4E480C0872D4001\r
+S32100000B58FFE82D680004FFF4222EFFEC7004B28067147005B280670E7006B280E8\r
+S32100000B7467087007B28067024E71222EFFE8703FB280620001307002B28065006B\r
+S32100000B9001285581323B1A0848C14EFB1A00003F005C0076008C008C008C00781C\r
+S32100000BAC007A007C007E0080008C00820084008C008C008C008C008C008C008CCD\r
+S32100000BC8008C00860088008800880088008800880088008A008A008A008A008A8F\r
+S32100000BE4008A008A008A008A008A008A008A008A008A008A008A008C008C008C5D\r
+S32100000C00008C008C008C008C008C008C008C008C008C008C008C008C008C4E71F7\r
+S32100000C1C222EFFF07004B28067147008B28067147009B2806714700CB2806714E2\r
+S32100000C3860164E716000008E4E71600000884E71600000824E71607C4E716078FD\r
+S32100000C544E71222EFFF07004B28067147008B28067127009B2806710700CB2806C\r
+S32100000C70670E60104E7160544E7160504E71604C4E7160484E7160444E71604007\r
+S32100000C8C4E71603C4E7160384E7160344E7160304E71602C4E7160284E7160241D\r
+S32100000CA84E7160204E71601C4E7160184E716014222EFFE87040B28065080C8133\r
+S32100000CC4000000C063024E714FEF00182E1F4E5E4E754E5600004FEFFFEC48D72C\r
+S32100000CE00307486F00184EB900000AFC4CEF030700044FEF00184E5E4E73202FB1\r
+S32100000CFC00044E7B08014E714E754E560000598F43F92000000041F9000000005C\r
+S32100000D182008B3C067227200601643F92000000041F90000000020301C00238008\r
+S32100000D341C0052810C810000010065E22EBC200000004EB900000CFA4E5E4E7553\r
+S32100000D504E5600004FEFFFF448D71C00206E0008266E000C222E001024484A889D\r
+S32100000D6C67244A8B67204A816F1C101349C057C049C044804A80660C20015381E7\r
+S32100000D884A806F0414DB60E642124CD71C004E5E4E754E5600004FEFFFF448D7E1\r
+S32100000DA41C00206E0008266E000C222E001024484A8867144A8B67104A81670C38\r
+S32100000DC0600214DB200153814A8066F64CD71C004E5E4E754E5600002F0C206E8A\r
+S32100000DDC0008242E000C222E001022484A8867104A81670C600212C22001538113\r
+S32100000DF84A8066F6285F4E5E4E754E560000226E0008206E000C242E00104A89B2\r
+S32100000E1467284A8867244A82672060107000101172001210B08166165289528886\r
+S32100000E3053827200121170001010B28067E27000600290814E5E4E754E56000035\r
+S32100000E4C700913C040000C77207C40000C08203CFF7FFFFFC190700813C04000D1\r
+S32100000E680C50207C40000C0C203CFFFEFFFEC190207C401500007000301008C008\r
+S32100000E8400023080303C050B33C040150000303C30D433C0401500024E5E4E75AD\r
+S32100000EA04E56000042394010006F700F13C04010002742394010000F4E5E4E7540\r
+S32100000EBC4E5600002F07222E00087004B2806502603C7E01E3AF4EB9000040A23F\r
+S32100000ED8700010394010000FC0876712207C4010000F700010104687C0871080F1\r
+S32100000EF4600E207C4010000F70001010808710804EB9000040D82E1F4E5E4E7571\r
+S32100000F104E5600004FEFFFDC48EF188000182E2E0008700C2E804EB900003F3413\r
+S32100000F2C264870022F40000470012E804EB9000028CA268870642740000441F911\r
+S32100000F482000041827480008700C2E804EB900003F342848289342AC000441F9D9\r
+S32100000F642000041E2948000842AF00142F4700102F4B000A303C00A03F4000080E\r
+S32100000F8041F9000041402F4800042EBC000011664EB900002FB042AF001442AFDC\r
+S32100000F9C00102F4C000A303C00A03F40000841F9000041482F4800042EBC0000E3\r
+S32100000FB811084EB900002FB0700C2E804EB900003F34284870022F4000047001AE\r
+S32100000FD42E804EB9000028CA288842AC000441F92000042029480008700C2E8091\r
+S32100000FF04EB900003F342648269470642740000441F92000041A2748000842AF1E\r
+S3210000100C001442AF00102F4C000A303C00A03F40000841F9000041502F4800044F\r
+S321000010282EBC000011664EB900002FB042AF00142F4700102F4B000A303C00A044\r
+S321000010443F40000841F9000041582F4800042EBC000011084EB900002FB0700C50\r
+S321000010602E804EB900003F34264870022F40000470052E804EB9000028CA268829\r
+S3210000107C70642740000441F92000042227480008700C2E804EB900003F34284808\r
+S32100001098289370642940000441F92000041C2948000842AF001442AF00102F4BC7\r
+S321000010B4000A303C00A03F40000841F9000041602F4800042EBC000011084EB91D\r
+S321000010D000002FB042AF001442AF00102F4C000A303C00A03F40000841F90000C7\r
+S321000010EC41682F4800042EBC000011664EB900002FB04CEF188000184E5E4E751D\r
+S321000011084E5600002F0C2F074FEFFFEC286E0008426EFFF47E0042AF000C2F6C30\r
+S321000011240004000841EEFFF42F4800042E944EB900002A907201B08157C049C0B9\r
+S3210000114044804A8066047E0160D4300748C0660A206C0008301052803080302E7F\r
+S3210000115CFFF452803D40FFF460B84E5600004FEFFFE048EF10C00014286E0008AA\r
+S321000011787C007E0042AF000C2F6C0004000841EEFFF02F4800042E944EB9000055\r
+S321000011942BFC7201B08156C049C044804A8066D87200322EFFF070003006B280EA\r
+S321000011B067083C2EFFF07E0160C2300748C0660A206C00083010528030805286D7\r
+S321000011CC60AE4E5600002F0770017200606641F9200004183E301A0048C741F929\r
+S321000011E82000042434301A0048C2BE826602700043F92000042441F92000041803\r
+S3210000120434301A0033821A0041F92000041E3E301A0048C741F92000042A34307C\r
+S321000012201A0048C2BE826602700043F92000042A41F92000041E34301A00338237\r
+S3210000123C1A0052817403B2826D942E1F4E5E4E754E5600002F074FEFFFE82E2EE0\r
+S32100001258000870042E804EB900003F34208742AF00142F4700102F48000A303CB1\r
+S3210000127400DC3F40000841F9000041702F4800042EBC000013124EB900002FB09A\r
+S321000012904EB90000373823C02000043452B9200004344FEF00182E1F4E5E4E7516\r
+S321000012AC4E5600002F0C4FEFFFF4206E00084A88674E285070022D40FFF87059DC\r
+S321000012C82D40FFF4222EFFF4202EFFF84C0108002D40FFF470142E804EB900002E\r
+S321000012E432524A8C57C049C044804A8066CE42974EB9000032522E8C4EB9000087\r
+S3210000130030F042974EB9000030F060B47000284060AE4E5600002F074FEFFFE8B2\r
+S3210000131C206E00082E102E884EB900003F9E70642E804EB90000325242B9200019\r
+S32100001338043C41F92000043C2F4800142F47001042AF000A303C00A03F4000081A\r
+S3210000135441F9000041782F4800042EBC000012AC4EB900002FB042AF00142F4700\r
+S32100001370001041F92000043C2F48000A303C00A03F40000841F9000041802F482B\r
+S3210000138C00042EBC000012AC4EB900002FB0303920000430528033C020000430D7\r
+S321000013A860804E5600002F077E01720032392000040C7000303920000430B2807E\r
+S321000013C466287E004EB90000373823C020000438B0B920000434652090B9200097\r
+S321000013E004347202B08163027E002007601230392000043033C02000040C60CC86\r
+S321000013FC7E0060EA2E1F4E5E4E754E5600002F072F064FEFFFE82C2E00087E0037\r
+S32100001418602C42AF00142F46001042AF000A303C00A03F40000841F9000041880B\r
+S321000014342F4800042EBC000014584EB900002FB052877003BE806DCE4FEF0018C4\r
+S321000014502C1F2E1F4E5E4E754E5600002F072F064FEFFFF44EB9000040A22C39E5\r
+S3210000146C2000044052B9200004404EB9000040D8200652802E3C0000014D4C0070\r
+S321000014887800700A4C407007E28F4EB9000037182D40FFF42F47000441EEFFF48A\r
+S321000014A42E884EB9000031882E864EB900000EBC2F47000441EEFFF42E884EB9D2\r
+S321000014C0000031882E864EB900000EBC60CE4E5600002F0C2F074FEFFFE82E2E08\r
+S321000014DC000870042F40000470052E804EB9000028CA42AF00142F4700102F48E1\r
+S321000014F8000A303C00A03F40000841F90000418D2F4800042EBC000015BA4EB9F2\r
+S3210000151400002FB04EB90000297A284842AF001442AF00102F4C000A303C00A025\r
+S321000015303F40000841F9000041922F4800042EBC000019B04EB900002FB041F9B7\r
+S3210000154C2000045C2F48001470022F40001042AF000A303C00A03F40000841F9B9\r
+S32100001568000041982F4800042EBC00001ABC4EB900002FB041F9200004602F4832\r
+S32100001584001470032F4000102F4C000A303C00A03F40000841F90000419E2F4897\r
+S321000015A000042EBC00001AD24EB900002FB04FEF00182E1F285F4E5E4E754E562C\r
+S321000015BC00002F0C4FEFFFE8286E000870012F40000C42AF000841F92000044884\r
+S321000015D82F4800042E8C4EB900002A902E8C4EB900002DC27201B08157C049C087\r
+S321000015F444804A80660623C12000044442AF000C42AF000841EEFFF82F480004F8\r
+S321000016102E8C4EB900002BFC7201B081670623C120000444202EFFF8B0B92000A5\r
+S3210000162C04486708700123C0200004442E8C4EB900002DC24A806708700123C0E8\r
+S321000016482000044442AF000C42AF000841F9200004482F4800042E8C4EB9000040\r
+S321000016642A902E8C4EB900002DC27201B081670623C12000044442AF000C42AFAF\r
+S32100001680000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000A2\r
+S3210000169C04442E8C4EB900002DC24A806708700123C020000444202EFFF8B0B991\r
+S321000016B8200004486708700123C02000044470022D40FFF8601C42AF000C42AF39\r
+S321000016D4000841EEFFF82F4800042E8C4EB900002A9052AEFFF87205B2AEFFF80B\r
+S321000016F062DC2E8C4EB900002DC27203B0816708700123C02000044470012D403B\r
+S3210000170CFFF82F40000C42AF000841EEFFF82F4800042E8C4EB900002A9042AE44\r
+S32100001728FFF870012F40000C42AF000841EEFFF82F4800042E8C4EB900002A90A7\r
+S321000017442E8C4EB900002DC27205B0816708700123C02000044470012F40000C14\r
+S3210000176042AF000841EEFFF82F4800042E8C4EB900002A904A806708700123C0C5\r
+S3210000177C2000044442AF000C42AF000841EEFFF82F4800042E8C4EB900002A90D1\r
+S321000017984A806708700123C02000044442AEFFF8607C70012F40000C42AF000892\r
+S321000017B441EEFFF42F4800042E8C4EB900002BFC7201B081670623C12000044431\r
+S321000017D0222EFFF8B2AEFFF46708700123C020000444202EFFF446802D40FFF4CB\r
+S321000017EC42AF000C42AF000841EEFFF42F4800042E8C4EB900002BFC7201B081BC\r
+S32100001808670623C120000444222EFFF8B2AEFFF46708700123C02000044452AE40\r
+S32100001824FFF87205B2AEFFF86200FF7C2E8C4EB900002DC24A806708700123C0C3\r
+S3210000184020000444700A2D40FFF842AF000C42AF000841EEFFF82F4800042E8CEF\r
+S3210000185C4EB900002A907201B081670623C120000444700B2D40FFF842AF000C70\r
+S3210000187842AF000841EEFFF82F4800042E8C4EB900002A907201B081670623C144\r
+S32100001894200004442E8C4EB900002DC27202B0816708700123C0200004447009D1\r
+S321000018B02D40FFF8602A70012F40000C42AF000841EEFFF82F4800042E8C4EB9E1\r
+S321000018CC00002A907201B081670623C12000044453AEFFF87207B2AEFFF863CEEA\r
+S321000018E82E8C4EB900002DC27205B0816708700123C02000044470012F40000C6F\r
+S3210000190442AF000841EEFFF82F4800042E8C4EB900002A904A806708700123C01F\r
+S321000019202000044442AF000C42AF000841EEFFF82F4800042E8C4EB900002A902B\r
+S3210000193C4A806708700123C02000044470072D40FFF8603A42AF000C42AF000829\r
+S3210000195841EEFFF42F4800042E8C4EB900002BFC7201B081670623C1200004448B\r
+S32100001974222EFFF8B2AEFFF46708700123C02000044452AEFFF8720CB2AEFFF8C0\r
+S3210000199062BE2E8C4EB900002DC24A806708700123C02000044452B920000448F9\r
+S321000019AC6000FC1A4E5600002F0C4FEFFFF0286E000842AF000C42AF000842AF12\r
+S321000019C800042E8C4EB900002BFC7201B08157C049C044804A80660623C120004F\r
+S321000019E4044442B92000045042974EB9000032E84A806708700123C0200004443B\r
+S32100001A002EB9200004604EB9000034F042974EB9000032E87203B08167087001AE\r
+S32100001A1C23C02000044470012F40000442974EB90000332042974EB9000032E84C\r
+S32100001A387203B0816708700123C0200004442EB92000045C4EB9000034F04AB926\r
+S32100001A54200004506708700123C02000044442AF000C42AF000842AF00042E8C2C\r
+S32100001A704EB900002A907201B081670623C1200004447001B0B92000045067067B\r
+S32100001A8C23C02000044442974EB9000032E87201B081670623C12000044442AFA5\r
+S32100001AA8000442974EB90000332052B92000044C6000FF044E560000598F4297A2\r
+S32100001AC44EB90000341A52B92000045060F04E5600002F0C4FEFFFF0286E000832\r
+S32100001AE042974EB90000341A42AF000C70FF2F40000842AF00042E8C4EB900001D\r
+S32100001AFC2BFC7201B08157C049C044804A80660623C12000044442AF000C42AFA9\r
+S32100001B18000842AF00042E8C4EB900002A907201B08167B423C12000044460AC1C\r
+S32100001B344E560000203920000454B0B9200004486734203920000458B0B920004C\r
+S32100001B50044C673020392000044823C02000045420392000044C23C02000045844\r
+S32100001B6C4AB92000044457C049C044806014700123C02000044460C2700123C062\r
+S32100001B882000044460C64E5E4E754E5600002F074FEFFFE82E2E000870022F40FA\r
+S32100001BA40004700A2E804EB9000028CA23C82000046C42AF00142F47001041F9BA\r
+S32100001BC02000046C2F48000A303C00A03F40000841F9000041A52F4800042EBCDA\r
+S32100001BDC00001C924EB900002FB042AF00142F47001041F92000046C2F48000A7D\r
+S32100001BF8303C00A03F40000841F9000041AD2F4800042EBC00001C204EB9000068\r
+S32100001C142FB04FEF00182E1F4E5E4E754E5600004FEFFFE048EF10C00014286E4B\r
+S32100001C300008426EFFF07E007C00604442AF000C42AF000841EEFFF02F480004BE\r
+S32100001C4C2E944EB900002A907201B08167047E0160204A8766124EB9000040A2B3\r
+S32100001C6852B9200004684EB9000040D8302EFFF052803D40FFF052867003BC8092\r
+S32100001C846DB670142E804EB90000325260A64E5600004FEFFFE048EF10C000147C\r
+S32100001CA0286E00087C007E00604C42AF000C42AF000841EEFFF02F4800042E948D\r
+S32100001CBC4EB900002BFC7201B081662E7200322EFFF070003006B28067087E0119\r
+S32100001CD83C2EFFF060164A8766124EB9000040A252B9200004644EB9000040D837\r
+S32100001CF452862E944EB900002DC24A8066A870122E804EB90000325260E84E56BF\r
+S32100001D1000004AB92000046467184AB9200004686710700142B92000046442B9B2\r
+S32100001D2C200004686004700060EE4E5E4E754E5600002F0C4FEFFFE870042F4091\r
+S32100001D48000470052E804EB9000028CA284842AF001442AF00102F4C000A303CF2\r
+S32100001D6400A03F40000841F9000041B52F4800042EBC0000208C4EB900002FB00F\r
+S32100001D8041F9200004842F48001470012F4000102F4C000A303C00A03F400008CC\r
+S32100001D9C41F9000041BB2F4800042EBC000020164EB900002FB041F92000048090\r
+S32100001DB82F48001470022F4000102F4C000A303C00A03F40000841F9000041C139\r
+S32100001DD42F4800042EBC00001F624EB900002FB041F92000047C2F480014700349\r
+S32100001DF02F4000102F4C000A303C00A03F40000841F9000041C82F4800042EBC92\r
+S32100001E0C00001E204EB900002FB04FEF0018285F4E5E4E754E5600002F0C4FEF27\r
+S32100001E28FFEC286E000870012F40000C70FF2F40000841EEFFF82F4800042E8CE2\r
+S32100001E444EB900002BFC7201B08157C049C044804A80660623C120000470223CBA\r
+S32100001E6011223344B2AEFFF86708700123C0200004702E8C4EB900002DC27201E5\r
+S32100001E7CB081670623C12000047042AEFFF842AF000C42AF000841EEFFF82F48B4\r
+S32100001E9800042E8C4EB900002BFC7201B081670623C120000470223C11223344AB\r
+S32100001EB4B2AEFFF86708700123C02000047070012F40000C70FF2F40000841EE5D\r
+S32100001ED0FFF82F4800042E8C4EB900002BFC7201B081670623C120000470223CAF\r
+S32100001EEC01234567B2AEFFF86708700123C0200004702E8C4EB900002DC2720133\r
+S32100001F08B081670623C12000047042974EB90000341A70012F40000C70FF2F40A9\r
+S32100001F24000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000F5\r
+S32100001F400470223CAABBAABBB2AEFFF86708700123C02000047042974EB9000055\r
+S32100001F5C341A6000FECE4E5600002F0C4FEFFFEC286E000870012F40000C70FFE8\r
+S32100001F782F40000841EEFFF82F4800042E8C4EB900002BFC7201B08157C049C083\r
+S32100001F9444804A80660623C120000470223C01234567B2AEFFF86708700123C071\r
+S32100001FB0200004702E8C4EB900002DC27201B081670623C12000047042974EB962\r
+S32100001FCC0000341A42AF000C70FF2F40000841EEFFF82F4800042E8C4EB9000060\r
+S32100001FE82BFC7201B081670623C120000470223CAABBAABBB2AEFFF867087001C8\r
+S3210000200423C02000047042974EB90000341A6000FF5C4E5600002F0C4FEFFFEC52\r
+S32100002020286E000870012F40000C70FF2F40000841EEFFF82F4800042E8C4EB9CC\r
+S3210000203C00002BFC7201B08157C049C044804A80660623C120000470223C0123A3\r
+S321000020584567B2AEFFF86708700123C0200004702E8C4EB900002DC27201B081B8\r
+S32100002074670623C12000047052B92000047442974EB90000341A60984E560000F8\r
+S321000020902F0C4FEFFFEC286E0008203C112233442D40FFF842AF000C42AF0008CC\r
+S321000020AC41EEFFF82F4800042E8C4EB900002A907201B08157C049C044804A80A4\r
+S321000020C8660623C1200004702E8C4EB900002DC24A806708700123C02000047041\r
+S321000020E4203C012345672D40FFF842AF000C42AF000841EEFFF82F4800042E8CF9\r
+S321000021004EB900002A907201B081670623C12000047042AEFFF842AF000C42AF9E\r
+S3210000211C000841EEFFF82F4800042E8C4EB900002BFC7201B081670623C12000FB\r
+S321000021380470700A2E804EB9000032522EB9200004844EB9000034F02EB920009D\r
+S3210000215404804EB9000034F02EB92000047C4EB9000034F0203CAABBAABB2D4075\r
+S32100002170FFF870012F40000C42AF000841EEFFF82F4800042E8C4EB900002A9055\r
+S3210000218C7201B081670623C12000047070012F40000C42AF000841EEFFF82F4826\r
+S321000021A800042E8C4EB900002BFC4A806708700123C0200004702EB9200004807D\r
+S321000021C44EB9000034F02EB92000047C4EB9000034F0700A2E804EB90000325269\r
+S321000021E06000FEB84E560000203920000478B0B920000474671A203920000474BB\r
+S321000021FC23C0200004784AB92000047057C049C04480600A700123C02000047075\r
+S3210000221860DC4E5E4E754E5600004FEFFFE84EB90000297A23C8200004B44A88F1\r
+S321000022346700009041F9200004AC2F48001470022F40001042AF000A303C00A004\r
+S321000022503F40000841F9000041CF2F4800042EBC000022CA4EB900002FB041F92A\r
+S3210000226C200004A82F48001470012F40001042AF000A303C00A03F40000841F941\r
+S32100002288000041D42F4800042EBC0000238C4EB900002FB042AF001442AF00101F\r
+S321000022A442AF000A303C00A03F40000841F9000041D92F4800042EBC0000241A93\r
+S321000022C04EB900002FB04E5E4E754E5600002F07518F2EB9200004B44EB9000027\r
+S321000022DC29F27201B08156C049C044804A80660623C1200004887E00602A7002FE\r
+S321000022F82F4000042EB9200004B44EB900002A3E7201B081670623C12000048882\r
+S3210000231470022E804EB9000032525287700ABE8065D07E00602470022E804EB90D\r
+S32100002330000032522EB9200004B44EB9000029F27201B081670623C12000048885\r
+S3210000234C5287700ABE8065D62EB9200004B44EB9000029F27201B081660623C1CE\r
+S321000023682000048852B920000494700123C02000048C42974EB90000341A42B9B7\r
+S321000023842000048C6000FF484E560000518F70FF2F4000042EB9200004B44EB9B4\r
+S321000023A000002A3E7201B08156C049C044804A806640B2B92000048C670823C14E\r
+S321000023BC2000048860362EB9200004B44EB9000029F27201B081670623C12000C7\r
+S321000023D80488700123C02000049042974EB90000341A42B920000490600623C128\r
+S321000023F4200004882039200004B05280B0B9200004946708700123C0200004888C\r
+S3210000241052B9200004B06000FF7A4E560000518F42AF00042EB9200004B44EB9B3\r
+S3210000242C00002A3E7201B08156C049C044804A8066E2B2B920000490670823C11B\r
+S321000024482000048860D252B9200004982EB9200004A84EB9000034F02EB92000E8\r
+S3210000246404AC4EB9000034F02EB9200004B44EB9000029F27201B08167A223C109\r
+S3210000248020000488609A4E56000020392000049CB0B92000049467502039200086\r
+S3210000249C049423C02000049C2039200004A0B0B9200004B067402039200004B0B5\r
+S321000024B823C0200004A02039200004A4B0B920000498673020392000049823C086\r
+S321000024D4200004A47001B0B92000048856C049C04480601E700123C02000048837\r
+S321000024F060B2700123C02000048860C2700123C02000048860D24E5E4E754E5651\r
+S3210000250C00002F0C2F074FEFFFE82E2E0008700C2E804EB900003F3428484A8CC9\r
+S321000025286700009E42AF000470012E804EB9000028CA28882014671442AF000C23\r
+S3210000254442AF000842AF00042E804EB900002A904A94677070042E804EB900003A\r
+S321000025603F3429480004206C000420BC000000FF42AC000842AF001442AF00100A\r
+S3210000257C2F4C000A303C00A03F40000841F9000041DE2F4800042EBC00002684BD\r
+S321000025984EB900002FB042AF001442AF00102F4C000A303C00A03F40000841F9E3\r
+S321000025B4000041E62F4800042EBC000026844EB900002FB0700C2E804EB90000B8\r
+S321000025D03F3428484A8C670000A042AF000470012E804EB9000028CA2888201438\r
+S321000025EC671442AF000C42AF000842AF00042E804EB900002A904A9467727004CD\r
+S321000026082E804EB900003F3429480004206C000420BC00000FFF700A29400008AE\r
+S3210000262442AF00142F4700102F4C000A303C00A03F40000841F9000041EE2F4811\r
+S3210000264000042EBC000026844EB900002FB042AF00142F4700102F4C000A303C7E\r
+S3210000265C00A03F40000841F9000041F62F4800042EBC000026844EB900002FB0CF\r
+S321000026784FEF00182E1F285F4E5E4E754E5600004FEFFFDC48EF18C00014286E31\r
+S3210000269400087C004EB9000040A23E39200004C03039200004C0528033C020002A\r
+S321000026B004C04EB9000040D8266C00044AAC0008670C203C00000FFF2D40FFEC5C\r
+S321000026CC600A203C000000FF2D40FFEC42AF000C2F6C0008000842AF00042E9470\r
+S321000026E84EB900002BFC7201B081666C202EFFECB09367027C017200600A268147\r
+S32100002704B29367027C015281B2AEFFEC63F042AF000C42AF000842AF00042E946A\r
+S321000027204EB900002A904A8066027C01300648C0661A320748C17004B2806C1005\r
+S3210000273C41F9200004B841F01A00301052803080700A4C2C080000082E804EB9A1\r
+S32100002758000032526000FF7A4AAC00086600FF72203C0001000023C040000C148D\r
+S321000027744E714E716000FF5E4E5600002F0770017E00603441F9200004C2343027\r
+S321000027907A0048C241F9200004B832307A0048C1B4816602700043F9200004C279\r
+S321000027AC41F9200004B832307A0033817A0052877204BE816DC62E1F4E5E4E756E\r
+S321000027C84E560000226E000841E900082348000470FF234000082348000C234856\r
+S321000027E4001042914E5E4E754E560000206E000842A800104E5E4E754E5600003A\r
+S321000028002F0C2F0B286E0008226E000C266C0004236B00040004236C0004000840\r
+S3210000281C206B0004214900082749000429490004234C00105294265F285F4E5E92\r
+S321000028384E754E5600002F0C2F0B266E0008226E000C221170FFB280673041EBD3\r
+S32100002854000860042068000428680004B29464F42368000400042869000429499E\r
+S3210000287000082348000821490004234B001052936006206B001060DC265F285FB1\r
+S3210000288C4E5E4E754E560000206E0008226800042368000800082268000823683B\r
+S321000028A80004000422680010B1E90004670842A800105391600823680008000482\r
+S321000028C460F04E5E4E754E5600004FEFFFF048EF10C000042C2E00082E2E000C8D\r
+S321000028E04A8666087000204060000086704C2E804EB900003F3428484A8C67E869\r
+S321000028FC20074C06080052802E804EB900003F3428882214675220074C0608001F\r
+S32100002918D0812940000442AC00382954000874FF2206D28220074C010800D09465\r
+S321000029342940000C2946003C29470040294200442942004841EC00102E884EB955\r
+S32100002950000027C841EC00242E884EB9000027C8204C600C2E8C4EB900003F9E03\r
+S3210000296C6000FF764CEF10C000044E5E4E754E5600002F0C4FEFFFF0704C2E8080\r
+S321000029884EB900003F3428484A8C675242AC0004429442AC000842AC000C42AC0E\r
+S321000029A4003870012940003C42AC004070FF294000442940004841EC00102E88D5\r
+S321000029C04EB9000027C841EC00242E884EB9000027C842AF000C42AF000842AF1B\r
+S321000029DC00042E8C4EB900002A90204C4FEF0010285F4E5E4E754E5600002F0CCB\r
+S321000029F84FEFFFF0286E00084EB900003DFAB1EC000467047000602453AC000CA9\r
+S32100002A144AAC000C67047001601642AF000C42AF000842AF00042E8C4EB90000A0\r
+S32100002A302A9060E64FEF0010285F4E5E4E754E5600002F0C2F074FEFFFF0286E68\r
+S32100002A4C00082E2E000C4EB900003DFAB1EC0004672042AF000C2F47000842AF26\r
+S32100002A6800042E8C4EB900002BFC7201B081660C52AC000C600652AC000C70015F\r
+S32100002A844FEF00102E1F285F4E5E4E754E5600004FEFFFDC48EF18C00014286E29\r
+S32100002AA00008266E000C2C2E00147E014AAE0010670000B64EB9000035E84EB92F\r
+S32100002ABC000040A270FFB0AC0044660442AC004470FFB0AC0048660442AC0048B8\r
+S32100002AD84EB9000040D87001BE80660C41EEFFE82E884EB900003B122E8C4EB9BB\r
+S32100002AF400002F804A80675E41EE00102F48000441EEFFE82E884EB900003B2E8C\r
+S32100002B104A8066362F6E0010000441EC00102E884EB9000039AA2E8C4EB90000EE\r
+S32100002B2C2EC64EB9000036024A806630203C0001000023C040000C144E714E71D6\r
+S32100002B48601E2E8C4EB900002EC64EB900003602600E2E8C4EB900002EC64EB9CF\r
+S32100002B64000036024EB9000040A2202C0038B0AC003C64442F4600082F4B00046F\r
+S32100002B802E8C4EB900002DE87E014AAC002457C049C044804A80662641EC002439\r
+S32100002B9C2E884EB900003A547201B0816614203C0001000023C040000C144E714F\r
+S32100002BB84E7160027E004EB9000040D84A8766204AAE0010671A41EE00102F48A7\r
+S32100002BD4000441EEFFE82E884EB900003B2E4A8066027EFF70FFBE806700FEBE20\r
+S32100002BF020074CEF18C000144E5E4E754E5600004FEFFFDC48EF1CC00010286E90\r
+S32100002C0C0008246E000C2C2E00147E014AAE0010670000D04EB9000035E84EB9A9\r
+S32100002C28000040A270FFB0AC0044660442AC004470FFB0AC0048660442AC00484A\r
+S32100002C444EB9000040D87001BE80660C41EEFFE42E884EB900003B122E8C4EB951\r
+S32100002C6000002F544A80677841EE00102F48000441EEFFE42E884EB900003B2E34\r
+S32100002C7C4A8066504A9466164EB9000040A22EAC00044EB900003E1A4EB900002F\r
+S32100002C9840D82F6E0010000441EC00242E884EB9000039AA2E8C4EB900002EC6AB\r
+S32100002CB44EB9000036024A806630203C0001000023C040000C144E714E71601EC3\r
+S32100002CD02E8C4EB900002EC64EB900003602600E2E8C4EB900002EC64EB90000C4\r
+S32100002CEC36024EB9000040A24AAC003867000088266C000C2F4A00042E8C4EB9AC\r
+S32100002D0800002E844A86664453AC00384A94660A4EB900003DFA294800044AAC4F\r
+S32100002D24001057C049C044804A80664E41EC00102E884EB900003A547201B081EF\r
+S32100002D40663C203C0001000023C040000C144E714E71602A294B000C4AAC00248D\r
+S32100002D5C672041EC00242E884EB900003A544A806710203C0001000023C0400071\r
+S32100002D780C144E714E717E0160027E004EB9000040D84A8766204AAE0010671A3D\r
+S32100002D9441EE00102F48000441EEFFE42E884EB900003B2E4A8066027EFF70FF0D\r
+S32100002DB0BE806700FE6420074CEF1CC000104E5E4E754E5600002F0C2F07286E92\r
+S32100002DCC00084EB9000040A22E2C00384EB9000040D820072E1F285F4E5E4E75D9\r
+S32100002DE84E5600002F0C4FEFFFF4286E0008206E000C222E0010202C0040661817\r
+S32100002E044A94660E2EAC00044EB900003EC242AC000452AC0038605E4A81662A34\r
+S32100002E202F4000082F4800042EAC00084EB900000D9A202C0040D1AC0008202CB1\r
+S32100002E3C0008B0AC000465D22954000860CC2F4000082F4800042EAC000C4EB945\r
+S32100002E5800000D9A202C004091AC000C202C000CB09464AA202C000490AC004066\r
+S32100002E742940000C609C4FEF000C285F4E5E4E754E5600004FEFFFF4226E00081E\r
+S32100002E90206E000C4A91672A20290040D1A9000C2029000CB0A90004650423517C\r
+S32100002EAC000C2F69004000082F69000C00042E884EB900000D9A4E5E4E754E56F9\r
+S32100002EC800002F0C598F286E00084EB9000040A2601A4AAC0024671A41EC0024D8\r
+S32100002EE42E884EB900003A544A80664C53AC00484AAC00486EE070FF2940004812\r
+S32100002F004EB9000040D84EB9000040A2601A4AAC0010671A41EC00102E884EB9AC\r
+S32100002F1C00003A544A80662053AC00444AAC00446EE070FF294000444EB90000C7\r
+S32100002F3840D860104EB900003BB260AC4EB900003BB260D8588F285F4E5E4E75E6\r
+S32100002F544E5600002F0C2F07286E00084EB9000040A24AAC003857C749C7448798\r
+S32100002F704EB9000040D820072E1F285F4E5E4E754E5600002F0C2F07286E000803\r
+S32100002F8C4EB9000040A2202C0038B0AC003C57C749C744874EB9000040D82007DF\r
+S32100002FA82E1F285F4E5E4E754E5600004FEFFFE048EF1CC0000C246E000C3C2EDC\r
+S32100002FC400102E2E0018266E001C3E864EB900003D6428484A8C670000D62F4752\r
+S32100002FE000082F4A00042E8C4EB900003BCE206C00307200320670FFD28041F028\r
+S32100002FFC1C002F6E001200082F6E000800042E884EB90000405828884EB900002B\r
+S3210000301840A252B9200004D47001B0B9200004D4660E23CC200004CC4EB9000085\r
+S321000030343C44601A4AB9200004E466122079200004CCBEA8002C650623CC200068\r
+S3210000305004CC202C002CB0B9200004DC630623C0200004DC2039200004F8294083\r
+S3210000306C004052B9200004F8202C002CB0B9200004E0630623C0200004E041EC79\r
+S3210000308800042F48000470144C2C0800002C41F92000057441F008002E884EB9AE\r
+S321000030A4000027FC7C014EB9000040D860027CFF7001BC80662A4A8B6702268C41\r
+S321000030C04AB9200004E4671C2079200004CCBEA8002C6310203C0001000023C092\r
+S321000030DC40000C144E714E7120064CEF1CC0000C4E5E4E754E5600002F0C2F0B23\r
+S321000030F8518F266E00084EB9000040A2B7F9200004CC6604700026404A8B57C085\r
+S3210000311449C044804A8067082879200004CC6002284B41EC00042E884EB900003F\r
+S3210000313028904AAC0028670C41EC00182E884EB900002890588C2F4C00042EBC2D\r
+S3210000314C2000051C4EB9000027FC52B9200004D04EB9000040D84AB9200004E4CD\r
+S3210000316867144A8B6610203C0001000023C040000C144E714E71508F265F285F76\r
+S321000031844E5E4E754E5600004FEFFFEC48EF10C00008286E00082E2E000C7C005C\r
+S321000031A04EB9000035E82214DE812039200004D8B0816410BE81641ABEB9200006\r
+S321000031BC04D863127C01600EBE816508BEB9200004D863027C0128874A86675678\r
+S321000031D82039200004CC58802E804EB9000028902039200004CC5880204020871F\r
+S321000031F4BEB9200004D8641A2039200004CC58802F4000042EB9200005444EB9DD\r
+S321000032100000283A60182039200004CC58802F4000042EB9200005484EB90000D3\r
+S3210000322C283A4EB9000036024A806610203C0001000023C040000C144E714E7181\r
+S321000032484CEF10C000084E5E4E754E5600002F07518F2E2E000870004A876768B4\r
+S321000032644EB9000035E8DEB9200004D82039200004CC58802E804EB90000289003\r
+S321000032802039200004CC588020402087BEB9200004D8641A2039200004CC5880F2\r
+S3210000329C2F4000042EB9200005444EB90000283A60182039200004CC58802F40DC\r
+S321000032B800042EB9200005484EB90000283A4EB9000036024A806610203C000157\r
+S321000032D4000023C040000C144E714E71508F2E1F4E5E4E754E5600002F0C2F0767\r
+S321000032F0286E00084EB9000040A24A8C57C049C044804A8067062879200004CCB3\r
+S3210000330C2E2C002C4EB9000040D820072E1F285F4E5E4E754E5600004FEFFFE8C7\r
+S3210000332848EF18C00008266E00082C2E000C7E007006BC8065027C054EB900004B\r
+S3210000334440A2B7F9200004CC6604700026404A8B57C049C044804A806708287912\r
+S32100003360200004CC6002284B222C0044B2866700009ABC8163084A8B670A7E014E\r
+S3210000337C60064A8B66027E01202C0044B0AC002C66042946002C294600447006C7\r
+S3210000339890862940001870144C01080041F92000057441F00800B1EC0014664040\r
+S321000033B441EC00042E884EB900002890202C002CB0B9200004E0630623C0200000\r
+S321000033D004E041EC00042F48000470144C2C0800002C41F92000057441F008000F\r
+S321000033EC2E884EB9000027FC7001BE806610203C0001000023C040000C144E715B\r
+S321000034084E714EB9000040D84CEF18C000084E5E4E754E5600002F0C2F0B518F41\r
+S32100003424266E00084EB9000040A2B7F9200004CC6604700026404A8B57C049C02C\r
+S3210000344044804A8067082879200004CC6002284B41EC00042E884EB90000289061\r
+S3210000345C4AAC0028670C41EC00182E884EB900002890588C2F4C00042EBC200096\r
+S3210000347805084EB9000027FC4EB9000040D84A8B6610203C0001000023C0400011\r
+S321000034940C144E714E71508F265F285F4E5E4E754E5600002F07226E000870003C\r
+S321000034B041F920000508B1E9001457C149C144814A81672641F9200005302E29C0\r
+S321000034CC0028B1C757C149C144817401B282670E4A8757C149C14481B2826602E5\r
+S321000034E870012E1F4E5E4E754E5600002F0C518F286E00084A8C67000084B9F9C5\r
+S32100003504200004CC677A4EB9000040A22E8C4EB9000034A47201B081666041ECBB\r
+S3210000352000042E884EB900002890202C002CB0B9200004E0630623C0200004E0DB\r
+S3210000353C41EC00042F48000470144C2C0800002C41F92000057441F008002E88CF\r
+S321000035584EB9000027FC202C002C2079200004CCB0A8002C6510203C00010000D0\r
+S3210000357423C040000C144E714E714EB9000040D8508F285F4E5E4E754E560000DC\r
+S321000035904FEFFFE842AF001442AF001042AF000A303C00A03F40000841F9000026\r
+S321000035AC41FE2F4800042EBC00003BC24EB900002FB07201B0816702601E700477\r
+S321000035C82E804EB900003FDC700123C0200004E442B9200004D84EB900004086F1\r
+S321000035E44E5E4E754E5600004EB9000040A252B9200004E84EB9000040D84E5EE7\r
+S321000036004E754E5600004FEFFFE448EF18C0000C7E004EB9000040A253B9200072\r
+S3210000361C04E84AB9200004E8660000E04AB9200004D4670000D67C00605C41ECAE\r
+S3210000363800182E884EB90000289041EB00042E884EB900002890202C002CB0B95D\r
+S32100003654200004E0630623C0200004E0588B2F4B000470144C2C0800002C41F935\r
+S321000036702000057441F008002E884EB9000027FC202C002C2079200004CCB0A82D\r
+S3210000368C002C65027C014AB92000053056C049C044804A80670E20792000053C98\r
+S321000036A82D68000CFFEC600442AEFFEC286EFFEC264C4A8C6600FF784AB920006C\r
+S321000036C404EC6718600C4EB90000375853B9200004EC4AB9200004EC66EC7C0175\r
+S321000036E07001BC806708B0B9200004F066187E0142B9200004F0203C00010000C6\r
+S321000036FC23C040000C144E714E714EB9000040D820074CEF18C0000C4E5E4E7517\r
+S321000037184E5600002F074EB9000040A22E39200004D84EB9000040D820072E1FD6\r
+S321000037344E5E4E754E5600002F074EB9000040A22E39200004D44EB9000040D8C3\r
+S3210000375020072E1F4E5E4E754E5600002F0C4FEFFFF44AB9200004E8660000D21D\r
+S3210000376C52B9200004D84AB9200004D8670000822079200005484A9057C049C04C\r
+S3210000378844804A80660000A62079200005482068000C2D68000CFFF8286EFFF8C6\r
+S321000037A44A8C6700009A2039200004D8B0AC00046500008C41EC00042E884EB998\r
+S321000037C0000028904AAC00286654202C002CB0B9200004E0625641EC00042F4812\r
+S321000037DC000470144C2C0800002C41F92000057441F008002E884EB9000027FCAB\r
+S321000037F86082604620792000054820392000054423C02000054823C820000544BB\r
+S3210000381452B9200004F46000FF6041EC00182E884EB900002890609E23C02000F5\r
+S3210000383004E060A242AEFFF86000FF6652B9200004EC4FEF000C285F4E5E4E7589\r
+S3210000384C4E5600004FEFFFF44AB9200004E86600010E2079200004CC20102079AF\r
+S32100003868200004CCB0A80030621A72342039200004CCD0812F4000042EB9200090\r
+S3210000388404CC4EB9000006E870142F40000841F9000042032F48000420792000AF\r
+S321000038A004CC2EA800304EB900000E024A80670A600000C253B9200004E024394F\r
+S321000038BC200004E0721420014C02080043F9200005744AB1080067E02039200051\r
+S321000038D804E04C0018002041D1C92268000421690004000443E80008B3E8000499\r
+S321000038F46700009C206800042028000C23C0200004CC4AB9200004FC67000098DA\r
+S321000039102039200004102079200004CCB0A80040670000842039200005045080AA\r
+S3210000392CB0B920000500646C2079200004CC2028004023C020000410207920003A\r
+S32100003948050420B9200004D858B92000050420792000050420B92000041058B965\r
+S3210000396420000504603C700123C0200004F0603272342039200004CCD0812F40D3\r
+S3210000398000042EB9200004CC4EB9000006E86000FF2A22680004216900040004AC\r
+S3210000399C6000FF5A42B9200004FC4E5E4E754E5600002F07518F206E00082E2E1A\r
+S321000039B8000C72182039200004CCD0812F4000042E884EB90000283A20392000B2\r
+S321000039D404CC58802E804EB90000289070FFBE80674EDEB9200004D8203920004E\r
+S321000039F004CC588020402087BEB9200004D8641A2039200004CC58802F40000481\r
+S32100003A0C2EB9200005444EB90000283A60322039200004CC58802F4000042EB9D2\r
+S32100003A28200005484EB90000283A60182039200004CC58802F4000042EBC200090\r
+S32100003A4405084EB9000027FC508F2E1F4E5E4E754E5600002F0C4FEFFFF4206EF0\r
+S32100003A6000084A9056C049C044804A806700008A2068000C2D68000CFFF8286E02\r
+S32100003A7CFFF841EC00182E884EB9000028904AB9200004E8663C41EC00042E88DF\r
+S32100003A984EB900002890202C002CB0B9200004E0625641EC00042F480004701480\r
+S32100003AB44C2C0800002C41F92000057441F008002E884EB9000027FC601441ECB7\r
+S32100003AD000182F4800042EBC200005304EB9000027FC202C002C2079200004CCD7\r
+S32100003AECB0A8002C54C049C04480601042AEFFF86000FF7C23C0200004E060A238\r
+S32100003B084FEF000C285F4E5E4E754E560000206E000820B9200004F420392000B7\r
+S32100003B2404D8214000044E5E4E754E5600004FEFFFF448D71880286E0008266E11\r
+S32100003B40000C4EB9000040A270FFB09367382039200004F4B09467102039200078\r
+S32100003B5C04D8B0AC000465047E0160142039200004D8242C000490822213B0818E\r
+S32100003B7865107E014EB9000040D8200760247E0060F22039200004D89082928024\r
+S32100003B94268128B9200004F42039200004D8294000047E0060D24CD718804E5E96\r
+S32100003BB04E754E560000700123C0200004F04E5E4E754E5600004EB900003CCC02\r
+S32100003BCC60F84E5600002F0C2F074FEFFFF4286E0008206E000C2E2E0010700C19\r
+S32100003BE82F4000082F48000441EC00342E884EB900000D50422C003F7006BE80ED\r
+S32100003C0465027E052947002C2947004441EC00042E884EB9000027EC41EC00181E\r
+S32100003C202E884EB9000027EC294C00107006908729400018294C00244FEF000C3C\r
+S32100003C3C2E1F285F4E5E4E754E5600002F07598F7E00601A70144C07080041F950\r
+S32100003C582000057441F008002E884EB9000027C852877006BE8065E02EBC2000F0\r
+S32100003C7405604EB9000027C82EBC2000054C4EB9000027C82EBC200005304EB93C\r
+S32100003C90000027C82EBC2000051C4EB9000027C82EBC200005084EB9000027C8F5\r
+S32100003CAC41F92000056023C82000054841F92000054C23C820000544588F2E1FAC\r
+S32100003CC84E5E4E754E5600002F0C2F07518F4AB9200004D06602607A4EB9000036\r
+S32100003CE440A252B9200004E84EB9000040D84AB92000051C57C749C744874EB962\r
+S32100003D00000036024A8766524EB9000040A24AB92000051C56C049C044804A8006\r
+S32100003D1C670E2079200005282D68000CFFF4600442AEFFF4286EFFF441EC000495\r
+S32100003D382E884EB90000289053B9200004D453B9200004D04EB9000040D82E8C17\r
+S32100003D544EB900003DD4508F2E1F285F4E5E4E754E5600002F0C2F074FEFFFF4CD\r
+S32100003D703E2E000870482E804EB900003F3428484A8C674270003007E5882E802C\r
+S32100003D8C4EB900003F3429480030222C0030671E70003007E5882F400008203C10\r
+S32100003DA8000000A52F4000042E814EB900000DD4600C2E8C4EB900003F9E7000D0\r
+S32100003DC42840204C4FEF000C2E1F285F4E5E4E754E5600002F0C598F286E000817\r
+S32100003DE02EAC00304EB900003F9E2E8C4EB900003F9E588F285F4E5E4E754E56B4\r
+S32100003DFC00002F0C4EB9000040A22879200004CC4EB9000040D8204C285F4E5E32\r
+S32100003E184E754E5600002F0C518F286E0008202C002C2079200004CCB0A8002CE3\r
+S32100003E34640000842079200004CC700690A8002C2940001870144C2C0800002C70\r
+S32100003E5041F92000057441F00800B1EC0014670E2079200004CC2968002C002CAC\r
+S32100003E6C604C41EC00042E884EB9000028902079200004CC2968002C002C202C24\r
+S32100003E88002CB0B9200004E0630623C0200004E041EC00042F48000470144C2C87\r
+S32100003EA40800002C41F92000057441F008002E884EB9000027FC508F285F4E5ECA\r
+S32100003EC04E754E5600002F0C518F286E00084A8C675A202C002CB0AC004467505A\r
+S32100003EDC41EC00042E884EB900002890296C0044002C700690AC002C29400018BA\r
+S32100003EF8202C002CB0B9200004E0630623C0200004E041EC00042F480004701443\r
+S32100003F144C2C0800002C41F92000057441F008002E884EB9000027FC508F285F8D\r
+S32100003F304E5E4E754E5600002F0C2F072E2E0008700028404EB9000035E84AB988\r
+S32100003F4C200005EC670C4A874EB900003602204C603841F92000060423C820004C\r
+S32100003F6805F842B9200005FC42B9200005F442B9200005F041F92000060442A8AC\r
+S32100003F84000420BC200005F0700123C0200005EC60BC2E1F285F4E5E4E754E56BE\r
+S32100003FA000002F0C286E00084A8C672A518C4EB9000035E8222C000443F9200010\r
+S32100003FBC05F860022251201158802040B29062F42891228C4EB900003602285FE3\r
+S32100003FD84E5E4E754E56FFF848D700C040C72007028000000700E0882C2E00085D\r
+S32100003FF4028600000007E18E02870000F8FF8E8646C74CD700C04FEF00084E5E37\r
+S321000040104E75202F00044E7B00024E714E754FEFFFC448D77FFF2079200004CC04\r
+S3210000402C208F4EB9000040FE2079200004CC2E504CD77FFF4FEF003C4E73207902\r
+S32100004048200004CC2E504CD77FFF4FEF003C4E734E5600002F0C206E0008286E01\r
+S32100004064000C226E00102089213CDEADBEEF210C213C4000200042A041E8FFC894\r
+S32100004080285F4E5E4E754E56000042B9200004144EB900000E484EB90000404667\r
+S3210000409C70004E5E4E754E560000598F4AB920000414670852B920000414601C2E\r
+S321000040B870042E804EB900003FDC4AB940000C1067E642974EB900003FDC60E4B7\r
+S321000040D44E5E4E754E560000598F203920000414538023C0200004144A8067021D\r
+S321000040F0600842974EB900003FDC4E5E4E754E5600002F07598F70042E804EB9F1\r
+S3210000410C00003FDC2E0042B940000C144EB90000384C2E874EB900003FDC588FA4\r
+S321000041282E1F4E5E4E75000052656731005265673200436865636B0051436F6ECB\r
+S32100004144734231005150726F644232005150726F6442330051436F6E7342340064\r
+S321000041605150726F6442350051436F6E7342360043524541544F52005355494340\r
+S3210000417C4944310053554943494432004C4544780047656E51004D754C6F7700C4\r
+S321000041984D754D6564004D75486967680051436F6E734E42005150726F644E4201\r
+S321000041B4005065656B4C005065656B4D005065656B4831005065656B48320052F7\r
+S321000041D06563310052656332005265633300506F6C53454D3100506F6C53454DEA\r
+S321000041EC3200426C6B53454D3100426C6B53454D320049444C4500A5A5A5A5A5C9\r
+S31500004208A5A5A5A5A5A5A5A5A5A5A5A5A5A5A500F5\r
+S31D000042180000000011111111222222220FFF0000000000FF000099997D\r
+S31D00004230000042182000040000000018000000000000000000000000DA\r
+S70500000A529E\r
--- /dev/null
+\r
+\r
+#>00001000 ___heap_size (linker command file)\r
+#>00001000 ___stack_size (linker command file)\r
+#>40000000 ___IPSBAR (linker command file)\r
+#>20000000 ___RAMBAR (linker command file)\r
+#>00004000 ___RAMBAR_SIZE (linker command file)\r
+#>00000000 ___FLASHBAR (linker command file)\r
+#>00020000 ___FLASHBAR_SIZE (linker command file)\r
+#>20003FFC ___SP_AFTER_RESET (linker command file)\r
+\r
+# .userram\r
+\r
+# .code\r
+\r
+# .vectorram\r
+\r
+# .vectors\r
+ 00000000 00000400 .vectortable _vect (exceptions.c)\r
+\r
+# .cfmprotect\r
+ 00000400 00000018 .cfmconfig _cfm (cfm.c)\r
+\r
+# .text\r
+ 00000500 000000EA .text main (main.c)\r
+ 000005EA 000000E4 .text prvCheckTask (main.c)\r
+ 000006CE 0000001A .text prvSetupHardware (main.c)\r
+ 000006E8 0000000A .text vApplicationStackOverflowHook (main.c)\r
+ 000006F2 000000F8 .text vRegTest1Task (main.c)\r
+ 000007EA 000000F8 .text vRegTest2Task (main.c)\r
+ 000008E2 0000000A .text exit (main.c)\r
+ 000008EC 00000026 .text pll_init (MCF52221_sysinit.c)\r
+ 00000912 00000062 .text __initialize_hardware (MCF52221_sysinit.c)\r
+ 00000974 00000008 .text __initialize_system (startcf.c)\r
+ 0000097C 00000008 .text __call_static_initializers (startcf.c)\r
+ 00000984 00000022 .text __copy_rom_section (startcf.c)\r
+ 000009A6 0000003C .text __copy_rom_sections_to_ram (startcf.c)\r
+ 000009E2 00000070 .text clear_mem (startcf.c)\r
+ 00000A52 000000AA .text _startup (startcf.c)\r
+ 00000AFC 000001DA .text mcf_exception_handler (exceptions.c)\r
+ 00000CD6 00000024 .text asm_exception_handler (exceptions.c)\r
+ 00000CFA 0000000C .text mcf5xxx_wr_vbr (exceptions.c)\r
+ 00000D06 0000004A .text initialize_exceptions (exceptions.c)\r
+ 00000D50 0000004A .text strncpy (stdlib.c)\r
+ 00000D9A 0000003A .text memcpy (stdlib.c)\r
+ 00000DD4 0000002E .text memset (stdlib.c)\r
+ 00000E02 00000046 .text memcmp (stdlib.c)\r
+ 00000E48 00000058 .text vApplicationSetupInterrupts (FreeRTOS_Tick_Setup.c)\r
+ 00000EA0 0000001C .text vParTestInitialise (ParTest.c)\r
+ 00000EBC 00000054 .text vParTestToggleLED (ParTest.c)\r
+ 00000F10 000001F8 .text vStartBlockingQueueTasks (BlockQ.c)\r
+ 00001108 0000005E .text vBlockingQueueProducer (BlockQ.c)\r
+ 00001166 00000068 .text vBlockingQueueConsumer (BlockQ.c)\r
+ 000011CE 0000007E .text xAreBlockingQueuesStillRunning (BlockQ.c)\r
+ 0000124C 00000060 .text vCreateSuicidalTasks (death.c)\r
+ 000012AC 00000066 .text vSuicidalTask (death.c)\r
+ 00001312 00000098 .text vCreateTasks (death.c)\r
+ 000013AA 0000005C .text xIsCreateTaskStillRunning (death.c)\r
+ 00001406 00000052 .text vStartLEDFlashTasks (flash.c)\r
+ 00001458 00000076 .text vLEDFlashTask (flash.c)\r
+ 000014CE 000000EC .text vStartGenericQueueTasks (GenQTest.c)\r
+ 000015BA 000003F6 .text prvSendFrontAndBackTest (GenQTest.c)\r
+ 000019B0 0000010C .text prvLowPriorityMutexTask (GenQTest.c)\r
+ 00001ABC 00000016 .text prvMediumPriorityMutexTask (GenQTest.c)\r
+ 00001AD2 00000062 .text prvHighPriorityMutexTask (GenQTest.c)\r
+ 00001B34 0000005E .text xAreGenericQueueTasksStillRunning (GenQTest.c)\r
+ 00001B92 0000008E .text vStartPolledQueueTasks (PollQ.c)\r
+ 00001C20 00000072 .text vPolledQueueProducer (PollQ.c)\r
+ 00001C92 0000007C .text vPolledQueueConsumer (PollQ.c)\r
+ 00001D0E 0000002C .text xArePollingQueuesStillRunning (PollQ.c)\r
+ 00001D3A 000000E6 .text vStartQueuePeekTasks (QPeek.c)\r
+ 00001E20 00000142 .text prvHighestPriorityPeekTask (QPeek.c)\r
+ 00001F62 000000B4 .text prvHighPriorityPeekTask (QPeek.c)\r
+ 00002016 00000076 .text prvMediumPriorityPeekTask (QPeek.c)\r
+ 0000208C 00000158 .text prvLowPriorityPeekTask (QPeek.c)\r
+ 000021E4 0000003A .text xAreQueuePeekTasksStillRunning (QPeek.c)\r
+ 0000221E 000000AC .text vStartRecursiveMutexTasks (recmutex.c)\r
+ 000022CA 000000C2 .text prvRecursiveMutexControllingTask (recmutex.c)\r
+ 0000238C 0000008E .text prvRecursiveMutexBlockingTask (recmutex.c)\r
+ 0000241A 0000006C .text prvRecursiveMutexPollingTask (recmutex.c)\r
+ 00002486 00000084 .text xAreRecursiveMutexTasksStillRunning (recmutex.c)\r
+ 0000250A 0000017A .text vStartSemaphoreTasks (semtest.c)\r
+ 00002684 000000F8 .text prvSemaphoreTest (semtest.c)\r
+ 0000277C 0000004C .text xAreSemaphoreTasksStillRunning (semtest.c)\r
+ 000027C8 00000024 .text vListInitialise (list.c)\r
+ 000027EC 00000010 .text vListInitialiseItem (list.c)\r
+ 000027FC 0000003E .text vListInsertEnd (list.c)\r
+ 0000283A 00000056 .text vListInsert (list.c)\r
+ 00002890 0000003A .text vListRemove (list.c)\r
+ 000028CA 000000B0 .text xQueueCreate (queue.c)\r
+ 0000297A 00000078 .text xQueueCreateMutex (queue.c)\r
+ 000029F2 0000004C .text xQueueGiveMutexRecursive (queue.c)\r
+ 00002A3E 00000052 .text xQueueTakeMutexRecursive (queue.c)\r
+ 00002A90 0000016C .text xQueueGenericSend (queue.c)\r
+ 00002BFC 000001C6 .text xQueueGenericReceive (queue.c)\r
+ 00002DC2 00000026 .text uxQueueMessagesWaiting (queue.c)\r
+ 00002DE8 0000009C .text prvCopyDataToQueue (queue.c)\r
+ 00002E84 00000042 .text prvCopyDataFromQueue (queue.c)\r
+ 00002EC6 0000008E .text prvUnlockQueue (queue.c)\r
+ 00002F54 0000002C .text prvIsQueueEmpty (queue.c)\r
+ 00002F80 00000030 .text prvIsQueueFull (queue.c)\r
+ 00002FB0 00000140 .text xTaskCreate (tasks.c)\r
+ 000030F0 00000098 .text vTaskDelete (tasks.c)\r
+ 00003188 000000CA .text vTaskDelayUntil (tasks.c)\r
+ 00003252 00000096 .text vTaskDelay (tasks.c)\r
+ 000032E8 00000038 .text uxTaskPriorityGet (tasks.c)\r
+ 00003320 000000FA .text vTaskPrioritySet (tasks.c)\r
+ 0000341A 0000008A .text vTaskSuspend (tasks.c)\r
+ 000034A4 0000004C .text xTaskIsTaskSuspended (tasks.c)\r
+ 000034F0 0000009C .text vTaskResume (tasks.c)\r
+ 0000358C 0000005C .text vTaskStartScheduler (tasks.c)\r
+ 000035E8 0000001A .text vTaskSuspendAll (tasks.c)\r
+ 00003602 00000116 .text xTaskResumeAll (tasks.c)\r
+ 00003718 00000020 .text xTaskGetTickCount (tasks.c)\r
+ 00003738 00000020 .text uxTaskGetNumberOfTasks (tasks.c)\r
+ 00003758 000000F4 .text vTaskIncrementTick (tasks.c)\r
+ 0000384C 0000015E .text vTaskSwitchContext (tasks.c)\r
+ 000039AA 000000AA .text vTaskPlaceOnEventList (tasks.c)\r
+ 00003A54 000000BE .text xTaskRemoveFromEventList (tasks.c)\r
+ 00003B12 0000001C .text vTaskSetTimeOutState (tasks.c)\r
+ 00003B2E 00000084 .text xTaskCheckForTimeOut (tasks.c)\r
+ 00003BB2 00000010 .text vTaskMissedYield (tasks.c)\r
+ 00003BC2 0000000C .text prvIdleTask (tasks.c)\r
+ 00003BCE 00000076 .text prvInitialiseTCBVariables (tasks.c)\r
+ 00003C44 00000088 .text prvInitialiseTaskLists (tasks.c)\r
+ 00003CCC 00000098 .text prvCheckTasksWaitingTermination (tasks.c)\r
+ 00003D64 00000070 .text prvAllocateTCBAndStack (tasks.c)\r
+ 00003DD4 00000026 .text prvDeleteTCB (tasks.c)\r
+ 00003DFA 00000020 .text xTaskGetCurrentTaskHandle (tasks.c)\r
+ 00003E1A 000000A8 .text vTaskPriorityInherit (tasks.c)\r
+ 00003EC2 00000072 .text vTaskPriorityDisinherit (tasks.c)\r
+ 00003F34 0000006A .text pvPortMalloc (heap_2.c)\r
+ 00003F9E 0000003E .text vPortFree (heap_2.c)\r
+ 00003FDC 00000000 .text ulPortSetIPL (portasm.S)\r
+ 00003FDC 0000007C .text @DummyFn1 (portasm.S)\r
+ 00003FDC 0000007C .text .text (portasm.S)\r
+ 00003FDC 00000000 .text ulPortSetIPL (portasm.S)\r
+ 00004012 00000000 .text mcf5xxx_wr_cacrx (portasm.S)\r
+ 00004012 00000000 .text mcf5xxx_wr_cacrx (portasm.S)\r
+ 0000401E 00000000 .text vPortYieldISR (portasm.S)\r
+ 0000401E 00000000 .text vPortYieldISR (portasm.S)\r
+ 00004046 00000000 .text vPortStartFirstTask (portasm.S)\r
+ 00004046 00000000 .text vPortStartFirstTask (portasm.S)\r
+ 00004058 0000002E .text pxPortInitialiseStack (port.c)\r
+ 00004086 0000001C .text xPortStartScheduler (port.c)\r
+ 000040A2 00000036 .text vPortEnterCritical (port.c)\r
+ 000040D8 00000026 .text vPortExitCritical (port.c)\r
+ 000040FE 00000030 .text vPortYieldHandler (port.c)\r
+ 00004130 00000005 .rodata @147 (main.c)\r
+ 00004135 00000005 .rodata @148 (main.c)\r
+ 0000413A 00000006 .rodata @149 (main.c)\r
+ 00004140 00000008 .rodata @115 (BlockQ.c)\r
+ 00004148 00000008 .rodata @116 (BlockQ.c)\r
+ 00004150 00000008 .rodata @117 (BlockQ.c)\r
+ 00004158 00000008 .rodata @118 (BlockQ.c)\r
+ 00004160 00000008 .rodata @119 (BlockQ.c)\r
+ 00004168 00000008 .rodata @120 (BlockQ.c)\r
+ 00004170 00000008 .rodata @55 (death.c)\r
+ 00004178 00000008 .rodata @116 (death.c)\r
+ 00004180 00000008 .rodata @117 (death.c)\r
+ 00004188 00000005 .rodata @62 (flash.c)\r
+ 0000418D 00000005 .rodata @105 (GenQTest.c)\r
+ 00004192 00000006 .rodata @106 (GenQTest.c)\r
+ 00004198 00000006 .rodata @107 (GenQTest.c)\r
+ 0000419E 00000007 .rodata @108 (GenQTest.c)\r
+ 000041A5 00000008 .rodata @102 (PollQ.c)\r
+ 000041AD 00000008 .rodata @103 (PollQ.c)\r
+ 000041B5 00000006 .rodata @102 (QPeek.c)\r
+ 000041BB 00000006 .rodata @103 (QPeek.c)\r
+ 000041C1 00000007 .rodata @104 (QPeek.c)\r
+ 000041C8 00000007 .rodata @105 (QPeek.c)\r
+ 000041CF 00000005 .rodata @101 (recmutex.c)\r
+ 000041D4 00000005 .rodata @102 (recmutex.c)\r
+ 000041D9 00000005 .rodata @103 (recmutex.c)\r
+ 000041DE 00000008 .rodata @116 (semtest.c)\r
+ 000041E6 00000008 .rodata @117 (semtest.c)\r
+ 000041EE 00000008 .rodata @118 (semtest.c)\r
+ 000041F6 00000008 .rodata @119 (semtest.c)\r
+ 000041FE 00000005 .rodata @410 (tasks.c)\r
+ 00004203 00000014 .rodata ucExpectedStackBytes$615 (tasks.c)\r
+#>00004218 ___ROM_AT (linker command file)\r
+#>00004218 ___DATA_ROM (linker command file)\r
+\r
+# .data\r
+#>20000400 ___DATA_RAM (linker command file)\r
+#>20000400 __exception_table_start__ (linker command file)\r
+# Exception index\r
+ 20000400 00000000 Exception Table Index ()\r
+#>20000400 __exception_table_end__ (linker command file)\r
+#>20000400 ___sinit__ (linker command file)\r
+# Linker generated symbols\r
+ 20000400 00000004 static initializer (linker generated)\r
+#>20000404 __START_DATA (linker command file)\r
+ 20000404 00000004 .data ulRegTest1Counter (main.c)\r
+ 20000408 00000004 .data ulRegTest2Counter (main.c)\r
+ 2000040C 00000002 .data usLastCreationCount$155 (death.c)\r
+ 20000410 00000004 .data uxPreviousTask (tasks.c)\r
+ 20000414 00000004 .data ulCriticalNesting (port.c)\r
+#>20000418 __END_DATA (linker command file)\r
+#>20000418 __START_SDATA (linker command file)\r
+#>20000418 __END_SDATA (linker command file)\r
+#>20000418 ___DATA_END (linker command file)\r
+#>20000418 __SDA_BASE (linker command file)\r
+\r
+# .bss\r
+#>20000418 ___BSS_START (linker command file)\r
+#>20000418 __START_SBSS (linker command file)\r
+#>20000418 __END_SBSS (linker command file)\r
+#>20000418 __START_BSS (linker command file)\r
+ 20000418 00000006 .bss sBlockingConsumerCount (BlockQ.c)\r
+ 2000041E 00000006 .bss sBlockingProducerCount (BlockQ.c)\r
+ 20000424 00000006 .bss sLastBlockingConsumerCount$321 (BlockQ.c)\r
+ 2000042A 00000006 .bss sLastBlockingProducerCount$322 (BlockQ.c)\r
+ 20000430 00000002 .bss usCreationCount (death.c)\r
+ 20000434 00000004 .bss uxTasksRunningAtStart (death.c)\r
+ 20000438 00000004 .bss uxTasksRunningNow$157 (death.c)\r
+ 2000043C 00000004 .bss xCreatedTask (death.c)\r
+ 20000440 00000004 .bss uxFlashTaskNumber (flash.c)\r
+ 20000444 00000004 .bss xErrorDetected (GenQTest.c)\r
+ 20000448 00000004 .bss ulLoopCounter (GenQTest.c)\r
+ 2000044C 00000004 .bss ulLoopCounter2 (GenQTest.c)\r
+ 20000450 00000004 .bss ulGuardedVariable (GenQTest.c)\r
+ 20000454 00000004 .bss ulLastLoopCounter$625 (GenQTest.c)\r
+ 20000458 00000004 .bss ulLastLoopCounter2$626 (GenQTest.c)\r
+ 2000045C 00000004 .bss xMediumPriorityMutexTask (GenQTest.c)\r
+ 20000460 00000004 .bss xHighPriorityMutexTask (GenQTest.c)\r
+ 20000464 00000004 .bss xPollingConsumerCount (PollQ.c)\r
+ 20000468 00000004 .bss xPollingProducerCount (PollQ.c)\r
+ 2000046C 00000004 .bss xPolledQueue$101 (PollQ.c)\r
+ 20000470 00000004 .bss xErrorDetected (QPeek.c)\r
+ 20000474 00000004 .bss ulLoopCounter (QPeek.c)\r
+ 20000478 00000004 .bss ulLastLoopCounter$438 (QPeek.c)\r
+ 2000047C 00000004 .bss xHighestPriorityTask (QPeek.c)\r
+ 20000480 00000004 .bss xHighPriorityTask (QPeek.c)\r
+ 20000484 00000004 .bss xMediumPriorityTask (QPeek.c)\r
+ 20000488 00000004 .bss xErrorOccurred (recmutex.c)\r
+ 2000048C 00000004 .bss xControllingIsSuspended (recmutex.c)\r
+ 20000490 00000004 .bss xBlockingIsSuspended (recmutex.c)\r
+ 20000494 00000004 .bss uxControllingCycles (recmutex.c)\r
+ 20000498 00000004 .bss uxPollingCycles (recmutex.c)\r
+ 2000049C 00000004 .bss uxLastControllingCycles$264 (recmutex.c)\r
+ 200004A0 00000004 .bss uxLastBlockingCycles$265 (recmutex.c)\r
+ 200004A4 00000004 .bss uxLastPollingCycles$266 (recmutex.c)\r
+ 200004A8 00000004 .bss xBlockingTaskHandle (recmutex.c)\r
+ 200004AC 00000004 .bss xControllingTaskHandle (recmutex.c)\r
+ 200004B0 00000004 .bss uxBlockingCycles (recmutex.c)\r
+ 200004B4 00000004 .bss xMutex (recmutex.c)\r
+ 200004B8 00000008 .bss sCheckVariables (semtest.c)\r
+ 200004C0 00000002 .bss sNextCheckVariable (semtest.c)\r
+ 200004C2 00000008 .bss sLastCheckVariables$297 (semtest.c)\r
+ 200004CC 00000004 .bss pxCurrentTCB (tasks.c)\r
+ 200004D0 00000004 .bss uxTasksDeleted (tasks.c)\r
+ 200004D4 00000004 .bss uxCurrentNumberOfTasks (tasks.c)\r
+ 200004D8 00000004 .bss xTickCount (tasks.c)\r
+ 200004DC 00000004 .bss uxTopUsedPriority (tasks.c)\r
+ 200004E0 00000004 .bss uxTopReadyPriority (tasks.c)\r
+ 200004E4 00000004 .bss xSchedulerRunning (tasks.c)\r
+ 200004E8 00000004 .bss uxSchedulerSuspended (tasks.c)\r
+ 200004EC 00000004 .bss uxMissedTicks (tasks.c)\r
+ 200004F0 00000004 .bss xMissedYield (tasks.c)\r
+ 200004F4 00000004 .bss xNumOfOverflows (tasks.c)\r
+ 200004F8 00000004 .bss uxTaskNumber (tasks.c)\r
+ 200004FC 00000004 .bss xTracing (tasks.c)\r
+ 20000500 00000004 .bss pcTraceBufferEnd (tasks.c)\r
+ 20000504 00000004 .bss pcTraceBuffer (tasks.c)\r
+ 20000508 00000014 .bss xSuspendedTaskList (tasks.c)\r
+ 2000051C 00000014 .bss xTasksWaitingTermination (tasks.c)\r
+ 20000530 00000014 .bss xPendingReadyList (tasks.c)\r
+ 20000544 00000004 .bss pxOverflowDelayedTaskList (tasks.c)\r
+ 20000548 00000004 .bss pxDelayedTaskList (tasks.c)\r
+ 2000054C 00000014 .bss xDelayedTaskList2 (tasks.c)\r
+ 20000560 00000014 .bss xDelayedTaskList1 (tasks.c)\r
+ 20000574 00000078 .bss pxReadyTasksLists (tasks.c)\r
+ 200005EC 00000004 .bss xHeapHasBeenInitialised$54 (heap_2.c)\r
+ 200005F0 00000008 .bss xEnd (heap_2.c)\r
+ 200005F8 00000008 .bss xStart (heap_2.c)\r
+ 20000600 00000004 .bss xHeap (heap_2.c)\r
+#>20000604 __END_BSS (linker command file)\r
+#>20000604 ___BSS_END (linker command file)\r
+\r
+# .custom\r
+#>20000604 ___HEAP_START (linker command file)\r
+#>20000604 ___heap_addr (linker command file)\r
+#>20001604 ___HEAP_END (linker command file)\r
+#>20001604 ___SP_END (linker command file)\r
+#>20002604 ___SP_INIT (linker command file)\r
+#>20000000 ___VECTOR_RAM (linker command file)\r
+#>20002604 __SP_INIT (linker command file)\r
+#>00004230 _romp_at (linker command file)\r
+\r
+# .romp\r
+#>00004230 __S_romp (linker command file)\r
+\r
+\r
+# Memory map:\r
+ v_addr p_addr size name\r
+ 00000000 00000000 00000400 .vectors vectorrom\r
+ 00000400 00000400 00000018 .cfmprotect cfmprotrom\r
+ 00000500 00000500 00000000 .code code\r
+ 00000500 00000500 00003D18 .text code\r
+ 20000000 20000000 00000000 .vectorram vectorram\r
+ 20000400 20000400 00000000 .userram userram\r
+ 20000400 00004218 00000018 .data userram\r
+ 20000418 20000418 000001EC .bss userram\r
+ 20000604 20000604 00000000 .custom userram\r
+ 20000604 00004230 00000018 .romp userram\r
+\r
+# Link start time: Fri Oct 17 15:01:49 2008\r
+# Link end time: Fri Oct 17 15:01:49 2008\r
--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r
--- /dev/null
+// Memory Configuration File\r
+//\r
+// Description:\r
+// A memory configuration file contains commands that define the legally accessible\r
+// areas of memory for your specific board. Useful for example when the debugger\r
+// tries to display the content of a "char *" variable, that has not yet been initialized.\r
+// In this case the debugger may try to read from a bogus address, which could cause a\r
+// bus error.\r
+//\r
+// Board:\r
+// Freescale M52221DEMO\r
+//\r
+// Reference:\r
+// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7\r
+\r
+\r
+// All reserved ranges read back 0xBABA...\r
+reservedchar 0xBA\r
+\r
+address IPSBAR_BASE 0x40000000\r
+\r
+usederivative "MCF52221"\r
+\r
+// Memory Map:\r
+// ----------------------------------------------------------------------\r
+range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory\r
+reserved 0x00020000 0x1FFFFFFF\r
+range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM\r
+reserved 0x20004000 0x40000007\r
+// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers\r
+reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF\r
--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r
--- /dev/null
+// Memory Configuration File\r
+//\r
+// Description:\r
+// A memory configuration file contains commands that define the legally accessible\r
+// areas of memory for your specific board. Useful for example when the debugger\r
+// tries to display the content of a "char *" variable, that has not yet been initialized.\r
+// In this case the debugger may try to read from a bogus address, which could cause a\r
+// bus error.\r
+//\r
+// Board:\r
+// Freescale M52221DEMO\r
+//\r
+// Reference:\r
+// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7\r
+\r
+\r
+// All reserved ranges read back 0xBABA...\r
+reservedchar 0xBA\r
+\r
+address IPSBAR_BASE 0x40000000\r
+\r
+usederivative "MCF52221"\r
+\r
+// Memory Map:\r
+// ----------------------------------------------------------------------\r
+range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory\r
+reserved 0x00020000 0x1FFFFFFF\r
+range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM\r
+reserved 0x20004000 0x40000007\r
+// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers\r
+reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF\r
--- /dev/null
+ResetHalt\r
+\r
+; Set VBR to the beginning of what will be SRAM\r
+; VBR is an absolute CPU register\r
+writecontrolreg 0x0801 0x20000000\r
+\r
+; Set RAMBAR1 (SRAM)\r
+writecontrolreg 0x0C05 0x20000021\r
+\r
+; Set FLASHBAR (Flash)\r
+writecontrolreg 0x0C04 0x00000061\r
+\r
+; Enable PST[3:0] signals\r
+writemem.b 0x40100074 0x0F\r
--- /dev/null
+// Memory Configuration File\r
+//\r
+// Description:\r
+// A memory configuration file contains commands that define the legally accessible\r
+// areas of memory for your specific board. Useful for example when the debugger\r
+// tries to display the content of a "char *" variable, that has not yet been initialized.\r
+// In this case the debugger may try to read from a bogus address, which could cause a\r
+// bus error.\r
+//\r
+// Board:\r
+// Freescale M52221DEMO\r
+//\r
+// Reference:\r
+// Kirin2u_SoC_Guide.pdf - KIRIN2U_SG V0.7\r
+\r
+\r
+// All reserved ranges read back 0xBABA...\r
+reservedchar 0xBA\r
+\r
+address IPSBAR_BASE 0x40000000\r
+\r
+usederivative "MCF52221"\r
+\r
+// Memory Map:\r
+// ----------------------------------------------------------------------\r
+range 0x00000000 0x0001FFFF 4 Read // 128 KByte Internal Flash Memory\r
+reserved 0x00020000 0x1FFFFFFF\r
+range 0x20000000 0x20003FFF 4 ReadWrite // 16 Kbytes Internal SRAM\r
+reserved 0x20004000 0x40000007\r
+// $IPSBAR_BASE $IPSBAR_BASE + 0x1FFFFF // Memory Mapped Registers\r
+reserved $IPSBAR_BASE + 0x001D004C 0xFFFFFFFF\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>\r
+\r
+<fpconfig xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="fp_config.xsd">\r
+\r
+ <targetconfwindow>\r
+ <usecustomsettings>false</usecustomsettings>\r
+ <targetprocessor>52221</targetprocessor>\r
+ <connection></connection>\r
+ <usetargetinit>true</usetargetinit>\r
+ <targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\M52221DEMO.cfg</targetinitfile>\r
+ <targetmembuffaddr>0x20000000</targetmembuffaddr>\r
+ <targetmembuffsize>0x00004000</targetmembuffsize>\r
+ <enablelogging>true</enablelogging>\r
+ <verifywrites>false</verifywrites>\r
+ </targetconfwindow>\r
+\r
+ <flashconfwindow>\r
+ <membaseaddr>0x00000000</membaseaddr>\r
+ <device>CFM_MCF52221</device>\r
+ <organization>4Kx32x1</organization>\r
+ <flashstart>0x00000000</flashstart>\r
+ <flashend>0x0001FFFF</flashend>\r
+ </flashconfwindow>\r
+\r
+ <programverifywindow>\r
+ <useselectedfile>false</useselectedfile>\r
+ <projbuildtargetfile>nofile</projbuildtargetfile>\r
+ <fileiotype>Auto Detect</fileiotype>\r
+ <restrictaddrrange>false</restrictaddrrange>\r
+ <restrictaddrrangestart>0x00000000</restrictaddrrangestart>\r
+ <restrictaddrrangeend>0x0001FFFF</restrictaddrrangeend>\r
+ <applyaddroffset>false</applyaddroffset>\r
+ <addroffset>0x00000000</addroffset>\r
+ </programverifywindow>\r
+\r
+ <eraseblankcheckwindow>\r
+ <eraseallsectors>true</eraseallsectors>\r
+ <sector/>\r
+ <processsectorsindividually>false</processsectorsindividually>\r
+ </eraseblankcheckwindow>\r
+\r
+ <checksumwindow>\r
+ <computechecksumover>FileOnTarg</computechecksumover>\r
+ <addrstart>0x00000000</addrstart>\r
+ <addrsize>0x0000FFFF</addrsize>\r
+ </checksumwindow>\r
+\r
+</fpconfig>\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_H__\r
+#define __MCF52221_H__\r
+\r
+\r
+/********************************************************************/\r
+/*\r
+ * The basic data types\r
+ */\r
+\r
+typedef unsigned char uint8; /* 8 bits */\r
+typedef unsigned short int uint16; /* 16 bits */\r
+typedef unsigned long int uint32; /* 32 bits */\r
+\r
+typedef signed char int8; /* 8 bits */\r
+typedef signed short int int16; /* 16 bits */\r
+typedef signed long int int32; /* 32 bits */\r
+\r
+typedef volatile uint8 vuint8; /* 8 bits */\r
+typedef volatile uint16 vuint16; /* 16 bits */\r
+typedef volatile uint32 vuint32; /* 32 bits */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#pragma define_section system ".system" far_absolute RW\r
+\r
+/***\r
+ * MCF52221 Derivative Memory map definitions from linker command files:\r
+ * __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+ * symbols must be defined in the linker command file.\r
+ */\r
+\r
+extern __declspec(system) uint8 __IPSBAR[];\r
+extern __declspec(system) uint8 __RAMBAR[];\r
+extern __declspec(system) uint8 __RAMBAR_SIZE[];\r
+extern __declspec(system) uint8 __FLASHBAR[];\r
+extern __declspec(system) uint8 __FLASHBAR_SIZE[];\r
+\r
+#define IPSBAR_ADDRESS (uint32)__IPSBAR\r
+#define RAMBAR_ADDRESS (uint32)__RAMBAR\r
+#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE\r
+#define FLASHBAR_ADDRESS (uint32)__FLASHBAR\r
+#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE\r
+\r
+\r
+#include "MCF52221_SCM.h"\r
+#include "MCF52221_DMA.h"\r
+#include "MCF52221_UART.h"\r
+#include "MCF52221_I2C.h"\r
+#include "MCF52221_QSPI.h"\r
+#include "MCF52221_RTC.h"\r
+#include "MCF52221_DTIM.h"\r
+#include "MCF52221_INTC.h"\r
+#include "MCF52221_GPIO.h"\r
+#include "MCF52221_PAD.h"\r
+#include "MCF52221_RCM.h"\r
+#include "MCF52221_CCM.h"\r
+#include "MCF52221_PMM.h"\r
+#include "MCF52221_CLOCK.h"\r
+#include "MCF52221_EPORT.h"\r
+#include "MCF52221_PIT.h"\r
+#include "MCF52221_ADC.h"\r
+#include "MCF52221_GPTA.h"\r
+#include "MCF52221_PWM.h"\r
+#include "MCF52221_USB_OTG.h"\r
+#include "MCF52221_CFM.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* __MCF52221_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_ADC_H__\r
+#define __MCF52221_ADC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Analog-to-Digital Converter (ADC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_ADC_CTRL1 (*(vuint16*)(0x40190000))\r
+#define MCF_ADC_CTRL2 (*(vuint16*)(0x40190002))\r
+#define MCF_ADC_ADZCC (*(vuint16*)(0x40190004))\r
+#define MCF_ADC_ADLST1 (*(vuint16*)(0x40190006))\r
+#define MCF_ADC_ADLST2 (*(vuint16*)(0x40190008))\r
+#define MCF_ADC_ADSDIS (*(vuint16*)(0x4019000A))\r
+#define MCF_ADC_ADSTAT (*(vuint16*)(0x4019000C))\r
+#define MCF_ADC_ADLSTAT (*(vuint16*)(0x4019000E))\r
+#define MCF_ADC_ADZCSTAT (*(vuint16*)(0x40190010))\r
+#define MCF_ADC_ADRSLT0 (*(vuint16*)(0x40190012))\r
+#define MCF_ADC_ADRSLT1 (*(vuint16*)(0x40190014))\r
+#define MCF_ADC_ADRSLT2 (*(vuint16*)(0x40190016))\r
+#define MCF_ADC_ADRSLT3 (*(vuint16*)(0x40190018))\r
+#define MCF_ADC_ADRSLT4 (*(vuint16*)(0x4019001A))\r
+#define MCF_ADC_ADRSLT5 (*(vuint16*)(0x4019001C))\r
+#define MCF_ADC_ADRSLT6 (*(vuint16*)(0x4019001E))\r
+#define MCF_ADC_ADRSLT7 (*(vuint16*)(0x40190020))\r
+#define MCF_ADC_ADLLMT0 (*(vuint16*)(0x40190022))\r
+#define MCF_ADC_ADLLMT1 (*(vuint16*)(0x40190024))\r
+#define MCF_ADC_ADLLMT2 (*(vuint16*)(0x40190026))\r
+#define MCF_ADC_ADLLMT3 (*(vuint16*)(0x40190028))\r
+#define MCF_ADC_ADLLMT4 (*(vuint16*)(0x4019002A))\r
+#define MCF_ADC_ADLLMT5 (*(vuint16*)(0x4019002C))\r
+#define MCF_ADC_ADLLMT6 (*(vuint16*)(0x4019002E))\r
+#define MCF_ADC_ADLLMT7 (*(vuint16*)(0x40190030))\r
+#define MCF_ADC_ADHLMT0 (*(vuint16*)(0x40190032))\r
+#define MCF_ADC_ADHLMT1 (*(vuint16*)(0x40190034))\r
+#define MCF_ADC_ADHLMT2 (*(vuint16*)(0x40190036))\r
+#define MCF_ADC_ADHLMT3 (*(vuint16*)(0x40190038))\r
+#define MCF_ADC_ADHLMT4 (*(vuint16*)(0x4019003A))\r
+#define MCF_ADC_ADHLMT5 (*(vuint16*)(0x4019003C))\r
+#define MCF_ADC_ADHLMT6 (*(vuint16*)(0x4019003E))\r
+#define MCF_ADC_ADHLMT7 (*(vuint16*)(0x40190040))\r
+#define MCF_ADC_ADOFS0 (*(vuint16*)(0x40190042))\r
+#define MCF_ADC_ADOFS1 (*(vuint16*)(0x40190044))\r
+#define MCF_ADC_ADOFS2 (*(vuint16*)(0x40190046))\r
+#define MCF_ADC_ADOFS3 (*(vuint16*)(0x40190048))\r
+#define MCF_ADC_ADOFS4 (*(vuint16*)(0x4019004A))\r
+#define MCF_ADC_ADOFS5 (*(vuint16*)(0x4019004C))\r
+#define MCF_ADC_ADOFS6 (*(vuint16*)(0x4019004E))\r
+#define MCF_ADC_ADOFS7 (*(vuint16*)(0x40190050))\r
+#define MCF_ADC_POWER (*(vuint16*)(0x40190052))\r
+#define MCF_ADC_CAL (*(vuint16*)(0x40190054))\r
+#define MCF_ADC_ADRSLT(x) (*(vuint16*)(0x40190012 + ((x)*0x2)))\r
+#define MCF_ADC_ADLLMT(x) (*(vuint16*)(0x40190022 + ((x)*0x2)))\r
+#define MCF_ADC_ADHLMT(x) (*(vuint16*)(0x40190032 + ((x)*0x2)))\r
+#define MCF_ADC_ADOFS(x) (*(vuint16*)(0x40190042 + ((x)*0x2)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL1 */\r
+#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)\r
+#define MCF_ADC_CTRL1_HLMTIE (0x100)\r
+#define MCF_ADC_CTRL1_LLMTIE (0x200)\r
+#define MCF_ADC_CTRL1_ZCIE (0x400)\r
+#define MCF_ADC_CTRL1_EOSIE0 (0x800)\r
+#define MCF_ADC_CTRL1_SYNC0 (0x1000)\r
+#define MCF_ADC_CTRL1_START0 (0x2000)\r
+#define MCF_ADC_CTRL1_STOP0 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CTRL2 */\r
+#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)\r
+#define MCF_ADC_CTRL2_SIMULT (0x20)\r
+#define MCF_ADC_CTRL2_EOSIE1 (0x800)\r
+#define MCF_ADC_CTRL2_SYNC1 (0x1000)\r
+#define MCF_ADC_CTRL2_START1 (0x2000)\r
+#define MCF_ADC_CTRL2_STOP1 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCC */\r
+#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)\r
+#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)\r
+#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)\r
+#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)\r
+#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)\r
+#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)\r
+#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)\r
+#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST1 */\r
+#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLST2 */\r
+#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)\r
+#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)\r
+#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)\r
+#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSDIS */\r
+#define MCF_ADC_ADSDIS_DS0 (0x1)\r
+#define MCF_ADC_ADSDIS_DS1 (0x2)\r
+#define MCF_ADC_ADSDIS_DS2 (0x4)\r
+#define MCF_ADC_ADSDIS_DS3 (0x8)\r
+#define MCF_ADC_ADSDIS_DS4 (0x10)\r
+#define MCF_ADC_ADSDIS_DS5 (0x20)\r
+#define MCF_ADC_ADSDIS_DS6 (0x40)\r
+#define MCF_ADC_ADSDIS_DS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADSTAT */\r
+#define MCF_ADC_ADSTAT_RDY0 (0x1)\r
+#define MCF_ADC_ADSTAT_RDY1 (0x2)\r
+#define MCF_ADC_ADSTAT_RDY2 (0x4)\r
+#define MCF_ADC_ADSTAT_RDY3 (0x8)\r
+#define MCF_ADC_ADSTAT_RDY4 (0x10)\r
+#define MCF_ADC_ADSTAT_RDY5 (0x20)\r
+#define MCF_ADC_ADSTAT_RDY6 (0x40)\r
+#define MCF_ADC_ADSTAT_RDY7 (0x80)\r
+#define MCF_ADC_ADSTAT_HLMTI (0x100)\r
+#define MCF_ADC_ADSTAT_LLMTI (0x200)\r
+#define MCF_ADC_ADSTAT_ZCI (0x400)\r
+#define MCF_ADC_ADSTAT_EOSI0 (0x800)\r
+#define MCF_ADC_ADSTAT_EOSI1 (0x1000)\r
+#define MCF_ADC_ADSTAT_CIP1 (0x4000)\r
+#define MCF_ADC_ADSTAT_CIP0 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLSTAT */\r
+#define MCF_ADC_ADLSTAT_LLS0 (0x1)\r
+#define MCF_ADC_ADLSTAT_LLS1 (0x2)\r
+#define MCF_ADC_ADLSTAT_LLS2 (0x4)\r
+#define MCF_ADC_ADLSTAT_LLS3 (0x8)\r
+#define MCF_ADC_ADLSTAT_LLS4 (0x10)\r
+#define MCF_ADC_ADLSTAT_LLS5 (0x20)\r
+#define MCF_ADC_ADLSTAT_LLS6 (0x40)\r
+#define MCF_ADC_ADLSTAT_LLS7 (0x80)\r
+#define MCF_ADC_ADLSTAT_HLS0 (0x100)\r
+#define MCF_ADC_ADLSTAT_HLS1 (0x200)\r
+#define MCF_ADC_ADLSTAT_HLS2 (0x400)\r
+#define MCF_ADC_ADLSTAT_HLS3 (0x800)\r
+#define MCF_ADC_ADLSTAT_HLS4 (0x1000)\r
+#define MCF_ADC_ADLSTAT_HLS5 (0x2000)\r
+#define MCF_ADC_ADLSTAT_HLS6 (0x4000)\r
+#define MCF_ADC_ADLSTAT_HLS7 (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADZCSTAT */\r
+#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)\r
+#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)\r
+#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)\r
+#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)\r
+#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)\r
+#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)\r
+#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)\r
+#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADRSLT */\r
+#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)\r
+#define MCF_ADC_ADRSLT_SEXT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADLLMT */\r
+#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADHLMT */\r
+#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_ADOFS */\r
+#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_ADC_POWER */\r
+#define MCF_ADC_POWER_PD0 (0x1)\r
+#define MCF_ADC_POWER_PD1 (0x2)\r
+#define MCF_ADC_POWER_PD2 (0x4)\r
+#define MCF_ADC_POWER_APD (0x8)\r
+#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)\r
+#define MCF_ADC_POWER_PSTS0 (0x400)\r
+#define MCF_ADC_POWER_PSTS1 (0x800)\r
+#define MCF_ADC_POWER_PSTS2 (0x1000)\r
+#define MCF_ADC_POWER_ASB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_ADC_CAL */\r
+#define MCF_ADC_CAL_SEL_VREFL (0x4000)\r
+#define MCF_ADC_CAL_SEL_VREFH (0x8000)\r
+\r
+\r
+#endif /* __MCF52221_ADC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_CCM_H__\r
+#define __MCF52221_CCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Chip Configuration Module (CCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CCM_CCR (*(vuint16*)(0x40110004))\r
+#define MCF_CCM_RCON (*(vuint16*)(0x40110008))\r
+#define MCF_CCM_CIR (*(vuint16*)(0x4011000A))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CCM_CCR */\r
+#define MCF_CCM_CCR_Mode(x) (((x)&0x7)<<0x8)\r
+#define MCF_CCM_CCR_MODE_SINGLECHIP (0x600)\r
+#define MCF_CCM_CCR_MODE_EZPORT (0x500)\r
+\r
+/* Bit definitions and macros for MCF_CCM_RCON */\r
+#define MCF_CCM_RCON_MODE (0x1)\r
+#define MCF_CCM_RCON_RLOAD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_CCM_CIR */\r
+#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)\r
+#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)\r
+\r
+\r
+#endif /* __MCF52221_CCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_CFM_H__\r
+#define __MCF52221_CFM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* ColdFire Flash Module (CFM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CFM_CFMMCR (*(vuint16*)(0x401D0000))\r
+#define MCF_CFM_CFMCLKD (*(vuint8 *)(0x401D0002))\r
+#define MCF_CFM_CFMSEC (*(vuint32*)(0x401D0008))\r
+#define MCF_CFM_CFMPROT (*(vuint32*)(0x401D0010))\r
+#define MCF_CFM_CFMSACC (*(vuint32*)(0x401D0014))\r
+#define MCF_CFM_CFMDACC (*(vuint32*)(0x401D0018))\r
+#define MCF_CFM_CFMUSTAT (*(vuint8 *)(0x401D0020))\r
+#define MCF_CFM_CFMCMD (*(vuint8 *)(0x401D0024))\r
+#define MCF_CFM_CFMCLKSEL (*(vuint16*)(0x401D004A))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMMCR */\r
+#define MCF_CFM_CFMMCR_KEYACC (0x20)\r
+#define MCF_CFM_CFMMCR_CCIE (0x40)\r
+#define MCF_CFM_CFMMCR_CBEIE (0x80)\r
+#define MCF_CFM_CFMMCR_AEIE (0x100)\r
+#define MCF_CFM_CFMMCR_PVIE (0x200)\r
+#define MCF_CFM_CFMMCR_LOCK (0x400)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKD */\r
+#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)\r
+#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)\r
+#define MCF_CFM_CFMCLKD_DIVLD (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSEC */\r
+#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)\r
+#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)\r
+#define MCF_CFM_CFMSEC_KEYEN (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMPROT */\r
+#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMSACC */\r
+#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMDACC */\r
+#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMUSTAT */\r
+#define MCF_CFM_CFMUSTAT_BLANK (0x4)\r
+#define MCF_CFM_CFMUSTAT_ACCERR (0x10)\r
+#define MCF_CFM_CFMUSTAT_PVIOL (0x20)\r
+#define MCF_CFM_CFMUSTAT_CCIF (0x40)\r
+#define MCF_CFM_CFMUSTAT_CBEIF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCMD */\r
+#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)\r
+#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)\r
+#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)\r
+#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)\r
+#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)\r
+\r
+/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */\r
+#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)\r
+\r
+\r
+#endif /* __MCF52221_CFM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_CLOCK_H__\r
+#define __MCF52221_CLOCK_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Clock Module (CLOCK)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_CLOCK_SYNCR (*(vuint16*)(0x40120000))\r
+#define MCF_CLOCK_SYNSR (*(vuint8 *)(0x40120002))\r
+#define MCF_CLOCK_ROCR (*(vuint16*)(0x40120004))\r
+#define MCF_CLOCK_LPDR (*(vuint8 *)(0x40120007))\r
+#define MCF_CLOCK_CCHR (*(vuint8 *)(0x40120008))\r
+#define MCF_CLOCK_CCLR (*(vuint8 *)(0x40120009))\r
+#define MCF_CLOCK_OCHR (*(vuint8 *)(0x4012000A))\r
+#define MCF_CLOCK_OCLR (*(vuint8 *)(0x4012000B))\r
+#define MCF_CLOCK_RTCDR (*(vuint32*)(0x4012000C))\r
+\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNCR */\r
+#define MCF_CLOCK_SYNCR_PLLEN (0x1)\r
+#define MCF_CLOCK_SYNCR_PLLMODE (0x2)\r
+#define MCF_CLOCK_SYNCR_CLKSRC (0x4)\r
+#define MCF_CLOCK_SYNCR_FWKUP (0x20)\r
+#define MCF_CLOCK_SYNCR_DISCLK (0x40)\r
+#define MCF_CLOCK_SYNCR_LOCEN (0x80)\r
+#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)\r
+#define MCF_CLOCK_SYNCR_LOCRE (0x800)\r
+#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)\r
+#define MCF_CLOCK_SYNCR_LOLRE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_SYNSR */\r
+#define MCF_CLOCK_SYNSR_LOCS (0x4)\r
+#define MCF_CLOCK_SYNSR_LOCK (0x8)\r
+#define MCF_CLOCK_SYNSR_LOCKS (0x10)\r
+#define MCF_CLOCK_SYNSR_CRYOSC (0x20)\r
+#define MCF_CLOCK_SYNSR_OCOSC (0x40)\r
+#define MCF_CLOCK_SYNSR_EXTOSC (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_ROCR */\r
+#define MCF_CLOCK_ROCR_TRIM(x) (((x)&0x3FF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_LPDR */\r
+#define MCF_CLOCK_LPDR_LPD(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_CCHR */\r
+#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_CCLR */\r
+#define MCF_CLOCK_CCLR_OSCSEL (0x1)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_OCHR */\r
+#define MCF_CLOCK_OCHR_STBY (0x40)\r
+#define MCF_CLOCK_OCHR_OCOEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_OCLR */\r
+#define MCF_CLOCK_OCLR_RANGE (0x10)\r
+#define MCF_CLOCK_OCLR_LPEN (0x20)\r
+#define MCF_CLOCK_OCLR_REFS (0x40)\r
+#define MCF_CLOCK_OCLR_OSCEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_CLOCK_RTCDR */\r
+#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_CLOCK_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_DMA_H__\r
+#define __MCF52221_DMA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Controller (DMA)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DMA0_SAR (*(vuint32*)(0x40000100))\r
+#define MCF_DMA0_DAR (*(vuint32*)(0x40000104))\r
+#define MCF_DMA0_DSR (*(vuint8 *)(0x40000108))\r
+#define MCF_DMA0_BCR (*(vuint32*)(0x40000108))\r
+#define MCF_DMA0_DCR (*(vuint32*)(0x4000010C))\r
+\r
+#define MCF_DMA1_SAR (*(vuint32*)(0x40000110))\r
+#define MCF_DMA1_DAR (*(vuint32*)(0x40000114))\r
+#define MCF_DMA1_DSR (*(vuint8 *)(0x40000118))\r
+#define MCF_DMA1_BCR (*(vuint32*)(0x40000118))\r
+#define MCF_DMA1_DCR (*(vuint32*)(0x4000011C))\r
+\r
+#define MCF_DMA2_SAR (*(vuint32*)(0x40000120))\r
+#define MCF_DMA2_DAR (*(vuint32*)(0x40000124))\r
+#define MCF_DMA2_DSR (*(vuint8 *)(0x40000128))\r
+#define MCF_DMA2_BCR (*(vuint32*)(0x40000128))\r
+#define MCF_DMA2_DCR (*(vuint32*)(0x4000012C))\r
+\r
+#define MCF_DMA3_SAR (*(vuint32*)(0x40000130))\r
+#define MCF_DMA3_DAR (*(vuint32*)(0x40000134))\r
+#define MCF_DMA3_DSR (*(vuint8 *)(0x40000138))\r
+#define MCF_DMA3_BCR (*(vuint32*)(0x40000138))\r
+#define MCF_DMA3_DCR (*(vuint32*)(0x4000013C))\r
+\r
+#define MCF_DMA_SAR(x) (*(vuint32*)(0x40000100 + ((x)*0x10)))\r
+#define MCF_DMA_DAR(x) (*(vuint32*)(0x40000104 + ((x)*0x10)))\r
+#define MCF_DMA_DSR(x) (*(vuint8 *)(0x40000108 + ((x)*0x10)))\r
+#define MCF_DMA_BCR(x) (*(vuint32*)(0x40000108 + ((x)*0x10)))\r
+#define MCF_DMA_DCR(x) (*(vuint32*)(0x4000010C + ((x)*0x10)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DMA_SAR */\r
+#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DAR */\r
+#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DSR */\r
+#define MCF_DMA_DSR_DONE (0x1)\r
+#define MCF_DMA_DSR_BSY (0x2)\r
+#define MCF_DMA_DSR_REQ (0x4)\r
+#define MCF_DMA_DSR_BED (0x10)\r
+#define MCF_DMA_DSR_BES (0x20)\r
+#define MCF_DMA_DSR_CE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_DMA_BCR */\r
+#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)\r
+#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)\r
+\r
+/* Bit definitions and macros for MCF_DMA_DCR */\r
+#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)\r
+#define MCF_DMA_DCR_LCH2_CH0 (0)\r
+#define MCF_DMA_DCR_LCH2_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH2_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH2_CH3 (0x3)\r
+#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)\r
+#define MCF_DMA_DCR_LCH1_CH0 (0)\r
+#define MCF_DMA_DCR_LCH1_CH1 (0x1)\r
+#define MCF_DMA_DCR_LCH1_CH2 (0x2)\r
+#define MCF_DMA_DCR_LCH1_CH3 (0x3)\r
+#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)\r
+#define MCF_DMA_DCR_D_REQ (0x80)\r
+#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)\r
+#define MCF_DMA_DCR_DMOD_DIS (0)\r
+#define MCF_DMA_DCR_DMOD_16 (0x1)\r
+#define MCF_DMA_DCR_DMOD_32 (0x2)\r
+#define MCF_DMA_DCR_DMOD_64 (0x3)\r
+#define MCF_DMA_DCR_DMOD_128 (0x4)\r
+#define MCF_DMA_DCR_DMOD_256 (0x5)\r
+#define MCF_DMA_DCR_DMOD_512 (0x6)\r
+#define MCF_DMA_DCR_DMOD_1K (0x7)\r
+#define MCF_DMA_DCR_DMOD_2K (0x8)\r
+#define MCF_DMA_DCR_DMOD_4K (0x9)\r
+#define MCF_DMA_DCR_DMOD_8K (0xA)\r
+#define MCF_DMA_DCR_DMOD_16K (0xB)\r
+#define MCF_DMA_DCR_DMOD_32K (0xC)\r
+#define MCF_DMA_DCR_DMOD_64K (0xD)\r
+#define MCF_DMA_DCR_DMOD_128K (0xE)\r
+#define MCF_DMA_DCR_DMOD_256K (0xF)\r
+#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)\r
+#define MCF_DMA_DCR_SMOD_DIS (0)\r
+#define MCF_DMA_DCR_SMOD_16 (0x1)\r
+#define MCF_DMA_DCR_SMOD_32 (0x2)\r
+#define MCF_DMA_DCR_SMOD_64 (0x3)\r
+#define MCF_DMA_DCR_SMOD_128 (0x4)\r
+#define MCF_DMA_DCR_SMOD_256 (0x5)\r
+#define MCF_DMA_DCR_SMOD_512 (0x6)\r
+#define MCF_DMA_DCR_SMOD_1K (0x7)\r
+#define MCF_DMA_DCR_SMOD_2K (0x8)\r
+#define MCF_DMA_DCR_SMOD_4K (0x9)\r
+#define MCF_DMA_DCR_SMOD_8K (0xA)\r
+#define MCF_DMA_DCR_SMOD_16K (0xB)\r
+#define MCF_DMA_DCR_SMOD_32K (0xC)\r
+#define MCF_DMA_DCR_SMOD_64K (0xD)\r
+#define MCF_DMA_DCR_SMOD_128K (0xE)\r
+#define MCF_DMA_DCR_SMOD_256K (0xF)\r
+#define MCF_DMA_DCR_START (0x10000)\r
+#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)\r
+#define MCF_DMA_DCR_DSIZE_LONG (0)\r
+#define MCF_DMA_DCR_DSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_DSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_DSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_DINC (0x80000)\r
+#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)\r
+#define MCF_DMA_DCR_SSIZE_LONG (0)\r
+#define MCF_DMA_DCR_SSIZE_BYTE (0x1)\r
+#define MCF_DMA_DCR_SSIZE_WORD (0x2)\r
+#define MCF_DMA_DCR_SSIZE_LINE (0x3)\r
+#define MCF_DMA_DCR_SINC (0x400000)\r
+#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)\r
+#define MCF_DMA_DCR_BWC_16K (0x1)\r
+#define MCF_DMA_DCR_BWC_32K (0x2)\r
+#define MCF_DMA_DCR_BWC_64K (0x3)\r
+#define MCF_DMA_DCR_BWC_128K (0x4)\r
+#define MCF_DMA_DCR_BWC_256K (0x5)\r
+#define MCF_DMA_DCR_BWC_512K (0x6)\r
+#define MCF_DMA_DCR_BWC_1024K (0x7)\r
+#define MCF_DMA_DCR_AA (0x10000000)\r
+#define MCF_DMA_DCR_CS (0x20000000)\r
+#define MCF_DMA_DCR_EEXT (0x40000000)\r
+#define MCF_DMA_DCR_INT (0x80000000)\r
+\r
+\r
+#endif /* __MCF52221_DMA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_DTIM_H__\r
+#define __MCF52221_DTIM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* DMA Timers (DTIM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_DTIM0_DTMR (*(vuint16*)(0x40000400))\r
+#define MCF_DTIM0_DTXMR (*(vuint8 *)(0x40000402))\r
+#define MCF_DTIM0_DTER (*(vuint8 *)(0x40000403))\r
+#define MCF_DTIM0_DTRR (*(vuint32*)(0x40000404))\r
+#define MCF_DTIM0_DTCR (*(vuint32*)(0x40000408))\r
+#define MCF_DTIM0_DTCN (*(vuint32*)(0x4000040C))\r
+\r
+#define MCF_DTIM1_DTMR (*(vuint16*)(0x40000440))\r
+#define MCF_DTIM1_DTXMR (*(vuint8 *)(0x40000442))\r
+#define MCF_DTIM1_DTER (*(vuint8 *)(0x40000443))\r
+#define MCF_DTIM1_DTRR (*(vuint32*)(0x40000444))\r
+#define MCF_DTIM1_DTCR (*(vuint32*)(0x40000448))\r
+#define MCF_DTIM1_DTCN (*(vuint32*)(0x4000044C))\r
+\r
+#define MCF_DTIM2_DTMR (*(vuint16*)(0x40000480))\r
+#define MCF_DTIM2_DTXMR (*(vuint8 *)(0x40000482))\r
+#define MCF_DTIM2_DTER (*(vuint8 *)(0x40000483))\r
+#define MCF_DTIM2_DTRR (*(vuint32*)(0x40000484))\r
+#define MCF_DTIM2_DTCR (*(vuint32*)(0x40000488))\r
+#define MCF_DTIM2_DTCN (*(vuint32*)(0x4000048C))\r
+\r
+#define MCF_DTIM3_DTMR (*(vuint16*)(0x400004C0))\r
+#define MCF_DTIM3_DTXMR (*(vuint8 *)(0x400004C2))\r
+#define MCF_DTIM3_DTER (*(vuint8 *)(0x400004C3))\r
+#define MCF_DTIM3_DTRR (*(vuint32*)(0x400004C4))\r
+#define MCF_DTIM3_DTCR (*(vuint32*)(0x400004C8))\r
+#define MCF_DTIM3_DTCN (*(vuint32*)(0x400004CC))\r
+\r
+#define MCF_DTIM_DTMR(x) (*(vuint16*)(0x40000400 + ((x)*0x40)))\r
+#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(0x40000402 + ((x)*0x40)))\r
+#define MCF_DTIM_DTER(x) (*(vuint8 *)(0x40000403 + ((x)*0x40)))\r
+#define MCF_DTIM_DTRR(x) (*(vuint32*)(0x40000404 + ((x)*0x40)))\r
+#define MCF_DTIM_DTCR(x) (*(vuint32*)(0x40000408 + ((x)*0x40)))\r
+#define MCF_DTIM_DTCN(x) (*(vuint32*)(0x4000040C + ((x)*0x40)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTMR */\r
+#define MCF_DTIM_DTMR_RST (0x1)\r
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)\r
+#define MCF_DTIM_DTMR_CLK_STOP (0)\r
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)\r
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)\r
+#define MCF_DTIM_DTMR_CLK_DTIN (0x6)\r
+#define MCF_DTIM_DTMR_FRR (0x8)\r
+#define MCF_DTIM_DTMR_ORRI (0x10)\r
+#define MCF_DTIM_DTMR_OM (0x20)\r
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)\r
+#define MCF_DTIM_DTMR_CE_NONE (0)\r
+#define MCF_DTIM_DTMR_CE_RISE (0x40)\r
+#define MCF_DTIM_DTMR_CE_FALL (0x80)\r
+#define MCF_DTIM_DTMR_CE_ANY (0xC0)\r
+#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTXMR */\r
+#define MCF_DTIM_DTXMR_MODE16 (0x1)\r
+#define MCF_DTIM_DTXMR_HALTED (0x40)\r
+#define MCF_DTIM_DTXMR_DMAEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTER */\r
+#define MCF_DTIM_DTER_CAP (0x1)\r
+#define MCF_DTIM_DTER_REF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTRR */\r
+#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCR */\r
+#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_DTIM_DTCN */\r
+#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_DTIM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_EPORT_H__\r
+#define __MCF52221_EPORT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Edge Port Module (EPORT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_EPORT_EPPAR (*(vuint16*)(0x40130000))\r
+#define MCF_EPORT_EPDDR (*(vuint8 *)(0x40130002))\r
+#define MCF_EPORT_EPIER (*(vuint8 *)(0x40130003))\r
+#define MCF_EPORT_EPDR (*(vuint8 *)(0x40130004))\r
+#define MCF_EPORT_EPPDR (*(vuint8 *)(0x40130005))\r
+#define MCF_EPORT_EPFR (*(vuint8 *)(0x40130006))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPAR */\r
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)\r
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)\r
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)\r
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)\r
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)\r
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)\r
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)\r
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)\r
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)\r
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)\r
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)\r
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)\r
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)\r
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)\r
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)\r
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)\r
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)\r
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)\r
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)\r
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)\r
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)\r
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)\r
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)\r
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)\r
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)\r
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)\r
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)\r
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)\r
+#define MCF_EPORT_EPPAR_LEVEL (0)\r
+#define MCF_EPORT_EPPAR_RISING (0x1)\r
+#define MCF_EPORT_EPPAR_FALLING (0x2)\r
+#define MCF_EPORT_EPPAR_BOTH (0x3)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDDR */\r
+#define MCF_EPORT_EPDDR_EPDD1 (0x2)\r
+#define MCF_EPORT_EPDDR_EPDD2 (0x4)\r
+#define MCF_EPORT_EPDDR_EPDD3 (0x8)\r
+#define MCF_EPORT_EPDDR_EPDD4 (0x10)\r
+#define MCF_EPORT_EPDDR_EPDD5 (0x20)\r
+#define MCF_EPORT_EPDDR_EPDD6 (0x40)\r
+#define MCF_EPORT_EPDDR_EPDD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPIER */\r
+#define MCF_EPORT_EPIER_EPIE1 (0x2)\r
+#define MCF_EPORT_EPIER_EPIE2 (0x4)\r
+#define MCF_EPORT_EPIER_EPIE3 (0x8)\r
+#define MCF_EPORT_EPIER_EPIE4 (0x10)\r
+#define MCF_EPORT_EPIER_EPIE5 (0x20)\r
+#define MCF_EPORT_EPIER_EPIE6 (0x40)\r
+#define MCF_EPORT_EPIER_EPIE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPDR */\r
+#define MCF_EPORT_EPDR_EPD1 (0x2)\r
+#define MCF_EPORT_EPDR_EPD2 (0x4)\r
+#define MCF_EPORT_EPDR_EPD3 (0x8)\r
+#define MCF_EPORT_EPDR_EPD4 (0x10)\r
+#define MCF_EPORT_EPDR_EPD5 (0x20)\r
+#define MCF_EPORT_EPDR_EPD6 (0x40)\r
+#define MCF_EPORT_EPDR_EPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPPDR */\r
+#define MCF_EPORT_EPPDR_EPPD1 (0x2)\r
+#define MCF_EPORT_EPPDR_EPPD2 (0x4)\r
+#define MCF_EPORT_EPPDR_EPPD3 (0x8)\r
+#define MCF_EPORT_EPPDR_EPPD4 (0x10)\r
+#define MCF_EPORT_EPPDR_EPPD5 (0x20)\r
+#define MCF_EPORT_EPPDR_EPPD6 (0x40)\r
+#define MCF_EPORT_EPPDR_EPPD7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_EPORT_EPFR */\r
+#define MCF_EPORT_EPFR_EPF1 (0x2)\r
+#define MCF_EPORT_EPFR_EPF2 (0x4)\r
+#define MCF_EPORT_EPFR_EPF3 (0x8)\r
+#define MCF_EPORT_EPFR_EPF4 (0x10)\r
+#define MCF_EPORT_EPFR_EPF5 (0x20)\r
+#define MCF_EPORT_EPFR_EPF6 (0x40)\r
+#define MCF_EPORT_EPFR_EPF7 (0x80)\r
+\r
+\r
+#endif /* __MCF52221_EPORT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_GPIO_H__\r
+#define __MCF52221_GPIO_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose I/O (GPIO)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPIO_PORTNQ (*(vuint8 *)(0x40100008))\r
+#define MCF_GPIO_DDRNQ (*(vuint8 *)(0x40100020))\r
+#define MCF_GPIO_SETNQ (*(vuint8 *)(0x40100038))\r
+#define MCF_GPIO_CLRNQ (*(vuint8 *)(0x40100050))\r
+#define MCF_GPIO_PNQPAR (*(vuint16*)(0x40100068))\r
+\r
+#define MCF_GPIO_PORTAN (*(vuint8 *)(0x4010000A))\r
+#define MCF_GPIO_DDRAN (*(vuint8 *)(0x40100022))\r
+#define MCF_GPIO_SETAN (*(vuint8 *)(0x4010003A))\r
+#define MCF_GPIO_CLRAN (*(vuint8 *)(0x40100052))\r
+#define MCF_GPIO_PANPAR (*(vuint8 *)(0x4010006A))\r
+\r
+#define MCF_GPIO_PORTAS (*(vuint8 *)(0x4010000B))\r
+#define MCF_GPIO_DDRAS (*(vuint8 *)(0x40100023))\r
+#define MCF_GPIO_SETAS (*(vuint8 *)(0x4010003B))\r
+#define MCF_GPIO_CLRAS (*(vuint8 *)(0x40100053))\r
+#define MCF_GPIO_PASPAR (*(vuint8 *)(0x4010006B))\r
+\r
+#define MCF_GPIO_PORTQS (*(vuint8 *)(0x4010000C))\r
+#define MCF_GPIO_DDRQS (*(vuint8 *)(0x40100024))\r
+#define MCF_GPIO_SETQS (*(vuint8 *)(0x4010003C))\r
+#define MCF_GPIO_CLRQS (*(vuint8 *)(0x40100054))\r
+#define MCF_GPIO_PQSPAR (*(vuint16*)(0x4010006C))\r
+\r
+#define MCF_GPIO_PORTTA (*(vuint8 *)(0x4010000E))\r
+#define MCF_GPIO_DDRTA (*(vuint8 *)(0x40100026))\r
+#define MCF_GPIO_SETTA (*(vuint8 *)(0x4010003E))\r
+#define MCF_GPIO_CLRTA (*(vuint8 *)(0x40100056))\r
+#define MCF_GPIO_PTAPAR (*(vuint8 *)(0x4010006E))\r
+\r
+#define MCF_GPIO_PORTTC (*(vuint8 *)(0x4010000F))\r
+#define MCF_GPIO_DDRTC (*(vuint8 *)(0x40100027))\r
+#define MCF_GPIO_SETTC (*(vuint8 *)(0x4010003F))\r
+#define MCF_GPIO_CLRTC (*(vuint8 *)(0x40100057))\r
+#define MCF_GPIO_PTCPAR (*(vuint8 *)(0x4010006F))\r
+\r
+#define MCF_GPIO_PORTUA (*(vuint8 *)(0x40100011))\r
+#define MCF_GPIO_DDRUA (*(vuint8 *)(0x40100029))\r
+#define MCF_GPIO_SETUA (*(vuint8 *)(0x40100041))\r
+#define MCF_GPIO_CLRUA (*(vuint8 *)(0x40100059))\r
+#define MCF_GPIO_PUAPAR (*(vuint8 *)(0x40100071))\r
+\r
+#define MCF_GPIO_PORTUB (*(vuint8 *)(0x40100012))\r
+#define MCF_GPIO_DDRUB (*(vuint8 *)(0x4010002A))\r
+#define MCF_GPIO_SETUB (*(vuint8 *)(0x40100042))\r
+#define MCF_GPIO_CLRUB (*(vuint8 *)(0x4010005A))\r
+#define MCF_GPIO_PUBPAR (*(vuint8 *)(0x40100072))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTNQ */\r
+#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)\r
+#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)\r
+#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)\r
+#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)\r
+#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)\r
+#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)\r
+#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRNQ */\r
+#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)\r
+#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)\r
+#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)\r
+#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)\r
+#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)\r
+#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)\r
+#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETNQ */\r
+#define MCF_GPIO_SETNQ_SETNQ1 (0x2)\r
+#define MCF_GPIO_SETNQ_SETNQ2 (0x4)\r
+#define MCF_GPIO_SETNQ_SETNQ3 (0x8)\r
+#define MCF_GPIO_SETNQ_SETNQ4 (0x10)\r
+#define MCF_GPIO_SETNQ_SETNQ5 (0x20)\r
+#define MCF_GPIO_SETNQ_SETNQ6 (0x40)\r
+#define MCF_GPIO_SETNQ_SETNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRNQ */\r
+#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)\r
+#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)\r
+#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)\r
+#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)\r
+#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)\r
+#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)\r
+#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PNQPAR */\r
+#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)\r
+#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8)\r
+#define MCF_GPIO_PNQPAR_IRQ1_USB_ALT_CLK (0xC)\r
+#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10)\r
+#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)\r
+#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100)\r
+#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)\r
+#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)\r
+#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)\r
+#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)\r
+#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAN */\r
+#define MCF_GPIO_PORTAN_PORTAN0 (0x1)\r
+#define MCF_GPIO_PORTAN_PORTAN1 (0x2)\r
+#define MCF_GPIO_PORTAN_PORTAN2 (0x4)\r
+#define MCF_GPIO_PORTAN_PORTAN3 (0x8)\r
+#define MCF_GPIO_PORTAN_PORTAN4 (0x10)\r
+#define MCF_GPIO_PORTAN_PORTAN5 (0x20)\r
+#define MCF_GPIO_PORTAN_PORTAN6 (0x40)\r
+#define MCF_GPIO_PORTAN_PORTAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAN */\r
+#define MCF_GPIO_DDRAN_DDRAN0 (0x1)\r
+#define MCF_GPIO_DDRAN_DDRAN1 (0x2)\r
+#define MCF_GPIO_DDRAN_DDRAN2 (0x4)\r
+#define MCF_GPIO_DDRAN_DDRAN3 (0x8)\r
+#define MCF_GPIO_DDRAN_DDRAN4 (0x10)\r
+#define MCF_GPIO_DDRAN_DDRAN5 (0x20)\r
+#define MCF_GPIO_DDRAN_DDRAN6 (0x40)\r
+#define MCF_GPIO_DDRAN_DDRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAN */\r
+#define MCF_GPIO_SETAN_SETAN0 (0x1)\r
+#define MCF_GPIO_SETAN_SETAN1 (0x2)\r
+#define MCF_GPIO_SETAN_SETAN2 (0x4)\r
+#define MCF_GPIO_SETAN_SETAN3 (0x8)\r
+#define MCF_GPIO_SETAN_SETAN4 (0x10)\r
+#define MCF_GPIO_SETAN_SETAN5 (0x20)\r
+#define MCF_GPIO_SETAN_SETAN6 (0x40)\r
+#define MCF_GPIO_SETAN_SETAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAN */\r
+#define MCF_GPIO_CLRAN_CLRAN0 (0x1)\r
+#define MCF_GPIO_CLRAN_CLRAN1 (0x2)\r
+#define MCF_GPIO_CLRAN_CLRAN2 (0x4)\r
+#define MCF_GPIO_CLRAN_CLRAN3 (0x8)\r
+#define MCF_GPIO_CLRAN_CLRAN4 (0x10)\r
+#define MCF_GPIO_CLRAN_CLRAN5 (0x20)\r
+#define MCF_GPIO_CLRAN_CLRAN6 (0x40)\r
+#define MCF_GPIO_CLRAN_CLRAN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PANPAR */\r
+#define MCF_GPIO_PANPAR_PANPAR0 (0x1)\r
+#define MCF_GPIO_PANPAR_AN0_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)\r
+#define MCF_GPIO_PANPAR_PANPAR1 (0x2)\r
+#define MCF_GPIO_PANPAR_AN1_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)\r
+#define MCF_GPIO_PANPAR_PANPAR2 (0x4)\r
+#define MCF_GPIO_PANPAR_AN2_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)\r
+#define MCF_GPIO_PANPAR_PANPAR3 (0x8)\r
+#define MCF_GPIO_PANPAR_AN3_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)\r
+#define MCF_GPIO_PANPAR_PANPAR4 (0x10)\r
+#define MCF_GPIO_PANPAR_AN4_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)\r
+#define MCF_GPIO_PANPAR_PANPAR5 (0x20)\r
+#define MCF_GPIO_PANPAR_AN5_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)\r
+#define MCF_GPIO_PANPAR_PANPAR6 (0x40)\r
+#define MCF_GPIO_PANPAR_AN6_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)\r
+#define MCF_GPIO_PANPAR_PANPAR7 (0x80)\r
+#define MCF_GPIO_PANPAR_AN7_GPIO (0)\r
+#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTAS */\r
+#define MCF_GPIO_PORTAS_PORTAS0 (0x1)\r
+#define MCF_GPIO_PORTAS_PORTAS1 (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRAS */\r
+#define MCF_GPIO_DDRAS_DDRAS0 (0x1)\r
+#define MCF_GPIO_DDRAS_DDRAS1 (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETAS */\r
+#define MCF_GPIO_SETAS_SETAS0 (0x1)\r
+#define MCF_GPIO_SETAS_SETAS1 (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRAS */\r
+#define MCF_GPIO_CLRAS_CLRAS0 (0x1)\r
+#define MCF_GPIO_CLRAS_CLRAS1 (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PASPAR */\r
+#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PASPAR_SCL_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SCL_SCL (0x1)\r
+#define MCF_GPIO_PASPAR_SCL_USB_DMI (0x2)\r
+#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3)\r
+#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PASPAR_SDA_GPIO (0)\r
+#define MCF_GPIO_PASPAR_SDA_SDA (0x4)\r
+#define MCF_GPIO_PASPAR_SDA_USB_DPI (0x8)\r
+#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTQS */\r
+#define MCF_GPIO_PORTQS_PORTQS0 (0x1)\r
+#define MCF_GPIO_PORTQS_PORTQS1 (0x2)\r
+#define MCF_GPIO_PORTQS_PORTQS2 (0x4)\r
+#define MCF_GPIO_PORTQS_PORTQS3 (0x8)\r
+#define MCF_GPIO_PORTQS_PORTQS4 (0x10)\r
+#define MCF_GPIO_PORTQS_PORTQS5 (0x20)\r
+#define MCF_GPIO_PORTQS_PORTQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRQS */\r
+#define MCF_GPIO_DDRQS_DDRQS0 (0x1)\r
+#define MCF_GPIO_DDRQS_DDRQS1 (0x2)\r
+#define MCF_GPIO_DDRQS_DDRQS2 (0x4)\r
+#define MCF_GPIO_DDRQS_DDRQS3 (0x8)\r
+#define MCF_GPIO_DDRQS_DDRQS4 (0x10)\r
+#define MCF_GPIO_DDRQS_DDRQS5 (0x20)\r
+#define MCF_GPIO_DDRQS_DDRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETQS */\r
+#define MCF_GPIO_SETQS_SETQS0 (0x1)\r
+#define MCF_GPIO_SETQS_SETQS1 (0x2)\r
+#define MCF_GPIO_SETQS_SETQS2 (0x4)\r
+#define MCF_GPIO_SETQS_SETQS3 (0x8)\r
+#define MCF_GPIO_SETQS_SETQS4 (0x10)\r
+#define MCF_GPIO_SETQS_SETQS5 (0x20)\r
+#define MCF_GPIO_SETQS_SETQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRQS */\r
+#define MCF_GPIO_CLRQS_CLRQS0 (0x1)\r
+#define MCF_GPIO_CLRQS_CLRQS1 (0x2)\r
+#define MCF_GPIO_CLRQS_CLRQS2 (0x4)\r
+#define MCF_GPIO_CLRQS_CLRQS3 (0x8)\r
+#define MCF_GPIO_CLRQS_CLRQS4 (0x10)\r
+#define MCF_GPIO_CLRQS_CLRQS5 (0x20)\r
+#define MCF_GPIO_CLRQS_CLRQS6 (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PQSPAR */\r
+#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)\r
+#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)\r
+#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)\r
+#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20)\r
+#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)\r
+#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)\r
+#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS1_USB_PULLUP (0x300)\r
+#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS2_USB_DM_PD (0xC00)\r
+#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)\r
+#define MCF_GPIO_PQSPAR_QSPI_CS3_USB_DP_PD (0x3000)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTA */\r
+#define MCF_GPIO_PORTTA_PORTTA0 (0x1)\r
+#define MCF_GPIO_PORTTA_PORTTA1 (0x2)\r
+#define MCF_GPIO_PORTTA_PORTTA2 (0x4)\r
+#define MCF_GPIO_PORTTA_PORTTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTA */\r
+#define MCF_GPIO_DDRTA_DDRTA0 (0x1)\r
+#define MCF_GPIO_DDRTA_DDRTA1 (0x2)\r
+#define MCF_GPIO_DDRTA_DDRTA2 (0x4)\r
+#define MCF_GPIO_DDRTA_DDRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTA */\r
+#define MCF_GPIO_SETTA_SETTA0 (0x1)\r
+#define MCF_GPIO_SETTA_SETTA1 (0x2)\r
+#define MCF_GPIO_SETTA_SETTA2 (0x4)\r
+#define MCF_GPIO_SETTA_SETTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTA */\r
+#define MCF_GPIO_CLRTA_CLRTA0 (0x1)\r
+#define MCF_GPIO_CLRTA_CLRTA1 (0x2)\r
+#define MCF_GPIO_CLRTA_CLRTA2 (0x4)\r
+#define MCF_GPIO_CLRTA_CLRTA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTAPAR */\r
+#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTAPAR_GPT0_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1)\r
+#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3)\r
+#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTAPAR_GPT1_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4)\r
+#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC)\r
+#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTAPAR_GPT2_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10)\r
+#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30)\r
+#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTAPAR_GPT3_GPIO (0)\r
+#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40)\r
+#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTTC */\r
+#define MCF_GPIO_PORTTC_PORTTC0 (0x1)\r
+#define MCF_GPIO_PORTTC_PORTTC1 (0x2)\r
+#define MCF_GPIO_PORTTC_PORTTC2 (0x4)\r
+#define MCF_GPIO_PORTTC_PORTTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRTC */\r
+#define MCF_GPIO_DDRTC_DDRTC0 (0x1)\r
+#define MCF_GPIO_DDRTC_DDRTC1 (0x2)\r
+#define MCF_GPIO_DDRTC_DDRTC2 (0x4)\r
+#define MCF_GPIO_DDRTC_DDRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETTC */\r
+#define MCF_GPIO_SETTC_SETTC0 (0x1)\r
+#define MCF_GPIO_SETTC_SETTC1 (0x2)\r
+#define MCF_GPIO_SETTC_SETTC2 (0x4)\r
+#define MCF_GPIO_SETTC_SETTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRTC */\r
+#define MCF_GPIO_CLRTC_CLRTC0 (0x1)\r
+#define MCF_GPIO_CLRTC_CLRTC1 (0x2)\r
+#define MCF_GPIO_CLRTC_CLRTC2 (0x4)\r
+#define MCF_GPIO_CLRTC_CLRTC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PTCPAR */\r
+#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)\r
+#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)\r
+#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)\r
+#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)\r
+#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)\r
+#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)\r
+#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)\r
+#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)\r
+#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)\r
+#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUA */\r
+#define MCF_GPIO_PORTUA_PORTUA0 (0x1)\r
+#define MCF_GPIO_PORTUA_PORTUA1 (0x2)\r
+#define MCF_GPIO_PORTUA_PORTUA2 (0x4)\r
+#define MCF_GPIO_PORTUA_PORTUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUA */\r
+#define MCF_GPIO_DDRUA_DDRUA0 (0x1)\r
+#define MCF_GPIO_DDRUA_DDRUA1 (0x2)\r
+#define MCF_GPIO_DDRUA_DDRUA2 (0x4)\r
+#define MCF_GPIO_DDRUA_DDRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUA */\r
+#define MCF_GPIO_SETUA_SETUA0 (0x1)\r
+#define MCF_GPIO_SETUA_SETUA1 (0x2)\r
+#define MCF_GPIO_SETUA_SETUA2 (0x4)\r
+#define MCF_GPIO_SETUA_SETUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUA */\r
+#define MCF_GPIO_CLRUA_CLRUA0 (0x1)\r
+#define MCF_GPIO_CLRUA_CLRUA1 (0x2)\r
+#define MCF_GPIO_CLRUA_CLRUA2 (0x4)\r
+#define MCF_GPIO_CLRUA_CLRUA3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUAPAR */\r
+#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)\r
+#define MCF_GPIO_PUAPAR_UTXD0_USB_SUSPEND (0x3)\r
+#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)\r
+#define MCF_GPIO_PUAPAR_URXD0_USB_RCV (0xC)\r
+#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)\r
+#define MCF_GPIO_PUAPAR_URTS0_USB_VBUSD (0x30)\r
+#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)\r
+#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)\r
+#define MCF_GPIO_PUAPAR_UCTS0_USB_VBUSE (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PORTUB */\r
+#define MCF_GPIO_PORTUB_PORTUB0 (0x1)\r
+#define MCF_GPIO_PORTUB_PORTUB1 (0x2)\r
+#define MCF_GPIO_PORTUB_PORTUB2 (0x4)\r
+#define MCF_GPIO_PORTUB_PORTUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_DDRUB */\r
+#define MCF_GPIO_DDRUB_DDRUB0 (0x1)\r
+#define MCF_GPIO_DDRUB_DDRUB1 (0x2)\r
+#define MCF_GPIO_DDRUB_DDRUB2 (0x4)\r
+#define MCF_GPIO_DDRUB_DDRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_SETUB */\r
+#define MCF_GPIO_SETUB_SETUB0 (0x1)\r
+#define MCF_GPIO_SETUB_SETUB1 (0x2)\r
+#define MCF_GPIO_SETUB_SETUB2 (0x4)\r
+#define MCF_GPIO_SETUB_SETUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_CLRUB */\r
+#define MCF_GPIO_CLRUB_CLRUB0 (0x1)\r
+#define MCF_GPIO_CLRUB_CLRUB1 (0x2)\r
+#define MCF_GPIO_CLRUB_CLRUB2 (0x4)\r
+#define MCF_GPIO_CLRUB_CLRUB3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPIO_PUBPAR */\r
+#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)\r
+#define MCF_GPIO_PUBPAR_UTXD1_USB_SPEED (0x3)\r
+#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)\r
+#define MCF_GPIO_PUBPAR_URXD1_USB_OE (0xC)\r
+#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)\r
+#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)\r
+#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)\r
+#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)\r
+#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)\r
+#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)\r
+#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)\r
+#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)\r
+#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)\r
+\r
+\r
+#endif /* __MCF52221_GPIO_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_GPTA_H__\r
+#define __MCF52221_GPTA_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* General Purpose Timer Module (GPT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_GPTA_GPTIOS (*(vuint8 *)(0x401A0000))\r
+#define MCF_GPTA_GPTCFORC (*(vuint8 *)(0x401A0001))\r
+#define MCF_GPTA_GPTOC3M (*(vuint8 *)(0x401A0002))\r
+#define MCF_GPTA_GPTOC3D (*(vuint8 *)(0x401A0003))\r
+#define MCF_GPTA_GPTCNT (*(vuint16*)(0x401A0004))\r
+#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(0x401A0006))\r
+#define MCF_GPTA_GPTTOV (*(vuint8 *)(0x401A0008))\r
+#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(0x401A0009))\r
+#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(0x401A000B))\r
+#define MCF_GPTA_GPTIE (*(vuint8 *)(0x401A000C))\r
+#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(0x401A000D))\r
+#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(0x401A000E))\r
+#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(0x401A000F))\r
+#define MCF_GPTA_GPTC0 (*(vuint16*)(0x401A0010))\r
+#define MCF_GPTA_GPTC1 (*(vuint16*)(0x401A0012))\r
+#define MCF_GPTA_GPTC2 (*(vuint16*)(0x401A0014))\r
+#define MCF_GPTA_GPTC3 (*(vuint16*)(0x401A0016))\r
+#define MCF_GPTA_GPTPACTL (*(vuint8 *)(0x401A0018))\r
+#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(0x401A0019))\r
+#define MCF_GPTA_GPTPACNT (*(vuint16*)(0x401A001A))\r
+#define MCF_GPTA_GPTPORT (*(vuint8 *)(0x401A001D))\r
+#define MCF_GPTA_GPTDDR (*(vuint8 *)(0x401A001E))\r
+#define MCF_GPTA_GPTC(x) (*(vuint16*)(0x401A0010 + ((x)*0x2)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIOS */\r
+#define MCF_GPTA_GPTIOS_IOS0 (0x1)\r
+#define MCF_GPTA_GPTIOS_IOS1 (0x2)\r
+#define MCF_GPTA_GPTIOS_IOS2 (0x4)\r
+#define MCF_GPTA_GPTIOS_IOS3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCFORC */\r
+#define MCF_GPTA_GPTCFORC_FOC0 (0x1)\r
+#define MCF_GPTA_GPTCFORC_FOC1 (0x2)\r
+#define MCF_GPTA_GPTCFORC_FOC2 (0x4)\r
+#define MCF_GPTA_GPTCFORC_FOC3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3M */\r
+#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)\r
+#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)\r
+#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)\r
+#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTOC3D */\r
+#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)\r
+#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)\r
+#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)\r
+#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCNT */\r
+#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */\r
+#define MCF_GPTA_GPTSCR1_TFFCA (0x10)\r
+#define MCF_GPTA_GPTSCR1_GPTEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTTOV */\r
+#define MCF_GPTA_GPTTOV_TOV0 (0x1)\r
+#define MCF_GPTA_GPTTOV_TOV1 (0x2)\r
+#define MCF_GPTA_GPTTOV_TOV2 (0x4)\r
+#define MCF_GPTA_GPTTOV_TOV3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */\r
+#define MCF_GPTA_GPTCTL1_OL0 (0x1)\r
+#define MCF_GPTA_GPTCTL1_OM0 (0x2)\r
+#define MCF_GPTA_GPTCTL1_OL1 (0x4)\r
+#define MCF_GPTA_GPTCTL1_OM1 (0x8)\r
+#define MCF_GPTA_GPTCTL1_OL2 (0x10)\r
+#define MCF_GPTA_GPTCTL1_OM2 (0x20)\r
+#define MCF_GPTA_GPTCTL1_OL3 (0x40)\r
+#define MCF_GPTA_GPTCTL1_OM3 (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)\r
+#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */\r
+#define MCF_GPTA_GPTCTL2_EDG0A (0x1)\r
+#define MCF_GPTA_GPTCTL2_EDG0B (0x2)\r
+#define MCF_GPTA_GPTCTL2_EDG1A (0x4)\r
+#define MCF_GPTA_GPTCTL2_EDG1B (0x8)\r
+#define MCF_GPTA_GPTCTL2_EDG2A (0x10)\r
+#define MCF_GPTA_GPTCTL2_EDG2B (0x20)\r
+#define MCF_GPTA_GPTCTL2_EDG3A (0x40)\r
+#define MCF_GPTA_GPTCTL2_EDG3B (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)\r
+#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)\r
+#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)\r
+#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)\r
+#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTIE */\r
+#define MCF_GPTA_GPTIE_CI0 (0x1)\r
+#define MCF_GPTA_GPTIE_CI1 (0x2)\r
+#define MCF_GPTA_GPTIE_CI2 (0x4)\r
+#define MCF_GPTA_GPTIE_CI3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */\r
+#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)\r
+#define MCF_GPTA_GPTSCR2_PR_1 (0)\r
+#define MCF_GPTA_GPTSCR2_PR_2 (0x1)\r
+#define MCF_GPTA_GPTSCR2_PR_4 (0x2)\r
+#define MCF_GPTA_GPTSCR2_PR_8 (0x3)\r
+#define MCF_GPTA_GPTSCR2_PR_16 (0x4)\r
+#define MCF_GPTA_GPTSCR2_PR_32 (0x5)\r
+#define MCF_GPTA_GPTSCR2_PR_64 (0x6)\r
+#define MCF_GPTA_GPTSCR2_PR_128 (0x7)\r
+#define MCF_GPTA_GPTSCR2_TCRE (0x8)\r
+#define MCF_GPTA_GPTSCR2_RDPT (0x10)\r
+#define MCF_GPTA_GPTSCR2_PUPT (0x20)\r
+#define MCF_GPTA_GPTSCR2_TOI (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */\r
+#define MCF_GPTA_GPTFLG1_CF0 (0x1)\r
+#define MCF_GPTA_GPTFLG1_CF1 (0x2)\r
+#define MCF_GPTA_GPTFLG1_CF2 (0x4)\r
+#define MCF_GPTA_GPTFLG1_CF3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */\r
+#define MCF_GPTA_GPTFLG2_TOF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTC */\r
+#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACTL */\r
+#define MCF_GPTA_GPTPACTL_PAI (0x1)\r
+#define MCF_GPTA_GPTPACTL_PAOVI (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)\r
+#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)\r
+#define MCF_GPTA_GPTPACTL_PEDGE (0x10)\r
+#define MCF_GPTA_GPTPACTL_PAMOD (0x20)\r
+#define MCF_GPTA_GPTPACTL_PAE (0x40)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */\r
+#define MCF_GPTA_GPTPAFLG_PAIF (0x1)\r
+#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPACNT */\r
+#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTPORT */\r
+#define MCF_GPTA_GPTPORT_PORTT0 (0x1)\r
+#define MCF_GPTA_GPTPORT_PORTT1 (0x2)\r
+#define MCF_GPTA_GPTPORT_PORTT2 (0x4)\r
+#define MCF_GPTA_GPTPORT_PORTT3 (0x8)\r
+\r
+/* Bit definitions and macros for MCF_GPTA_GPTDDR */\r
+#define MCF_GPTA_GPTDDR_DDRT0 (0x1)\r
+#define MCF_GPTA_GPTDDR_DDRT1 (0x2)\r
+#define MCF_GPTA_GPTDDR_DDRT2 (0x4)\r
+#define MCF_GPTA_GPTDDR_DDRT3 (0x8)\r
+\r
+\r
+#endif /* __MCF52221_GPTA_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_I2C_H__\r
+#define __MCF52221_I2C_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* I2C Module (I2C)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_I2C_I2ADR (*(vuint8 *)(0x40000300))\r
+#define MCF_I2C_I2FDR (*(vuint8 *)(0x40000304))\r
+#define MCF_I2C_I2CR (*(vuint8 *)(0x40000308))\r
+#define MCF_I2C_I2SR (*(vuint8 *)(0x4000030C))\r
+#define MCF_I2C_I2DR (*(vuint8 *)(0x40000310))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2ADR */\r
+#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2FDR */\r
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2CR */\r
+#define MCF_I2C_I2CR_RSTA (0x4)\r
+#define MCF_I2C_I2CR_TXAK (0x8)\r
+#define MCF_I2C_I2CR_MTX (0x10)\r
+#define MCF_I2C_I2CR_MSTA (0x20)\r
+#define MCF_I2C_I2CR_IIEN (0x40)\r
+#define MCF_I2C_I2CR_IEN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2SR */\r
+#define MCF_I2C_I2SR_RXAK (0x1)\r
+#define MCF_I2C_I2SR_IIF (0x2)\r
+#define MCF_I2C_I2SR_SRW (0x4)\r
+#define MCF_I2C_I2SR_IAL (0x10)\r
+#define MCF_I2C_I2SR_IBB (0x20)\r
+#define MCF_I2C_I2SR_IAAS (0x40)\r
+#define MCF_I2C_I2SR_ICF (0x80)\r
+\r
+/* Bit definitions and macros for MCF_I2C_I2DR */\r
+#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_I2C_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_INTC_H__\r
+#define __MCF52221_INTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Interrupt Controller (INTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_INTC0_IPRH (*(vuint32*)(0x40000C00))\r
+#define MCF_INTC0_IPRL (*(vuint32*)(0x40000C04))\r
+#define MCF_INTC0_IMRH (*(vuint32*)(0x40000C08))\r
+#define MCF_INTC0_IMRL (*(vuint32*)(0x40000C0C))\r
+#define MCF_INTC0_INTFRCH (*(vuint32*)(0x40000C10))\r
+#define MCF_INTC0_INTFRCL (*(vuint32*)(0x40000C14))\r
+#define MCF_INTC0_IRLR (*(vuint8 *)(0x40000C18))\r
+#define MCF_INTC0_IACKLPR (*(vuint8 *)(0x40000C19))\r
+#define MCF_INTC0_ICR01 (*(vuint8 *)(0x40000C41))\r
+#define MCF_INTC0_ICR02 (*(vuint8 *)(0x40000C42))\r
+#define MCF_INTC0_ICR03 (*(vuint8 *)(0x40000C43))\r
+#define MCF_INTC0_ICR04 (*(vuint8 *)(0x40000C44))\r
+#define MCF_INTC0_ICR05 (*(vuint8 *)(0x40000C45))\r
+#define MCF_INTC0_ICR06 (*(vuint8 *)(0x40000C46))\r
+#define MCF_INTC0_ICR07 (*(vuint8 *)(0x40000C47))\r
+#define MCF_INTC0_ICR08 (*(vuint8 *)(0x40000C48))\r
+#define MCF_INTC0_ICR09 (*(vuint8 *)(0x40000C49))\r
+#define MCF_INTC0_ICR10 (*(vuint8 *)(0x40000C4A))\r
+#define MCF_INTC0_ICR11 (*(vuint8 *)(0x40000C4B))\r
+#define MCF_INTC0_ICR12 (*(vuint8 *)(0x40000C4C))\r
+#define MCF_INTC0_ICR13 (*(vuint8 *)(0x40000C4D))\r
+#define MCF_INTC0_ICR14 (*(vuint8 *)(0x40000C4E))\r
+#define MCF_INTC0_ICR15 (*(vuint8 *)(0x40000C4F))\r
+#define MCF_INTC0_ICR16 (*(vuint8 *)(0x40000C50))\r
+#define MCF_INTC0_ICR17 (*(vuint8 *)(0x40000C51))\r
+#define MCF_INTC0_ICR18 (*(vuint8 *)(0x40000C52))\r
+#define MCF_INTC0_ICR19 (*(vuint8 *)(0x40000C53))\r
+#define MCF_INTC0_ICR20 (*(vuint8 *)(0x40000C54))\r
+#define MCF_INTC0_ICR21 (*(vuint8 *)(0x40000C55))\r
+#define MCF_INTC0_ICR22 (*(vuint8 *)(0x40000C56))\r
+#define MCF_INTC0_ICR23 (*(vuint8 *)(0x40000C57))\r
+#define MCF_INTC0_ICR24 (*(vuint8 *)(0x40000C58))\r
+#define MCF_INTC0_ICR25 (*(vuint8 *)(0x40000C59))\r
+#define MCF_INTC0_ICR26 (*(vuint8 *)(0x40000C5A))\r
+#define MCF_INTC0_ICR27 (*(vuint8 *)(0x40000C5B))\r
+#define MCF_INTC0_ICR28 (*(vuint8 *)(0x40000C5C))\r
+#define MCF_INTC0_ICR29 (*(vuint8 *)(0x40000C5D))\r
+#define MCF_INTC0_ICR30 (*(vuint8 *)(0x40000C5E))\r
+#define MCF_INTC0_ICR31 (*(vuint8 *)(0x40000C5F))\r
+#define MCF_INTC0_ICR32 (*(vuint8 *)(0x40000C60))\r
+#define MCF_INTC0_ICR33 (*(vuint8 *)(0x40000C61))\r
+#define MCF_INTC0_ICR34 (*(vuint8 *)(0x40000C62))\r
+#define MCF_INTC0_ICR35 (*(vuint8 *)(0x40000C63))\r
+#define MCF_INTC0_ICR36 (*(vuint8 *)(0x40000C64))\r
+#define MCF_INTC0_ICR37 (*(vuint8 *)(0x40000C65))\r
+#define MCF_INTC0_ICR38 (*(vuint8 *)(0x40000C66))\r
+#define MCF_INTC0_ICR39 (*(vuint8 *)(0x40000C67))\r
+#define MCF_INTC0_ICR40 (*(vuint8 *)(0x40000C68))\r
+#define MCF_INTC0_ICR41 (*(vuint8 *)(0x40000C69))\r
+#define MCF_INTC0_ICR42 (*(vuint8 *)(0x40000C6A))\r
+#define MCF_INTC0_ICR43 (*(vuint8 *)(0x40000C6B))\r
+#define MCF_INTC0_ICR44 (*(vuint8 *)(0x40000C6C))\r
+#define MCF_INTC0_ICR45 (*(vuint8 *)(0x40000C6D))\r
+#define MCF_INTC0_ICR46 (*(vuint8 *)(0x40000C6E))\r
+#define MCF_INTC0_ICR47 (*(vuint8 *)(0x40000C6F))\r
+#define MCF_INTC0_ICR48 (*(vuint8 *)(0x40000C70))\r
+#define MCF_INTC0_ICR49 (*(vuint8 *)(0x40000C71))\r
+#define MCF_INTC0_ICR50 (*(vuint8 *)(0x40000C72))\r
+#define MCF_INTC0_ICR51 (*(vuint8 *)(0x40000C73))\r
+#define MCF_INTC0_ICR52 (*(vuint8 *)(0x40000C74))\r
+#define MCF_INTC0_ICR53 (*(vuint8 *)(0x40000C75))\r
+#define MCF_INTC0_ICR54 (*(vuint8 *)(0x40000C76))\r
+#define MCF_INTC0_ICR55 (*(vuint8 *)(0x40000C77))\r
+#define MCF_INTC0_ICR56 (*(vuint8 *)(0x40000C78))\r
+#define MCF_INTC0_ICR57 (*(vuint8 *)(0x40000C79))\r
+#define MCF_INTC0_ICR58 (*(vuint8 *)(0x40000C7A))\r
+#define MCF_INTC0_ICR59 (*(vuint8 *)(0x40000C7B))\r
+#define MCF_INTC0_ICR60 (*(vuint8 *)(0x40000C7C))\r
+#define MCF_INTC0_ICR61 (*(vuint8 *)(0x40000C7D))\r
+#define MCF_INTC0_ICR62 (*(vuint8 *)(0x40000C7E))\r
+#define MCF_INTC0_ICR63 (*(vuint8 *)(0x40000C7F))\r
+#define MCF_INTC0_SWIACK (*(vuint8 *)(0x40000CE0))\r
+#define MCF_INTC0_L1IACK (*(vuint8 *)(0x40000CE4))\r
+#define MCF_INTC0_L2IACK (*(vuint8 *)(0x40000CE8))\r
+#define MCF_INTC0_L3IACK (*(vuint8 *)(0x40000CEC))\r
+#define MCF_INTC0_L4IACK (*(vuint8 *)(0x40000CF0))\r
+#define MCF_INTC0_L5IACK (*(vuint8 *)(0x40000CF4))\r
+#define MCF_INTC0_L6IACK (*(vuint8 *)(0x40000CF8))\r
+#define MCF_INTC0_L7IACK (*(vuint8 *)(0x40000CFC))\r
+#define MCF_INTC0_ICR(x) (*(vuint8 *)(0x40000C41 + ((x-1)*0x1)))\r
+#define MCF_INTC0_LIACK(x) (*(vuint8 *)(0x40000CE4 + ((x-1)*0x4)))\r
+\r
+\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRH */\r
+#define MCF_INTC_IPRH_INT32 (0x1)\r
+#define MCF_INTC_IPRH_INT33 (0x2)\r
+#define MCF_INTC_IPRH_INT34 (0x4)\r
+#define MCF_INTC_IPRH_INT35 (0x8)\r
+#define MCF_INTC_IPRH_INT36 (0x10)\r
+#define MCF_INTC_IPRH_INT37 (0x20)\r
+#define MCF_INTC_IPRH_INT38 (0x40)\r
+#define MCF_INTC_IPRH_INT39 (0x80)\r
+#define MCF_INTC_IPRH_INT40 (0x100)\r
+#define MCF_INTC_IPRH_INT41 (0x200)\r
+#define MCF_INTC_IPRH_INT42 (0x400)\r
+#define MCF_INTC_IPRH_INT43 (0x800)\r
+#define MCF_INTC_IPRH_INT44 (0x1000)\r
+#define MCF_INTC_IPRH_INT45 (0x2000)\r
+#define MCF_INTC_IPRH_INT46 (0x4000)\r
+#define MCF_INTC_IPRH_INT47 (0x8000)\r
+#define MCF_INTC_IPRH_INT48 (0x10000)\r
+#define MCF_INTC_IPRH_INT49 (0x20000)\r
+#define MCF_INTC_IPRH_INT50 (0x40000)\r
+#define MCF_INTC_IPRH_INT51 (0x80000)\r
+#define MCF_INTC_IPRH_INT52 (0x100000)\r
+#define MCF_INTC_IPRH_INT53 (0x200000)\r
+#define MCF_INTC_IPRH_INT54 (0x400000)\r
+#define MCF_INTC_IPRH_INT55 (0x800000)\r
+#define MCF_INTC_IPRH_INT56 (0x1000000)\r
+#define MCF_INTC_IPRH_INT57 (0x2000000)\r
+#define MCF_INTC_IPRH_INT58 (0x4000000)\r
+#define MCF_INTC_IPRH_INT59 (0x8000000)\r
+#define MCF_INTC_IPRH_INT60 (0x10000000)\r
+#define MCF_INTC_IPRH_INT61 (0x20000000)\r
+#define MCF_INTC_IPRH_INT62 (0x40000000)\r
+#define MCF_INTC_IPRH_INT63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IPRL */\r
+#define MCF_INTC_IPRL_INT1 (0x2)\r
+#define MCF_INTC_IPRL_INT2 (0x4)\r
+#define MCF_INTC_IPRL_INT3 (0x8)\r
+#define MCF_INTC_IPRL_INT4 (0x10)\r
+#define MCF_INTC_IPRL_INT5 (0x20)\r
+#define MCF_INTC_IPRL_INT6 (0x40)\r
+#define MCF_INTC_IPRL_INT7 (0x80)\r
+#define MCF_INTC_IPRL_INT8 (0x100)\r
+#define MCF_INTC_IPRL_INT9 (0x200)\r
+#define MCF_INTC_IPRL_INT10 (0x400)\r
+#define MCF_INTC_IPRL_INT11 (0x800)\r
+#define MCF_INTC_IPRL_INT12 (0x1000)\r
+#define MCF_INTC_IPRL_INT13 (0x2000)\r
+#define MCF_INTC_IPRL_INT14 (0x4000)\r
+#define MCF_INTC_IPRL_INT15 (0x8000)\r
+#define MCF_INTC_IPRL_INT16 (0x10000)\r
+#define MCF_INTC_IPRL_INT17 (0x20000)\r
+#define MCF_INTC_IPRL_INT18 (0x40000)\r
+#define MCF_INTC_IPRL_INT19 (0x80000)\r
+#define MCF_INTC_IPRL_INT20 (0x100000)\r
+#define MCF_INTC_IPRL_INT21 (0x200000)\r
+#define MCF_INTC_IPRL_INT22 (0x400000)\r
+#define MCF_INTC_IPRL_INT23 (0x800000)\r
+#define MCF_INTC_IPRL_INT24 (0x1000000)\r
+#define MCF_INTC_IPRL_INT25 (0x2000000)\r
+#define MCF_INTC_IPRL_INT26 (0x4000000)\r
+#define MCF_INTC_IPRL_INT27 (0x8000000)\r
+#define MCF_INTC_IPRL_INT28 (0x10000000)\r
+#define MCF_INTC_IPRL_INT29 (0x20000000)\r
+#define MCF_INTC_IPRL_INT30 (0x40000000)\r
+#define MCF_INTC_IPRL_INT31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRH */\r
+#define MCF_INTC_IMRH_INT_MASK32 (0x1)\r
+#define MCF_INTC_IMRH_INT_MASK33 (0x2)\r
+#define MCF_INTC_IMRH_INT_MASK34 (0x4)\r
+#define MCF_INTC_IMRH_INT_MASK35 (0x8)\r
+#define MCF_INTC_IMRH_INT_MASK36 (0x10)\r
+#define MCF_INTC_IMRH_INT_MASK37 (0x20)\r
+#define MCF_INTC_IMRH_INT_MASK38 (0x40)\r
+#define MCF_INTC_IMRH_INT_MASK39 (0x80)\r
+#define MCF_INTC_IMRH_INT_MASK40 (0x100)\r
+#define MCF_INTC_IMRH_INT_MASK41 (0x200)\r
+#define MCF_INTC_IMRH_INT_MASK42 (0x400)\r
+#define MCF_INTC_IMRH_INT_MASK43 (0x800)\r
+#define MCF_INTC_IMRH_INT_MASK44 (0x1000)\r
+#define MCF_INTC_IMRH_INT_MASK45 (0x2000)\r
+#define MCF_INTC_IMRH_INT_MASK46 (0x4000)\r
+#define MCF_INTC_IMRH_INT_MASK47 (0x8000)\r
+#define MCF_INTC_IMRH_INT_MASK48 (0x10000)\r
+#define MCF_INTC_IMRH_INT_MASK49 (0x20000)\r
+#define MCF_INTC_IMRH_INT_MASK50 (0x40000)\r
+#define MCF_INTC_IMRH_INT_MASK51 (0x80000)\r
+#define MCF_INTC_IMRH_INT_MASK52 (0x100000)\r
+#define MCF_INTC_IMRH_INT_MASK53 (0x200000)\r
+#define MCF_INTC_IMRH_INT_MASK54 (0x400000)\r
+#define MCF_INTC_IMRH_INT_MASK55 (0x800000)\r
+#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)\r
+#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)\r
+#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)\r
+#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)\r
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)\r
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)\r
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)\r
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IMRL */\r
+#define MCF_INTC_IMRL_MASKALL (0x1)\r
+#define MCF_INTC_IMRL_INT_MASK1 (0x2)\r
+#define MCF_INTC_IMRL_INT_MASK2 (0x4)\r
+#define MCF_INTC_IMRL_INT_MASK3 (0x8)\r
+#define MCF_INTC_IMRL_INT_MASK4 (0x10)\r
+#define MCF_INTC_IMRL_INT_MASK5 (0x20)\r
+#define MCF_INTC_IMRL_INT_MASK6 (0x40)\r
+#define MCF_INTC_IMRL_INT_MASK7 (0x80)\r
+#define MCF_INTC_IMRL_INT_MASK8 (0x100)\r
+#define MCF_INTC_IMRL_INT_MASK9 (0x200)\r
+#define MCF_INTC_IMRL_INT_MASK10 (0x400)\r
+#define MCF_INTC_IMRL_INT_MASK11 (0x800)\r
+#define MCF_INTC_IMRL_INT_MASK12 (0x1000)\r
+#define MCF_INTC_IMRL_INT_MASK13 (0x2000)\r
+#define MCF_INTC_IMRL_INT_MASK14 (0x4000)\r
+#define MCF_INTC_IMRL_INT_MASK15 (0x8000)\r
+#define MCF_INTC_IMRL_INT_MASK16 (0x10000)\r
+#define MCF_INTC_IMRL_INT_MASK17 (0x20000)\r
+#define MCF_INTC_IMRL_INT_MASK18 (0x40000)\r
+#define MCF_INTC_IMRL_INT_MASK19 (0x80000)\r
+#define MCF_INTC_IMRL_INT_MASK20 (0x100000)\r
+#define MCF_INTC_IMRL_INT_MASK21 (0x200000)\r
+#define MCF_INTC_IMRL_INT_MASK22 (0x400000)\r
+#define MCF_INTC_IMRL_INT_MASK23 (0x800000)\r
+#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)\r
+#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)\r
+#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)\r
+#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)\r
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)\r
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)\r
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)\r
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCH */\r
+#define MCF_INTC_INTFRCH_INTFRC32 (0x1)\r
+#define MCF_INTC_INTFRCH_INTFRC33 (0x2)\r
+#define MCF_INTC_INTFRCH_INTFRC34 (0x4)\r
+#define MCF_INTC_INTFRCH_INTFRC35 (0x8)\r
+#define MCF_INTC_INTFRCH_INTFRC36 (0x10)\r
+#define MCF_INTC_INTFRCH_INTFRC37 (0x20)\r
+#define MCF_INTC_INTFRCH_INTFRC38 (0x40)\r
+#define MCF_INTC_INTFRCH_INTFRC39 (0x80)\r
+#define MCF_INTC_INTFRCH_INTFRC40 (0x100)\r
+#define MCF_INTC_INTFRCH_INTFRC41 (0x200)\r
+#define MCF_INTC_INTFRCH_INTFRC42 (0x400)\r
+#define MCF_INTC_INTFRCH_INTFRC43 (0x800)\r
+#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)\r
+#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)\r
+#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)\r
+#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)\r
+#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)\r
+#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)\r
+#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)\r
+#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)\r
+#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)\r
+#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)\r
+#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)\r
+#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)\r
+#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)\r
+#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)\r
+#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)\r
+#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)\r
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)\r
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)\r
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)\r
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_INTFRCL */\r
+#define MCF_INTC_INTFRCL_INTFRC1 (0x2)\r
+#define MCF_INTC_INTFRCL_INTFRC2 (0x4)\r
+#define MCF_INTC_INTFRCL_INTFRC3 (0x8)\r
+#define MCF_INTC_INTFRCL_INTFRC4 (0x10)\r
+#define MCF_INTC_INTFRCL_INTFRC5 (0x20)\r
+#define MCF_INTC_INTFRCL_INTFRC6 (0x40)\r
+#define MCF_INTC_INTFRCL_INTFRC7 (0x80)\r
+#define MCF_INTC_INTFRCL_INTFRC8 (0x100)\r
+#define MCF_INTC_INTFRCL_INTFRC9 (0x200)\r
+#define MCF_INTC_INTFRCL_INTFRC10 (0x400)\r
+#define MCF_INTC_INTFRCL_INTFRC11 (0x800)\r
+#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)\r
+#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)\r
+#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)\r
+#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)\r
+#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)\r
+#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)\r
+#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)\r
+#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)\r
+#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)\r
+#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)\r
+#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)\r
+#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)\r
+#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)\r
+#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)\r
+#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)\r
+#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)\r
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)\r
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)\r
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)\r
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IRLR */\r
+#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)\r
+\r
+/* Bit definitions and macros for MCF_INTC_IACKLPR */\r
+#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)\r
+#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_INTC_ICR */\r
+#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)\r
+#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_INTC_SWIACK */\r
+#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_INTC_LIACK */\r
+#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_INTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_PAD_H__\r
+#define __MCF52221_PAD_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Common GPIO\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PAD_PSRR (*(vuint32*)(0x40100078))\r
+#define MCF_PAD_PDSR (*(vuint32*)(0x4010007C))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PAD_PSRR */\r
+#define MCF_PAD_PSRR_PSRR0 (0x1)\r
+#define MCF_PAD_PSRR_PSRR1 (0x2)\r
+#define MCF_PAD_PSRR_PSRR2 (0x4)\r
+#define MCF_PAD_PSRR_PSRR3 (0x8)\r
+#define MCF_PAD_PSRR_PSRR4 (0x10)\r
+#define MCF_PAD_PSRR_PSRR5 (0x20)\r
+#define MCF_PAD_PSRR_PSRR6 (0x40)\r
+#define MCF_PAD_PSRR_PSRR7 (0x80)\r
+#define MCF_PAD_PSRR_PSRR8 (0x100)\r
+#define MCF_PAD_PSRR_PSRR9 (0x200)\r
+#define MCF_PAD_PSRR_PSRR10 (0x400)\r
+#define MCF_PAD_PSRR_PSRR11 (0x800)\r
+#define MCF_PAD_PSRR_PSRR12 (0x1000)\r
+#define MCF_PAD_PSRR_PSRR13 (0x2000)\r
+#define MCF_PAD_PSRR_PSRR14 (0x4000)\r
+#define MCF_PAD_PSRR_PSRR15 (0x8000)\r
+#define MCF_PAD_PSRR_PSRR16 (0x10000)\r
+#define MCF_PAD_PSRR_PSRR17 (0x20000)\r
+#define MCF_PAD_PSRR_PSRR18 (0x40000)\r
+#define MCF_PAD_PSRR_PSRR19 (0x80000)\r
+#define MCF_PAD_PSRR_PSRR20 (0x100000)\r
+#define MCF_PAD_PSRR_PSRR21 (0x200000)\r
+#define MCF_PAD_PSRR_PSRR22 (0x400000)\r
+#define MCF_PAD_PSRR_PSRR23 (0x800000)\r
+#define MCF_PAD_PSRR_PSRR24 (0x1000000)\r
+#define MCF_PAD_PSRR_PSRR25 (0x2000000)\r
+#define MCF_PAD_PSRR_PSRR26 (0x4000000)\r
+#define MCF_PAD_PSRR_PSRR27 (0x8000000)\r
+\r
+/* Bit definitions and macros for MCF_PAD_PDSR */\r
+#define MCF_PAD_PDSR_PDSR0 (0x1)\r
+#define MCF_PAD_PDSR_PDSR1 (0x2)\r
+#define MCF_PAD_PDSR_PDSR2 (0x4)\r
+#define MCF_PAD_PDSR_PDSR3 (0x8)\r
+#define MCF_PAD_PDSR_PDSR4 (0x10)\r
+#define MCF_PAD_PDSR_PDSR5 (0x20)\r
+#define MCF_PAD_PDSR_PDSR6 (0x40)\r
+#define MCF_PAD_PDSR_PDSR7 (0x80)\r
+#define MCF_PAD_PDSR_PDSR8 (0x100)\r
+#define MCF_PAD_PDSR_PDSR9 (0x200)\r
+#define MCF_PAD_PDSR_PDSR10 (0x400)\r
+#define MCF_PAD_PDSR_PDSR11 (0x800)\r
+#define MCF_PAD_PDSR_PDSR12 (0x1000)\r
+#define MCF_PAD_PDSR_PDSR13 (0x2000)\r
+#define MCF_PAD_PDSR_PDSR14 (0x4000)\r
+#define MCF_PAD_PDSR_PDSR15 (0x8000)\r
+#define MCF_PAD_PDSR_PDSR16 (0x10000)\r
+#define MCF_PAD_PDSR_PDSR17 (0x20000)\r
+#define MCF_PAD_PDSR_PDSR18 (0x40000)\r
+#define MCF_PAD_PDSR_PDSR19 (0x80000)\r
+#define MCF_PAD_PDSR_PDSR20 (0x100000)\r
+#define MCF_PAD_PDSR_PDSR21 (0x200000)\r
+#define MCF_PAD_PDSR_PDSR22 (0x400000)\r
+#define MCF_PAD_PDSR_PDSR23 (0x800000)\r
+#define MCF_PAD_PDSR_PDSR24 (0x1000000)\r
+#define MCF_PAD_PDSR_PDSR25 (0x2000000)\r
+#define MCF_PAD_PDSR_PDSR26 (0x4000000)\r
+#define MCF_PAD_PDSR_PDSR27 (0x8000000)\r
+\r
+\r
+#endif /* __MCF52221_PAD_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_PIT_H__\r
+#define __MCF52221_PIT_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Programmable Interrupt Timer (PIT)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PIT0_PCSR (*(vuint16*)(0x40150000))\r
+#define MCF_PIT0_PMR (*(vuint16*)(0x40150002))\r
+#define MCF_PIT0_PCNTR (*(vuint16*)(0x40150004))\r
+\r
+#define MCF_PIT1_PCSR (*(vuint16*)(0x40160000))\r
+#define MCF_PIT1_PMR (*(vuint16*)(0x40160002))\r
+#define MCF_PIT1_PCNTR (*(vuint16*)(0x40160004))\r
+\r
+#define MCF_PIT_PCSR(x) (*(vuint16*)(0x40150000 + ((x)*0x10000)))\r
+#define MCF_PIT_PMR(x) (*(vuint16*)(0x40150002 + ((x)*0x10000)))\r
+#define MCF_PIT_PCNTR(x) (*(vuint16*)(0x40150004 + ((x)*0x10000)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCSR */\r
+#define MCF_PIT_PCSR_EN (0x1)\r
+#define MCF_PIT_PCSR_RLD (0x2)\r
+#define MCF_PIT_PCSR_PIF (0x4)\r
+#define MCF_PIT_PCSR_PIE (0x8)\r
+#define MCF_PIT_PCSR_OVW (0x10)\r
+#define MCF_PIT_PCSR_DBG (0x20)\r
+#define MCF_PIT_PCSR_DOZE (0x40)\r
+#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PMR */\r
+#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PIT_PCNTR */\r
+#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_PIT_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_PMM_H__\r
+#define __MCF52221_PMM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Power Management (PMM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PMM_LPICR (*(vuint8 *)(0x40000012))\r
+#define MCF_PMM_LPCR (*(vuint8 *)(0x40110007))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPICR */\r
+#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)\r
+#define MCF_PMM_LPICR_ENBSTOP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PMM_LPCR */\r
+#define MCF_PMM_LPCR_STPMD (0x8)\r
+#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)\r
+#define MCF_PMM_LPCR_LPMD_RUN (0)\r
+#define MCF_PMM_LPCR_LPMD_DOZE (0x40)\r
+#define MCF_PMM_LPCR_LPMD_WAIT (0x80)\r
+#define MCF_PMM_LPCR_LPMD_STOP (0xC0)\r
+\r
+\r
+#endif /* __MCF52221_PMM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_PWM_H__\r
+#define __MCF52221_PWM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Pulse Width Modulation (PWM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_PWM_PWME (*(vuint8 *)(0x401B0000))\r
+#define MCF_PWM_PWMPOL (*(vuint8 *)(0x401B0001))\r
+#define MCF_PWM_PWMCLK (*(vuint8 *)(0x401B0002))\r
+#define MCF_PWM_PWMPRCLK (*(vuint8 *)(0x401B0003))\r
+#define MCF_PWM_PWMCAE (*(vuint8 *)(0x401B0004))\r
+#define MCF_PWM_PWMCTL (*(vuint8 *)(0x401B0005))\r
+#define MCF_PWM_PWMSCLA (*(vuint8 *)(0x401B0008))\r
+#define MCF_PWM_PWMSCLB (*(vuint8 *)(0x401B0009))\r
+#define MCF_PWM_PWMCNT0 (*(vuint8 *)(0x401B000C))\r
+#define MCF_PWM_PWMCNT1 (*(vuint8 *)(0x401B000D))\r
+#define MCF_PWM_PWMCNT2 (*(vuint8 *)(0x401B000E))\r
+#define MCF_PWM_PWMCNT3 (*(vuint8 *)(0x401B000F))\r
+#define MCF_PWM_PWMCNT4 (*(vuint8 *)(0x401B0010))\r
+#define MCF_PWM_PWMCNT5 (*(vuint8 *)(0x401B0011))\r
+#define MCF_PWM_PWMCNT6 (*(vuint8 *)(0x401B0012))\r
+#define MCF_PWM_PWMCNT7 (*(vuint8 *)(0x401B0013))\r
+#define MCF_PWM_PWMPER0 (*(vuint8 *)(0x401B0014))\r
+#define MCF_PWM_PWMPER1 (*(vuint8 *)(0x401B0015))\r
+#define MCF_PWM_PWMPER2 (*(vuint8 *)(0x401B0016))\r
+#define MCF_PWM_PWMPER3 (*(vuint8 *)(0x401B0017))\r
+#define MCF_PWM_PWMPER4 (*(vuint8 *)(0x401B0018))\r
+#define MCF_PWM_PWMPER5 (*(vuint8 *)(0x401B0019))\r
+#define MCF_PWM_PWMPER6 (*(vuint8 *)(0x401B001A))\r
+#define MCF_PWM_PWMPER7 (*(vuint8 *)(0x401B001B))\r
+#define MCF_PWM_PWMDTY0 (*(vuint8 *)(0x401B001C))\r
+#define MCF_PWM_PWMDTY1 (*(vuint8 *)(0x401B001D))\r
+#define MCF_PWM_PWMDTY2 (*(vuint8 *)(0x401B001E))\r
+#define MCF_PWM_PWMDTY3 (*(vuint8 *)(0x401B001F))\r
+#define MCF_PWM_PWMDTY4 (*(vuint8 *)(0x401B0020))\r
+#define MCF_PWM_PWMDTY5 (*(vuint8 *)(0x401B0021))\r
+#define MCF_PWM_PWMDTY6 (*(vuint8 *)(0x401B0022))\r
+#define MCF_PWM_PWMDTY7 (*(vuint8 *)(0x401B0023))\r
+#define MCF_PWM_PWMSDN (*(vuint8 *)(0x401B0024))\r
+#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(0x401B000C + ((x)*0x1)))\r
+#define MCF_PWM_PWMPER(x) (*(vuint8 *)(0x401B0014 + ((x)*0x1)))\r
+#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(0x401B001C + ((x)*0x1)))\r
+\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWME */\r
+#define MCF_PWM_PWME_PWME0 (0x1)\r
+#define MCF_PWM_PWME_PWME1 (0x2)\r
+#define MCF_PWM_PWME_PWME2 (0x4)\r
+#define MCF_PWM_PWME_PWME3 (0x8)\r
+#define MCF_PWM_PWME_PWME4 (0x10)\r
+#define MCF_PWM_PWME_PWME5 (0x20)\r
+#define MCF_PWM_PWME_PWME6 (0x40)\r
+#define MCF_PWM_PWME_PWME7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPOL */\r
+#define MCF_PWM_PWMPOL_PPOL0 (0x1)\r
+#define MCF_PWM_PWMPOL_PPOL1 (0x2)\r
+#define MCF_PWM_PWMPOL_PPOL2 (0x4)\r
+#define MCF_PWM_PWMPOL_PPOL3 (0x8)\r
+#define MCF_PWM_PWMPOL_PPOL4 (0x10)\r
+#define MCF_PWM_PWMPOL_PPOL5 (0x20)\r
+#define MCF_PWM_PWMPOL_PPOL6 (0x40)\r
+#define MCF_PWM_PWMPOL_PPOL7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCLK */\r
+#define MCF_PWM_PWMCLK_PCLK0 (0x1)\r
+#define MCF_PWM_PWMCLK_PCLK1 (0x2)\r
+#define MCF_PWM_PWMCLK_PCLK2 (0x4)\r
+#define MCF_PWM_PWMCLK_PCLK3 (0x8)\r
+#define MCF_PWM_PWMCLK_PCLK4 (0x10)\r
+#define MCF_PWM_PWMCLK_PCLK5 (0x20)\r
+#define MCF_PWM_PWMCLK_PCLK6 (0x40)\r
+#define MCF_PWM_PWMCLK_PCLK7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPRCLK */\r
+#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)\r
+#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCAE */\r
+#define MCF_PWM_PWMCAE_CAE0 (0x1)\r
+#define MCF_PWM_PWMCAE_CAE1 (0x2)\r
+#define MCF_PWM_PWMCAE_CAE2 (0x4)\r
+#define MCF_PWM_PWMCAE_CAE3 (0x8)\r
+#define MCF_PWM_PWMCAE_CAE4 (0x10)\r
+#define MCF_PWM_PWMCAE_CAE5 (0x20)\r
+#define MCF_PWM_PWMCAE_CAE6 (0x40)\r
+#define MCF_PWM_PWMCAE_CAE7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCTL */\r
+#define MCF_PWM_PWMCTL_PFRZ (0x4)\r
+#define MCF_PWM_PWMCTL_PSWAI (0x8)\r
+#define MCF_PWM_PWMCTL_CON01 (0x10)\r
+#define MCF_PWM_PWMCTL_CON23 (0x20)\r
+#define MCF_PWM_PWMCTL_CON45 (0x40)\r
+#define MCF_PWM_PWMCTL_CON67 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLA */\r
+#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSCLB */\r
+#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMCNT */\r
+#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMPER */\r
+#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMDTY */\r
+#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_PWM_PWMSDN */\r
+#define MCF_PWM_PWMSDN_SDNEN (0x1)\r
+#define MCF_PWM_PWMSDN_PWM7IL (0x2)\r
+#define MCF_PWM_PWMSDN_PWM7IN (0x4)\r
+#define MCF_PWM_PWMSDN_LVL (0x10)\r
+#define MCF_PWM_PWMSDN_RESTART (0x20)\r
+#define MCF_PWM_PWMSDN_IE (0x40)\r
+#define MCF_PWM_PWMSDN_IF (0x80)\r
+\r
+\r
+#endif /* __MCF52221_PWM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_QSPI_H__\r
+#define __MCF52221_QSPI_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Queued Serial Peripheral Interface (QSPI)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_QSPI_QMR (*(vuint16*)(0x40000340))\r
+#define MCF_QSPI_QDLYR (*(vuint16*)(0x40000344))\r
+#define MCF_QSPI_QWR (*(vuint16*)(0x40000348))\r
+#define MCF_QSPI_QIR (*(vuint16*)(0x4000034C))\r
+#define MCF_QSPI_QAR (*(vuint16*)(0x40000350))\r
+#define MCF_QSPI_QDR (*(vuint16*)(0x40000354))\r
+\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QMR */\r
+#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QMR_CPHA (0x100)\r
+#define MCF_QSPI_QMR_CPOL (0x200)\r
+#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)\r
+#define MCF_QSPI_QMR_DOHIE (0x4000)\r
+#define MCF_QSPI_QMR_MSTR (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDLYR */\r
+#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)\r
+#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)\r
+#define MCF_QSPI_QDLYR_SPE (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QWR */\r
+#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)\r
+#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)\r
+#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)\r
+#define MCF_QSPI_QWR_CSIV (0x1000)\r
+#define MCF_QSPI_QWR_WRTO (0x2000)\r
+#define MCF_QSPI_QWR_WREN (0x4000)\r
+#define MCF_QSPI_QWR_HALT (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QIR */\r
+#define MCF_QSPI_QIR_SPIF (0x1)\r
+#define MCF_QSPI_QIR_ABRT (0x4)\r
+#define MCF_QSPI_QIR_WCEF (0x8)\r
+#define MCF_QSPI_QIR_SPIFE (0x100)\r
+#define MCF_QSPI_QIR_ABRTE (0x400)\r
+#define MCF_QSPI_QIR_WCEFE (0x800)\r
+#define MCF_QSPI_QIR_ABRTL (0x1000)\r
+#define MCF_QSPI_QIR_ABRTB (0x4000)\r
+#define MCF_QSPI_QIR_WCEFB (0x8000)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QAR */\r
+#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)\r
+#define MCF_QSPI_QAR_TRANS (0)\r
+#define MCF_QSPI_QAR_RECV (0x10)\r
+#define MCF_QSPI_QAR_CMD (0x20)\r
+\r
+/* Bit definitions and macros for MCF_QSPI_QDR */\r
+#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)\r
+#define MCF_QSPI_QDR_CONT (0x8000)\r
+#define MCF_QSPI_QDR_BITSE (0x4000)\r
+#define MCF_QSPI_QDR_DT (0x2000)\r
+#define MCF_QSPI_QDR_DSCK (0x1000)\r
+#define MCF_QSPI_QDR_QSPI_CS3 (0x800)\r
+#define MCF_QSPI_QDR_QSPI_CS2 (0x400)\r
+#define MCF_QSPI_QDR_QSPI_CS1 (0x200)\r
+#define MCF_QSPI_QDR_QSPI_CS0 (0x100)\r
+\r
+\r
+#endif /* __MCF52221_QSPI_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_RCM_H__\r
+#define __MCF52221_RCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Reset Controller Module (RCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))\r
+#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RCM_RCR */\r
+#define MCF_RCM_RCR_LVDE (0x1)\r
+#define MCF_RCM_RCR_LVDRE (0x4)\r
+#define MCF_RCM_RCR_LVDIE (0x8)\r
+#define MCF_RCM_RCR_LVDF (0x10)\r
+#define MCF_RCM_RCR_FRCRSTOUT (0x40)\r
+#define MCF_RCM_RCR_SOFTRST (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RCM_RSR */\r
+#define MCF_RCM_RSR_LOL (0x1)\r
+#define MCF_RCM_RSR_LOC (0x2)\r
+#define MCF_RCM_RSR_EXT (0x4)\r
+#define MCF_RCM_RSR_POR (0x8)\r
+#define MCF_RCM_RSR_SOFT (0x20)\r
+#define MCF_RCM_RSR_LVD (0x40)\r
+\r
+\r
+#endif /* __MCF52221_RCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_RTC_H__\r
+#define __MCF52221_RTC_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Real-Time Clock (RTC)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_RTC_HOURMIN (*(vuint32*)(0x400003C0))\r
+#define MCF_RTC_SECONDS (*(vuint32*)(0x400003C4))\r
+#define MCF_RTC_ALRM_HM (*(vuint32*)(0x400003C8))\r
+#define MCF_RTC_ALRM_SEC (*(vuint32*)(0x400003CC))\r
+#define MCF_RTC_RTCCTL (*(vuint32*)(0x400003D0))\r
+#define MCF_RTC_RTCISR (*(vuint32*)(0x400003D4))\r
+#define MCF_RTC_RTCIENR (*(vuint32*)(0x400003D8))\r
+#define MCF_RTC_STPWCH (*(vuint32*)(0x400003DC))\r
+#define MCF_RTC_DAYS (*(vuint32*)(0x400003E0))\r
+#define MCF_RTC_ALRM_DAY (*(vuint32*)(0x400003E4))\r
+\r
+\r
+/* Bit definitions and macros for MCF_RTC_HOURMIN */\r
+#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_SECONDS */\r
+#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_HM */\r
+#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)\r
+#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_SEC */\r
+#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCCTL */\r
+#define MCF_RTC_RTCCTL_SWR (0x1)\r
+#define MCF_RTC_RTCCTL_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCISR */\r
+#define MCF_RTC_RTCISR_SW (0x1)\r
+#define MCF_RTC_RTCISR_MIN (0x2)\r
+#define MCF_RTC_RTCISR_ALM (0x4)\r
+#define MCF_RTC_RTCISR_DAY (0x8)\r
+#define MCF_RTC_RTCISR_1HZ (0x10)\r
+#define MCF_RTC_RTCISR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_RTCIENR */\r
+#define MCF_RTC_RTCIENR_SW (0x1)\r
+#define MCF_RTC_RTCIENR_MIN (0x2)\r
+#define MCF_RTC_RTCIENR_ALM (0x4)\r
+#define MCF_RTC_RTCIENR_DAY (0x8)\r
+#define MCF_RTC_RTCIENR_1HZ (0x10)\r
+#define MCF_RTC_RTCIENR_HR (0x20)\r
+\r
+/* Bit definitions and macros for MCF_RTC_STPWCH */\r
+#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_DAYS */\r
+#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_RTC_ALRM_DAY */\r
+#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)\r
+\r
+\r
+#endif /* __MCF52221_RTC_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_SCM_H__\r
+#define __MCF52221_SCM_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* System Control Module (SCM)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008))\r
+#define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C))\r
+#define MCF_SCM_CRSR (*(vuint8 *)(0x40000010))\r
+#define MCF_SCM_CWCR (*(vuint8 *)(0x40000011))\r
+#define MCF_SCM_CWSR (*(vuint8 *)(0x40000013))\r
+#define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014))\r
+#define MCF_SCM_PPMRL (*(vuint32*)(0x40000018))\r
+#define MCF_SCM_MPARK (*(vuint32*)(0x4000001C))\r
+#define MCF_SCM_MPR (*(vuint8 *)(0x40000020))\r
+#define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021))\r
+#define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022))\r
+#define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023))\r
+#define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024))\r
+#define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025))\r
+#define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026))\r
+#define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027))\r
+#define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028))\r
+#define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029))\r
+#define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A))\r
+#define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B))\r
+#define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C))\r
+#define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030))\r
+#define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031))\r
+#define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1)))\r
+#define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1)))\r
+\r
+/* Other macros */\r
+#define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000))\r
+#define MCF_SCM_IPSBAR_V (0x1)\r
+#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)\r
+\r
+\r
+/* Bit definitions and macros for MCF_SCM_RAMBAR */\r
+#define MCF_SCM_RAMBAR_BDE (0x200)\r
+#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRH */\r
+#define MCF_SCM_PPMRH_CDPORTS (0x1)\r
+#define MCF_SCM_PPMRH_CDEPORT (0x2)\r
+#define MCF_SCM_PPMRH_CDPIT0 (0x8)\r
+#define MCF_SCM_PPMRH_CDPIT1 (0x10)\r
+#define MCF_SCM_PPMRH_CDADC (0x80)\r
+#define MCF_SCM_PPMRH_CDGPT (0x100)\r
+#define MCF_SCM_PPMRH_CDPWM (0x200)\r
+#define MCF_SCM_PPMRH_CDFCAN (0x400)\r
+#define MCF_SCM_PPMRH_CDCFM (0x800)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CRSR */\r
+#define MCF_SCM_CRSR_EXT (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWCR */\r
+#define MCF_SCM_CWCR_CWTIF (0x1)\r
+#define MCF_SCM_CWCR_CWTAVAL (0x2)\r
+#define MCF_SCM_CWCR_CWTA (0x4)\r
+#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)\r
+#define MCF_SCM_CWCR_CWT_2_9 (0)\r
+#define MCF_SCM_CWCR_CWT_2_11 (0x8)\r
+#define MCF_SCM_CWCR_CWT_2_13 (0x10)\r
+#define MCF_SCM_CWCR_CWT_2_15 (0x18)\r
+#define MCF_SCM_CWCR_CWT_2_19 (0x20)\r
+#define MCF_SCM_CWCR_CWT_2_23 (0x28)\r
+#define MCF_SCM_CWCR_CWT_2_27 (0x30)\r
+#define MCF_SCM_CWCR_CWT_2_31 (0x38)\r
+#define MCF_SCM_CWCR_CWRI (0x40)\r
+#define MCF_SCM_CWCR_CWE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_CWSR */\r
+#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_DMAREQC */\r
+#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)\r
+#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRL */\r
+#define MCF_SCM_PPMRL_CDG (0x2)\r
+#define MCF_SCM_PPMRL_CDDMA (0x10)\r
+#define MCF_SCM_PPMRL_CDUART0 (0x20)\r
+#define MCF_SCM_PPMRL_CDUART1 (0x40)\r
+#define MCF_SCM_PPMRL_CDUART2 (0x80)\r
+#define MCF_SCM_PPMRL_CDI2C (0x200)\r
+#define MCF_SCM_PPMRL_CDQSPI (0x400)\r
+#define MCF_SCM_PPMRL_CDTMR0 (0x2000)\r
+#define MCF_SCM_PPMRL_CDTMR1 (0x4000)\r
+#define MCF_SCM_PPMRL_CDTMR2 (0x8000)\r
+#define MCF_SCM_PPMRL_CDTMR3 (0x10000)\r
+#define MCF_SCM_PPMRL_CDINTC0 (0x20000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPARK */\r
+#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)\r
+#define MCF_SCM_MPARK_PRKLAST (0x1000)\r
+#define MCF_SCM_MPARK_TIMEOUT (0x2000)\r
+#define MCF_SCM_MPARK_FIXED (0x4000)\r
+#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)\r
+#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)\r
+#define MCF_SCM_MPARK_BCR24BIT (0x1000000)\r
+#define MCF_SCM_MPARK_M2_P_EN (0x2000000)\r
+\r
+/* Bit definitions and macros for MCF_SCM_MPR */\r
+#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRS */\r
+#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRS_SET_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PPMRC */\r
+#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)\r
+#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)\r
+#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)\r
+#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)\r
+#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)\r
+#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)\r
+#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)\r
+#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)\r
+#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)\r
+#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)\r
+#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)\r
+#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)\r
+#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)\r
+#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)\r
+#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)\r
+#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)\r
+#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)\r
+#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)\r
+#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)\r
+\r
+/* Bit definitions and macros for MCF_SCM_IPSBMT */\r
+#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)\r
+#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)\r
+#define MCF_SCM_IPSBMT_BME (0x8)\r
+\r
+/* Bit definitions and macros for MCF_SCM_PACR */\r
+#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)\r
+#define MCF_SCM_PACR_LOCK0 (0x8)\r
+#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)\r
+#define MCF_SCM_PACR_LOCK1 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_SCM_GPACR */\r
+#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)\r
+#define MCF_SCM_GPACR_LOCK (0x80)\r
+\r
+\r
+#endif /* __MCF52221_SCM_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_UART_H__\r
+#define __MCF52221_UART_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Asynchronous Receiver Transmitter (UART)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_UART0_UMR1 (*(vuint8 *)(0x40000200))\r
+#define MCF_UART0_UMR2 (*(vuint8 *)(0x40000200))\r
+#define MCF_UART0_USR (*(vuint8 *)(0x40000204))\r
+#define MCF_UART0_UCSR (*(vuint8 *)(0x40000204))\r
+#define MCF_UART0_UCR (*(vuint8 *)(0x40000208))\r
+#define MCF_UART0_URB (*(vuint8 *)(0x4000020C))\r
+#define MCF_UART0_UTB (*(vuint8 *)(0x4000020C))\r
+#define MCF_UART0_UIPCR (*(vuint8 *)(0x40000210))\r
+#define MCF_UART0_UACR (*(vuint8 *)(0x40000210))\r
+#define MCF_UART0_UIMR (*(vuint8 *)(0x40000214))\r
+#define MCF_UART0_UISR (*(vuint8 *)(0x40000214))\r
+#define MCF_UART0_UBG1 (*(vuint8 *)(0x40000218))\r
+#define MCF_UART0_UBG2 (*(vuint8 *)(0x4000021C))\r
+#define MCF_UART0_UIP (*(vuint8 *)(0x40000234))\r
+#define MCF_UART0_UOP1 (*(vuint8 *)(0x40000238))\r
+#define MCF_UART0_UOP0 (*(vuint8 *)(0x4000023C))\r
+\r
+#define MCF_UART1_UMR1 (*(vuint8 *)(0x40000240))\r
+#define MCF_UART1_UMR2 (*(vuint8 *)(0x40000240))\r
+#define MCF_UART1_USR (*(vuint8 *)(0x40000244))\r
+#define MCF_UART1_UCSR (*(vuint8 *)(0x40000244))\r
+#define MCF_UART1_UCR (*(vuint8 *)(0x40000248))\r
+#define MCF_UART1_URB (*(vuint8 *)(0x4000024C))\r
+#define MCF_UART1_UTB (*(vuint8 *)(0x4000024C))\r
+#define MCF_UART1_UIPCR (*(vuint8 *)(0x40000250))\r
+#define MCF_UART1_UACR (*(vuint8 *)(0x40000250))\r
+#define MCF_UART1_UIMR (*(vuint8 *)(0x40000254))\r
+#define MCF_UART1_UISR (*(vuint8 *)(0x40000254))\r
+#define MCF_UART1_UBG1 (*(vuint8 *)(0x40000258))\r
+#define MCF_UART1_UBG2 (*(vuint8 *)(0x4000025C))\r
+#define MCF_UART1_UIP (*(vuint8 *)(0x40000274))\r
+#define MCF_UART1_UOP1 (*(vuint8 *)(0x40000278))\r
+#define MCF_UART1_UOP0 (*(vuint8 *)(0x4000027C))\r
+\r
+#define MCF_UART2_UMR1 (*(vuint8 *)(0x40000280))\r
+#define MCF_UART2_UMR2 (*(vuint8 *)(0x40000280))\r
+#define MCF_UART2_USR (*(vuint8 *)(0x40000284))\r
+#define MCF_UART2_UCSR (*(vuint8 *)(0x40000284))\r
+#define MCF_UART2_UCR (*(vuint8 *)(0x40000288))\r
+#define MCF_UART2_URB (*(vuint8 *)(0x4000028C))\r
+#define MCF_UART2_UTB (*(vuint8 *)(0x4000028C))\r
+#define MCF_UART2_UIPCR (*(vuint8 *)(0x40000290))\r
+#define MCF_UART2_UACR (*(vuint8 *)(0x40000290))\r
+#define MCF_UART2_UIMR (*(vuint8 *)(0x40000294))\r
+#define MCF_UART2_UISR (*(vuint8 *)(0x40000294))\r
+#define MCF_UART2_UBG1 (*(vuint8 *)(0x40000298))\r
+#define MCF_UART2_UBG2 (*(vuint8 *)(0x4000029C))\r
+#define MCF_UART2_UIP (*(vuint8 *)(0x400002B4))\r
+#define MCF_UART2_UOP1 (*(vuint8 *)(0x400002B8))\r
+#define MCF_UART2_UOP0 (*(vuint8 *)(0x400002BC))\r
+\r
+#define MCF_UART_UMR(x) (*(vuint8 *)(0x40000200 + ((x)*0x40)))\r
+#define MCF_UART_USR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))\r
+#define MCF_UART_UCSR(x) (*(vuint8 *)(0x40000204 + ((x)*0x40)))\r
+#define MCF_UART_UCR(x) (*(vuint8 *)(0x40000208 + ((x)*0x40)))\r
+#define MCF_UART_URB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))\r
+#define MCF_UART_UTB(x) (*(vuint8 *)(0x4000020C + ((x)*0x40)))\r
+#define MCF_UART_UIPCR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))\r
+#define MCF_UART_UACR(x) (*(vuint8 *)(0x40000210 + ((x)*0x40)))\r
+#define MCF_UART_UIMR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))\r
+#define MCF_UART_UISR(x) (*(vuint8 *)(0x40000214 + ((x)*0x40)))\r
+#define MCF_UART_UBG1(x) (*(vuint8 *)(0x40000218 + ((x)*0x40)))\r
+#define MCF_UART_UBG2(x) (*(vuint8 *)(0x4000021C + ((x)*0x40)))\r
+#define MCF_UART_UIP(x) (*(vuint8 *)(0x40000234 + ((x)*0x40)))\r
+#define MCF_UART_UOP1(x) (*(vuint8 *)(0x40000238 + ((x)*0x40)))\r
+#define MCF_UART_UOP0(x) (*(vuint8 *)(0x4000023C + ((x)*0x40)))\r
+\r
+/* Bit definitions and macros for MCF_UART_UMR */\r
+#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UMR_BC_5 (0)\r
+#define MCF_UART_UMR_BC_6 (0x1)\r
+#define MCF_UART_UMR_BC_7 (0x2)\r
+#define MCF_UART_UMR_BC_8 (0x3)\r
+#define MCF_UART_UMR_PT (0x4)\r
+#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)\r
+#define MCF_UART_UMR_ERR (0x20)\r
+#define MCF_UART_UMR_RXIRQ (0x40)\r
+#define MCF_UART_UMR_RXRTS (0x80)\r
+#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)\r
+#define MCF_UART_UMR_PM_MULTI_DATA (0x18)\r
+#define MCF_UART_UMR_PM_NONE (0x10)\r
+#define MCF_UART_UMR_PM_FORCE_HI (0xC)\r
+#define MCF_UART_UMR_PM_FORCE_LO (0x8)\r
+#define MCF_UART_UMR_PM_ODD (0x4)\r
+#define MCF_UART_UMR_PM_EVEN (0)\r
+#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)\r
+#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)\r
+#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)\r
+#define MCF_UART_UMR_TXCTS (0x10)\r
+#define MCF_UART_UMR_TXRTS (0x20)\r
+#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)\r
+#define MCF_UART_UMR_CM_NORMAL (0)\r
+#define MCF_UART_UMR_CM_ECHO (0x40)\r
+#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)\r
+#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)\r
+\r
+/* Bit definitions and macros for MCF_UART_USR */\r
+#define MCF_UART_USR_RXRDY (0x1)\r
+#define MCF_UART_USR_FFULL (0x2)\r
+#define MCF_UART_USR_TXRDY (0x4)\r
+#define MCF_UART_USR_TXEMP (0x8)\r
+#define MCF_UART_USR_OE (0x10)\r
+#define MCF_UART_USR_PE (0x20)\r
+#define MCF_UART_USR_FE (0x40)\r
+#define MCF_UART_USR_RB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCSR */\r
+#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)\r
+#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)\r
+#define MCF_UART_UCSR_TCS_CTM16 (0xE)\r
+#define MCF_UART_UCSR_TCS_CTM (0xF)\r
+#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)\r
+#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)\r
+#define MCF_UART_UCSR_RCS_CTM16 (0xE0)\r
+#define MCF_UART_UCSR_RCS_CTM (0xF0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UCR */\r
+#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)\r
+#define MCF_UART_UCR_RX_ENABLED (0x1)\r
+#define MCF_UART_UCR_RX_DISABLED (0x2)\r
+#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)\r
+#define MCF_UART_UCR_TX_ENABLED (0x4)\r
+#define MCF_UART_UCR_TX_DISABLED (0x8)\r
+#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)\r
+#define MCF_UART_UCR_NONE (0)\r
+#define MCF_UART_UCR_RESET_MR (0x10)\r
+#define MCF_UART_UCR_RESET_RX (0x20)\r
+#define MCF_UART_UCR_RESET_TX (0x30)\r
+#define MCF_UART_UCR_RESET_ERROR (0x40)\r
+#define MCF_UART_UCR_RESET_BKCHGINT (0x50)\r
+#define MCF_UART_UCR_START_BREAK (0x60)\r
+#define MCF_UART_UCR_STOP_BREAK (0x70)\r
+\r
+/* Bit definitions and macros for MCF_UART_URB */\r
+#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UTB */\r
+#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIPCR */\r
+#define MCF_UART_UIPCR_CTS (0x1)\r
+#define MCF_UART_UIPCR_COS (0x10)\r
+\r
+/* Bit definitions and macros for MCF_UART_UACR */\r
+#define MCF_UART_UACR_IEC (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIMR */\r
+#define MCF_UART_UIMR_TXRDY (0x1)\r
+#define MCF_UART_UIMR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UIMR_DB (0x4)\r
+#define MCF_UART_UIMR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UISR */\r
+#define MCF_UART_UISR_TXRDY (0x1)\r
+#define MCF_UART_UISR_FFULL_RXRDY (0x2)\r
+#define MCF_UART_UISR_DB (0x4)\r
+#define MCF_UART_UISR_COS (0x80)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG1 */\r
+#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UBG2 */\r
+#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_UART_UIP */\r
+#define MCF_UART_UIP_CTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP1 */\r
+#define MCF_UART_UOP1_RTS (0x1)\r
+\r
+/* Bit definitions and macros for MCF_UART_UOP0 */\r
+#define MCF_UART_UOP0_RTS (0x1)\r
+\r
+\r
+#endif /* __MCF52221_UART_H__ */\r
--- /dev/null
+/* Coldfire C Header File\r
+ * Copyright Freescale Semiconductor Inc\r
+ * All rights reserved.\r
+ *\r
+ * 2008/05/23 Revision: 0.95\r
+ *\r
+ * (c) Copyright UNIS, a.s. 1997-2008\r
+ * UNIS, a.s.\r
+ * Jundrovska 33\r
+ * 624 00 Brno\r
+ * Czech Republic\r
+ * http : www.processorexpert.com\r
+ * mail : info@processorexpert.com\r
+ */\r
+\r
+#ifndef __MCF52221_USB_OTG_H__\r
+#define __MCF52221_USB_OTG_H__\r
+\r
+\r
+/*********************************************************************\r
+*\r
+* Universal Serial Bus - OTG Controller (USB_OTG)\r
+*\r
+*********************************************************************/\r
+\r
+/* Register read/write macros */\r
+#define MCF_USB_OTG_PER_ID (*(vuint8 *)(0x401C0000))\r
+#define MCF_USB_OTG_ID_COMP (*(vuint8 *)(0x401C0004))\r
+#define MCF_USB_OTG_REV (*(vuint8 *)(0x401C0008))\r
+#define MCF_USB_OTG_ADD_INFO (*(vuint8 *)(0x401C000C))\r
+#define MCF_USB_OTG_OTG_INT_STAT (*(vuint8 *)(0x401C0010))\r
+#define MCF_USB_OTG_OTG_INT_EN (*(vuint8 *)(0x401C0014))\r
+#define MCF_USB_OTG_OTG_STAT (*(vuint8 *)(0x401C0018))\r
+#define MCF_USB_OTG_OTG_CTRL (*(vuint8 *)(0x401C001C))\r
+#define MCF_USB_OTG_INT_STAT (*(vuint8 *)(0x401C0080))\r
+#define MCF_USB_OTG_INT_ENB (*(vuint8 *)(0x401C0084))\r
+#define MCF_USB_OTG_ERR_STAT (*(vuint8 *)(0x401C0088))\r
+#define MCF_USB_OTG_ERR_ENB (*(vuint8 *)(0x401C008C))\r
+#define MCF_USB_OTG_STAT (*(vuint8 *)(0x401C0090))\r
+#define MCF_USB_OTG_CTL (*(vuint8 *)(0x401C0094))\r
+#define MCF_USB_OTG_ADDR (*(vuint8 *)(0x401C0098))\r
+#define MCF_USB_OTG_BDT_PAGE_01 (*(vuint8 *)(0x401C009C))\r
+#define MCF_USB_OTG_FRM_NUML (*(vuint8 *)(0x401C00A0))\r
+#define MCF_USB_OTG_FRM_NUMH (*(vuint8 *)(0x401C00A4))\r
+#define MCF_USB_OTG_TOKEN (*(vuint8 *)(0x401C00A8))\r
+#define MCF_USB_OTG_SOF_THLD (*(vuint8 *)(0x401C00AC))\r
+#define MCF_USB_OTG_BDT_PAGE_02 (*(vuint8 *)(0x401C00B0))\r
+#define MCF_USB_OTG_BDT_PAGE_03 (*(vuint8 *)(0x401C00B4))\r
+#define MCF_USB_OTG_ENDPT0 (*(vuint8 *)(0x401C00C0))\r
+#define MCF_USB_OTG_ENDPT1 (*(vuint8 *)(0x401C00C4))\r
+#define MCF_USB_OTG_ENDPT2 (*(vuint8 *)(0x401C00C8))\r
+#define MCF_USB_OTG_ENDPT3 (*(vuint8 *)(0x401C00CC))\r
+#define MCF_USB_OTG_ENDPT4 (*(vuint8 *)(0x401C00D0))\r
+#define MCF_USB_OTG_ENDPT5 (*(vuint8 *)(0x401C00D4))\r
+#define MCF_USB_OTG_ENDPT6 (*(vuint8 *)(0x401C00D8))\r
+#define MCF_USB_OTG_ENDPT7 (*(vuint8 *)(0x401C00DC))\r
+#define MCF_USB_OTG_ENDPT8 (*(vuint8 *)(0x401C00E0))\r
+#define MCF_USB_OTG_ENDPT9 (*(vuint8 *)(0x401C00E4))\r
+#define MCF_USB_OTG_ENDPT10 (*(vuint8 *)(0x401C00E8))\r
+#define MCF_USB_OTG_ENDPT11 (*(vuint8 *)(0x401C00EC))\r
+#define MCF_USB_OTG_ENDPT12 (*(vuint8 *)(0x401C00F0))\r
+#define MCF_USB_OTG_ENDPT13 (*(vuint8 *)(0x401C00F4))\r
+#define MCF_USB_OTG_ENDPT14 (*(vuint8 *)(0x401C00F8))\r
+#define MCF_USB_OTG_ENDPT15 (*(vuint8 *)(0x401C00FC))\r
+#define MCF_USB_OTG_USB_CTRL (*(vuint8 *)(0x401C0100))\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE (*(vuint8 *)(0x401C0104))\r
+#define MCF_USB_OTG_USB_OTG_CONTROL (*(vuint8 *)(0x401C0108))\r
+#define MCF_USB_OTG_ENDPT(x) (*(vuint8 *)(0x401C00C0 + ((x)*0x4)))\r
+\r
+/* Other macros */\r
+#define MCF_USB_OTG_FRM_NUM (MCF_USB_OTG_INT_STAT=MCF_USB_OTG_INT_STAT_SOF_TOK ,MCF_USB_OTG_FRM_NUML | (((vuint16)MCF_USB_OTG_FRM_NUMH)<<8))\r
+\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_PER_ID */\r
+#define MCF_USB_OTG_PER_ID_ID(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ID_COMP */\r
+#define MCF_USB_OTG_ID_COMP_NID(x) (((x)&0x3F)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_REV */\r
+#define MCF_USB_OTG_REV_REV(x) (((x)&0xFF)<<0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ADD_INFO */\r
+#define MCF_USB_OTG_ADD_INFO_IEHOST (0x1)\r
+#define MCF_USB_OTG_ADD_INFO_IRQ_NUM(x) (((x)&0x1F)<<0x3)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_STAT */\r
+#define MCF_USB_OTG_OTG_INT_STAT_A_VBUS_CHG (0x1)\r
+#define MCF_USB_OTG_OTG_INT_STAT_B_SESS_CHG (0x4)\r
+#define MCF_USB_OTG_OTG_INT_STAT_SESS_VLD_CHG (0x8)\r
+#define MCF_USB_OTG_OTG_INT_STAT_LINE_STATE_CHG (0x20)\r
+#define MCF_USB_OTG_OTG_INT_STAT_1_MSEC (0x40)\r
+#define MCF_USB_OTG_OTG_INT_STAT_ID_CHG (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_INT_EN */\r
+#define MCF_USB_OTG_OTG_INT_EN_A_VBUS_EN (0x1)\r
+#define MCF_USB_OTG_OTG_INT_EN_B_SESS_EN (0x4)\r
+#define MCF_USB_OTG_OTG_INT_EN_SESS_VLD_EN (0x8)\r
+#define MCF_USB_OTG_OTG_INT_EN_LINE_STATE_EN (0x20)\r
+#define MCF_USB_OTG_OTG_INT_EN_1_MSEC_EN (0x40)\r
+#define MCF_USB_OTG_OTG_INT_EN_ID_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_STAT */\r
+#define MCF_USB_OTG_OTG_STAT_A_VBUS_VLD (0x1)\r
+#define MCF_USB_OTG_OTG_STAT_B_SESS_END (0x4)\r
+#define MCF_USB_OTG_OTG_STAT_SESS_VLD (0x8)\r
+#define MCF_USB_OTG_OTG_STAT_LINE_STATE_STABLE (0x20)\r
+#define MCF_USB_OTG_OTG_STAT_1_MSEC_EN (0x40)\r
+#define MCF_USB_OTG_OTG_STAT_ID (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_OTG_CTRL */\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_DSCHG (0x1)\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_CHG (0x2)\r
+#define MCF_USB_OTG_OTG_CTRL_OTG_EN (0x4)\r
+#define MCF_USB_OTG_OTG_CTRL_VBUS_ON (0x8)\r
+#define MCF_USB_OTG_OTG_CTRL_DM_LOW (0x10)\r
+#define MCF_USB_OTG_OTG_CTRL_DP_LOW (0x20)\r
+#define MCF_USB_OTG_OTG_CTRL_DP_HIGH (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_INT_STAT */\r
+#define MCF_USB_OTG_INT_STAT_USB_RST (0x1)\r
+#define MCF_USB_OTG_INT_STAT_ERROR (0x2)\r
+#define MCF_USB_OTG_INT_STAT_SOF_TOK (0x4)\r
+#define MCF_USB_OTG_INT_STAT_TOK_DNE (0x8)\r
+#define MCF_USB_OTG_INT_STAT_SLEEP (0x10)\r
+#define MCF_USB_OTG_INT_STAT_RESUME (0x20)\r
+#define MCF_USB_OTG_INT_STAT_ATTACH (0x40)\r
+#define MCF_USB_OTG_INT_STAT_STALL (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_INT_ENB */\r
+#define MCF_USB_OTG_INT_ENB_USB_RST_EN (0x1)\r
+#define MCF_USB_OTG_INT_ENB_ERROR_EN (0x2)\r
+#define MCF_USB_OTG_INT_ENB_SOF_TOK_EN (0x4)\r
+#define MCF_USB_OTG_INT_ENB_TOK_DNE_EN (0x8)\r
+#define MCF_USB_OTG_INT_ENB_SLEEP_EN (0x10)\r
+#define MCF_USB_OTG_INT_ENB_RESUME_EN (0x20)\r
+#define MCF_USB_OTG_INT_ENB_ATTACH_EN (0x40)\r
+#define MCF_USB_OTG_INT_ENB_STALL_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ERR_STAT */\r
+#define MCF_USB_OTG_ERR_STAT_PID_ERR (0x1)\r
+#define MCF_USB_OTG_ERR_STAT_CRC5_EOF (0x2)\r
+#define MCF_USB_OTG_ERR_STAT_CRC16 (0x4)\r
+#define MCF_USB_OTG_ERR_STAT_DFN8 (0x8)\r
+#define MCF_USB_OTG_ERR_STAT_BTO_ERR (0x10)\r
+#define MCF_USB_OTG_ERR_STAT_DMA_ERR (0x20)\r
+#define MCF_USB_OTG_ERR_STAT_BTS_ERR (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ERR_ENB */\r
+#define MCF_USB_OTG_ERR_ENB_PID_ERR_EN (0x1)\r
+#define MCF_USB_OTG_ERR_ENB_CRC5_EOF_EN (0x2)\r
+#define MCF_USB_OTG_ERR_ENB_CRC16_EN (0x4)\r
+#define MCF_USB_OTG_ERR_ENB_DFN8_EN (0x8)\r
+#define MCF_USB_OTG_ERR_ENB_BTO_ERR_EN (0x10)\r
+#define MCF_USB_OTG_ERR_ENB_DMA_ERR_EN (0x20)\r
+#define MCF_USB_OTG_ERR_ENB_BTS_ERR_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_STAT */\r
+#define MCF_USB_OTG_STAT_ODD (0x4)\r
+#define MCF_USB_OTG_STAT_TX (0x8)\r
+#define MCF_USB_OTG_STAT_ENDP(x) (((x)&0xF)<<0x4)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_CTL */\r
+#define MCF_USB_OTG_CTL_USB_EN_SOF_EN (0x1)\r
+#define MCF_USB_OTG_CTL_ODD_RST (0x2)\r
+#define MCF_USB_OTG_CTL_RESUME (0x4)\r
+#define MCF_USB_OTG_CTL_HOST_MODE_EN (0x8)\r
+#define MCF_USB_OTG_CTL_RESET (0x10)\r
+#define MCF_USB_OTG_CTL_TXSUSPEND_TOKENBUSY (0x20)\r
+#define MCF_USB_OTG_CTL_SE0 (0x40)\r
+#define MCF_USB_OTG_CTL_JSTATE (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ADDR */\r
+#define MCF_USB_OTG_ADDR_ADDR(x) (((x)&0x7F)<<0)\r
+#define MCF_USB_OTG_ADDR_LS_EN (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_01 */\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA9 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA10 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA11 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA12 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA13 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA14 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_01_BDT_BA15 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUML */\r
+#define MCF_USB_OTG_FRM_NUML_FRM0 (0x1)\r
+#define MCF_USB_OTG_FRM_NUML_FRM1 (0x2)\r
+#define MCF_USB_OTG_FRM_NUML_FRM2 (0x4)\r
+#define MCF_USB_OTG_FRM_NUML_FRM3 (0x8)\r
+#define MCF_USB_OTG_FRM_NUML_FRM4 (0x10)\r
+#define MCF_USB_OTG_FRM_NUML_FRM5 (0x20)\r
+#define MCF_USB_OTG_FRM_NUML_FRM6 (0x40)\r
+#define MCF_USB_OTG_FRM_NUML_FRM7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_FRM_NUMH */\r
+#define MCF_USB_OTG_FRM_NUMH_FRM8 (0x1)\r
+#define MCF_USB_OTG_FRM_NUMH_FRM9 (0x2)\r
+#define MCF_USB_OTG_FRM_NUMH_FRM10 (0x4)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_TOKEN */\r
+#define MCF_USB_OTG_TOKEN_TOKEN_ENDPT(x) (((x)&0xF)<<0)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID(x) (((x)&0xF)<<0x4)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_OUT (0x10)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_IN (0x90)\r
+#define MCF_USB_OTG_TOKEN_TOKEN_PID_SETUP (0xD0)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_SOF_THLD */\r
+#define MCF_USB_OTG_SOF_THLD_CNT0 (0x1)\r
+#define MCF_USB_OTG_SOF_THLD_CNT1 (0x2)\r
+#define MCF_USB_OTG_SOF_THLD_CNT2 (0x4)\r
+#define MCF_USB_OTG_SOF_THLD_CNT3 (0x8)\r
+#define MCF_USB_OTG_SOF_THLD_CNT4 (0x10)\r
+#define MCF_USB_OTG_SOF_THLD_CNT5 (0x20)\r
+#define MCF_USB_OTG_SOF_THLD_CNT6 (0x40)\r
+#define MCF_USB_OTG_SOF_THLD_CNT7 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_02 */\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA16 (0x1)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA17 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA18 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA19 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA20 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA21 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA22 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_02_BDT_BA23 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_BDT_PAGE_03 */\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA24 (0x1)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA25 (0x2)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA26 (0x4)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA27 (0x8)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA28 (0x10)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA29 (0x20)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA30 (0x40)\r
+#define MCF_USB_OTG_BDT_PAGE_03_BDT_BA31 (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_ENDPT */\r
+#define MCF_USB_OTG_ENDPT_EP_HSHK (0x1)\r
+#define MCF_USB_OTG_ENDPT_EP_STALL (0x2)\r
+#define MCF_USB_OTG_ENDPT_EP_TX_EN (0x4)\r
+#define MCF_USB_OTG_ENDPT_EP_RX_EN (0x8)\r
+#define MCF_USB_OTG_ENDPT_EP_CTL_DIS (0x10)\r
+#define MCF_USB_OTG_ENDPT_RETRY_DIS (0x40)\r
+#define MCF_USB_OTG_ENDPT_HOST_WO_HUB (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_CTRL */\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC(x) (((x)&0x3)<<0)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_ALTCLK (0)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_OSCCLK (0x1)\r
+#define MCF_USB_OTG_USB_CTRL_CLK_SRC_SYSCLK (0x3)\r
+#define MCF_USB_OTG_USB_CTRL_PDE (0x40)\r
+#define MCF_USB_OTG_USB_CTRL_SUSP (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_OBSERVE */\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSDIS (0x2)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSCHG (0x4)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_VBUSE (0x8)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DM_PD (0x10)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PD (0x40)\r
+#define MCF_USB_OTG_USB_OTG_OBSERVE_DP_PU (0x80)\r
+\r
+/* Bit definitions and macros for MCF_USB_OTG_USB_OTG_CONTROL */\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSEND (0x1)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_SESSVLD (0x2)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSVLD (0x4)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_ID (0x8)\r
+#define MCF_USB_OTG_USB_OTG_CONTROL_VBUSD (0x10)\r
+\r
+\r
+#endif /* __MCF52221_USB_OTG_H__ */\r
--- /dev/null
+# Sample Linker Command File for CodeWarrior for ColdFire\r
+\r
+KEEP_SECTION {.vectortable}\r
+\r
+# Memory ranges \r
+\r
+MEMORY {\r
+ vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500\r
+ code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00\r
+ userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000\r
+}\r
+\r
+SECTIONS {\r
+ \r
+# Heap and Stack sizes definition\r
+ ___heap_size = 0x400;\r
+ ___stack_size = 0x400;\r
+\r
+\r
+\r
+# MCF52221 Derivative Memory map definitions from linker command files:\r
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+# symbols must be defined in the linker command file.\r
+\r
+# Memory Mapped Registers (IPSBAR= 0x40000000)\r
+ ___IPSBAR = 0x40000000;\r
+\r
+# 16 Kbytes Internal SRAM\r
+ ___RAMBAR = 0x20000000;\r
+ ___RAMBAR_SIZE = 0x00004000;\r
+\r
+# 128 KByte Internal Flash Memory\r
+ ___FLASHBAR = 0x00000000;\r
+ ___FLASHBAR_SIZE = 0x00020000;\r
+\r
+ ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;\r
+ \r
+ .userram : {} > userram \r
+ .code : {} > code \r
+ .vectorram : {} > vectorram \r
+ \r
+ .vectors :\r
+ {\r
+ exceptions.c(.vectortable)\r
+ . = ALIGN (0x4); \r
+ } >> code\r
+\r
+\r
+ .text :\r
+ {\r
+ *(.text)\r
+ . = ALIGN (0x4);\r
+ *(.rodata)\r
+ . = ALIGN (0x4); \r
+ ___ROM_AT = .;\r
+ ___DATA_ROM = .;\r
+ } >> code\r
+\r
+ .data : AT(___ROM_AT) \r
+ { \r
+ ___DATA_RAM = .;\r
+ . = ALIGN(0x4);\r
+ *(.exception) \r
+ . = ALIGN(0x4); \r
+ __exception_table_start__ = .;\r
+ EXCEPTION\r
+ __exception_table_end__ = .;\r
+ \r
+ ___sinit__ = .;\r
+ STATICINIT\r
+ __START_DATA = .;\r
+\r
+ *(.data)\r
+ . = ALIGN (0x4);\r
+ __END_DATA = .;\r
+\r
+ __START_SDATA = .;\r
+ *(.sdata)\r
+ . = ALIGN (0x4);\r
+ __END_SDATA = .;\r
+\r
+ ___DATA_END = .;\r
+ __SDA_BASE = .;\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+\r
+ .bss :\r
+ {\r
+ ___BSS_START = .;\r
+ __START_SBSS = .;\r
+ *(.sbss)\r
+ . = ALIGN (0x4);\r
+ *(SCOMMON)\r
+ __END_SBSS = .;\r
+\r
+ __START_BSS = .;\r
+ *(.bss)\r
+ . = ALIGN (0x4);\r
+ *(COMMON)\r
+ __END_BSS = .;\r
+ ___BSS_END = .;\r
+\r
+ . = ALIGN(0x4);\r
+ } >> userram\r
+\r
+ .custom :\r
+ {\r
+ ___HEAP_START = .;\r
+ ___heap_addr = ___HEAP_START;\r
+ ___HEAP_END = ___HEAP_START + ___heap_size;\r
+ ___SP_END = ___HEAP_END;\r
+ ___SP_INIT = ___SP_END + ___stack_size;\r
+\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+ \r
+ ___VECTOR_RAM = ADDR(.vectorram);\r
+ \r
+ __SP_INIT = ___SP_INIT;\r
+\r
+ _romp_at = ___ROM_AT + SIZEOF(.data);\r
+ .romp : AT(_romp_at)\r
+ {\r
+ __S_romp = _romp_at;\r
+ WRITEW(___ROM_AT);\r
+ WRITEW(ADDR(.data));\r
+ WRITEW(SIZEOF(.data));\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ }\r
+\r
+}
\ No newline at end of file
--- /dev/null
+# Sample Linker Command File for CodeWarrior for ColdFire\r
+\r
+KEEP_SECTION {.vectortable}\r
+\r
+# Memory ranges \r
+\r
+MEMORY {\r
+ vectorrom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400\r
+ cfmprotrom (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000020 \r
+ code (RX) : ORIGIN = 0x00000500, LENGTH = 0x0001FB00\r
+ vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400\r
+ userram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x00003C00\r
+}\r
+\r
+SECTIONS {\r
+\r
+# Heap and Stack sizes definition\r
+ ___heap_size = 0x1000;\r
+ ___stack_size = 0x1000;\r
+\r
+\r
+\r
+# MCF52221 Derivative Memory map definitions from linker command files:\r
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+# symbols must be defined in the linker command file.\r
+\r
+# Memory Mapped Registers (IPSBAR= 0x40000000)\r
+ ___IPSBAR = 0x40000000;\r
+\r
+# 16 Kbytes Internal SRAM\r
+ ___RAMBAR = 0x20000000;\r
+ ___RAMBAR_SIZE = 0x00004000;\r
+\r
+# 128 KByte Internal Flash Memory\r
+ ___FLASHBAR = 0x00000000;\r
+ ___FLASHBAR_SIZE = 0x00020000;\r
+\r
+ ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;\r
+ \r
+ .userram : {} > userram \r
+ .code : {} > code \r
+ .vectorram : {} > vectorram \r
+ \r
+ .vectors :\r
+ {\r
+ exceptions.c(.vectortable)\r
+ . = ALIGN (0x4); \r
+ } > vectorrom\r
+\r
+ .cfmprotect :\r
+ {\r
+ *(.cfmconfig)\r
+ . = ALIGN (0x4);\r
+ } > cfmprotrom\r
+\r
+ .text :\r
+ {\r
+ *(.text)\r
+ . = ALIGN (0x4);\r
+ *(.rodata)\r
+ . = ALIGN (0x4); \r
+ ___ROM_AT = .;\r
+ ___DATA_ROM = .;\r
+ } >> code\r
+\r
+ .data : AT(___ROM_AT) \r
+ { \r
+ ___DATA_RAM = .;\r
+ . = ALIGN(0x4);\r
+ *(.exception) \r
+ . = ALIGN(0x4); \r
+ __exception_table_start__ = .;\r
+ EXCEPTION\r
+ __exception_table_end__ = .;\r
+ \r
+ ___sinit__ = .;\r
+ STATICINIT\r
+ __START_DATA = .;\r
+\r
+ *(.data)\r
+ . = ALIGN (0x4);\r
+ __END_DATA = .;\r
+\r
+ __START_SDATA = .;\r
+ *(.sdata)\r
+ . = ALIGN (0x4);\r
+ __END_SDATA = .;\r
+\r
+ ___DATA_END = .;\r
+ __SDA_BASE = .;\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+\r
+ .bss :\r
+ {\r
+ ___BSS_START = .;\r
+ __START_SBSS = .;\r
+ *(.sbss)\r
+ . = ALIGN (0x4);\r
+ *(SCOMMON)\r
+ __END_SBSS = .;\r
+\r
+ __START_BSS = .;\r
+ *(.bss)\r
+ . = ALIGN (0x4);\r
+ *(COMMON)\r
+ __END_BSS = .;\r
+ ___BSS_END = .;\r
+\r
+ . = ALIGN(0x4);\r
+ } >> userram\r
+\r
+ .custom :\r
+ {\r
+ ___HEAP_START = .;\r
+ ___heap_addr = ___HEAP_START;\r
+ ___HEAP_END = ___HEAP_START + ___heap_size;\r
+ ___SP_END = ___HEAP_END;\r
+ ___SP_INIT = ___SP_END + ___stack_size;\r
+\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+ \r
+ ___VECTOR_RAM = ADDR(.vectorram);\r
+ \r
+ __SP_INIT = ___SP_INIT;\r
+\r
+ _romp_at = ___ROM_AT + SIZEOF(.data);\r
+ .romp : AT(_romp_at)\r
+ {\r
+ __S_romp = _romp_at;\r
+ WRITEW(___ROM_AT);\r
+ WRITEW(ADDR(.data));\r
+ WRITEW(SIZEOF(.data));\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ }\r
+\r
+}
\ No newline at end of file
--- /dev/null
+# Sample Linker Command File for CodeWarrior for ColdFire\r
+\r
+KEEP_SECTION {.vectortable}\r
+\r
+# Memory ranges \r
+\r
+MEMORY {\r
+ vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000500\r
+ code (RX) : ORIGIN = 0x20000500, LENGTH = 0x00002B00\r
+ userram (RWX) : ORIGIN = 0x20003000, LENGTH = 0x00001000\r
+}\r
+\r
+SECTIONS {\r
+ \r
+# Heap and Stack sizes definition\r
+ ___heap_size = 0x400;\r
+ ___stack_size = 0x400;\r
+\r
+\r
+\r
+# MCF52221 Derivative Memory map definitions from linker command files:\r
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+# symbols must be defined in the linker command file.\r
+\r
+# Memory Mapped Registers (IPSBAR= 0x40000000)\r
+ ___IPSBAR = 0x40000000;\r
+\r
+# 16 Kbytes Internal SRAM\r
+ ___RAMBAR = 0x20000000;\r
+ ___RAMBAR_SIZE = 0x00004000;\r
+\r
+# 128 KByte Internal Flash Memory\r
+ ___FLASHBAR = 0x00000000;\r
+ ___FLASHBAR_SIZE = 0x00020000;\r
+\r
+ ___SP_AFTER_RESET = ___RAMBAR + ___RAMBAR_SIZE - 4;\r
+ \r
+ .userram : {} > userram \r
+ .code : {} > code \r
+ .vectorram : {} > vectorram \r
+ \r
+ .vectors :\r
+ {\r
+ exceptions.c(.vectortable)\r
+ . = ALIGN (0x4); \r
+ } >> code\r
+\r
+\r
+ .text :\r
+ {\r
+ *(.text)\r
+ . = ALIGN (0x4);\r
+ *(.rodata)\r
+ . = ALIGN (0x4); \r
+ ___ROM_AT = .;\r
+ ___DATA_ROM = .;\r
+ } >> code\r
+\r
+ .data : AT(___ROM_AT) \r
+ { \r
+ ___DATA_RAM = .;\r
+ . = ALIGN(0x4);\r
+ *(.exception) \r
+ . = ALIGN(0x4); \r
+ __exception_table_start__ = .;\r
+ EXCEPTION\r
+ __exception_table_end__ = .;\r
+ \r
+ ___sinit__ = .;\r
+ STATICINIT\r
+ __START_DATA = .;\r
+\r
+ *(.data)\r
+ . = ALIGN (0x4);\r
+ __END_DATA = .;\r
+\r
+ __START_SDATA = .;\r
+ *(.sdata)\r
+ . = ALIGN (0x4);\r
+ __END_SDATA = .;\r
+\r
+ ___DATA_END = .;\r
+ __SDA_BASE = .;\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+\r
+ .bss :\r
+ {\r
+ ___BSS_START = .;\r
+ __START_SBSS = .;\r
+ *(.sbss)\r
+ . = ALIGN (0x4);\r
+ *(SCOMMON)\r
+ __END_SBSS = .;\r
+\r
+ __START_BSS = .;\r
+ *(.bss)\r
+ . = ALIGN (0x4);\r
+ *(COMMON)\r
+ __END_BSS = .;\r
+ ___BSS_END = .;\r
+\r
+ . = ALIGN(0x4);\r
+ } >> userram\r
+\r
+ .custom :\r
+ {\r
+ ___HEAP_START = .;\r
+ ___heap_addr = ___HEAP_START;\r
+ ___HEAP_END = ___HEAP_START + ___heap_size;\r
+ ___SP_END = ___HEAP_END;\r
+ ___SP_INIT = ___SP_END + ___stack_size;\r
+\r
+ . = ALIGN (0x4);\r
+ } >> userram\r
+ \r
+ ___VECTOR_RAM = ADDR(.vectorram);\r
+ \r
+ __SP_INIT = ___SP_INIT;\r
+\r
+ _romp_at = ___ROM_AT + SIZEOF(.data);\r
+ .romp : AT(_romp_at)\r
+ {\r
+ __S_romp = _romp_at;\r
+ WRITEW(___ROM_AT);\r
+ WRITEW(ADDR(.data));\r
+ WRITEW(SIZEOF(.data));\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ WRITEW(0);\r
+ }\r
+\r
+}
\ No newline at end of file
--- /dev/null
+//------------------------------------------------------------------------\r
+// Readme.txt\r
+//------------------------------------------------------------------------\r
+This project is configure to get you up and running quickly using \r
+CodeWarrior with the Freescale MCF52221 board.\r
+\r
+This project provides full support for the selected board.\r
+The created project provides Standard IO Support through console and terminal window.\r
+\r
+Sample code for the following language:\r
+- C\r
+\r
+\r
+//------------------------------------------------------------------------\r
+// Memory Maps\r
+//------------------------------------------------------------------------\r
+The Hardware has the following memory map:\r
+\r
+# MCF52221 Derivative Memory map definitions from linker command files:\r
+# __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker\r
+# symbols must be defined in the linker command file.\r
+\r
+# Memory Mapped Registers (IPSBAR= 0x40000000)\r
+ ___IPSBAR = 0x40000000;\r
+\r
+# 16 Kbytes Internal SRAM\r
+ ___RAMBAR = 0x20000000;\r
+ ___RAMBAR_SIZE = 0x00004000;\r
+\r
+# 128 KByte Internal Flash Memory\r
+ ___FLASHBAR = 0x00000000;\r
+ ___FLASHBAR_SIZE = 0x00020000;\r
+\r
+\r
+\r
+//------------------------------------------------------------------------\r
+// Project Structure\r
+//------------------------------------------------------------------------\r
+The project generated contains various files/groups:\r
+- readme.txt: information for this project\r
+- Sources: application source codes, user customizable startup \r
+ code, uart library, exception table\r
+- Includes: derivative and board header files, ... \r
+- Libs: runtime and libs \r
+- Project Settings: linker command files for the different build \r
+ targets, the initialization and memory configuration files for \r
+ the hardware debugging, the common startup code, etc...\r
+ \r
+//------------------------------------------------------------------------\r
+// Build Targets\r
+//------------------------------------------------------------------------\r
+- CONSOLE_INTERNAL_RAM:\r
+This project target is setup to load and debug code from internal RAM.\r
+It should be used during your application development.\r
+The application outputs to the CodeWarrior's console window.\r
+\r
+- INTERNAL_RAM:\r
+This project target is setup to load and debug code from internal RAM.\r
+It should be used during your application development.\r
+This is the very basic project that outputs to the UART.\r
+You needs to connect a Terminal Program to see the output.\r
+\r
+- INTERNAL_FLASH:\r
+This project target is setup to load and debug code in Internal FLASH.\r
+This is the very basic project that outputs to the UART. User needs\r
+to connect the terminal to see the output.\r
+\r
+\r
+\r
+===================================================================\r
+WARNING regarding debugging new project wizard code with CCS-SIM\r
+===================================================================\r
+The CCS-SIM is an instruction set simulator, it does not implement\r
+any peripherals.\r
+The new project generated by the wizard are using startup code \r
+performing some hardware peripheral initializations.\r
+When debugging with the CCS-SIM it might happen that the simulation\r
+stuck on loop using non implemented peripheral register flag as \r
+condition (PLL initialization as example). \r
+In this case, you should either:\r
+- move the PC to next statement\r
+- use a skip point\r
+- define a simulator specific macro which used when define allos you \r
+to comment out the unwanted code in order to debug with CCS-SIM\r
+ \r
+\r
+===================================================================\r
+WARNING regarding code located in RAM\r
+===================================================================\r
+Many possible ColdFire target processors have an external bus, so \r
+you can use large external RAM devices for debugging applications \r
+during development. But some processors do not have an external \r
+bus, so you must accommodate applications in on-chip memory. \r
+Although this on-chip RAM accommodates this CodeWarrior project, \r
+it probably is too small for full development of your application. \r
+Accordingly, for a processor without external bus, you should locate \r
+your applications in flash memory. \r
+\r
+//------------------------------------------------------------------------\r
+// Flashing the code\r
+//------------------------------------------------------------------------\r
+1. Select the appropriate project target and build it\r
+2. Make sure the correct remote connection is selected in the Remote \r
+ Connection debugger panel\r
+3. In the CodeWarrior IDE menu, select Project > Set Default Project \r
+ and select your project\r
+4. In the CodeWarrior IDE menu, select Project > Set Default Target \r
+ and select the project target that has the code you want to flash\r
+5. In the CodeWarrior IDE menu, select Tools > Flash Programmer\r
+6. Go to the flash programmer Target Configuration panel, click Load \r
+ Settings \r
+7. Browse to the <your project location>\cfg sub folder and\r
+ select the flash settings xml file matching your build target \r
+8. Check that Use Custom Settings checkbox is not selected\r
+9. Go to the Erase/Blank Check panel, select the All Sectors option and \r
+ click Erase\r
+10. Go to Program/Verify panel, click Program\r
+11. Your code should now be flashed\r
+\r
+//------------------------------------------------------------------------\r
+// Terminal Settings\r
+//------------------------------------------------------------------------\r
+In case the UART is supported, the terminal should be setup with:\r
+- 19200 bauds,\r
+- 8 data bits,\r
+- no parity,\r
+- 1 stop bit,\r
+- no flow control.\r
+\r
+Please check this file in the project.\r
+\r
+//------------------------------------------------------------------------\r
+// Getting Started\r
+//------------------------------------------------------------------------\r
+To build/debug your project, use the CodeWarrior IDE menu Project > Debug \r
+or press F5. This will launch the debugger. Press again F5 in the \r
+debugger (or the CodeWarrior IDE menu Project > Run) to start the \r
+application. The CodeWarrior IDE menu Project > Break stops the \r
+application.\r
+\r
+//------------------------------------------------------------------------\r
+// Adding your own code\r
+//------------------------------------------------------------------------\r
+Once everything is working as expected, you can begin adding your own code\r
+to the project. Keep in mind that we provide this as an example of how to\r
+get up and running quickly with CodeWarrior. There are certainly other\r
+ways to handle interrupts and set up your linker command file. Feel free\r
+to modify any of the source files provided.\r
+\r
+//------------------------------------------------------------------------\r
+// Additional documentation\r
+//------------------------------------------------------------------------\r
+Read the online documentation provided. In CodeWarrior IDE menu, select\r
+Help > CodeWarrior Help.\r
+\r
+//------------------------------------------------------------------------\r
+// Contacting Freescale\r
+//------------------------------------------------------------------------\r
+For bug reports, technical questions, and suggestions, please use the\r
+forms installed in the Release_Notes folder.\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+#include "support_common.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 100 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 160 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0 ) ) /* The heap size is worked out from the linker script, so this constant is not used. */\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_MUTEXES 1\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+#define configUSE_COUNTING_SEMAPHORES 0\r
+\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+#define configYIELD_INTERRUPT_VECTOR 16UL\r
+#define configKERNEL_INTERRUPT_PRIORITY 1\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4\r
+\r
+void vApplicationSetupInterrupts( void );\r
+\r
+/* Ethernet configuration. */\r
+#define configMAC_0 0x00\r
+#define configMAC_1 0x04\r
+#define configMAC_2 0x9F\r
+#define configMAC_3 0x00\r
+#define configMAC_4 0xAB\r
+#define configMAC_5 0x2B\r
+\r
+#define configIP_ADDR0 192\r
+#define configIP_ADDR1 168\r
+#define configIP_ADDR2 0\r
+#define configIP_ADDR3 11\r
+\r
+#define configGW_ADDR0 172\r
+#define configGW_ADDR1 25\r
+#define configGW_ADDR2 218\r
+#define configGW_ADDR3 3\r
+\r
+#define configNET_MASK0 255\r
+#define configNET_MASK1 255\r
+#define configNET_MASK2 255\r
+#define configNET_MASK3 0\r
+\r
+#define configNUM_FEC_TX_BUFFERS 2\r
+#define configNUM_FEC_RX_BUFFERS 4\r
+#define configFEC_BUFFER_SIZE 1520\r
+#define configUSE_PROMISCUOUS_MODE 0\r
+#define configETHERNET_INPUT_TASK_STACK_SIZE ( 320 )\r
+#define configETHERNET_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
+\r
+#define configPHY_ADDRESS 1\r
+\r
+#if ( configFEC_BUFFER_SIZE & 0x0F ) != 0\r
+ #error configFEC_BUFFER_SIZE must be a multiple of 16.\r
+#endif\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+__declspec(interrupt:0) void vPIT0InterruptHandler( void );\r
+extern unsigned portLONG __VECTOR_RAM[];\r
+\r
+/* Constants used to configure the interrupts. */\r
+#define portPRESCALE_VALUE 64\r
+#define portPRESCALE_REG_SETTING ( 5 << 8 )\r
+#define portPIT_INTERRUPT_ENABLED ( 0x08 )\r
+#define configPIT0_INTERRUPT_VECTOR ( 55 )\r
+\r
+/*\r
+ * FreeRTOS.org requires two interrupts - a tick interrupt generated from a\r
+ * timer source, and a spare interrupt vector used for context switching.\r
+ * The configuration below uses PIT0 for the former, and vector 63 for the\r
+ * latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO\r
+ * NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided\r
+ * here for using alternative interrupt sources.\r
+ *\r
+ * To change the tick interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * peripheral is to be used to generate the tick interrupt.\r
+ *\r
+ * 2) Change the name of the function __cs3_isr_interrupt_119() defined within\r
+ * this file to be correct for the interrupt vector used by the timer peripheral.\r
+ * The name of the function should contain the vector number, so by default vector\r
+ * number 119 is being used.\r
+ *\r
+ * 3) Make sure the tick interrupt is cleared within the interrupt handler function.\r
+ * Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt.\r
+ *\r
+ * To change the spare interrupt source:\r
+ *\r
+ * 1) Modify vApplicationSetupInterrupts() below to be correct for whichever\r
+ * interrupt vector is to be used. Make sure you use a spare interrupt on interrupt\r
+ * controller 0, otherwise the register used to request context switches will also\r
+ * require modification.\r
+ *\r
+ * 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h\r
+ * to be correct for your chosen interrupt vector.\r
+ *\r
+ * 3) Change the name of the function __cs3_isr_interrupt_127() within portasm.S\r
+ * to be correct for whichever vector number is being used. By default interrupt\r
+ * controller 0 number 63 is used, which corresponds to vector number 127.\r
+ */\r
+void vApplicationSetupInterrupts( void )\r
+{\r
+const unsigned portSHORT usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );\r
+\r
+ /* Configure interrupt priority and level and unmask interrupt for PIT0. */\r
+ MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );\r
+ MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );\r
+\r
+ /* Do the same for vector 63 (interrupt controller 0. I don't think the\r
+ write to MCF_INTC0_IMRH is actually required here but is included for\r
+ completeness. */\r
+ MCF_INTC0_ICR16 = ( 0 | configKERNEL_INTERRUPT_PRIORITY << 3 );\r
+ MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK16 | 0x01 );\r
+\r
+ /* Configure PIT0 to generate the RTOS tick. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+ MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );\r
+ MCF_PIT0_PMR = usCompareMatchValue;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+__declspec(interrupt:0) void vPIT0InterruptHandler( void )\r
+{\r
+unsigned portLONG ulSavedInterruptMask;\r
+\r
+ /* Clear the PIT0 interrupt. */\r
+ MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;\r
+\r
+ /* Increment the RTOS tick. */\r
+ ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ vTaskIncrementTick();\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );\r
+\r
+ /* If we are using the pre-emptive scheduler then also request a\r
+ context switch as incrementing the tick could have unblocked a task. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+}\r
--- /dev/null
+/*\r
+ * File: mcf52221_sysinit.c\r
+ * Purpose: Power-on Reset configuration of the MCF52221.\r
+ *\r
+ * Notes: \r
+ *\r
+ */\r
+#include "support_common.h"\r
+#include "exceptions.h"\r
+\r
+\r
+\r
+/********************************************************************/\r
+static void pll_init(void)\r
+{\r
+\r
+ MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 48MHz / 6 = 8MHz \r
+\r
+ /* The PLL pre-divider affects this!!! \r
+ * Multiply 8Mhz reference crystal /CCHR by 10 to acheive system clock of 80Mhz\r
+ */\r
+\r
+ MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;\r
+\r
+ while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))\r
+ {\r
+ }\r
+}\r
+/********************************************************************/\r
+static void scm_init(void)\r
+{\r
+ /*\r
+ * Enable on-chip modules to access internal SRAM\r
+ */\r
+ MCF_SCM_RAMBAR = (0\r
+ | MCF_SCM_RAMBAR_BA(RAMBAR_ADDRESS)\r
+ | MCF_SCM_RAMBAR_BDE);\r
+}\r
+\r
+/********************************************************************/\r
+\r
+ /*\r
+ * Out of reset, the low-level assembly code calls this routine to\r
+ * initialize the mcf5206e for this board. A temporary stack has been\r
+ * setup in the internal SRAM, and the stack pointer will be changed\r
+ * to point to DRAM once this routine returns.\r
+ */\r
+void __initialize_hardware(void)\r
+{\r
+ /*******************************************************\r
+ * Out of reset, the low-level assembly code calls this \r
+ * routine to initialize the MCF52221 modules for the \r
+ * M522223EVB board. \r
+ ********************************************************/\r
+\r
+\r
+ asm \r
+ {\r
+ /* Initialize IPSBAR */\r
+ move.l #__IPSBAR,d0\r
+ andi.l #0xC0000000,d0 // need to mask\r
+ add.l #0x1,d0\r
+ move.l d0,0x40000000\r
+\r
+ \r
+\r
+ /* Initialize FLASHBAR */\r
+ move.l #__FLASHBAR,d0\r
+ andi.l #0xFFF80000,d0 // need to mask\r
+ add.l #0x61,d0\r
+ movec d0,FLASHBAR\r
+\r
+ }\r
+\r
+ \r
+ /* Set real time clock freq */\r
+ MCF_CLOCK_RTCDR = 48000000;\r
+ \r
+ pll_init();\r
+ scm_init();\r
+\r
+ initialize_exceptions();\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * File: mcf52221demo_sysinit.h\r
+ * Purpose: Power-on Reset configuration of the MCF52221.\r
+ *\r
+ * Notes:\r
+ *\r
+ */\r
+\r
+#ifndef __MCF52221DEMO_SYSINIT_H__\r
+#define __MCF52221DEMO_SYSINIT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+\r
+#if ENABLE_UART_SUPPORT==1 \r
+\r
+#define TERMINAL_PORT 0\r
+#define TERMINAL_BAUD kBaud19200\r
+\r
+#endif /* ENABLE_UART_SUPPORT==1 */\r
+\r
+#define SYSTEM_CLOCK_KHZ 80000 /* system bus frequency in kHz */\r
+\r
+\r
+/********************************************************************/\r
+/* __initialize_hardware Startup code routine\r
+ * \r
+ * __initialize_hardware is called by the startup code right after reset, \r
+ * with interrupt disabled and SP pre-set to a valid memory area.\r
+ * Here you should initialize memory and some peripherics;\r
+ * at this point global variables are not initialized yet.\r
+ * The startup code will initialize SP on return of this function.\r
+ */\r
+void __initialize_hardware(void);\r
+\r
+/********************************************************************/\r
+/* __initialize_system Startup code routine\r
+ * \r
+ * __initialize_system is called by the startup code when all languages \r
+ * specific initialization are done to allow additional hardware setup.\r
+ */ \r
+void __initialize_system(void);\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MCF52221DEMO_SYSINIT_H__ */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.3 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ Changes from V2.5.2\r
+\r
+ + All LED's are turned off to start.\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "partest.h"\r
+\r
+#define partstNUM_LEDs 4\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Enable signals as GPIO */\r
+ MCF_GPIO_PTCPAR = 0\r
+ | MCF_GPIO_PTCPAR_DTIN3_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN2_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN1_GPIO\r
+ | MCF_GPIO_PTCPAR_DTIN0_GPIO;\r
+ \r
+ /* Enable signals as digital outputs */\r
+ MCF_GPIO_DDRTC = 0\r
+ | MCF_GPIO_DDRTC_DDRTC3\r
+ | MCF_GPIO_DDRTC_DDRTC2\r
+ | MCF_GPIO_DDRTC_DDRTC1\r
+ | MCF_GPIO_DDRTC_DDRTC0;\r
+\r
+ MCF_GPIO_PORTTC = 0x00; // TURN LEDS OFF\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portBASE_TYPE uxLEDMask;\r
+\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ uxLEDMask = 1UL << uxLED;\r
+ \r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xValue )\r
+ {\r
+ MCF_GPIO_PORTTC |= uxLEDMask;\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC &= ~uxLEDMask;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portBASE_TYPE uxLEDMask;\r
+\r
+ if( uxLED < partstNUM_LEDs )\r
+ {\r
+ uxLEDMask = 1UL << uxLED;\r
+ \r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( MCF_GPIO_PORTTC & uxLEDMask )\r
+ {\r
+ MCF_GPIO_PORTTC &= ~uxLEDMask;\r
+ }\r
+ else\r
+ {\r
+ MCF_GPIO_PORTTC |= uxLEDMask;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+}\r
+\r
--- /dev/null
+\r
+/* CFM init */\r
+\r
+#define KEY_UPPER 0\r
+#define KEY_LOWER 0\r
+#define CFMPROT 0\r
+#define CFMSACC 0\r
+#define CFMDACC 0\r
+#define CFMSEC 0\r
+\r
+#pragma define_section cfmconfig ".cfmconfig" far_absolute R\r
+#pragma explicit_zero_data on\r
+\r
+__declspec(cfmconfig) unsigned long _cfm[6] = {\r
+ KEY_UPPER, /* 0x00000400 */\r
+ KEY_LOWER, /* 0x00000404 */\r
+ CFMPROT, /* 0x00000408 */\r
+ CFMSACC, /* 0x0000040C */\r
+ CFMDACC, /* 0x00000410 */\r
+ CFMSEC, /* 0x00000414 */\r
+};\r
--- /dev/null
+/*\r
+ * File: exceptions.c\r
+ * Purpose: Generic exception handling for ColdFire processors\r
+ *\r
+ */\r
+#include "exceptions.h"\r
+#include "startcf.h"\r
+#include "support_common.h"\r
+#include <ansi_parms.h>\r
+\r
+#define REGISTER_ABI __REGABI__\r
+\r
+extern __declspec(system) unsigned long __VECTOR_RAM[];\r
+#define VECTOR_RAM_ADDRESS (uint32)__VECTOR_RAM\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Set NO_PRINTF to 0 in order the exceptions.c interrupt handler\r
+ * to output messages to the standard io. \r
+ * \r
+ */\r
+#define NO_PRINTF 1\r
+\r
+#if NO_PRINTF\r
+#define VECTORDISPLAY(MESSAGE) asm { nop; };\r
+#define VECTORDISPLAY2(MESSAGE,MESSAGE2) asm { nop; };\r
+#define VECTORDISPLAY3(MESSAGE,MESSAGE2,MESSAGE3) asm { nop; };\r
+#else\r
+#include <stdio.h>\r
+#define VECTORDISPLAY(MESSAGE1) printf(MESSAGE1);\r
+#define VECTORDISPLAY2(MESSAGE1,MESSAGE2) printf(MESSAGE1,MESSAGE2);\r
+#define VECTORDISPLAY3(MESSAGE1,MESSAGE2,MESSAGE3) printf(MESSAGE1,MESSAGE2,MESSAGE3);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+extern unsigned long far _SP_INIT[];\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Handling of the TRK ColdFire libs (printf support in Debugger Terminal) \r
+ * \r
+ * To enable this support (setup by default in CONSOLE_RAM build target\r
+ * if available): \r
+ * - Set CONSOLE_IO_SUPPORT to 1 in this file; this will enable \r
+ * TrapHandler_printf for the trap #14 exception.\r
+ * (this is set by default to 1 in the ColdFire Pre-Processor panel for\r
+ * the CONSOLE_RAM build target)\r
+ *\r
+ * - Make sure the file:\r
+ * {Compiler}ColdFire_Support\msl\MSL_C\MSL_ColdFire\Src\console_io_cf.c\r
+ * is referenced from your project. \r
+ *\r
+ * - Make sure that in the CF Exceptions panel the check box\r
+ * "46 TRAP #14 for Console I/O", in the "User Application Exceptions"\r
+ * area is set.\r
+ *\r
+ */\r
+#ifndef CONSOLE_IO_SUPPORT\r
+#define CONSOLE_IO_SUPPORT 0 \r
+#endif\r
+\r
+#if CONSOLE_IO_SUPPORT\r
+asm void TrapHandler_printf(void) {\r
+ HALT\r
+ RTE\r
+}\r
+#endif \r
+\r
+/***********************************************************************/\r
+/*\r
+ * This is the handler for all exceptions which are not common to all \r
+ * ColdFire Chips. \r
+ *\r
+ * Called by mcf_exception_handler\r
+ * \r
+ */\r
+void derivative_interrupt(unsigned long vector)\r
+{\r
+ if (vector < 64 || vector > 192) {\r
+ VECTORDISPLAY2("User Defined Vector #%d\n",vector);\r
+ }\r
+}\r
+\r
+/***********************************************************************\r
+ *\r
+ * This is the exception handler for all exceptions common to all \r
+ * chips ColdFire. Most exceptions do nothing, but some of the more \r
+ * important ones are handled to some extent.\r
+ *\r
+ * Called by asm_exception_handler \r
+ *\r
+ * The ColdFire family of processors has a simplified exception stack\r
+ * frame that looks like the following:\r
+ *\r
+ * 3322222222221111 111111\r
+ * 1098765432109876 5432109876543210\r
+ * 8 +----------------+----------------+\r
+ * | Program Counter |\r
+ * 4 +----------------+----------------+\r
+ * |FS/Fmt/Vector/FS| SR |\r
+ * SP --> 0 +----------------+----------------+\r
+ *\r
+ * The stack self-aligns to a 4-byte boundary at an exception, with\r
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment\r
+ * (SP += 0,1,2,3 bytes).\r
+ * 31 28 27 26 25 18 17 16 15 0\r
+ * 4 +---------------------------------------+------------------------------------+\r
+ * | Format | FS[3..2] | Vector | FS[1..0] | SR |\r
+ * SP --> 0 +---------------------------------------+------------------------------------+\r
+ */ \r
+#define MCF5XXX_RD_SF_FORMAT(PTR) \\r
+ ((*((unsigned short *)(PTR)) >> 12) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_VECTOR(PTR) \\r
+ ((*((unsigned short *)(PTR)) >> 2) & 0x00FF)\r
+\r
+#define MCF5XXX_RD_SF_FS(PTR) \\r
+ ( ((*((unsigned short *)(PTR)) & 0x0C00) >> 8) | (*((unsigned short *)(PTR)) & 0x0003) )\r
+\r
+#define MCF5XXX_SF_SR(PTR) *(((unsigned short *)(PTR))+1)\r
+\r
+#define MCF5XXX_SF_PC(PTR) *((unsigned long *)(PTR)+1)\r
+\r
+#define MCF5XXX_EXCEPTFMT "%s -- PC = %#08X\n"\r
+\r
+\r
+void mcf_exception_handler(void *framepointer) \r
+{\r
+ volatile unsigned long exceptionStackFrame = (*(unsigned long *)(framepointer)); \r
+ volatile unsigned short stackFrameSR = MCF5XXX_SF_SR(framepointer); \r
+ volatile unsigned short stackFrameWord = (*(unsigned short *)(framepointer)); \r
+ volatile unsigned long stackFrameFormat = (unsigned long)MCF5XXX_RD_SF_FORMAT(&stackFrameWord);\r
+ volatile unsigned long stackFrameFS = (unsigned long)MCF5XXX_RD_SF_FS(&stackFrameWord);\r
+ volatile unsigned long stackFrameVector = (unsigned long)MCF5XXX_RD_SF_VECTOR(&stackFrameWord);\r
+ volatile unsigned long stackFramePC = MCF5XXX_SF_PC(framepointer);\r
+\r
+ switch (stackFrameFormat)\r
+ {\r
+ case 4:\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ break;\r
+ default:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT,"Illegal stack type", stackFramePC);\r
+ break;\r
+ }\r
+\r
+ switch (stackFrameVector)\r
+ {\r
+ case 2:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Access Error", stackFramePC);\r
+ switch (stackFrameFS)\r
+ {\r
+ case 4:\r
+ VECTORDISPLAY("Error on instruction fetch\n");\r
+ break;\r
+ case 8:\r
+ VECTORDISPLAY("Error on operand write\n");\r
+ break;\r
+ case 9:\r
+ VECTORDISPLAY("Attempted write to write-protected space\n");\r
+ break;\r
+ case 12:\r
+ VECTORDISPLAY("Error on operand read\n");\r
+ break;\r
+ default:\r
+ VECTORDISPLAY("Reserved Fault Status Encoding\n");\r
+ break;\r
+ }\r
+ break;\r
+ case 3:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Address Error", stackFramePC);\r
+ switch (stackFrameFS)\r
+ {\r
+ case 4:\r
+ VECTORDISPLAY("Error on instruction fetch\n");\r
+ break;\r
+ case 8:\r
+ VECTORDISPLAY("Error on operand write\n");\r
+ break;\r
+ case 9:\r
+ VECTORDISPLAY("Attempted write to write-protected space\n");\r
+ break;\r
+ case 12:\r
+ VECTORDISPLAY("Error on operand read\n");\r
+ break;\r
+ default:\r
+ VECTORDISPLAY("Reserved Fault Status Encoding\n");\r
+ break;\r
+ }\r
+ break;\r
+ case 4:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Illegal instruction", stackFramePC);\r
+ break;\r
+ case 8:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Privilege violation", stackFramePC);\r
+ break;\r
+ case 9:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Trace Exception", stackFramePC);\r
+ break;\r
+ case 10:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented A-Line Instruction", stackFramePC);\r
+ break;\r
+ case 11:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unimplemented F-Line Instruction", stackFramePC);\r
+ break;\r
+ case 12:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Debug Interrupt", stackFramePC);\r
+ break;\r
+ case 14:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Format Error", stackFramePC);\r
+ break;\r
+ case 15:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Unitialized Interrupt", stackFramePC);\r
+ break;\r
+ case 24:\r
+ VECTORDISPLAY3(MCF5XXX_EXCEPTFMT, "Spurious Interrupt", stackFramePC);\r
+ break;\r
+ case 25:\r
+ case 26:\r
+ case 27:\r
+ case 28:\r
+ case 29:\r
+ case 30:\r
+ case 31:\r
+ VECTORDISPLAY2("Autovector interrupt level %d\n", stackFrameVector - 24);\r
+ break;\r
+ case 32:\r
+ case 33:\r
+ case 34:\r
+ case 35:\r
+ case 36:\r
+ case 37:\r
+ case 38:\r
+ case 39:\r
+ case 40:\r
+ case 41:\r
+ case 42:\r
+ case 43:\r
+ case 44:\r
+ case 45:\r
+ case 46:\r
+ case 47:\r
+ VECTORDISPLAY2("TRAP #%d\n", stackFrameVector - 32);\r
+ break;\r
+ case 5:\r
+ case 6:\r
+ case 7:\r
+ case 13:\r
+ case 16:\r
+ case 17:\r
+ case 18:\r
+ case 19:\r
+ case 20:\r
+ case 21:\r
+ case 22:\r
+ case 23:\r
+ case 48:\r
+ case 49:\r
+ case 50:\r
+ case 51:\r
+ case 52:\r
+ case 53:\r
+ case 54:\r
+ case 55:\r
+ case 56:\r
+ case 57:\r
+ case 58:\r
+ case 59:\r
+ case 60:\r
+ case 61:\r
+ case 62:\r
+ case 63:\r
+ VECTORDISPLAY2("Reserved: #%d\n", stackFrameVector);\r
+ break;\r
+ default:\r
+ derivative_interrupt(stackFrameVector);\r
+ break;\r
+ }\r
+}\r
+\r
+#if REGISTER_ABI\r
+asm void asm_exception_handler(void)\r
+{\r
+ link a6,#0 \r
+ lea -20(sp), sp\r
+ movem.l d0-d2/a0-a1, (sp)\r
+ lea 24(sp),a0 /* A0 point to exception stack frame on the stack */\r
+ jsr mcf_exception_handler\r
+ movem.l (sp), d0-d2/a0-a1\r
+ lea 20(sp), sp\r
+ unlk a6\r
+ rte\r
+}\r
+#else\r
+asm void asm_exception_handler(void)\r
+{\r
+ link a6,#0 \r
+ lea -20(sp), sp\r
+ movem.l d0-d2/a0-a1, (sp)\r
+ pea 24(sp) /* push exception frame address */\r
+ jsr mcf_exception_handler\r
+ movem.l 4(sp), d0-d2/a0-a1\r
+ lea 24(sp), sp\r
+ unlk a6\r
+ rte\r
+}\r
+#endif\r
+\r
+typedef void (* vectorTableEntryType)(void);\r
+\r
+#pragma define_section vectortable ".vectortable" far_absolute R\r
+\r
+/* CF have 255 vector + SP_INIT in the vector table (256 entries)\r
+*/ \r
+__declspec(vectortable) vectorTableEntryType _vect[256] = { /* Interrupt vector table */\r
+ (vectorTableEntryType)__SP_AFTER_RESET, /* 0 (0x000) Initial supervisor SP */\r
+ _startup, /* 1 (0x004) Initial PC */\r
+ asm_exception_handler, /* 2 (0x008) Access Error */\r
+ asm_exception_handler, /* 3 (0x00C) Address Error */\r
+ asm_exception_handler, /* 4 (0x010) Illegal Instruction */\r
+ asm_exception_handler, /* 5 (0x014) Reserved */\r
+ asm_exception_handler, /* 6 (0x018) Reserved */\r
+ asm_exception_handler, /* 7 (0x01C) Reserved */\r
+ asm_exception_handler, /* 8 (0x020) Privilege Violation */\r
+ asm_exception_handler, /* 9 (0x024) Trace */\r
+ asm_exception_handler, /* 10 (0x028) Unimplemented A-Line */\r
+ asm_exception_handler, /* 11 (0x02C) Unimplemented F-Line */\r
+ asm_exception_handler, /* 12 (0x030) Debug Interrupt */\r
+ asm_exception_handler, /* 13 (0x034) Reserved */\r
+ asm_exception_handler, /* 14 (0x038) Format Error */\r
+ asm_exception_handler, /* 15 (0x03C) Unitialized Int */\r
+ asm_exception_handler, /* 16 (0x040) Reserved */\r
+ asm_exception_handler, /* 17 (0x044) Reserved */\r
+ asm_exception_handler, /* 18 (0x048) Reserved */\r
+ asm_exception_handler, /* 19 (0x04C) Reserved */\r
+ asm_exception_handler, /* 20 (0x050) Reserved */\r
+ asm_exception_handler, /* 21 (0x054) Reserved */\r
+ asm_exception_handler, /* 22 (0x058) Reserved */\r
+ asm_exception_handler, /* 23 (0x05C) Reserved */\r
+ asm_exception_handler, /* 24 (0x060) Spurious Interrupt */\r
+ asm_exception_handler, /* 25 (0x064) Autovector Level 1 */\r
+ asm_exception_handler, /* 26 (0x068) Autovector Level 2 */\r
+ asm_exception_handler, /* 27 (0x06C) Autovector Level 3 */\r
+ asm_exception_handler, /* 28 (0x070) Autovector Level 4 */\r
+ asm_exception_handler, /* 29 (0x074) Autovector Level 5 */\r
+ asm_exception_handler, /* 30 (0x078) Autovector Level 6 */\r
+ asm_exception_handler, /* 31 (0x07C) Autovector Level 7 */\r
+ asm_exception_handler, /* 32 (0x080) TRAP #0 */\r
+ asm_exception_handler, /* 33 (0x084) TRAP #1 */\r
+ asm_exception_handler, /* 34 (0x088) TRAP #2 */\r
+ asm_exception_handler, /* 35 (0x08C) TRAP #3 */\r
+ asm_exception_handler, /* 36 (0x090) TRAP #4 */\r
+ asm_exception_handler, /* 37 (0x094) TRAP #5 */\r
+ asm_exception_handler, /* 38 (0x098) TRAP #6 */\r
+ asm_exception_handler, /* 39 (0x09C) TRAP #7 */\r
+ asm_exception_handler, /* 40 (0x0A0) TRAP #8 */\r
+ asm_exception_handler, /* 41 (0x0A4) TRAP #9 */\r
+ asm_exception_handler, /* 42 (0x0A8) TRAP #10 */\r
+ asm_exception_handler, /* 43 (0x0AC) TRAP #11 */\r
+ asm_exception_handler, /* 44 (0x0B0) TRAP #12 */\r
+ asm_exception_handler, /* 45 (0x0B4) TRAP #13 */\r
+#if CONSOLE_IO_SUPPORT \r
+ TrapHandler_printf, /* 46 (0x0B8) TRAP #14 */\r
+#else\r
+ asm_exception_handler, /* 46 (0x0B8) TRAP #14 */\r
+#endif \r
+ asm_exception_handler, /* 47 (0x0BC) TRAP #15 */\r
+ asm_exception_handler, /* 48 (0x0C0) Reserved */\r
+ asm_exception_handler, /* 49 (0x0C4) Reserved */\r
+ asm_exception_handler, /* 50 (0x0C8) Reserved */\r
+ asm_exception_handler, /* 51 (0x0CC) Reserved */\r
+ asm_exception_handler, /* 52 (0x0D0) Reserved */\r
+ asm_exception_handler, /* 53 (0x0D4) Reserved */\r
+ asm_exception_handler, /* 54 (0x0D8) Reserved */\r
+ asm_exception_handler, /* 55 (0x0DC) Reserved */\r
+ asm_exception_handler, /* 56 (0x0E0) Reserved */\r
+ asm_exception_handler, /* 57 (0x0E4) Reserved */\r
+ asm_exception_handler, /* 58 (0x0E8) Reserved */\r
+ asm_exception_handler, /* 59 (0x0EC) Reserved */\r
+ asm_exception_handler, /* 60 (0x0F0) Reserved */\r
+ asm_exception_handler, /* 61 (0x0F4) Reserved */\r
+ asm_exception_handler, /* 62 (0x0F8) Reserved */\r
+ asm_exception_handler, /* 63 (0x0FC) Reserved */\r
+ asm_exception_handler, /* 64 (0x100) Device-specific interrupts */\r
+ asm_exception_handler, /* 65 (0x104) Device-specific interrupts */\r
+ asm_exception_handler, /* 66 (0x108) Device-specific interrupts */\r
+ asm_exception_handler, /* 67 (0x10C) Device-specific interrupts */\r
+ asm_exception_handler, /* 68 (0x110) Device-specific interrupts */\r
+ asm_exception_handler, /* 69 (0x114) Device-specific interrupts */\r
+ asm_exception_handler, /* 70 (0x118) Device-specific interrupts */\r
+ asm_exception_handler, /* 71 (0x11C) Device-specific interrupts */\r
+ asm_exception_handler, /* 72 (0x120) Device-specific interrupts */\r
+ asm_exception_handler, /* 73 (0x124) Device-specific interrupts */\r
+ asm_exception_handler, /* 74 (0x128) Device-specific interrupts */\r
+ asm_exception_handler, /* 75 (0x12C) Device-specific interrupts */\r
+ asm_exception_handler, /* 76 (0x130) Device-specific interrupts */\r
+ asm_exception_handler, /* 77 (0x134) Device-specific interrupts */\r
+ asm_exception_handler, /* 78 (0x138) Device-specific interrupts */\r
+ asm_exception_handler, /* 79 (0x13C) Device-specific interrupts */\r
+ asm_exception_handler, /* 80 (0x140) Device-specific interrupts */\r
+ asm_exception_handler, /* 81 (0x144) Device-specific interrupts */\r
+ asm_exception_handler, /* 82 (0x148) Device-specific interrupts */\r
+ asm_exception_handler, /* 83 (0x14C) Device-specific interrupts */\r
+ asm_exception_handler, /* 84 (0x150) Device-specific interrupts */\r
+ asm_exception_handler, /* 85 (0x154) Device-specific interrupts */\r
+ asm_exception_handler, /* 86 (0x158) Device-specific interrupts */\r
+ asm_exception_handler, /* 87 (0x15C) Device-specific interrupts */\r
+ asm_exception_handler, /* 88 (0x160) Device-specific interrupts */\r
+ asm_exception_handler, /* 89 (0x164) Device-specific interrupts */\r
+ asm_exception_handler, /* 90 (0x168) Device-specific interrupts */\r
+ asm_exception_handler, /* 91 (0x16C) Device-specific interrupts */\r
+ asm_exception_handler, /* 92 (0x170) Device-specific interrupts */\r
+ asm_exception_handler, /* 93 (0x174) Device-specific interrupts */\r
+ asm_exception_handler, /* 94 (0x178) Device-specific interrupts */\r
+ asm_exception_handler, /* 95 (0x17C) Device-specific interrupts */\r
+ asm_exception_handler, /* 96 (0x180) Level 1 software interrupt */\r
+ asm_exception_handler, /* 97 (0x184) Level 2 software interrupt */\r
+ asm_exception_handler, /* 98 (0x188) Level 3 software interrupt */\r
+ asm_exception_handler, /* 99 (0x18C) Level 4 software interrupt */\r
+ asm_exception_handler, /* 100 (0x190) Level 5 software interrupt */\r
+ asm_exception_handler, /* 101 (0x194) Level 6 software interrupt */\r
+ asm_exception_handler, /* 102 (0x198) Level 7 software interrupt */\r
+ asm_exception_handler, /* 103 (0x19C) Reserved */\r
+ asm_exception_handler, /* 104 (0x1A0) Reserved */\r
+ asm_exception_handler, /* 105 (0x1A4) Reserved */\r
+ asm_exception_handler, /* 106 (0x1A8) Reserved */\r
+ asm_exception_handler, /* 107 (0x___) Reserved */\r
+ asm_exception_handler, /* 108 (0x___) Reserved */\r
+ asm_exception_handler, /* 109 (0x___) Reserved */\r
+ asm_exception_handler, /* 110 (0x___) Reserved */\r
+ asm_exception_handler, /* 111 (0x___) Reserved */\r
+ asm_exception_handler, /* 112 (0x___) Reserved */\r
+ asm_exception_handler, /* 113 (0x___) Reserved */\r
+ asm_exception_handler, /* 114 (0x___) Reserved */\r
+ asm_exception_handler, /* 115 (0x___) Reserved */\r
+ asm_exception_handler, /* 116 (0x___) Reserved */\r
+ asm_exception_handler, /* 117 (0x___) Reserved */\r
+ asm_exception_handler, /* 118 (0x___) Reserved */\r
+ asm_exception_handler, /* 119 (0x___) Reserved */\r
+ asm_exception_handler, /* 120 (0x___) Reserved */\r
+ asm_exception_handler, /* 121 (0x___) Reserved */\r
+ asm_exception_handler, /* 122 (0x___) Reserved */\r
+ asm_exception_handler, /* 123 (0x___) Reserved */\r
+ asm_exception_handler, /* 124 (0x___) Reserved */\r
+ asm_exception_handler, /* 125 (0x___) Reserved */\r
+ asm_exception_handler, /* 126 (0x___) Reserved */\r
+ asm_exception_handler, /* 127 (0x___) Reserved */\r
+ asm_exception_handler, /* 128 (0x___) Reserved */\r
+ asm_exception_handler, /* 129 (0x___) Reserved */\r
+ asm_exception_handler, /* 130 (0x___) Reserved */\r
+ asm_exception_handler, /* 131 (0x___) Reserved */\r
+ asm_exception_handler, /* 132 (0x___) Reserved */\r
+ asm_exception_handler, /* 133 (0x___) Reserved */\r
+ asm_exception_handler, /* 134 (0x___) Reserved */\r
+ asm_exception_handler, /* 135 (0x___) Reserved */\r
+ asm_exception_handler, /* 136 (0x___) Reserved */\r
+ asm_exception_handler, /* 137 (0x___) Reserved */\r
+ asm_exception_handler, /* 138 (0x___) Reserved */\r
+ asm_exception_handler, /* 139 (0x___) Reserved */\r
+ asm_exception_handler, /* 140 (0x___) Reserved */\r
+ asm_exception_handler, /* 141 (0x___) Reserved */\r
+ asm_exception_handler, /* 142 (0x___) Reserved */\r
+ asm_exception_handler, /* 143 (0x___) Reserved */\r
+ asm_exception_handler, /* 144 (0x___) Reserved */\r
+ asm_exception_handler, /* 145 (0x___) Reserved */\r
+ asm_exception_handler, /* 146 (0x___) Reserved */\r
+ asm_exception_handler, /* 147 (0x___) Reserved */\r
+ asm_exception_handler, /* 148 (0x___) Reserved */\r
+ asm_exception_handler, /* 149 (0x___) Reserved */\r
+ asm_exception_handler, /* 150 (0x___) Reserved */\r
+ asm_exception_handler, /* 151 (0x___) Reserved */\r
+ asm_exception_handler, /* 152 (0x___) Reserved */\r
+ asm_exception_handler, /* 153 (0x___) Reserved */\r
+ asm_exception_handler, /* 154 (0x___) Reserved */\r
+ asm_exception_handler, /* 155 (0x___) Reserved */\r
+ asm_exception_handler, /* 156 (0x___) Reserved */\r
+ asm_exception_handler, /* 157 (0x___) Reserved */\r
+ asm_exception_handler, /* 158 (0x___) Reserved */\r
+ asm_exception_handler, /* 159 (0x___) Reserved */\r
+ asm_exception_handler, /* 160 (0x___) Reserved */\r
+ asm_exception_handler, /* 161 (0x___) Reserved */\r
+ asm_exception_handler, /* 162 (0x___) Reserved */\r
+ asm_exception_handler, /* 163 (0x___) Reserved */\r
+ asm_exception_handler, /* 164 (0x___) Reserved */\r
+ asm_exception_handler, /* 165 (0x___) Reserved */\r
+ asm_exception_handler, /* 166 (0x___) Reserved */\r
+ asm_exception_handler, /* 167 (0x___) Reserved */\r
+ asm_exception_handler, /* 168 (0x___) Reserved */\r
+ asm_exception_handler, /* 169 (0x___) Reserved */\r
+ asm_exception_handler, /* 170 (0x___) Reserved */\r
+ asm_exception_handler, /* 171 (0x___) Reserved */\r
+ asm_exception_handler, /* 172 (0x___) Reserved */\r
+ asm_exception_handler, /* 173 (0x___) Reserved */\r
+ asm_exception_handler, /* 174 (0x___) Reserved */\r
+ asm_exception_handler, /* 175 (0x___) Reserved */\r
+ asm_exception_handler, /* 176 (0x___) Reserved */\r
+ asm_exception_handler, /* 177 (0x___) Reserved */\r
+ asm_exception_handler, /* 178 (0x___) Reserved */\r
+ asm_exception_handler, /* 179 (0x___) Reserved */\r
+ asm_exception_handler, /* 180 (0x___) Reserved */\r
+ asm_exception_handler, /* 181 (0x___) Reserved */\r
+ asm_exception_handler, /* 182 (0x___) Reserved */\r
+ asm_exception_handler, /* 183 (0x___) Reserved */\r
+ asm_exception_handler, /* 184 (0x___) Reserved */\r
+ asm_exception_handler, /* 185 (0x___) Reserved */\r
+ asm_exception_handler, /* 186 (0x___) Reserved */\r
+ asm_exception_handler, /* 187 (0x___) Reserved */\r
+ asm_exception_handler, /* 188 (0x___) Reserved */\r
+ asm_exception_handler, /* 189 (0x___) Reserved */\r
+ asm_exception_handler, /* 190 (0x___) Reserved */\r
+ asm_exception_handler, /* 191 (0x___) Reserved */\r
+ asm_exception_handler, /* 192 (0x___) Reserved */\r
+ asm_exception_handler, /* 193 (0x___) Reserved */\r
+ asm_exception_handler, /* 194 (0x___) Reserved */\r
+ asm_exception_handler, /* 195 (0x___) Reserved */\r
+ asm_exception_handler, /* 196 (0x___) Reserved */\r
+ asm_exception_handler, /* 197 (0x___) Reserved */\r
+ asm_exception_handler, /* 198 (0x___) Reserved */\r
+ asm_exception_handler, /* 199 (0x___) Reserved */\r
+ asm_exception_handler, /* 200 (0x___) Reserved */\r
+ asm_exception_handler, /* 201 (0x___) Reserved */\r
+ asm_exception_handler, /* 202 (0x___) Reserved */\r
+ asm_exception_handler, /* 203 (0x___) Reserved */\r
+ asm_exception_handler, /* 204 (0x___) Reserved */\r
+ asm_exception_handler, /* 205 (0x___) Reserved */\r
+ asm_exception_handler, /* 206 (0x___) Reserved */\r
+ asm_exception_handler, /* 207 (0x___) Reserved */\r
+ asm_exception_handler, /* 208 (0x___) Reserved */\r
+ asm_exception_handler, /* 209 (0x___) Reserved */\r
+ asm_exception_handler, /* 210 (0x___) Reserved */\r
+ asm_exception_handler, /* 211 (0x___) Reserved */\r
+ asm_exception_handler, /* 212 (0x___) Reserved */\r
+ asm_exception_handler, /* 213 (0x___) Reserved */\r
+ asm_exception_handler, /* 214 (0x___) Reserved */\r
+ asm_exception_handler, /* 215 (0x___) Reserved */\r
+ asm_exception_handler, /* 216 (0x___) Reserved */\r
+ asm_exception_handler, /* 217 (0x___) Reserved */\r
+ asm_exception_handler, /* 218 (0x___) Reserved */\r
+ asm_exception_handler, /* 219 (0x___) Reserved */\r
+ asm_exception_handler, /* 220 (0x___) Reserved */\r
+ asm_exception_handler, /* 221 (0x___) Reserved */\r
+ asm_exception_handler, /* 222 (0x___) Reserved */\r
+ asm_exception_handler, /* 223 (0x___) Reserved */\r
+ asm_exception_handler, /* 224 (0x___) Reserved */\r
+ asm_exception_handler, /* 225 (0x___) Reserved */\r
+ asm_exception_handler, /* 226 (0x___) Reserved */\r
+ asm_exception_handler, /* 227 (0x___) Reserved */\r
+ asm_exception_handler, /* 228 (0x___) Reserved */\r
+ asm_exception_handler, /* 229 (0x___) Reserved */\r
+ asm_exception_handler, /* 230 (0x___) Reserved */\r
+ asm_exception_handler, /* 231 (0x___) Reserved */\r
+ asm_exception_handler, /* 232 (0x___) Reserved */\r
+ asm_exception_handler, /* 233 (0x___) Reserved */\r
+ asm_exception_handler, /* 234 (0x___) Reserved */\r
+ asm_exception_handler, /* 235 (0x___) Reserved */\r
+ asm_exception_handler, /* 236 (0x___) Reserved */\r
+ asm_exception_handler, /* 237 (0x___) Reserved */\r
+ asm_exception_handler, /* 238 (0x___) Reserved */\r
+ asm_exception_handler, /* 239 (0x___) Reserved */\r
+ asm_exception_handler, /* 240 (0x___) Reserved */\r
+ asm_exception_handler, /* 241 (0x___) Reserved */\r
+ asm_exception_handler, /* 242 (0x___) Reserved */\r
+ asm_exception_handler, /* 243 (0x___) Reserved */\r
+ asm_exception_handler, /* 244 (0x___) Reserved */\r
+ asm_exception_handler, /* 245 (0x___) Reserved */\r
+ asm_exception_handler, /* 246 (0x___) Reserved */\r
+ asm_exception_handler, /* 247 (0x___) Reserved */\r
+ asm_exception_handler, /* 248 (0x___) Reserved */\r
+ asm_exception_handler, /* 249 (0x___) Reserved */\r
+ asm_exception_handler, /* 250 (0x___) Reserved */\r
+ asm_exception_handler, /* 251 (0x___) Reserved */\r
+ asm_exception_handler, /* 252 (0x___) Reserved */\r
+ asm_exception_handler, /* 253 (0x___) Reserved */\r
+ asm_exception_handler, /* 254 (0x___) Reserved */\r
+ asm_exception_handler, /* 255 (0x___) Reserved */ \r
+};\r
+\r
+/********************************************************************\r
+ * MCF5xxx ASM utility functions\r
+ */\r
+asm void mcf5xxx_wr_vbr(unsigned long) { /* Set VBR */\r
+ move.l 4(SP),D0\r
+ movec d0,VBR \r
+ nop\r
+ rts \r
+} \r
+\r
+/********************************************************************\r
+ * MCF5xxx startup copy functions:\r
+ *\r
+ * Set VBR and performs RAM vector table initializatiom.\r
+ * The following symbol should be defined in the lcf:\r
+ * __VECTOR_RAM\r
+ *\r
+ * _vect is the start of the exception table in the code\r
+ * In case _vect address is different from __VECTOR_RAM,\r
+ * the vector table is copied from _vect to __VECTOR_RAM.\r
+ * In any case VBR is set to __VECTOR_RAM.\r
+ */ \r
+void initialize_exceptions(void)\r
+{\r
+ /*\r
+ * Memory map definitions from linker command files used by mcf5xxx_startup\r
+ */\r
+\r
+ register uint32 n;\r
+ \r
+ /* \r
+ * Copy the vector table to RAM \r
+ */\r
+ if (__VECTOR_RAM != (unsigned long*)_vect)\r
+ {\r
+ for (n = 0; n < 256; n++)\r
+ __VECTOR_RAM[n] = (unsigned long)_vect[n];\r
+ }\r
+ mcf5xxx_wr_vbr((unsigned long)__VECTOR_RAM);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ * File: exceptions.h\r
+ * Purpose: Generic exception handling for ColdFire processors\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _MCF_EXCEPTIONS_H\r
+#define _MCF_EXCEPTIONS_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/***********************************************************************/\r
+/*\r
+ * This is the handler for all exceptions which are not common to all \r
+ * ColdFire Chips. \r
+ *\r
+ * Called by mcf_exception_handler\r
+ * \r
+ */\r
+void derivative_interrupt(unsigned long vector);\r
+\r
+/***********************************************************************/\r
+/*\r
+ * This is the exception handler for all exceptions common to all \r
+ * chips ColdFire. Most exceptions do nothing, but some of the more \r
+ * important ones are handled to some extent.\r
+ *\r
+ * Called by asm_exception_handler \r
+ */\r
+void mcf_exception_handler(void *framepointer);\r
+\r
+\r
+/***********************************************************************/\r
+/*\r
+ * This is the assembly exception handler defined in the vector table. \r
+ * This function is in assembler so that the frame pointer can be read \r
+ * from the stack.\r
+ * Note that the way to give the stack frame as argument to the c handler\r
+ * depends on the used ABI (Register, Compact or Standard).\r
+ *\r
+ */\r
+asm void asm_exception_handler(void);\r
+\r
+/***********************************************************************/\r
+/* MCF5xxx exceptions table initialization:\r
+ *\r
+ * Set VBR and performs RAM vector table initialization.\r
+ * The following symbol should be defined in the lcf:\r
+ * __VECTOR_RAM\r
+ *\r
+ * _vect is the start of the exception table in the code\r
+ * In case _vect address is different from __VECTOR_RAM,\r
+ * the vector table is copied from _vect to __VECTOR_RAM.\r
+ * In any case VBR is set to __VECTOR_RAM.\r
+ */ \r
+void initialize_exceptions(void);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _MCF_EXCEPTIONS_H */\r
+\r
--- /dev/null
+/*\r
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without modification,\r
+ * are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote products\r
+ * derived from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT\r
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING\r
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY\r
+ * OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+#ifndef __LWIPOPTS_H__\r
+#define __LWIPOPTS_H__\r
+\r
+#define TCPIP_THREAD_NAME "tcp/ip"\r
+#define TCPIP_THREAD_STACKSIZE 350\r
+#define TCPIP_THREAD_PRIO 2\r
+\r
+#define DEFAULT_THREAD_STACKSIZE 200\r
+#define DEFAULT_THREAD_PRIO 1\r
+\r
+#define ETH_PAD_SIZE 2\r
+\r
+#define NOT_LWIP_DEBUG 0\r
+#define DBG_TYPES_ON 0x00\r
+#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF\r
+\r
+#define ETHARP_DEBUG LWIP_DBG_OFF\r
+#define NETIF_DEBUG LWIP_DBG_OFF\r
+#define PBUF_DEBUG LWIP_DBG_OFF\r
+#define API_LIB_DEBUG LWIP_DBG_OFF\r
+#define API_MSG_DEBUG LWIP_DBG_OFF\r
+#define SOCKETS_DEBUG LWIP_DBG_OFF\r
+#define ICMP_DEBUG LWIP_DBG_OFF\r
+#define IGMP_DEBUG LWIP_DBG_OFF\r
+#define INET_DEBUG LWIP_DBG_OFF\r
+#define IP_DEBUG LWIP_DBG_OFF\r
+#define IP_REASS_DEBUG LWIP_DBG_OFF\r
+#define RAW_DEBUG LWIP_DBG_OFF\r
+#define MEM_DEBUG LWIP_DBG_OFF\r
+#define MEMP_DEBUG LWIP_DBG_OFF\r
+#define SYS_DEBUG LWIP_DBG_OFF\r
+#define TCP_DEBUG LWIP_DBG_OFF\r
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF\r
+#define TCP_FR_DEBUG LWIP_DBG_OFF\r
+#define TCP_RTO_DEBUG LWIP_DBG_OFF\r
+#define TCP_CWND_DEBUG LWIP_DBG_OFF\r
+#define TCP_WND_DEBUG LWIP_DBG_OFF\r
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF\r
+#define TCP_RST_DEBUG LWIP_DBG_OFF\r
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF\r
+#define UDP_DEBUG LWIP_DBG_OFF\r
+#define TCPIP_DEBUG LWIP_DBG_OFF\r
+#define PPP_DEBUG LWIP_DBG_OFF\r
+#define SLIP_DEBUG LWIP_DBG_OFF\r
+#define DHCP_DEBUG LWIP_DBG_OFF\r
+#define AUTOIP_DEBUG LWIP_DBG_OFF\r
+#define SNMP_MSG_DEBUG LWIP_DBG_OFF\r
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF\r
+#define DNS_DEBUG LWIP_DBG_OFF\r
+#define LWIP_NOASSERT 0\r
+\r
+#define ETHARP_TRUST_IP_MAC 0\r
+#define LWIP_UDP 0\r
+\r
+/**\r
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain\r
+ * critical regions during buffer allocation, deallocation and memory\r
+ * allocation and deallocation.\r
+ */\r
+#define SYS_LIGHTWEIGHT_PROT 1\r
+\r
+/*\r
+ ------------------------------------\r
+ ---------- Memory options ----------\r
+ ------------------------------------\r
+*/\r
+\r
+/**\r
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU\r
+ * 4 byte alignment -> #define MEM_ALIGNMENT 4\r
+ * 2 byte alignment -> #define MEM_ALIGNMENT 2\r
+ */\r
+#define MEM_ALIGNMENT 4\r
+\r
+/**\r
+ * MEM_SIZE: the size of the heap memory. If the application will send\r
+ * a lot of data that needs to be copied, this should be set high.\r
+ */\r
+#define MEM_SIZE (8*1024)\r
+\r
+/*\r
+ ------------------------------------------------\r
+ ---------- Internal Memory Pool Sizes ----------\r
+ ------------------------------------------------\r
+*/\r
+/**\r
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).\r
+ * If the application sends a lot of data out of ROM (or other static memory),\r
+ * this should be set high.\r
+ */\r
+#define MEMP_NUM_PBUF 20\r
+\r
+/**\r
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.\r
+ * (requires the LWIP_TCP option)\r
+ */\r
+#define MEMP_NUM_TCP_PCB 10\r
+\r
+/**\r
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.\r
+ * (requires the LWIP_TCP option)\r
+ */\r
+#define MEMP_NUM_TCP_SEG 8\r
+\r
+/**\r
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.\r
+ * (requires NO_SYS==0)\r
+ */\r
+#define MEMP_NUM_SYS_TIMEOUT 5\r
+\r
+/**\r
+ * MEMP_NUM_NETBUF: the number of struct netbufs.\r
+ * (only needed if you use the sequential API, like api_lib.c)\r
+ */\r
+#define MEMP_NUM_NETBUF 4\r
+\r
+/**\r
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.\r
+ */\r
+#define PBUF_POOL_SIZE 4\r
+\r
+\r
+/*\r
+ ----------------------------------\r
+ ---------- Pbuf options ----------\r
+ ----------------------------------\r
+*/\r
+\r
+/**\r
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is\r
+ * designed to accomodate single full size TCP frame in one pbuf, including\r
+ * TCP_MSS, IP header, and link header.\r
+ */\r
+#define PBUF_POOL_BUFSIZE 1500\r
+\r
+/*\r
+ ---------------------------------\r
+ ---------- TCP options ----------\r
+ ---------------------------------\r
+*/\r
+/**\r
+ * LWIP_TCP==1: Turn on TCP.\r
+ */\r
+#define LWIP_TCP 1\r
+\r
+/* TCP Maximum segment size. */\r
+#define TCP_MSS 1500\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#define TCP_SND_BUF 1500\r
+\r
+/**\r
+ * TCP_WND: The size of a TCP window.\r
+ */\r
+#define TCP_WND 1500\r
+\r
+/**\r
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.\r
+ */\r
+#define TCP_SYNMAXRTX 4\r
+\r
+/*\r
+ ---------------------------------\r
+ ---------- RAW options ----------\r
+ ---------------------------------\r
+*/\r
+/**\r
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.\r
+ */\r
+#define LWIP_RAW 0\r
+\r
+\r
+/*\r
+ ------------------------------------\r
+ ---------- Socket options ----------\r
+ ------------------------------------\r
+*/\r
+/**\r
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)\r
+ */\r
+#define LWIP_SOCKET 0\r
+\r
+\r
+/*\r
+ ----------------------------------------\r
+ ---------- Statistics options ----------\r
+ ----------------------------------------\r
+*/\r
+/**\r
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.\r
+ */\r
+#define LWIP_STATS 0\r
+\r
+/*\r
+ ----------------------------------\r
+ ---------- DHCP options ----------\r
+ ----------------------------------\r
+*/\r
+/**\r
+ * LWIP_DHCP==1: Enable DHCP module.\r
+ */\r
+#define LWIP_DHCP 0\r
+\r
+\r
+#define LWIP_PROVIDE_ERRNO 0\r
+\r
+#endif /* __LWIPOPTS_H__ */\r
--- /dev/null
+/*\r
+ FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.\r
+\r
+ This file is part of the FreeRTOS.org distribution.\r
+\r
+ FreeRTOS.org is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ FreeRTOS.org is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU General Public License for more details.\r
+\r
+ You should have received a copy of the GNU General Public License\r
+ along with FreeRTOS.org; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ A special exception to the GPL can be applied should you wish to distribute\r
+ a combined work that includes FreeRTOS.org, without being obliged to provide\r
+ the source code for any proprietary components. See the licensing section\r
+ of http://www.FreeRTOS.org for full details of how and when the exception\r
+ can be applied.\r
+\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+ * *\r
+ * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *\r
+ * and even write all or part of your application on your behalf. *\r
+ * See http://www.OpenRTOS.com for details of the services we provide to *\r
+ * expedite your project. *\r
+ * *\r
+ ***************************************************************************\r
+ ***************************************************************************\r
+\r
+ Please ensure to read the configuration and relevant port sections of the\r
+ online documentation.\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler. The WEB\r
+ * documentation provides more details of the standard demo application tasks.\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" task - This only executes every five seconds but has a high priority\r
+ * to ensure it gets processor time. Its main function is to check that all the\r
+ * standard demo tasks are still operational. While no errors have been\r
+ * discovered the check task will toggle an LED every 5 seconds - the toggle\r
+ * rate increasing to 500ms being a visual indication that at least one task has\r
+ * reported unexpected behaviour.\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register still contains its expected value. Each task uses\r
+ * different values. The tasks run with very low priority so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "death.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality - as described at the\r
+top of this file. */\r
+#define mainNO_ERROR_PERIOD ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* The rate at which the LED controlled by the 'check' task will flash should an\r
+error have been detected. */\r
+#define mainERROR_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )\r
+\r
+/* The LED controlled by the 'check' task. */\r
+#define mainCHECK_LED ( 3 )\r
+\r
+/* ComTest constants - there is no free LED for the comtest tasks. */\r
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 19200 )\r
+#define mainCOM_TEST_LED ( 5 )\r
+\r
+/* Task priorities. */\r
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+#define mainWEB_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * Implements the 'check' task functionality as described at the top of this\r
+ * file.\r
+ */\r
+static void prvCheckTask( void *pvParameters );\r
+\r
+/*\r
+ * Implement the 'Reg test' functionality as described at the top of this file.\r
+ */\r
+static void vRegTest1Task( void *pvParameters );\r
+static void vRegTest2Task( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Counters used to detect errors within the reg test tasks. */\r
+static volatile unsigned portLONG ulRegTest1Counter = 0x11111111, ulRegTest2Counter = 0x22222222;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Setup the hardware ready for this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* Start the standard demo tasks. */\r
+ vStartLEDFlashTasks( tskIDLE_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+ vStartQueuePeekTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+\r
+ /* Start the reg test tasks - defined in this file. */\r
+ xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest1Counter, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) &ulRegTest2Counter, tskIDLE_PRIORITY, NULL );\r
+\r
+ /* Create the check task. */\r
+ xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );\r
+\r
+ /* The suicide tasks must be created last as they need to know how many\r
+ tasks were running prior to their creation in order to ascertain whether\r
+ or not the correct/expected number of tasks are running at any given time. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Will only get here if there was insufficient memory to create the idle\r
+ task. */\r
+ for( ;; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTask( void *pvParameters )\r
+{\r
+unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;\r
+portTickType xLastExecutionTime;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ /* Initialise the variable used to control our iteration rate prior to\r
+ its first use. */\r
+ xLastExecutionTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until it is time to run the tests again. */\r
+ vTaskDelayUntil( &xLastExecutionTime, ulTicksToWait );\r
+\r
+ /* Has an error been found in any task? */\r
+ if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x01UL;\r
+ }\r
+\r
+ if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x02UL;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x04UL;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x20UL;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x40UL;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x80UL;\r
+ }\r
+\r
+ if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulError |= 0x200UL;\r
+ }\r
+\r
+ if( ulLastRegTest1Count == ulRegTest1Counter )\r
+ {\r
+ ulError |= 0x1000UL;\r
+ }\r
+\r
+ if( ulLastRegTest2Count == ulRegTest2Counter )\r
+ {\r
+ ulError |= 0x1000UL;\r
+ }\r
+\r
+ ulLastRegTest1Count = ulRegTest1Counter;\r
+ ulLastRegTest2Count = ulRegTest2Counter;\r
+\r
+ /* If an error has been found then increase our cycle rate, and in so\r
+ going increase the rate at which the check task LED toggles. */\r
+ if( ulError != 0 )\r
+ {\r
+ ulTicksToWait = mainERROR_PERIOD;\r
+ }\r
+\r
+ /* Toggle the LED each itteration. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ /* Setup the port used to toggle LEDs. */\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+ /* This will get called if a stack overflow is detected during the context\r
+ switch. Set configCHECK_FOR_STACK_OVERFLOWS to 2 to also check for stack\r
+ problems within nested interrupts, but only do this for debug purposes as\r
+ it will increase the context switch time. */\r
+\r
+ ( void ) pxTask;\r
+ ( void ) pcTaskName;\r
+\r
+ for( ;; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest1Task( void *pvParameters )\r
+{\r
+ /* Sanity check - did we receive the parameter expected? */\r
+ if( pvParameters != &ulRegTest1Counter )\r
+ {\r
+ /* Change here so the check task can detect that an error occurred. */\r
+ for( ;; )\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Set all the registers to known values, then check that each retains its\r
+ expected value - as described at the top of this file. If an error is\r
+ found then the loop counter will no longer be incremented allowing the check\r
+ task to recognise the error. */\r
+ asm volatile ( "reg_test_1_start: \n\t"\r
+ " moveq #1, d0 \n\t"\r
+ " moveq #2, d1 \n\t"\r
+ " moveq #3, d2 \n\t"\r
+ " moveq #4, d3 \n\t"\r
+ " moveq #5, d4 \n\t"\r
+ " moveq #6, d5 \n\t"\r
+ " moveq #7, d6 \n\t"\r
+ " moveq #8, d7 \n\t"\r
+ " move #9, a0 \n\t"\r
+ " move #10, a1 \n\t"\r
+ " move #11, a2 \n\t"\r
+ " move #12, a3 \n\t"\r
+ " move #13, a4 \n\t"\r
+ " move #14, a5 \n\t"\r
+ " move #15, a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #1, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #2, d1 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #3, d2 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #4, d3 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #5, d4 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #6, d5 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #7, d6 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " cmpi.l #8, d7 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a0, d0 \n\t"\r
+ " cmpi.l #9, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a1, d0 \n\t"\r
+ " cmpi.l #10, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a2, d0 \n\t"\r
+ " cmpi.l #11, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a3, d0 \n\t"\r
+ " cmpi.l #12, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a4, d0 \n\t"\r
+ " cmpi.l #13, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a5, d0 \n\t"\r
+ " cmpi.l #14, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move a6, d0 \n\t"\r
+ " cmpi.l #15, d0 \n\t"\r
+ " bne reg_test_1_error \n\t"\r
+ " move ulRegTest1Counter, d0 \n\t"\r
+ " addq #1, d0 \n\t"\r
+ " move d0, ulRegTest1Counter \n\t"\r
+ " bra reg_test_1_start \n\t"\r
+ "reg_test_1_error: \n\t"\r
+ " bra reg_test_1_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vRegTest2Task( void *pvParameters )\r
+{\r
+ /* Sanity check - did we receive the parameter expected? */\r
+ if( pvParameters != &ulRegTest2Counter )\r
+ {\r
+ /* Change here so the check task can detect that an error occurred. */\r
+ for( ;; )\r
+ {\r
+ }\r
+ }\r
+\r
+ /* Set all the registers to known values, then check that each retains its\r
+ expected value - as described at the top of this file. If an error is\r
+ found then the loop counter will no longer be incremented allowing the check\r
+ task to recognise the error. */\r
+ asm volatile ( "reg_test_2_start: \n\t"\r
+ " moveq #10, d0 \n\t"\r
+ " moveq #20, d1 \n\t"\r
+ " moveq #30, d2 \n\t"\r
+ " moveq #40, d3 \n\t"\r
+ " moveq #50, d4 \n\t"\r
+ " moveq #60, d5 \n\t"\r
+ " moveq #70, d6 \n\t"\r
+ " moveq #80, d7 \n\t"\r
+ " move #90, a0 \n\t"\r
+ " move #100, a1 \n\t"\r
+ " move #110, a2 \n\t"\r
+ " move #120, a3 \n\t"\r
+ " move #130, a4 \n\t"\r
+ " move #140, a5 \n\t"\r
+ " move #150, a6 \n\t"\r
+ " \n\t"\r
+ " cmpi.l #10, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #20, d1 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #30, d2 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #40, d3 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #50, d4 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #60, d5 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #70, d6 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " cmpi.l #80, d7 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a0, d0 \n\t"\r
+ " cmpi.l #90, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a1, d0 \n\t"\r
+ " cmpi.l #100, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a2, d0 \n\t"\r
+ " cmpi.l #110, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a3, d0 \n\t"\r
+ " cmpi.l #120, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a4, d0 \n\t"\r
+ " cmpi.l #130, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a5, d0 \n\t"\r
+ " cmpi.l #140, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move a6, d0 \n\t"\r
+ " cmpi.l #150, d0 \n\t"\r
+ " bne reg_test_2_error \n\t"\r
+ " move ulRegTest1Counter, d0 \n\t"\r
+ " addq #1, d0 \n\t"\r
+ " move d0, ulRegTest2Counter \n\t"\r
+ " bra reg_test_2_start \n\t"\r
+ "reg_test_2_error: \n\t"\r
+ " bra reg_test_2_error \n\t"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* To keep the linker happy. */\r
+void exit( int n )\r
+{\r
+ ( void ) n;\r
+ for( ;; ) {}\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+ stdarg version contributed by Christian Ettinger\r
+\r
+ This program is free software; you can redistribute it and/or modify\r
+ it under the terms of the GNU Lesser General Public License as published by\r
+ the Free Software Foundation; either version 2 of the License, or\r
+ (at your option) any later version.\r
+\r
+ This program is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ GNU Lesser General Public License for more details.\r
+\r
+ You should have received a copy of the GNU Lesser General Public License\r
+ along with this program; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+*/\r
+\r
+/*\r
+ putchar is the only external dependency for this file,\r
+ if you have a working putchar, leave it commented out.\r
+ If not, uncomment the define below and\r
+ replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+ //extern int putchar(int c);\r
+ \r
+ if (str) {\r
+ **str = (char)c;\r
+ ++(*str);\r
+ }\r
+ else\r
+ { \r
+ (void)putchar(c);\r
+ }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+ register int pc = 0, padchar = ' ';\r
+\r
+ if (width > 0) {\r
+ register int len = 0;\r
+ register const char *ptr;\r
+ for (ptr = string; *ptr; ++ptr) ++len;\r
+ if (len >= width) width = 0;\r
+ else width -= len;\r
+ if (pad & PAD_ZERO) padchar = '0';\r
+ }\r
+ if (!(pad & PAD_RIGHT)) {\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+ }\r
+ for ( ; *string ; ++string) {\r
+ printchar (out, *string);\r
+ ++pc;\r
+ }\r
+ for ( ; width > 0; --width) {\r
+ printchar (out, padchar);\r
+ ++pc;\r
+ }\r
+\r
+ return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+ char print_buf[PRINT_BUF_LEN];\r
+ register char *s;\r
+ register int t, neg = 0, pc = 0;\r
+ register unsigned int u = (unsigned int)i;\r
+\r
+ if (i == 0) {\r
+ print_buf[0] = '0';\r
+ print_buf[1] = '\0';\r
+ return prints (out, print_buf, width, pad);\r
+ }\r
+\r
+ if (sg && b == 10 && i < 0) {\r
+ neg = 1;\r
+ u = (unsigned int)-i;\r
+ }\r
+\r
+ s = print_buf + PRINT_BUF_LEN-1;\r
+ *s = '\0';\r
+\r
+ while (u) {\r
+ t = (int)u % b;\r
+ if( t >= 10 )\r
+ t += letbase - '0' - 10;\r
+ *--s = (char)(t + '0');\r
+ u /= b;\r
+ }\r
+\r
+ if (neg) {\r
+ if( width && (pad & PAD_ZERO) ) {\r
+ printchar (out, '-');\r
+ ++pc;\r
+ --width;\r
+ }\r
+ else {\r
+ *--s = '-';\r
+ }\r
+ }\r
+\r
+ return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+ register int width, pad;\r
+ register int pc = 0;\r
+ char scr[2];\r
+\r
+ for (; *format != 0; ++format) {\r
+ if (*format == '%') {\r
+ ++format;\r
+ width = pad = 0;\r
+ if (*format == '\0') break;\r
+ if (*format == '%') goto out;\r
+ if (*format == '-') {\r
+ ++format;\r
+ pad = PAD_RIGHT;\r
+ }\r
+ while (*format == '0') {\r
+ ++format;\r
+ pad |= PAD_ZERO;\r
+ }\r
+ for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+ width *= 10;\r
+ width += *format - '0';\r
+ }\r
+ if( *format == 's' ) {\r
+ register char *s = (char *)va_arg( args, int );\r
+ pc += prints (out, s?s:"(null)", width, pad);\r
+ continue;\r
+ }\r
+ if( *format == 'd' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'x' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'X' ) {\r
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+ continue;\r
+ }\r
+ if( *format == 'u' ) {\r
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+ continue;\r
+ }\r
+ if( *format == 'c' ) {\r
+ /* char are converted to int then pushed on the stack */\r
+ scr[0] = (char)va_arg( args, int );\r
+ scr[1] = '\0';\r
+ pc += prints (out, scr, width, pad);\r
+ continue;\r
+ }\r
+ }\r
+ else {\r
+ out:\r
+ printchar (out, *format);\r
+ ++pc;\r
+ }\r
+ }\r
+ if (out) **out = '\0';\r
+ va_end( args );\r
+ return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+ va_list args;\r
+ \r
+ va_start( args, format );\r
+ return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+ va_list args;\r
+ \r
+ ( void ) count;\r
+ \r
+ va_start( args, format );\r
+ return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+ char *ptr = "Hello world!";\r
+ char *np = 0;\r
+ int i = 5;\r
+ unsigned int bs = sizeof(int)*8;\r
+ int mi;\r
+ char buf[80];\r
+\r
+ mi = (1 << (bs-1)) + 1;\r
+ printf("%s\n", ptr);\r
+ printf("printf test\n");\r
+ printf("%s is null pointer\n", np);\r
+ printf("%d = 5\n", i);\r
+ printf("%d = - max int\n", mi);\r
+ printf("char %c = 'a'\n", 'a');\r
+ printf("hex %x = ff\n", 0xff);\r
+ printf("hex %02x = 00\n", 0);\r
+ printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+ printf("%d %s(s)%", 0, "message");\r
+ printf("\n");\r
+ printf("%d %s(s) with %%\n", 0, "message");\r
+ sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+ sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+ sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+ sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+ sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ * printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left "\r
+ * justif: " right"\r
+ * 3: 0003 zero padded\r
+ * 3: 3 left justif.\r
+ * 3: 3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3 left justif.\r
+ * -3: -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int write( int i, char* c, int n)\r
+{\r
+ (void)i;\r
+ (void)n;\r
+ (void)c;\r
+ return 0;\r
+}\r
+\r
--- /dev/null
+/*\r
+ * CF_Startup.c - Default init/startup/termination routines for\r
+ * Embedded Metrowerks C++\r
+ *\r
+ * Copyright © 1993-1998 Metrowerks, Inc. All Rights Reserved.\r
+ * Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved.\r
+ *\r
+ *\r
+ * THEORY OF OPERATION\r
+ *\r
+ * This version of thestartup code is intended for linker relocated\r
+ * executables. The startup code will assign the stack pointer to\r
+ * __SP_INIT, assign the address of the data relative base address\r
+ * to a5, initialize the .bss/.sbss sections to zero, call any\r
+ * static C++ initializers and then call main. Upon returning from\r
+ * main it will call C++ destructors and call exit to terminate.\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#pragma cplusplus off\r
+#endif\r
+#pragma PID off\r
+#pragma PIC off\r
+\r
+#include "startcf.h"\r
+#include "RuntimeConfig.h"\r
+\r
+ /* imported data */\r
+\r
+extern unsigned long far _SP_INIT, _SDA_BASE;\r
+extern unsigned long far _START_BSS, _END_BSS;\r
+extern unsigned long far _START_SBSS, _END_SBSS;\r
+extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;\r
+\r
+ /* imported routines */\r
+\r
+extern void __call_static_initializers(void);\r
+extern int main(int, char **);\r
+extern void exit(int);\r
+\r
+ /* exported routines */\r
+\r
+extern void _ExitProcess(void);\r
+extern asm void _startup(void);\r
+extern void __initialize_hardware(void);\r
+extern void __initialize_system(void);\r
+\r
+\r
+/*\r
+ * Dummy routine for initializing hardware. For user's custom systems, you\r
+ * can create your own routine of the same name that will perform HW\r
+ * initialization. The linker will do the right thing to ignore this\r
+ * definition and use the version in your file.\r
+ */\r
+#pragma overload void __initialize_hardware(void);\r
+void __initialize_hardware(void)\r
+{\r
+}\r
+\r
+/*\r
+ * Dummy routine for initializing systems. For user's custom systems,\r
+ * you can create your own routine of the same name that will perform\r
+ * initialization. The linker will do the right thing to ignore this\r
+ * definition and use the version in your file.\r
+ */\r
+#pragma overload void __initialize_system(void);\r
+void __initialize_system(void)\r
+{\r
+}\r
+\r
+/*\r
+ * Dummy routine for initializing C++. This routine will get overloaded by the C++ runtime.\r
+ */\r
+#pragma overload void __call_static_initializers(void);\r
+void __call_static_initializers(void)\r
+{\r
+}\r
+\r
+/*\r
+ * Routine to copy a single section from ROM to RAM ...\r
+ */\r
+static __declspec(register_abi) void __copy_rom_section(char* dst, const char* src, unsigned long size)\r
+{\r
+ if (dst != src)\r
+ while (size--)\r
+ *dst++ = *src++;\r
+}\r
+\r
+/*\r
+ * Routine that copies all sections the user marked as ROM into\r
+ * their target RAM addresses ...\r
+ *\r
+ * __S_romp is automatically generated by the linker if it\r
+ * is referenced by the program. It is a table of RomInfo\r
+ * structures. The final entry in the table has all-zero\r
+ * fields.\r
+ */\r
+static void __copy_rom_sections_to_ram(void)\r
+{\r
+ RomInfo *info;\r
+\r
+ /*\r
+ * Go through the entire table, copying sections from ROM to RAM.\r
+ */\r
+ for (info = _S_romp; info->Source != 0L || info->Target != 0L || info->Size != 0; ++info)\r
+ __copy_rom_section( (char *)info->Target,(char *)info->Source, info->Size);\r
+ \r
+}\r
+\r
+/*\r
+ * Exit handler called from the exit routine, if your OS needs\r
+ * to do something special for exit handling just replace this\r
+ * routines with what the OS needs to do ...\r
+ */\r
+asm void _ExitProcess(void)\r
+{\r
+ illegal\r
+ rts\r
+}\r
+\r
+/*\r
+ * Routine to clear out blocks of memory should give good\r
+ * performance regardless of 68k or ColdFire part.\r
+ */\r
+static __declspec(register_abi) void clear_mem(char *dst, unsigned long n)\r
+{\r
+ unsigned long i;\r
+ long *lptr;\r
+\r
+ if (n >= 32)\r
+ {\r
+ /* align start address to a 4 byte boundary */\r
+ i = (- (unsigned long) dst) & 3;\r
+\r
+ if (i)\r
+ {\r
+ n -= i;\r
+ do\r
+ *dst++ = 0;\r
+ while (--i);\r
+ }\r
+\r
+ /* use an unrolled loop to zero out 32byte blocks */\r
+ i = n >> 5;\r
+ if (i)\r
+ {\r
+ lptr = (long *)dst;\r
+ dst += i * 32;\r
+ do\r
+ {\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ *lptr++ = 0;\r
+ }\r
+ while (--i);\r
+ }\r
+ i = (n & 31) >> 2;\r
+\r
+ /* handle any 4 byte blocks left */\r
+ if (i)\r
+ {\r
+ lptr = (long *)dst;\r
+ dst += i * 4;\r
+ do\r
+ *lptr++ = 0;\r
+ while (--i);\r
+ }\r
+ n &= 3;\r
+ }\r
+\r
+ /* handle any byte blocks left */\r
+ if (n)\r
+ do\r
+ *dst++ = 0;\r
+ while (--n);\r
+}\r
+\r
+/*\r
+ * Startup routine for embedded application ...\r
+ */\r
+\r
+asm void _startup(void)\r
+{\r
+ /* disable interrupts */\r
+ move.w #0x2700,sr\r
+\r
+ /* Pre-init SP, in case memory for stack is not valid it should be setup using \r
+ MEMORY_INIT before __initialize_hardware is called \r
+ */\r
+ lea __SP_AFTER_RESET,a7; \r
+\r
+ /* initialize memory */\r
+ MEMORY_INIT\r
+\r
+ /* initialize any hardware specific issues */\r
+ jsr __initialize_hardware \r
+ \r
+ /* setup the stack pointer */\r
+ lea _SP_INIT,a7\r
+\r
+ /* setup A6 dummy stackframe */\r
+ movea.l #0,a6\r
+ link a6,#0\r
+\r
+ /* setup A5 */\r
+ lea _SDA_BASE,a5\r
+\r
+\r
+ /* zero initialize the .bss section */\r
+\r
+ lea _END_BSS, a0\r
+ lea _START_BSS, a1\r
+ suba.l a1, a0\r
+ move.l a0, d0\r
+\r
+ beq __skip_bss__\r
+\r
+ lea _START_BSS, a0\r
+\r
+ /* call clear_mem with base pointer in a0 and size in d0 */\r
+ jsr clear_mem\r
+\r
+__skip_bss__:\r
+\r
+ /* zero initialize the .sbss section */\r
+\r
+ lea _END_SBSS, a0\r
+ lea _START_SBSS, a1\r
+ suba.l a1, a0\r
+ move.l a0, d0\r
+\r
+ beq __skip_sbss__\r
+\r
+ lea _START_SBSS, a0\r
+\r
+ /* call clear_mem with base pointer in a0 and size in d0 */\r
+ jsr clear_mem\r
+\r
+__skip_sbss__:\r
+\r
+ /* copy all ROM sections to their RAM locations ... */\r
+#if SUPPORT_ROM_TO_RAM\r
+\r
+ /*\r
+ * _S_romp is a null terminated array of\r
+ * typedef struct RomInfo {\r
+ * unsigned long Source;\r
+ * unsigned long Target;\r
+ * unsigned long Size;\r
+ * } RomInfo;\r
+ *\r
+ * Watch out if you're rebasing using _PICPID_DELTA\r
+ */\r
+\r
+ lea _S_romp, a0\r
+ move.l a0, d0\r
+ beq __skip_rom_copy__ \r
+ jsr __copy_rom_sections_to_ram\r
+\r
+#else\r
+\r
+ /*\r
+ * There's a single block to copy from ROM to RAM, perform\r
+ * the copy directly without using the __S_romp structure\r
+ */\r
+\r
+ lea __DATA_RAM, a0\r
+ lea __DATA_ROM, a1\r
+ \r
+ cmpa a0,a1\r
+ beq __skip_rom_copy__\r
+ \r
+ move.l #__DATA_END, d0\r
+ sub.l a0, d0\r
+ \r
+ jsr __copy_rom_section\r
+\r
+#endif\r
+__skip_rom_copy__:\r
+ \r
+ /* call C++ static initializers (__sinit__(void)) */\r
+ jsr __call_static_initializers\r
+\r
+ jsr __initialize_system\r
+\r
+ /* call main(int, char **) */\r
+ pea __argv\r
+ clr.l -(sp) /* clearing a long is ok since it's caller cleanup */\r
+ jsr main\r
+ addq.l #8, sp\r
+ \r
+ unlk a6\r
+ \r
+ /* now call exit(0) to terminate the application */\r
+ clr.l -(sp)\r
+ jsr exit\r
+ addq.l #4, sp\r
+\r
+ /* should never reach here but just in case */\r
+ illegal\r
+ rts\r
+\r
+ /* exit will never return */\r
+__argv:\r
+ dc.l 0\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ FILE : startcf.h\r
+ PURPOSE : startup code for ColdFire\r
+ LANGUAGE: C\r
+\r
+\r
+ Notes:\r
+ 1) Default entry point is _startup. \r
+ . disable interrupts\r
+ . the SP is set to __SP_AFTER_RESET\r
+ . SP must be initialized to valid memory \r
+ in case the memory it points to is not valid using MEMORY_INIT macro\r
+ 2) __initialize_hardware is called. Here you can initialize memory and some peripherics\r
+ at this point global variables are not initialized yet\r
+ 3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform \r
+ needed initialisations for the language (clear memory, data rom copy).\r
+ 4) void __initialize_system(void); is called\r
+ to allow additional hardware initialization (UART, GPIOs, etc...)\r
+ 5) Jump to main \r
+\r
+*/\r
+/********************************************************************************/\r
+\r
+#ifndef STARTCF_H\r
+#define STARTCF_H\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "support_common.h"\r
+\r
+extern unsigned long far __SP_INIT[];\r
+extern unsigned long far __SP_AFTER_RESET[];\r
+\r
+\r
+#ifndef MEMORY_INIT\r
+/* If MEMORY_INIT is set then it performs\r
+ minimal memory initialization (to preset SP to __SP_AFTER_RESET, etc...)\r
+*/\r
+#define MEMORY_INIT\r
+#endif\r
+ \r
+\r
+void _startup(void);\r
+\r
+#ifndef SUPPORT_ROM_TO_RAM\r
+ /*\r
+ * If SUPPORT_ROM_TO_RAM is set, _S_romp is used to define the copy to be performed.\r
+ * If it is not set, there's a single block to copy, performed directly without \r
+ * using the __S_romp structure, based on __DATA_RAM, __DATA_ROM and\r
+ * __DATA_END symbols.\r
+ *\r
+ * Set to 0 for more aggressive dead stripping ...\r
+ */\r
+#define SUPPORT_ROM_TO_RAM 1\r
+#endif\r
+\r
+/* format of the ROM table info entry ... */\r
+typedef struct RomInfo {\r
+ void *Source;\r
+ void *Target;\r
+ unsigned long Size;\r
+} RomInfo;\r
+\r
+/* imported data */\r
+extern far RomInfo _S_romp[]; /* linker defined symbol */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/* FILENAME: stdlib.c\r
+ *\r
+ * Functions normally found in a standard C lib.\r
+ *\r
+ * 12/28/2005 - added memcmp and memmove\r
+ *\r
+ * Notes: These functions support ASCII only!!!\r
+ */\r
+\r
+#include "support_common.h"\r
+#include "stdlib.h"\r
+\r
+/***********************************************************************/\r
+/*\r
+ * Misc. Defines\r
+ */\r
+#ifdef FALSE\r
+#undef FALSE\r
+#endif\r
+#define FALSE (0)\r
+\r
+#ifdef TRUE\r
+#undef TRUE\r
+#endif\r
+#define TRUE (1)\r
+\r
+#ifdef NULL\r
+#undef NULL\r
+#endif\r
+#define NULL (0)\r
+\r
+#ifdef ON\r
+#undef ON\r
+#endif\r
+#define ON (1)\r
+\r
+#ifdef OFF\r
+#undef OFF\r
+#endif\r
+#define OFF (0)\r
+\r
+\r
+/****************************************************************/\r
+int\r
+isspace (int ch)\r
+{\r
+ if ((ch == ' ') || (ch == '\t')) /* \n ??? */\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isalnum (int ch)\r
+{\r
+ /* ASCII only */\r
+ if (((ch >= '0') && (ch <= '9')) ||\r
+ ((ch >= 'A') && (ch <= 'Z')) ||\r
+ ((ch >= 'a') && (ch <= 'z')))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isdigit (int ch)\r
+{\r
+ /* ASCII only */\r
+ if ((ch >= '0') && (ch <= '9'))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+isupper (int ch)\r
+{\r
+ /* ASCII only */\r
+ if ((ch >= 'A') && (ch <= 'Z'))\r
+ return TRUE;\r
+ else\r
+ return FALSE;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strcasecmp (const char *s1, const char *s2)\r
+{\r
+ char c1, c2;\r
+ int result = 0;\r
+\r
+ while (result == 0)\r
+ {\r
+ c1 = *s1++;\r
+ c2 = *s2++;\r
+ if ((c1 >= 'a') && (c1 <= 'z'))\r
+ c1 = (char)(c1 - ' ');\r
+ if ((c2 >= 'a') && (c2 <= 'z'))\r
+ c2 = (char)(c2 - ' ');\r
+ if ((result = (c1 - c2)) != 0)\r
+ break;\r
+ if ((c1 == 0) || (c2 == 0))\r
+ break;\r
+ }\r
+ return result;\r
+}\r
+\r
+\r
+/****************************************************************/\r
+int\r
+stricmp (const char *s1, const char *s2)\r
+{\r
+ return (strcasecmp(s1, s2));\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strncasecmp (const char *s1, const char *s2, int n)\r
+{\r
+ char c1, c2;\r
+ int k = 0;\r
+ int result = 0;\r
+\r
+ while ( k++ < n )\r
+ {\r
+ c1 = *s1++;\r
+ c2 = *s2++;\r
+ if ((c1 >= 'a') && (c1 <= 'z'))\r
+ c1 = (char)(c1 - ' ');\r
+ if ((c2 >= 'a') && (c2 <= 'z'))\r
+ c2 = (char)(c2 - ' ');\r
+ if ((result = (c1 - c2)) != 0)\r
+ break;\r
+ if ((c1 == 0) || (c2 == 0))\r
+ break;\r
+ }\r
+ return result;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strnicmp (const char *s1, const char *s2, int n)\r
+{\r
+ return (strncasecmp(s1, s2, n));\r
+}\r
+\r
+/****************************************************************/\r
+uint32\r
+strtoul (char *str, char **ptr, int base)\r
+{\r
+ unsigned long rvalue = 0;\r
+ int neg = 0;\r
+ int c;\r
+\r
+ /* Validate parameters */\r
+ if ((str != NULL) && (base >= 0) && (base <= 36))\r
+ {\r
+ /* Skip leading white spaces */\r
+ while (isspace(*str))\r
+ {\r
+ ++str;\r
+ }\r
+\r
+ /* Check for notations */\r
+ switch (str[0])\r
+ {\r
+ case '0':\r
+ if (base == 0)\r
+ {\r
+ if ((str[1] == 'x') || (str[1] == 'X'))\r
+ {\r
+ base = 16;\r
+ str += 2;\r
+ }\r
+ else\r
+ {\r
+ base = 8;\r
+ str++;\r
+ }\r
+ }\r
+ break;\r
+ \r
+ case '-':\r
+ neg = 1;\r
+ str++;\r
+ break;\r
+\r
+ case '+':\r
+ str++;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if (base == 0)\r
+ base = 10;\r
+\r
+ /* Valid "digits" are 0..9, A..Z, a..z */\r
+ while (isalnum(c = *str))\r
+ {\r
+ /* Convert char to num in 0..36 */\r
+ if ((c -= ('a' - 10)) < 10) /* 'a'..'z' */\r
+ {\r
+ if ((c += ('a' - 'A')) < 10) /* 'A'..'Z' */\r
+ {\r
+ c += ('A' - '0' - 10); /* '0'..'9' */\r
+ }\r
+ }\r
+\r
+ /* check c against base */\r
+ if (c >= base)\r
+ {\r
+ break;\r
+ }\r
+\r
+ if (neg)\r
+ {\r
+ rvalue = (rvalue * base) - c;\r
+ }\r
+ else\r
+ {\r
+ rvalue = (rvalue * base) + c;\r
+ }\r
+\r
+ ++str;\r
+ }\r
+ }\r
+\r
+ /* Upon exit, 'str' points to the character at which valid info */\r
+ /* STOPS. No chars including and beyond 'str' are used. */\r
+\r
+ if (ptr != NULL)\r
+ *ptr = str;\r
+ \r
+ return rvalue;\r
+ }\r
+\r
+/****************************************************************/\r
+int\r
+atoi (const char *str)\r
+{\r
+ char *s = (char *)str;\r
+ \r
+ return ((int)strtoul(s, NULL, 10));\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strlen (const char *str)\r
+{\r
+ char *s = (char *)str;\r
+ int len = 0;\r
+\r
+ if (s == NULL)\r
+ return 0;\r
+\r
+ while (*s++ != '\0')\r
+ ++len;\r
+\r
+ return len;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strcat (char *dest, const char *src)\r
+{\r
+ char *dp;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL))\r
+ {\r
+ dp = &dest[strlen(dest)];\r
+\r
+ while (*sp != '\0')\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strncat (char *dest, const char *src, int n)\r
+{\r
+ char *dp;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ dp = &dest[strlen(dest)];\r
+\r
+ while ((*sp != '\0') && (n-- > 0))\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strcpy (char *dest, const char *src)\r
+{\r
+ char *dp = (char *)dest;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL))\r
+ {\r
+ while (*sp != '\0')\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strncpy (char *dest, const char *src, int n)\r
+{\r
+ char *dp = (char *)dest;\r
+ char *sp = (char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ while ((*sp != '\0') && (n-- > 0))\r
+ {\r
+ *dp++ = *sp++;\r
+ }\r
+ *dp = '\0';\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strcmp (const char *s1, const char *s2)\r
+{\r
+ /* No checks for NULL */\r
+ char *s1p = (char *)s1;\r
+ char *s2p = (char *)s2;\r
+\r
+ while (*s2p != '\0')\r
+ {\r
+ if (*s1p != *s2p)\r
+ break;\r
+\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ return (*s1p - *s2p);\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+strncmp (const char *s1, const char *s2, int n)\r
+{\r
+ /* No checks for NULL */\r
+ char *s1p = (char *)s1;\r
+ char *s2p = (char *)s2;\r
+\r
+ if (n <= 0)\r
+ return 0;\r
+\r
+ while (*s2p != '\0')\r
+ {\r
+ if (*s1p != *s2p)\r
+ break;\r
+\r
+ if (--n == 0)\r
+ break;\r
+\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ return (*s1p - *s2p);\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strstr(const char *s1, const char *s2)\r
+{\r
+ char *sp = (char *)s1;\r
+ int len1 = strlen(s1);\r
+ int len2 = strlen(s2);\r
+\r
+ while (len1 >= len2) \r
+ {\r
+ if (strncmp(sp, s2, len2) == 0)\r
+ {\r
+ return (sp);\r
+ }\r
+ ++sp;\r
+ --len1;\r
+ }\r
+\r
+ return (NULL);\r
+}\r
+\r
+/****************************************************************/\r
+char *\r
+strchr(const char *str, int c)\r
+{\r
+ char *sp = (char *)str;\r
+ char ch = (char)(c & 0xff);\r
+\r
+ while (*sp != '\0')\r
+ {\r
+ if (*sp == ch)\r
+ {\r
+ return (sp);\r
+ }\r
+ ++sp;\r
+ }\r
+\r
+ return (NULL);\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memcpy (void *dest, const void *src, unsigned n)\r
+{\r
+ unsigned char *dbp = (unsigned char *)dest;\r
+ unsigned char *sbp = (unsigned char *)src;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ while (n--)\r
+ *dbp++ = *sbp++;\r
+ }\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memset (void *s, int c, unsigned n)\r
+{\r
+ /* Not optimized, but very portable */\r
+ unsigned char *sp = (unsigned char *)s;\r
+\r
+ if ((s != NULL) && (n > 0))\r
+ {\r
+ while (n--)\r
+ {\r
+ *sp++ = (unsigned char)c;\r
+ }\r
+ }\r
+ return s;\r
+}\r
+\r
+/****************************************************************/\r
+int\r
+memcmp (const void *s1, const void *s2, unsigned n)\r
+{\r
+ unsigned char *s1p, *s2p;\r
+\r
+ if (s1 && s2 && (n > 0))\r
+ {\r
+ s1p = (unsigned char *)s1;\r
+ s2p = (unsigned char *)s2;\r
+\r
+ while ((--n >= 0) && (*s1p == *s2p))\r
+ {\r
+ if (*s1p != *s2p)\r
+ return (*s1p - *s2p);\r
+ ++s1p;\r
+ ++s2p;\r
+ }\r
+ }\r
+\r
+ return (0);\r
+}\r
+\r
+/****************************************************************/\r
+void *\r
+memmove (void *dest, const void *src, unsigned n)\r
+{\r
+ unsigned char *dbp = (unsigned char *)dest;\r
+ unsigned char *sbp = (unsigned char *)src;\r
+ unsigned char *dend = dbp + n;\r
+ unsigned char *send = sbp + n;\r
+\r
+ if ((dest != NULL) && (src != NULL) && (n > 0))\r
+ {\r
+ /* see if a memcpy would overwrite source buffer */\r
+ if ((sbp < dbp) && (dbp < send))\r
+ {\r
+ while (n--)\r
+ *(--dend) = *(--send);\r
+ }\r
+ else\r
+ {\r
+ while (n--)\r
+ *dbp++ = *sbp++;\r
+ }\r
+ }\r
+\r
+ return dest;\r
+}\r
+\r
+/****************************************************************/\r
--- /dev/null
+/*\r
+ * File: stdlib.h\r
+ * Purpose: Function prototypes for standard library functions\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _STDLIB_H\r
+#define _STDLIB_H\r
+\r
+/********************************************************************\r
+ * Standard library functions\r
+ ********************************************************************/\r
+\r
+int\r
+isspace (int);\r
+\r
+int\r
+isalnum (int);\r
+\r
+int\r
+isdigit (int);\r
+\r
+int\r
+isupper (int);\r
+\r
+int\r
+strcasecmp (const char *, const char *);\r
+\r
+int\r
+strncasecmp (const char *, const char *, int);\r
+\r
+unsigned long\r
+strtoul (char *, char **, int);\r
+\r
+int\r
+strlen (const char *);\r
+\r
+char *\r
+strcat (char *, const char *);\r
+\r
+char *\r
+strncat (char *, const char *, int);\r
+\r
+char *\r
+strcpy (char *, const char *);\r
+\r
+char *\r
+strncpy (char *, const char *, int);\r
+\r
+int\r
+strcmp (const char *, const char *);\r
+\r
+int\r
+strncmp (const char *, const char *, int);\r
+\r
+void *\r
+memcpy (void *, const void *, unsigned);\r
+\r
+void *\r
+memset (void *, int, unsigned);\r
+\r
+void\r
+free (void *);\r
+ \r
+void *\r
+malloc (unsigned);\r
+\r
+#define RAND_MAX 32767\r
+\r
+int\r
+rand (void);\r
+\r
+void\r
+srand (int);\r
+\r
+/********************************************************************/\r
+\r
+#endif\r
--- /dev/null
+/*\r
+* File: support_common.h\r
+ * Purpose: Various project configurations.\r
+ *\r
+ * Notes:\r
+ */\r
+\r
+#ifndef _SUPPORT_COMMON_H_\r
+#define _SUPPORT_COMMON_H_\r
+\r
+/* Enable UART Support. */\r
+#define ENABLE_UART_SUPPORT 0\r
+\r
+\r
+#define MEMORY_INIT \\r
+ /* Initialize RAMBAR: locate SRAM and validate it */ \\r
+ move.l %#__RAMBAR + 0x21,d0; \\r
+ movec d0,RAMBAR;\r
+\r
+#define SUPPORT_ROM_TO_RAM 1\r
+\r
+/*\r
+ * Include the derivative header files\r
+ */\r
+#include "MCF52221.h"\r
+\r
+/*\r
+ * Include the board specific header files\r
+ */\r
+#include "MCF52221_sysinit.h"\r
+\r
+/********************************************************************/\r
+\r
+#endif /* _SUPPORT_COMMON_H_ */\r
+\r
--- /dev/null
+/*\r
+ * File: uart_support.c\r
+ * Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed \r
+ * for MSL Support (printf\cout to terminal), defined in <UART.h>\r
+ *\r
+ * Notes: \r
+ * \r
+ */\r
+#include "support_common.h"\r
+#include "uart_support.h"\r
+\r
+#if ENABLE_UART_SUPPORT==1\r
+\r
+\r
+#if UART_SUPPORT_TYPE==UART_PSC\r
+/* 5475 & 5485 boards have different names for uart access registers */\r
+void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate)\r
+{\r
+ register uint16 ubgs;\r
+\r
+ /* \r
+ * On Verdi, only PSC 0 & 1 are brought out to RS232 transceivers\r
+ */\r
+\r
+ /* Put PSC in UART mode */\r
+ MCF_PSC_PSCSICR(channel) = MCF_PSC_PSCSICR_SIM_UART;\r
+\r
+ /* Rx and Tx baud rate from timers */\r
+ MCF_PSC_PSCCSR(channel) = (0\r
+ | MCF_PSC_PSCCSR_RCSEL_SYS_CLK \r
+ | MCF_PSC_PSCCSR_TCSEL_SYS_CLK);\r
+\r
+ /*\r
+ * Calculate baud settings\r
+ */\r
+ ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32));\r
+\r
+ MCF_PSC_PSCCTUR(channel) = (uint8) ((ubgs >> 8) & 0xFF);\r
+ MCF_PSC_PSCCTLR(channel) = (uint8) (ubgs & 0xFF);\r
+\r
+ /* Reset transmitter, receiver, mode register, and error conditions */\r
+ MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_RX;\r
+ MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_TX;\r
+ MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_ERROR;\r
+ MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_BKCHGINT;\r
+ MCF_PSC_PSCCR(channel) = MCF_PSC_PSCCR_RESET_MR;\r
+\r
+ /* 8-bit data, no parity */\r
+ MCF_PSC_PSCMR(channel) = (0\r
+#ifdef UART_HARDWARE_FLOW_CONTROL\r
+ | MCF_PSC_PSCMR_RXRTS\r
+#endif\r
+ | MCF_PSC_PSCMR_PM_NONE\r
+ | MCF_PSC_PSCMR_BC_8);\r
+\r
+ /* No echo or loopback, 1 stop bit */\r
+ MCF_PSC_PSCMR(channel) = (0\r
+#ifdef UART_HARDWARE_FLOW_CONTROL\r
+ | MCF_PSC_PSCMR_TXCTS\r
+#endif \r
+ | MCF_PSC_PSCMR_CM_NORMAL\r
+ | MCF_PSC_PSCMR_SB_STOP_BITS_1);\r
+\r
+ /* Mask all UART interrupts */\r
+ MCF_PSC_PSCIMR(channel) = 0x0000;\r
+\r
+ /* Enable RTS to send */\r
+ MCF_PSC_PSCOPSET(channel) = MCF_PSC_PSCOPSET_RTS;\r
+\r
+ /* Setup FIFO Alarms */\r
+ MCF_PSC_PSCRFAR(channel) = MCF_PSC_PSCRFAR_ALARM(248);\r
+ MCF_PSC_PSCTFAR(channel) = MCF_PSC_PSCTFAR_ALARM(248);\r
+\r
+ /* Enable receiver and transmitter */\r
+ MCF_PSC_PSCCR(channel) =(0\r
+ | MCF_PSC_PSCCR_RX_ENABLED\r
+ | MCF_PSC_PSCCR_TX_ENABLED);\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for a character to be received on the specified UART\r
+ *\r
+ * Return Values:\r
+ * the received character\r
+ */\r
+char uart_getchar (int channel)\r
+{\r
+ /* Wait until character has been received */\r
+ while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_RXRDY))\r
+ {\r
+ \r
+ }\r
+ return (char)(*((uint8 *) &MCF_PSC_PSCRB_8BIT(channel)));\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for space in the UART Tx FIFO and then send a character\r
+ */ \r
+void uart_putchar (int channel, char ch)\r
+{\r
+ /* Wait until space is available in the FIFO */\r
+ while (!(MCF_PSC_PSCSR(channel) & MCF_PSC_PSCSR_TXRDY))\r
+ ;\r
+ *((uint8 *) &MCF_PSC_PSCTB_8BIT(channel)) = (uint8)ch;\r
+}\r
+\r
+\r
+#else /* UART_SUPPORT_TYPE==UART_PSC */\r
+\r
+#if UART_SUPPORT_TYPE == UART_5407\r
+/********************************************************************/\r
+/* \r
+ * 5407 derivative doesn't have macros to access URB/UTB by channel number \r
+ * because they have different sizes for UART0 & UART1\r
+ * But in UART mode only 8 bits of UART1 URB/UTB is used, so define these macros here\r
+ * if they doesn't defined before\r
+ */\r
+#ifndef MCF_UART_URB\r
+#define MCF_UART_URB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)]))\r
+#endif /* MCF_UART_URB */\r
+\r
+#ifndef MCF_UART_UTB\r
+#define MCF_UART_UTB(x) (*(vuint8 *)(&__MBAR[0x1CC + ((x)*0x40)]))\r
+#endif /* MCF_UART_UTB */\r
+\r
+#endif /* UART_SUPPORT_TYPE == UART_5407 */\r
+\r
+void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate)\r
+{\r
+ /*\r
+ * Initialize UART for serial communications\r
+ */\r
+\r
+ register uint16 ubgs;\r
+\r
+#if UART_SUPPORT_TYPE==UART_54451\r
+ uint32 vco;\r
+ uint32 divider;\r
+ uint32 bus_clk;\r
+\r
+ divider = ((MCF_CLOCK_PCR & 0x000000F0) >> 4) + 1;\r
+ vco = ((MCF_CLOCK_PCR >> 24) * systemClockKHz * 1000);\r
+ bus_clk = (vco / divider);\r
+#endif\r
+ /*\r
+ * Reset Transmitter\r
+ */\r
+ MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_TX;\r
+\r
+ /*\r
+ * Reset Receiver\r
+ */\r
+ MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_RX;\r
+\r
+ /*\r
+ * Reset Mode Register\r
+ */\r
+ MCF_UART_UCR(channel) = MCF_UART_UCR_RESET_MR;\r
+\r
+ /*\r
+ * No parity, 8-bits per character\r
+ */\r
+ MCF_UART_UMR(channel) = (0\r
+ | MCF_UART_UMR_PM_NONE\r
+ | MCF_UART_UMR_BC_8 );\r
+\r
+ /*\r
+ * No echo or loopback, 1 stop bit\r
+ */\r
+ MCF_UART_UMR(channel) = (0\r
+ | MCF_UART_UMR_CM_NORMAL\r
+ | MCF_UART_UMR_SB_STOP_BITS_1);\r
+\r
+ /*\r
+ * Set Rx and Tx baud by SYSTEM CLOCK\r
+ */\r
+ MCF_UART_UCSR(channel) = (0\r
+ | MCF_UART_UCSR_RCS_SYS_CLK\r
+ | MCF_UART_UCSR_TCS_SYS_CLK);\r
+\r
+ /*\r
+ * Mask all UART interrupts\r
+ */\r
+ MCF_UART_UIMR(channel) = 0;\r
+\r
+ /*\r
+ * Calculate baud settings\r
+ */\r
+#if UART_SUPPORT_TYPE==UART_54451\r
+ ubgs = (uint16)(((bus_clk >> 5) + (baudRate >> 1)) / baudRate);\r
+#else\r
+ ubgs = (uint16)((systemClockKHz * 1000)/(baudRate * 32));\r
+#endif\r
+\r
+#if UART_SUPPORT_TYPE==UART_DIVIDER || UART_SUPPORT_TYPE == UART_5407\r
+ MCF_UART_UDU(channel) = (uint8)((ubgs & 0xFF00) >> 8);\r
+ MCF_UART_UDL(channel) = (uint8)(ubgs & 0x00FF);\r
+#else /* UART_SUPPORT_TYPE!=UART_DIVIDER */\r
+ MCF_UART_UBG1(channel) = (uint8)((ubgs & 0xFF00) >> 8);\r
+ MCF_UART_UBG2(channel) = (uint8)(ubgs & 0x00FF);\r
+#endif /* UART_SUPPORT_TYPE==UART_DIVIDER */\r
+\r
+ /*\r
+ * Enable receiver and transmitter\r
+ */\r
+ MCF_UART_UCR(channel) = (0\r
+ | MCF_UART_UCR_TX_ENABLED\r
+ | MCF_UART_UCR_RX_ENABLED);\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for a character to be received on the specified UART\r
+ *\r
+ * Return Values:\r
+ * the received character\r
+ */\r
+char uart_getchar (int channel)\r
+{\r
+ /* Wait until character has been received */\r
+ while (!(MCF_UART_USR(channel) & MCF_UART_USR_RXRDY)) \r
+ {\r
+ \r
+ };\r
+\r
+ return (char)MCF_UART_URB(channel);\r
+}\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for space in the UART Tx FIFO and then send a character\r
+ */ \r
+void uart_putchar (int channel, char ch)\r
+{\r
+ /* Wait until space is available in the FIFO */\r
+ while (!(MCF_UART_USR(channel) & MCF_UART_USR_TXRDY)) \r
+ {\r
+ \r
+ };\r
+\r
+ /* Send the character */\r
+ MCF_UART_UTB(channel) = (uint8)ch;\r
+}\r
+\r
+#endif /* UART_SUPPORT_TYPE==UART_PSC */\r
+/********************************************************************/\r
+\r
+/********************************************************************/\r
+/** <UART.h> Neeeded functions **/\r
+/********************************************************************/\r
+\r
+/****************************************************************************/\r
+/*\r
+ * Implementation for CodeWarror MSL interface to serial device (UART.h). \r
+ * Needed for printf, etc...\r
+ * Only InitializeUART, ReadUARTN, and WriteUARTN are implemented.\r
+ *\r
+ */\r
+UARTError InitializeUART(UARTBaudRate baudRate)\r
+{\r
+#if UART_SUPPORT_TYPE==UART_54451\r
+ baudRate = kBaud115200;\r
+#endif\r
+ uart_init(TERMINAL_PORT, SYSTEM_CLOCK_KHZ, baudRate);\r
+ return kUARTNoError;\r
+}\r
+\r
+/****************************************************************************/\r
+/*\r
+ ReadUARTN\r
+ \r
+ Read N bytes from the UART.\r
+ \r
+ bytes pointer to result buffer\r
+ limit size of buffer and # of bytes to read\r
+*/\r
+/****************************************************************************/\r
+UARTError ReadUARTN(void* bytes, unsigned long limit)\r
+{\r
+ int count;\r
+ for (count = 0; count < limit; count++) {\r
+ *( (char *)bytes + count ) = uart_getchar(TERMINAL_PORT);\r
+ }\r
+ return kUARTNoError;\r
+}\r
+\r
+/****************************************************************************/\r
+UARTError WriteUARTN(const void* bytes, unsigned long length)\r
+{\r
+ int count;\r
+ for (count = 0; count < length; count++) {\r
+ uart_putchar(TERMINAL_PORT, *( ((char *)bytes) + count));\r
+ }\r
+ return kUARTNoError;\r
+}\r
+#endif /* ENABLE_UART_SUPPORT */\r
--- /dev/null
+/*\r
+ * File: uart_support.h\r
+ * Purpose: Implements UART basic support, Derivative Specific Interrupt handler and need function needed \r
+ * for MSL Support (printf\cout to terminal), defined in <UART.h>\r
+ *\r
+ * Notes: \r
+ * \r
+ */\r
+\r
+#ifndef __UART_SUPPORT_H__\r
+#define __UART_SUPPORT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+#include "support_common.h"\r
+\r
+#if ENABLE_UART_SUPPORT==1 \r
+\r
+/* \r
+ * Include the Freescale UART specific header file for printf/cout/scanf support \r
+ */\r
+#include <ansi_parms.h>\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+#include <UART.h>\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#define UART_STANDARD 0\r
+#define UART_DIVIDER 1\r
+#define UART_5407 2\r
+#define UART_PSC 3\r
+#define UART_54451 4\r
+\r
+#define UART_SUPPORT_TYPE UART_STANDARD\r
+\r
+void uart_init(int channel, unsigned long systemClockKHz, unsigned long baudRate);\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for a character to be received on the specified UART\r
+ *\r
+ * Return Values:\r
+ * the received character\r
+ */\r
+char uart_getchar (int channel);\r
+\r
+/********************************************************************/\r
+/*\r
+ * Wait for space in the UART Tx FIFO and then send a character\r
+ */ \r
+void uart_putchar (int channel, char ch);\r
+\r
+\r
+#endif /* ENABLE_UART_SUPPORT */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __UART_SUPPORT_H__ */\r
projects / freertos / commitdiff