--- /dev/null
+#use combined on interfaces or targets that can't set TRST/SRST separately\r
+reset_config srst_only srst_pulls_trst\r
+\r
+if { [info exists CHIPNAME] } { \r
+ set _CHIPNAME $CHIPNAME \r
+} else { \r
+ set _CHIPNAME at91sam7s\r
+}\r
+\r
+if { [info exists ENDIAN] } { \r
+ set _ENDIAN $ENDIAN \r
+} else { \r
+ set _ENDIAN little\r
+}\r
+\r
+if { [info exists CPUTAPID ] } {\r
+ set _CPUTAPID $CPUTAPID\r
+} else {\r
+ set _CPUTAPID 0x3f0f0f0f\r
+}\r
+\r
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\r
+\r
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]\r
+\r
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi\r
+$_TARGETNAME configure -event reset-init { \r
+ soft_reset_halt\r
+ # RSTC_CR : Reset peripherals\r
+ mww 0xfffffd00 0xa5000004\r
+ # disable watchdog\r
+ mww 0xfffffd44 0x00008000 \r
+ # enable user reset\r
+ mww 0xfffffd08 0xa5000001 \r
+ # CKGR_MOR : enable the main oscillator\r
+ mww 0xfffffc20 0x00000601 \r
+ sleep 10\r
+ # CKGR_PLLR: 96.1097 MHz\r
+ mww 0xfffffc2c 0x00481c0e \r
+ sleep 10\r
+ # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz\r
+ mww 0xfffffc30 0x00000007 \r
+ sleep 10\r
+ # MC_FMR: flash mode (FWS=1,FMCN=73)\r
+ mww 0xffffff60 0x00490100 \r
+ sleep 100 \r
+}\r
+\r
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\r
+\r
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]\r
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432\r
+\r
+# For more information about the configuration files, take a look at:\r
+# openocd.texi\r
--- /dev/null
+######################################\r
+# Target: Atmel AT91SAM9260\r
+######################################\r
+\r
+if { [info exists CHIPNAME] } { \r
+ set _CHIPNAME $CHIPNAME \r
+} else { \r
+ set _CHIPNAME at91sam9260\r
+}\r
+\r
+if { [info exists ENDIAN] } { \r
+ set _ENDIAN $ENDIAN \r
+} else { \r
+ set _ENDIAN little\r
+}\r
+\r
+if { [info exists CPUTAPID ] } {\r
+ set _CPUTAPID $CPUTAPID\r
+} else {\r
+ # force an error till we get a good number\r
+ set _CPUTAPID 0x0792603f\r
+}\r
+\r
+reset_config trst_and_srst separate trst_push_pull srst_open_drain\r
+\r
+#\r
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\r
+\r
+jtag_nsrst_delay 300\r
+jtag_ntrst_delay 10\r
+\r
+jtag_rclk 3\r
+\r
+######################\r
+# Target configuration\r
+######################\r
+\r
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]\r
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs\r
+\r
+# Internal sram1 memory\r
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1\r
+\r
+\r
--- /dev/null
+# Atmel AT91SAM7S-EK\r
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784\r
+\r
+set CHIPNAME at91sam7s256\r
+\r
+source [find target/at91sam7sx.cfg]\r
+\r
+\r
--- /dev/null
+################################################################################\r
+# Atmel AT91SAM9260-EK eval board\r
+#\r
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933\r
+#\r
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz\r
+# OSCSEL configured for external 32.768 kHz crystal\r
+#\r
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks\r
+#\r
+################################################################################\r
+\r
+# We add to the minimal configuration.\r
+source [find target/at91sam9260.cfg]\r
+\r
+# By default S1 is open and this means that NTRST is not connected.\r
+# The reset_config in target/at91sam9260.cfg is overridden here.\r
+# (or S1 must be populated with a 0 Ohm resistor)\r
+reset_config srst_only\r
+\r
+$_TARGETNAME configure -event reset-start {\r
+ # At reset CPU runs at 32.768 kHz.\r
+ # JTAG Frequency must be 6 times slower if RCLK is not supported.\r
+ jtag_rclk 5\r
+ halt\r
+ # RSTC_MR : enable user reset, MMU may be enabled... use physical address\r
+ arm926ejs mww_phys 0xfffffd08 0xa5000501\r
+}\r
+ \r
+$_TARGETNAME configure -event reset-init {\r
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog\r
+\r
+ mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator\r
+ sleep 20 # wait 20 ms\r
+ mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator\r
+ sleep 10 # wait 10 ms\r
+ mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz\r
+ sleep 20 # wait 20 ms\r
+ mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)\r
+ sleep 10 # wait 10 ms\r
+ mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)\r
+ sleep 10 # wait 10 ms\r
+\r
+ # Increase JTAG Speed to 6 MHz if RCLK is not supported\r
+ jtag_rclk 6000\r
+\r
+ arm7_9 dcc_downloads enable # Enable faster DCC downloads\r
+\r
+ mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31\r
+ mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31\r
+ \r
+ mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory\r
+\r
+ mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)\r
+\r
+ mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x0 # SDRAMC_MR : normal mode\r
+ mww 0x20000000 0\r
+ mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us\r
+}\r
--- /dev/null
+# Thanks to Pieter Conradie for this script! \r
+#\r
+# Unknown vendor board contains:\r
+#\r
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz\r
+# OSCSEL configured for internal RC oscillator (22 to 42 kHz)\r
+#\r
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit\r
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks\r
+##################################################################\r
+\r
+# We add to the minimal configuration.\r
+source [find target/at91sam9260.cfg]\r
+\r
+$_TARGETNAME configure -event reset-start {\r
+ # At reset CPU runs at 22 to 42 kHz.\r
+ # JTAG Frequency must be 6 times slower.\r
+ jtag_rclk 3 \r
+ halt\r
+ # RSTC_MR : enable user reset, MMU may be enabled... use physical address\r
+ arm926ejs mww_phys 0xfffffd08 0xa5000501\r
+}\r
+ \r
+\r
+$_TARGETNAME configure -event reset-init {\r
+ mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog\r
+\r
+ mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator\r
+ sleep 20 # wait 20 ms\r
+ mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator\r
+ sleep 10 # wait 10 ms\r
+ mww 0xfffffc28 0x205dbf09 # CKGR_PLLAR: Set PLLA Register for 192.512MHz\r
+ sleep 20 # wait 20 ms\r
+ mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)\r
+ sleep 10 # wait 10 ms\r
+ mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)\r
+ sleep 10 # wait 10 ms\r
+\r
+ # Increase JTAG Speed to 6 MHz if RCLK is not supported\r
+ jtag_rclk 6000 \r
+\r
+ arm7_9 dcc_downloads enable # Enable faster DCC downloads\r
+\r
+ mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit\r
+ mww 0xffffec04 0x09070806 # SMC_PULSE0\r
+ mww 0xffffec08 0x000d000b # SMC_CYCLE0\r
+ mww 0xffffec0c 0x00001003 # SMC_MODE0\r
+\r
+ flash probe 0 # Identify flash bank 0\r
+\r
+ mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31\r
+ mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31\r
+ mww 0xfffff860 0xffff0000 # PIO_PUDR : Disable D15..D31 pull-ups\r
+ \r
+ mww 0xffffef1c 0x00010102 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM\r
+ # VDDIOMSEL set for +3V3 memory\r
+ # Disable D0..D15 pull-ups\r
+\r
+ mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)\r
+\r
+ mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x4\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command\r
+ mww 0x20000000 0\r
+ mww 0xffffea00 0x0 # SDRAMC_MR : normal mode\r
+ mww 0x20000000 0\r
+ mww 0xffffea04 0x2a2 # SDRAMC_TR : Set refresh timer count to 7us\r
+}\r
+\r
+\r
+#####################\r
+# Flash configuration\r
+#####################\r
+\r
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>\r
+flash bank cfi 0x10000000 0x01000000 2 2 0\r
+\r
+\r
projects / openocd / commitdiff