/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-# FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+# FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
#\r
# This file is part of the FreeRTOS.org distribution.\r
#\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
-# FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+# FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
#\r
# This file is part of the FreeRTOS.org distribution.\r
#\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
by this Agreement.\r
\r
1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive,\r
-non-transferable right (1) to use the Software solely and exclusively on LMI's\r
-microcontroller products, (2) to reproduce the Software, (3) to prepare\r
-derivative works of the Software, (4) to distribute the Software and derivative\r
-works thereof in source (human-readable) form and object (machine-readable)\r
-form, and (5) to sublicense to others the right to use the distributed\r
-Software. If you violate any of the terms or restrictions of this Agreement,\r
-LMI may immediately terminate this Agreement, and require that you stop using\r
-and delete all copies of the Software in your possession or control.\r
+non-transferable rights solely and exclusively on or for LMI's microcontroller\r
+products: (1) to use and reproduce the Software, (2) to prepare derivative\r
+works of the Software, (3) to distribute the Software and derivative works\r
+thereof in source (human-readable) form and object (machine-readable) form, (4)\r
+to sublicense to others the right to use the distributed Software, (5) permit\r
+the Software and derivative works thereof to communicate with "viral open\r
+source" software (as defined below); provided however that you may not combine\r
+the two separate and independent works to form a larger program, and (6)\r
+combine the Software and derivative works thereof with "non-viral open source"\r
+software (as defined below). For the purposes of this Agreement, "viral open\r
+source" software means open source software made available on license terms,\r
+such as the GNU General Public License (GPL), that would alter the foregoing\r
+license grant restrictions if combined with the Software. For the purposes of\r
+this Agreement, "non-viral open source" software means open source software\r
+made available on license terms that would not alter the foregoing license\r
+grant restrictions if combined with the Software. For the avoidance of any\r
+doubt, the foregoing license grant does not permit you to combine the Software\r
+and derivative works thereof with "viral open-source" software in order to\r
+sublicense to others the right to use the combined software product. If you\r
+violate any of the terms or restrictions of this Agreement, LMI may immediately\r
+terminate this Agreement, and require that you stop using and delete all copies\r
+of the Software in your possession or control.\r
\r
2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the Software,\r
and United States copyright laws and international treaty provisions protect\r
//\r
// adc.h - ADC headers for using the ADC driver functions.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __ADC_H__\r
#define __ADC_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,\r
unsigned long ulFactor);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// can.h - Defines and Macros for the CAN controller.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __CAN_H__\r
#define __CAN_H__\r
\r
-#ifdef __cplusplus\r
-extern "C"\r
-{\r
-#endif\r
-\r
//*****************************************************************************\r
//\r
//! \addtogroup can_api\r
//\r
//*****************************************************************************\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
//*****************************************************************************\r
//\r
// Miscellaneous defines for Message ID Types\r
//*****************************************************************************\r
//\r
//! These are the flags used by the tCANMsgObject variable when calling the\r
-//! the CANMessageSet() and CANMessageGet() APIs.\r
+//! CANMessageSet() and CANMessageGet() functions.\r
//\r
//*****************************************************************************\r
typedef enum\r
MSG_OBJ_TX_INT_ENABLE = 0x00000001,\r
\r
//\r
- //! This indicates that receive interrupts should be enabled or are\r
+ //! This indicates that receive interrupts should be enabled, or are\r
//! enabled.\r
//\r
MSG_OBJ_RX_INT_ENABLE = 0x00000002,\r
\r
//\r
//! This indicates that a message object will use or is using filtering\r
- //! based on the object's message Identifier.\r
+ //! based on the object's message identifier.\r
//\r
MSG_OBJ_USE_ID_FILTER = 0x00000008,\r
\r
\r
//\r
//! This indicates that a message object will use or is using filtering\r
- //! based on the direction of the transfer. If the direction filtering is\r
- //! used then ID filtering must also be enabled.\r
+ //! based on the direction of the transfer. If the direction filtering is\r
+ //! used, then ID filtering must also be enabled.\r
//\r
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER),\r
\r
//\r
//! This indicates that a message object will use or is using message\r
- //! identifier filtering based of the the extended identifier.\r
- //! If the extended identifier filtering is used then ID filtering must\r
- //! also be enabled.\r
+ //! identifier filtering based on the extended identifier. If the extended\r
+ //! identifier filtering is used, then ID filtering must also be enabled.\r
//\r
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER),\r
\r
\r
//*****************************************************************************\r
//\r
-//! This structure used for encapsulating all the items associated with a CAN\r
+//! The structure used for encapsulating all the items associated with a CAN\r
//! message object in the CAN controller.\r
//\r
//*****************************************************************************\r
//*****************************************************************************\r
//\r
//! This structure is used for encapsulating the values associated with setting\r
-//! up the bit timing for a CAN controller. The structure is used when calling\r
+//! up the bit timing for a CAN controller. The structure is used when calling\r
//! the CANGetBitTiming and CANSetBitTiming functions.\r
//\r
//*****************************************************************************\r
unsigned int uSyncPropPhase1Seg;\r
\r
//\r
- //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
+ //! This value holds the Phase Buffer 2 segment in time quanta. The valid\r
//! values for this setting range from 1 to 8.\r
//\r
unsigned int uPhase2Seg;\r
\r
//\r
- //! This value holds the Resynchronization Jump Width in time quanta. The\r
+ //! This value holds the Resynchronization Jump Width in time quanta. The\r
//! valid values for this setting range from 1 to 4.\r
//\r
unsigned int uSJW;\r
//*****************************************************************************\r
//\r
//! This data type is used to identify the interrupt status register. This is\r
-//! used when calling the a CANIntStatus() function.\r
+//! used when calling the CANIntStatus() function.\r
//\r
//*****************************************************************************\r
typedef enum\r
\r
//*****************************************************************************\r
//\r
-//! This data type is used to identify which of the several status registers\r
-//! to read when calling the CANStatusGet() function.\r
+//! This data type is used to identify which of several status registers to\r
+//! read when calling the CANStatusGet() function.\r
//\r
//*****************************************************************************\r
typedef enum\r
CAN_STS_CONTROL,\r
\r
//\r
- //! Read the full 32 bit mask of message objects with a transmit request\r
+ //! Read the full 32-bit mask of message objects with a transmit request\r
//! set.\r
//\r
CAN_STS_TXREQUEST,\r
\r
//\r
- //! Read the full 32 bit mask of message objects with a new data available.\r
+ //! Read the full 32-bit mask of message objects with new data available.\r
//\r
CAN_STS_NEWDAT,\r
\r
//\r
- //! Read the full 32 bit mask of message objects that are enabled.\r
+ //! Read the full 32-bit mask of message objects that are enabled.\r
//\r
CAN_STS_MSGVAL\r
}\r
\r
//\r
//! This flag is used to allow a CAN controller to generate any CAN\r
- //! interrupts. If this is not set then no interrupts will be generated by\r
- //! the CAN controller.\r
+ //! interrupts. If this is not set, then no interrupts will be generated\r
+ //! by the CAN controller.\r
//\r
CAN_INT_MASTER = 0x00000002\r
}\r
\r
//*****************************************************************************\r
//\r
-//! The following enumeration contains all error or status indicators that\r
-//! can be returned when calling the CANStatusGet() API.\r
+//! The following enumeration contains all error or status indicators that can\r
+//! be returned when calling the CANStatusGet() function.\r
//\r
//*****************************************************************************\r
typedef enum\r
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg);\r
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID);\r
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void));\r
+extern void CANIntUnregister(unsigned long ulBase);\r
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr);\r
\r
//*****************************************************************************\r
//\r
-// Close the Doxygen group.\r
-//! @}\r
+// Mark the end of the C bindings section for C++ compilers.\r
//\r
//*****************************************************************************\r
-\r
#ifdef __cplusplus\r
}\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
#endif // __CAN_H__\r
//\r
// comp.h - Prototypes for the analog comparator driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __COMP_H__\r
#define __COMP_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
//\r
// Values that can be passed to ComparatorConfigure() as the ulConfig\r
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
-// the values may be selected and ORed together will values from the other\r
-// groups.\r
+// the values may be selected and combined together with values from the other\r
+// groups via a logical OR.\r
//\r
//*****************************************************************************\r
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger\r
tBoolean bMasked);\r
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __CPU_H__\r
#define __CPU_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
//*****************************************************************************\r
//\r
// Prototypes.\r
//\r
//*****************************************************************************\r
-extern void CPUcpsid(void);\r
-extern void CPUcpsie(void);\r
+extern unsigned long CPUcpsid(void);\r
+extern unsigned long CPUcpsie(void);\r
extern void CPUwfi(void);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
#endif // __CPU_H__\r
//\r
// debug.h - Macros for assisting debug of the driver library.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
//\r
// ethernet.h - Defines and Macros for the ethernet module.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __ETHERNET_H__\r
#define __ETHERNET_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#define ETH_INT_TXER 0x002 // TX Error\r
#define ETH_INT_RX 0x001 // RX Complete\r
\r
-//*****************************************************************************\r
-//\r
-// The following define values that can be passed as register addresses to\r
-// EthernetPHYRead and EthernetPHYWrite.\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR0 0 // Control\r
-#define PHY_MR1 1 // Status\r
-#define PHY_MR2 2 // PHY Identifier 1\r
-#define PHY_MR3 3 // PHY Identifier 2\r
-#define PHY_MR4 4 // Auto-Neg. Advertisement\r
-#define PHY_MR5 5 // Auto-Neg. Link Partner Ability\r
-#define PHY_MR6 6 // Auto-Neg. Expansion\r
- // 7-15 Reserved/Not Implemented\r
-#define PHY_MR16 16 // Vendor Specific\r
-#define PHY_MR17 17 // Interrupt Control/Status\r
-#define PHY_MR18 18 // Diagnostic Register\r
-#define PHY_MR19 19 // Transceiver Control\r
- // 20-22 Reserved\r
-#define PHY_MR23 23 // LED Configuration Register\r
-#define PHY_MR24 24 // MDI/MDIX Control Register\r
- // 25-31 Reserved/Not Implemented\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR0 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR0_RESET 0x8000 // Reset the PHY\r
-#define PHY_MR0_LOOPBK 0x4000 // TXD to RXD Loopback\r
-#define PHY_MR0_SPEEDSL 0x2000 // Speed Selection\r
-#define PHY_MR0_SPEEDSL_10 0x0000 // Speed Selection 10BASE-T\r
-#define PHY_MR0_SPEEDSL_100 0x2000 // Speed Selection 100BASE-T\r
-#define PHY_MR0_ANEGEN 0x1000 // Auto-Negotiation Enable\r
-#define PHY_MR0_PWRDN 0x0800 // Power Down\r
-#define PHY_MR0_RANEG 0x0200 // Restart Auto-Negotiation\r
-#define PHY_MR0_DUPLEX 0x0100 // Enable full duplex\r
-#define PHY_MR0_DUPLEX_HALF 0x0000 // Enable half duplex mode\r
-#define PHY_MR0_DUPLEX_FULL 0x0100 // Enable full duplex mode\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR1 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR1_ANEGC 0x0020 // Auto-Negotiate Complete\r
-#define PHY_MR1_RFAULT 0x0010 // Remove Fault Detected\r
-#define PHY_MR1_LINK 0x0004 // Link Established\r
-#define PHY_MR1_JAB 0x0002 // Jabber Condition Detected\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR17 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR17_RXER_IE 0x4000 // Enable Receive Error Interrupt\r
-#define PHY_MR17_LSCHG_IE 0x0400 // Enable Link Status Change Int.\r
-#define PHY_MR17_ANEGCOMP_IE 0x0100 // Enable Auto-Negotiate Cmpl. Int.\r
-#define PHY_MR17_RXER_INT 0x0040 // Receive Error Interrupt\r
-#define PHY_MR17_LSCHG_INT 0x0004 // Link Status Change Interrupt\r
-#define PHY_MR17_ANEGCOMP_INT 0x0001 // Auto-Negotiate Complete Int.\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR18 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR18_ANEGF 0x1000 // Auto-Negotiate Failed\r
-#define PHY_MR18_DPLX 0x0800 // Duplex Mode Negotiated\r
-#define PHY_MR18_DPLX_HALF 0x0000 // Half Duplex Mode Negotiated\r
-#define PHY_MR18_DPLX_FULL 0x0800 // Full Duplex Mode Negotiated\r
-#define PHY_MR18_RATE 0x0400 // Rate Negotiated\r
-#define PHY_MR18_RATE_10 0x0000 // Rate Negotiated is 10BASE-T\r
-#define PHY_MR18_RATE_100 0x0400 // Rate Negotiated is 100BASE-TX\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR23 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR23_LED1 0x00f0 // LED1 Configuration\r
-#define PHY_MR23_LED1_LINK 0x0000 // LED1 is Link Status\r
-#define PHY_MR23_LED1_RXTX 0x0010 // LED1 is RX or TX Activity\r
-#define PHY_MR23_LED1_TX 0x0020 // LED1 is TX Activity\r
-#define PHY_MR23_LED1_RX 0x0030 // LED1 is RX Activity\r
-#define PHY_MR23_LED1_COL 0x0040 // LED1 is RX Activity\r
-#define PHY_MR23_LED1_100 0x0050 // LED1 is RX Activity\r
-#define PHY_MR23_LED1_10 0x0060 // LED1 is RX Activity\r
-#define PHY_MR23_LED1_DUPLEX 0x0070 // LED1 is RX Activity\r
-#define PHY_MR23_LED1_LINKACT 0x0080 // LED1 is Link Status + Activity\r
-#define PHY_MR23_LED0 0x000f // LED0 Configuration\r
-#define PHY_MR23_LED0_LINK 0x0000 // LED0 is Link Status\r
-#define PHY_MR23_LED0_RXTX 0x0001 // LED0 is RX or TX Activity\r
-#define PHY_MR23_LED0_TX 0x0002 // LED0 is TX Activity\r
-#define PHY_MR23_LED0_RX 0x0003 // LED0 is RX Activity\r
-#define PHY_MR23_LED0_COL 0x0004 // LED0 is RX Activity\r
-#define PHY_MR23_LED0_100 0x0005 // LED0 is RX Activity\r
-#define PHY_MR23_LED0_10 0x0006 // LED0 is RX Activity\r
-#define PHY_MR23_LED0_DUPLEX 0x0007 // LED0 is RX Activity\r
-#define PHY_MR23_LED0_LINKACT 0x0008 // LED0 is Link Status + Activity\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define bit fields in the ETH_MR24 register\r
-//\r
-//*****************************************************************************\r
-#define PHY_MR24_MDIX 0x0020 // Auto-Switching Configuration\r
-#define PHY_MR24_MDIX_NORMAL 0x0000 // Auto-Switching in passthrough\r
-#define PHY_MR23_MDIX_CROSSOVER 0x0020 // Auto-Switching in crossover\r
-\r
//*****************************************************************************\r
//\r
// Helper Macros for Ethernet Processing\r
EthernetPacketPutNonBlocking(a, b, c)\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// gpio.h - Defines and Macros for GPIO API.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __GPIO_H__\r
#define __GPIO_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPortIntRegister(unsigned long ulPort,\r
- void (*pfIntHandler)(void));\r
+ void (*pfnIntHandler)(void));\r
extern void GPIOPortIntUnregister(unsigned long ulPort);\r
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
unsigned char ucVal);\r
+extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,\r
+ unsigned char ucPins);\r
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// grlib.h - Prototypes for the low level primitives provided by the graphics\r
+// library.\r
+//\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 2523 of the Stellaris Graphics Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GRLIB_H__\r
+#define __GRLIB_H__\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup primitives_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure defines the extents of a rectangle. All points greater than\r
+//! or equal to the minimum and less than or equal to the maximum are part of\r
+//! the rectangle.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The minimum X coordinate of the rectangle.\r
+ //\r
+ short sXMin;\r
+\r
+ //\r
+ //! The minimum Y coordinate of the rectangle.\r
+ //\r
+ short sYMin;\r
+\r
+ //\r
+ //! The maximum X coordinate of the rectangle.\r
+ //\r
+ short sXMax;\r
+\r
+ //\r
+ //! The maximum Y coordinate of the rectangle.\r
+ //\r
+ short sYMax;\r
+}\r
+tRectangle;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure defines the characteristics of a display driver.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The size of this structure.\r
+ //\r
+ long lSize;\r
+\r
+ //\r
+ //! A pointer to display driver-specific data.\r
+ //\r
+ void *pvDisplayData;\r
+\r
+ //\r
+ //! The width of this display.\r
+ //\r
+ unsigned short usWidth;\r
+\r
+ //\r
+ //! The height of this display.\r
+ //\r
+ unsigned short usHeight;\r
+\r
+ //\r
+ //! A pointer to the function to draw a pixel on this display.\r
+ //\r
+ void (*pfnPixelDraw)(void *pvDisplayData, long lX, long lY,\r
+ unsigned long ulValue);\r
+\r
+ //\r
+ //! A pointer to the function to draw multiple pixels on this display.\r
+ //\r
+ void (*pfnPixelDrawMultiple)(void *pvDisplayData, long lX, long lY,\r
+ long lX0, long lCount, long lBPP,\r
+ const unsigned char *pucData,\r
+ const unsigned char *pucPalette);\r
+\r
+ //\r
+ //! A pointer to the function to draw a horizontal line on this display.\r
+ //\r
+ void (*pfnLineDrawH)(void *pvDisplayData, long lX1, long lX2, long lY,\r
+ unsigned long ulValue);\r
+\r
+ //\r
+ //! A pointer to the function to draw a vertical line on this display.\r
+ //\r
+ void (*pfnLineDrawV)(void *pvDisplayData, long lX, long lY1, long lY2,\r
+ unsigned long ulValue);\r
+\r
+ //\r
+ //! A pointer to the function to draw a filled rectangle on this display.\r
+ //\r
+ void (*pfnRectFill)(void *pvDisplayData, const tRectangle *pRect,\r
+ unsigned long ulValue);\r
+\r
+ //\r
+ //! A pointer to the function to translate 24-bit RGB colors to\r
+ //! display-specific colors.\r
+ //\r
+ unsigned long (*pfnColorTranslate)(void *pvDisplayData,\r
+ unsigned long ulValue);\r
+\r
+ //\r
+ //! A pointer to the function to flush any cached drawing operations on\r
+ //! this display.\r
+ //\r
+ void (*pfnFlush)(void *pvDisplayData);\r
+}\r
+tDisplay;\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure describes a font used for drawing text onto the screen.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The format of the font. Can be one of FONT_FMT_UNCOMPRESSED or\r
+ //! FONT_FMT_PIXEL_RLE.\r
+ //\r
+ unsigned char ucFormat;\r
+\r
+ //\r
+ //! The maximum width of a character; this is the width of the widest\r
+ //! character in the font, though any individual character may be narrower\r
+ //! than this width.\r
+ //\r
+ unsigned char ucMaxWidth;\r
+\r
+ //\r
+ //! The height of the character cell; this may be taller than the font data\r
+ //! for the characters (to provide inter-line spacing).\r
+ //\r
+ unsigned char ucHeight;\r
+\r
+ //\r
+ //! The offset between the top of the character cell and the baseline of\r
+ //! the glyph. The baseline is the bottom row of a capital letter, below\r
+ //! which only the descenders of the lower case letters occur.\r
+ //\r
+ unsigned char ucBaseline;\r
+\r
+ //\r
+ //! The offset within pucData to the data for each character in the font.\r
+ //\r
+ unsigned short pusOffset[96];\r
+\r
+ //\r
+ //! A pointer to the data for the font.\r
+ //\r
+ const unsigned char *pucData;\r
+}\r
+tFont;\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the font data is stored in an uncompressed format.\r
+//\r
+//*****************************************************************************\r
+#define FONT_FMT_UNCOMPRESSED 0x00\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the font data is stored using a pixel-based RLE format.\r
+//\r
+//*****************************************************************************\r
+#define FONT_FMT_PIXEL_RLE 0x01\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is not compressed and represents each pixel\r
+//! with a single bit.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_1BPP_UNCOMP 0x01\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is not compressed and represents each pixel\r
+//! with four bits.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_4BPP_UNCOMP 0x04\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is not compressed and represents each pixel\r
+//! with eight bits.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_8BPP_UNCOMP 0x08\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is compressed and represents each pixel with\r
+//! a single bit.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_1BPP_COMP 0x81\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is compressed and represents each pixel with\r
+//! four bits.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_4BPP_COMP 0x84\r
+\r
+//*****************************************************************************\r
+//\r
+//! Indicates that the image data is compressed and represents each pixel with\r
+//! eight bits.\r
+//\r
+//*****************************************************************************\r
+#define IMAGE_FMT_8BPP_COMP 0x88\r
+\r
+//*****************************************************************************\r
+//\r
+//! This structure defines a drawing context to be used to draw onto the\r
+//! screen. Multiple drawing contexts may exist at any time.\r
+//\r
+//*****************************************************************************\r
+typedef struct\r
+{\r
+ //\r
+ //! The size of this structure.\r
+ //\r
+ long lSize;\r
+\r
+ //\r
+ //! The screen onto which drawing operations are performed.\r
+ //\r
+ const tDisplay *pDisplay;\r
+\r
+ //\r
+ //! The clipping region to be used when drawing onto the screen.\r
+ //\r
+ tRectangle sClipRegion;\r
+\r
+ //\r
+ //! The color used to draw primitives onto the screen.\r
+ //\r
+ unsigned long ulForeground;\r
+\r
+ //\r
+ //! The background color used to draw primitives onto the screen.\r
+ //\r
+ unsigned long ulBackground;\r
+\r
+ //\r
+ //! The font used to render text onto the screen.\r
+ //\r
+ const tFont *pFont;\r
+}\r
+tContext;\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the background color to be used.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to modify.\r
+//! \param ulValue is the 24-bit RGB color to be used.\r
+//!\r
+//! This function sets the background color to be used for drawing operations\r
+//! in the specified drawing context.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrContextBackgroundSet(pContext, ulValue) \\r
+ do \\r
+ { \\r
+ tContext *pC = pContext; \\r
+ pC->ulBackground = DpyColorTranslate(pC->pDisplay, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the background color to be used.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to modify.\r
+//! \param ulValue is the display driver-specific color to be used.\r
+//!\r
+//! This function sets the background color to be used for drawing operations\r
+//! in the specified drawing context, using a color that has been previously\r
+//! translated to a driver-specific color (for example, via\r
+//! DpyColorTranslate()).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrContextBackgroundSetTranslated(pContext, ulValue) \\r
+ do \\r
+ { \\r
+ tContext *pC = pContext; \\r
+ pC->ulBackground = ulValue; \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the width of the display being used by this drawing context.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to query.\r
+//!\r
+//! This function returns the width of the display that is being used by this\r
+//! drawing context.\r
+//!\r
+//! \return Returns the width of the display in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrContextDpyWidthGet(pContext) \\r
+ (DpyWidthGet((pContext)->pDisplay))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the height of the display being used by this drawing context.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to query.\r
+//!\r
+//! This function returns the height of the display that is being used by this\r
+//! drawing context.\r
+//!\r
+//! \return Returns the height of the display in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrContextDpyHeightGet(pContext) \\r
+ (DpyHeightGet((pContext)->pDisplay))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the font to be used.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to modify.\r
+//! \param pFnt is a pointer to the font to be used.\r
+//!\r
+//! This function sets the font to be used for string drawing operations in the\r
+//! specified drawing context.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrContextFontSet(pContext, pFnt) \\r
+ do \\r
+ { \\r
+ tContext *pC = pContext; \\r
+ const tFont *pF = pFnt; \\r
+ pC->pFont = pF; \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the foreground color to be used.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to modify.\r
+//! \param ulValue is the 24-bit RGB color to be used.\r
+//!\r
+//! This function sets the color to be used for drawing operations in the\r
+//! specified drawing context.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrContextForegroundSet(pContext, ulValue) \\r
+ do \\r
+ { \\r
+ tContext *pC = pContext; \\r
+ pC->ulForeground = DpyColorTranslate(pC->pDisplay, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Sets the foreground color to be used.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to modify.\r
+//! \param ulValue is the display driver-specific color to be used.\r
+//!\r
+//! This function sets the foreground color to be used for drawing operations\r
+//! in the specified drawing context, using a color that has been previously\r
+//! translated to a driver-specific color (for example, via\r
+//! DpyColorTranslate()).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrContextForegroundSetTranslated(pContext, ulValue) \\r
+ do \\r
+ { \\r
+ tContext *pC = pContext; \\r
+ pC->ulForeground = ulValue; \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Flushes any cached drawing operations.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to use.\r
+//!\r
+//! This function flushes any cached drawing operations. For display drivers\r
+//! that draw into a local frame buffer before writing to the actual display,\r
+//! calling this function will cause the display to be updated to match the\r
+//! contents of the local frame buffer.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrFlush(pContext) \\r
+ do \\r
+ { \\r
+ const tContext *pC = pContext; \\r
+ DpyFlush(pC->pDisplay); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the baseline of a font.\r
+//!\r
+//! \param pFont is a pointer to the font to query.\r
+//!\r
+//! This function determines the baseline position of a font. The baseline is\r
+//! the offset between the top of the font and the bottom of the capital\r
+//! letters. The only font data that exists below the baseline are the\r
+//! descenders on some lower-case letters (such as ``y'').\r
+//!\r
+//! \return Returns the baseline of the font, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrFontBaselineGet(pFont) \\r
+ ((pFont)->ucBaseline)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the height of a font.\r
+//!\r
+//! \param pFont is a pointer to the font to query.\r
+//!\r
+//! This function determines the height of a font. The height is the offset\r
+//! between the top of the font and the bottom of the font, including any\r
+//! ascenders and descenders.\r
+//!\r
+//! \return Returns the height of the font, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrFontHeightGet(pFont) \\r
+ ((pFont)->ucHeight)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the maximum width of a font.\r
+//!\r
+//! \param pFont is a pointer to the font to query.\r
+//!\r
+//! This function determines the maximum width of a font. The maximum width is\r
+//! the width of the widest individual character in the font.\r
+//!\r
+//! \return Returns the maximum width of the font, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrFontMaxWidthGet(pFont) \\r
+ ((pFont)->ucMaxWidth)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the number of colors in an image.\r
+//!\r
+//! \param pucImage is a pointer to the image to query.\r
+//!\r
+//! This function determines the number of colors in the palette of an image.\r
+//! This is only valid for 4bpp and 8bpp images; 1bpp images do not contain a\r
+//! palette.\r
+//!\r
+//! \return Returns the number of colors in the image.\r
+//\r
+//*****************************************************************************\r
+#define GrImageColorsGet(pucImage) \\r
+ (((unsigned char *)pucImage)[5] + 1)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the height of an image.\r
+//!\r
+//! \param pucImage is a pointer to the image to query.\r
+//!\r
+//! This function determines the height of an image in pixels.\r
+//!\r
+//! \return Returns the height of the image in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrImageHeightGet(pucImage) \\r
+ (*(unsigned short *)(pucImage + 3))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the width of an image.\r
+//!\r
+//! \param pucImage is a pointer to the image to query.\r
+//!\r
+//! This function determines the width of an image in pixels.\r
+//!\r
+//! \return Returns the width of the image in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrImageWidthGet(pucImage) \\r
+ (*(unsigned short *)(pucImage + 1))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines the size of the buffer for a 1 BPP off-screen image.\r
+//!\r
+//! \param lWidth is the width of the image in pixels.\r
+//! \param lHeight is the height of the image in pixels.\r
+//!\r
+//! This function determines the size of the memory buffer required to hold a\r
+//! 1 BPP off-screen image of the specified geometry.\r
+//!\r
+//! \return Returns the number of bytes required by the image.\r
+//\r
+//*****************************************************************************\r
+#define GrOffScreen1BPPSize(lWidth, lHeight) \\r
+ (5 + (((lWidth + 7) / 8) * lHeight))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines the size of the buffer for a 4 BPP off-screen image.\r
+//!\r
+//! \param lWidth is the width of the image in pixels.\r
+//! \param lHeight is the height of the image in pixels.\r
+//!\r
+//! This function determines the size of the memory buffer required to hold a\r
+//! 4 BPP off-screen image of the specified geometry.\r
+//!\r
+//! \return Returns the number of bytes required by the image.\r
+//\r
+//*****************************************************************************\r
+#define GrOffScreen4BPPSize(lWidth, lHeight) \\r
+ (6 + (16 * 3) + (((lWidth + 1) / 2) * lHeight))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Determines the size of the buffer for an 8 BPP off-screen image.\r
+//!\r
+//! \param lWidth is the width of the image in pixels.\r
+//! \param lHeight is the height of the image in pixels.\r
+//!\r
+//! This function determines the size of the memory buffer required to hold an\r
+//! 8 BPP off-screen image of the specified geometry.\r
+//!\r
+//! \return Returns the number of bytes required by the image.\r
+//\r
+//*****************************************************************************\r
+#define GrOffScreen8BPPSize(lWidth, lHeight) \\r
+ (6 + (256 * 3) + (lWidth * lHeight))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a pixel.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to use.\r
+//! \param lX is the X coordinate of the pixel.\r
+//! \param lY is the Y coordinate of the pixel.\r
+//!\r
+//! This function draws a pixel if it resides within the clipping region.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrPixelDraw(pContext, lX, lY) \\r
+ do \\r
+ { \\r
+ const tContext *pC = pContext; \\r
+ if((lX >= pC->sClipRegion.sXMin) && \\r
+ (lX <= pC->sClipRegion.sXMax) && \\r
+ (lY >= pC->sClipRegion.sYMin) && \\r
+ (lY <= pC->sClipRegion.sYMax)) \\r
+ { \\r
+ DpyPixelDraw(pC->pDisplay, lX, lY, pC->ulForeground); \\r
+ } \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the baseline of a string.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to query.\r
+//!\r
+//! This function determines the baseline position of a string. The baseline\r
+//! is the offset between the top of the string and the bottom of the capital\r
+//! letters. The only string data that exists below the baseline are the\r
+//! descenders on some lower-case letters (such as ``y'').\r
+//!\r
+//! \return Returns the baseline of the string, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrStringBaselineGet(pContext) \\r
+ ((pContext)->pFont->ucBaseline)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a centered string.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to use.\r
+//! \param pcString is a pointer to the string to be drawn.\r
+//! \param lLength is the number of characters from the string that should be\r
+//! drawn on the screen.\r
+//! \param lX is the X coordinate of the center of the string position on the\r
+//! screen.\r
+//! \param lY is the Y coordinate of the center of the string position on the\r
+//! screen.\r
+//! \param bOpaque is \b true if the background of each character should be\r
+//! drawn and \b false if it should not (leaving the background as is).\r
+//!\r
+//! This function draws a string of test on the screen centered upon the\r
+//! provided position. The \e lLength parameter allows a portion of the\r
+//! string to be examined without having to insert a NULL character at the\r
+//! stopping point (which would not be possible if the string was located in\r
+//! flash); specifying a length of -1 will cause the entire string to be\r
+//! rendered (subject to clipping).\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define GrStringDrawCentered(pContext, pcString, lLength, lX, lY, bOpaque) \\r
+ do \\r
+ { \\r
+ const tContext *pC = pContext; \\r
+ const char *pcStr = pcString; \\r
+ \\r
+ GrStringDraw(pC, pcStr, lLength, \\r
+ (lX) - (GrStringWidthGet(pC, pcStr, lLength) / 2), \\r
+ (lY) - (pC->pFont->ucBaseline / 2), bOpaque); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the height of a string.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to query.\r
+//!\r
+//! This function determines the height of a string. The height is the offset\r
+//! between the top of the string and the bottom of the string, including any\r
+//! ascenders and descenders. Note that this will not account for the case\r
+//! where the string in question does not have any characters that use\r
+//! descenders but the font in the drawing context does contain characters with\r
+//! descenders.\r
+//!\r
+//! \return Returns the height of the string, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrStringHeightGet(pContext) \\r
+ ((pContext)->pFont->ucHeight)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the maximum width of a character in a string.\r
+//!\r
+//! \param pContext is a pointer to the drawing context to query.\r
+//!\r
+//! This function determines the maximum width of a character in a string. The\r
+//! maximum width is the width of the widest individual character in the font\r
+//! used to render the string, which may be wider than the widest character\r
+//! that is used to render a particular string.\r
+//!\r
+//! \return Returns the maximum width of a character in a string, in pixels.\r
+//\r
+//*****************************************************************************\r
+#define GrStringMaxWidthGet(pContext) \\r
+ ((pContext)->pFont->ucMaxWidth)\r
+\r
+//*****************************************************************************\r
+//\r
+// A set of color definitions. This set is the subset of the X11 colors (from\r
+// rgb.txt) that are supported by typical web browsers.\r
+//\r
+//*****************************************************************************\r
+#define ClrAliceBlue 0x00F0F8FF\r
+#define ClrAntiqueWhite 0x00FAEBD7\r
+#define ClrAqua 0x0000FFFF\r
+#define ClrAquamarine 0x007FFFD4\r
+#define ClrAzure 0x00F0FFFF\r
+#define ClrBeige 0x00F5F5DC\r
+#define ClrBisque 0x00FFE4C4\r
+#define ClrBlack 0x00000000\r
+#define ClrBlanchedAlmond 0x00FFEBCD\r
+#define ClrBlue 0x000000FF\r
+#define ClrBlueViolet 0x008A2BE2\r
+#define ClrBrown 0x00A52A2A\r
+#define ClrBurlyWood 0x00DEB887\r
+#define ClrCadetBlue 0x005F9EA0\r
+#define ClrChartreuse 0x007FFF00\r
+#define ClrChocolate 0x00D2691E\r
+#define ClrCoral 0x00FF7F50\r
+#define ClrCornflowerBlue 0x006495ED\r
+#define ClrCornsilk 0x00FFF8DC\r
+#define ClrCrimson 0x00DC143C\r
+#define ClrCyan 0x0000FFFF\r
+#define ClrDarkBlue 0x0000008B\r
+#define ClrDarkCyan 0x00008B8B\r
+#define ClrDarkGoldenrod 0x00B8860B\r
+#define ClrDarkGray 0x00A9A9A9\r
+#define ClrDarkGreen 0x00006400\r
+#define ClrDarkKhaki 0x00BDB76B\r
+#define ClrDarkMagenta 0x008B008B\r
+#define ClrDarkOliveGreen 0x00556B2F\r
+#define ClrDarkOrange 0x00FF8C00\r
+#define ClrDarkOrchid 0x009932CC\r
+#define ClrDarkRed 0x008B0000\r
+#define ClrDarkSalmon 0x00E9967A\r
+#define ClrDarkSeaGreen 0x008FBC8F\r
+#define ClrDarkSlateBlue 0x00483D8B\r
+#define ClrDarkSlateGray 0x002F4F4F\r
+#define ClrDarkTurquoise 0x0000CED1\r
+#define ClrDarkViolet 0x009400D3\r
+#define ClrDeepPink 0x00FF1493\r
+#define ClrDeepSkyBlue 0x0000BFFF\r
+#define ClrDimGray 0x00696969\r
+#define ClrDodgerBlue 0x001E90FF\r
+#define ClrFireBrick 0x00B22222\r
+#define ClrFloralWhite 0x00FFFAF0\r
+#define ClrForestGreen 0x00228B22\r
+#define ClrFuchsia 0x00FF00FF\r
+#define ClrGainsboro 0x00DCDCDC\r
+#define ClrGhostWhite 0x00F8F8FF\r
+#define ClrGold 0x00FFD700\r
+#define ClrGoldenrod 0x00DAA520\r
+#define ClrGray 0x00808080\r
+#define ClrGreen 0x00008000\r
+#define ClrGreenYellow 0x00ADFF2F\r
+#define ClrHoneydew 0x00F0FFF0\r
+#define ClrHotPink 0x00FF69B4\r
+#define ClrIndianRed 0x00CD5C5C\r
+#define ClrIndigo 0x004B0082\r
+#define ClrIvory 0x00FFFFF0\r
+#define ClrKhaki 0x00F0E68C\r
+#define ClrLavender 0x00E6E6FA\r
+#define ClrLavenderBlush 0x00FFF0F5\r
+#define ClrLawnGreen 0x007CFC00\r
+#define ClrLemonChiffon 0x00FFFACD\r
+#define ClrLightBlue 0x00ADD8E6\r
+#define ClrLightCoral 0x00F08080\r
+#define ClrLightCyan 0x00E0FFFF\r
+#define ClrLightGoldenrodYellow 0x00FAFAD2\r
+#define ClrLightGreen 0x0090EE90\r
+#define ClrLightGrey 0x00D3D3D3\r
+#define ClrLightPink 0x00FFB6C1\r
+#define ClrLightSalmon 0x00FFA07A\r
+#define ClrLightSeaGreen 0x0020B2AA\r
+#define ClrLightSkyBlue 0x0087CEFA\r
+#define ClrLightSlateGray 0x00778899\r
+#define ClrLightSteelBlue 0x00B0C4DE\r
+#define ClrLightYellow 0x00FFFFE0\r
+#define ClrLime 0x0000FF00\r
+#define ClrLimeGreen 0x0032CD32\r
+#define ClrLinen 0x00FAF0E6\r
+#define ClrMagenta 0x00FF00FF\r
+#define ClrMaroon 0x00800000\r
+#define ClrMediumAquamarine 0x0066CDAA\r
+#define ClrMediumBlue 0x000000CD\r
+#define ClrMediumOrchid 0x00BA55D3\r
+#define ClrMediumPurple 0x009370DB\r
+#define ClrMediumSeaGreen 0x003CB371\r
+#define ClrMediumSlateBlue 0x007B68EE\r
+#define ClrMediumSpringGreen 0x0000FA9A\r
+#define ClrMediumTurquoise 0x0048D1CC\r
+#define ClrMediumVioletRed 0x00C71585\r
+#define ClrMidnightBlue 0x00191970\r
+#define ClrMintCream 0x00F5FFFA\r
+#define ClrMistyRose 0x00FFE4E1\r
+#define ClrMoccasin 0x00FFE4B5\r
+#define ClrNavajoWhite 0x00FFDEAD\r
+#define ClrNavy 0x00000080\r
+#define ClrOldLace 0x00FDF5E6\r
+#define ClrOlive 0x00808000\r
+#define ClrOliveDrab 0x006B8E23\r
+#define ClrOrange 0x00FFA500\r
+#define ClrOrangeRed 0x00FF4500\r
+#define ClrOrchid 0x00DA70D6\r
+#define ClrPaleGoldenrod 0x00EEE8AA\r
+#define ClrPaleGreen 0x0098FB98\r
+#define ClrPaleTurquoise 0x00AFEEEE\r
+#define ClrPaleVioletRed 0x00DB7093\r
+#define ClrPapayaWhip 0x00FFEFD5\r
+#define ClrPeachPuff 0x00FFDAB9\r
+#define ClrPeru 0x00CD853F\r
+#define ClrPink 0x00FFC0CB\r
+#define ClrPlum 0x00DDA0DD\r
+#define ClrPowderBlue 0x00B0E0E6\r
+#define ClrPurple 0x00800080\r
+#define ClrRed 0x00FF0000\r
+#define ClrRosyBrown 0x00BC8F8F\r
+#define ClrRoyalBlue 0x004169E1\r
+#define ClrSaddleBrown 0x008B4513\r
+#define ClrSalmon 0x00FA8072\r
+#define ClrSandyBrown 0x00F4A460\r
+#define ClrSeaGreen 0x002E8B57\r
+#define ClrSeashell 0x00FFF5EE\r
+#define ClrSienna 0x00A0522D\r
+#define ClrSilver 0x00C0C0C0\r
+#define ClrSkyBlue 0x0087CEEB\r
+#define ClrSlateBlue 0x006A5ACD\r
+#define ClrSlateGray 0x00708090\r
+#define ClrSnow 0x00FFFAFA\r
+#define ClrSpringGreen 0x0000FF7F\r
+#define ClrSteelBlue 0x004682B4\r
+#define ClrTan 0x00D2B48C\r
+#define ClrTeal 0x00008080\r
+#define ClrThistle 0x00D8BFD8\r
+#define ClrTomato 0x00FF6347\r
+#define ClrTurquoise 0x0040E0D0\r
+#define ClrViolet 0x00EE82EE\r
+#define ClrWheat 0x00F5DEB3\r
+#define ClrWhite 0x00FFFFFF\r
+#define ClrWhiteSmoke 0x00F5F5F5\r
+#define ClrYellow 0x00FFFF00\r
+#define ClrYellowGreen 0x009ACD32\r
+\r
+//*****************************************************************************\r
+//\r
+// Masks and shifts to aid in color format translation by drivers.\r
+//\r
+//*****************************************************************************\r
+#define ClrRedMask 0x00FF0000\r
+#define ClrRedShift 16\r
+#define ClrGreenMask 0x0000FF00\r
+#define ClrGreenShift 8\r
+#define ClrBlueMask 0x000000FF\r
+#define ClrBlueShift 0\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the predefined fonts in the graphics library. ..Cm.. is the\r
+// computer modern font, which is a serif font. ..Cmsc.. is the computer\r
+// modern small-caps font, which is also a serif font. ..Cmss.. is the\r
+// computer modern sans-serif font.\r
+//\r
+//*****************************************************************************\r
+extern const tFont g_sFontCm12;\r
+extern const tFont g_sFontCm12b;\r
+extern const tFont g_sFontCm12i;\r
+extern const tFont g_sFontCm14;\r
+extern const tFont g_sFontCm14b;\r
+extern const tFont g_sFontCm14i;\r
+extern const tFont g_sFontCm16;\r
+extern const tFont g_sFontCm16b;\r
+extern const tFont g_sFontCm16i;\r
+extern const tFont g_sFontCm18;\r
+extern const tFont g_sFontCm18b;\r
+extern const tFont g_sFontCm18i;\r
+extern const tFont g_sFontCm20;\r
+extern const tFont g_sFontCm20b;\r
+extern const tFont g_sFontCm20i;\r
+extern const tFont g_sFontCm22;\r
+extern const tFont g_sFontCm22b;\r
+extern const tFont g_sFontCm22i;\r
+extern const tFont g_sFontCm24;\r
+extern const tFont g_sFontCm24b;\r
+extern const tFont g_sFontCm24i;\r
+extern const tFont g_sFontCm26;\r
+extern const tFont g_sFontCm26b;\r
+extern const tFont g_sFontCm26i;\r
+extern const tFont g_sFontCm28;\r
+extern const tFont g_sFontCm28b;\r
+extern const tFont g_sFontCm28i;\r
+extern const tFont g_sFontCm30;\r
+extern const tFont g_sFontCm30b;\r
+extern const tFont g_sFontCm30i;\r
+extern const tFont g_sFontCm32;\r
+extern const tFont g_sFontCm32b;\r
+extern const tFont g_sFontCm32i;\r
+extern const tFont g_sFontCm34;\r
+extern const tFont g_sFontCm34b;\r
+extern const tFont g_sFontCm34i;\r
+extern const tFont g_sFontCm36;\r
+extern const tFont g_sFontCm36b;\r
+extern const tFont g_sFontCm36i;\r
+extern const tFont g_sFontCm38;\r
+extern const tFont g_sFontCm38b;\r
+extern const tFont g_sFontCm38i;\r
+extern const tFont g_sFontCm40;\r
+extern const tFont g_sFontCm40b;\r
+extern const tFont g_sFontCm40i;\r
+extern const tFont g_sFontCm42;\r
+extern const tFont g_sFontCm42b;\r
+extern const tFont g_sFontCm42i;\r
+extern const tFont g_sFontCm44;\r
+extern const tFont g_sFontCm44b;\r
+extern const tFont g_sFontCm44i;\r
+extern const tFont g_sFontCm46;\r
+extern const tFont g_sFontCm46b;\r
+extern const tFont g_sFontCm46i;\r
+extern const tFont g_sFontCm48;\r
+extern const tFont g_sFontCm48b;\r
+extern const tFont g_sFontCm48i;\r
+extern const tFont g_sFontCmsc12;\r
+extern const tFont g_sFontCmsc14;\r
+extern const tFont g_sFontCmsc16;\r
+extern const tFont g_sFontCmsc18;\r
+extern const tFont g_sFontCmsc20;\r
+extern const tFont g_sFontCmsc22;\r
+extern const tFont g_sFontCmsc24;\r
+extern const tFont g_sFontCmsc26;\r
+extern const tFont g_sFontCmsc28;\r
+extern const tFont g_sFontCmsc30;\r
+extern const tFont g_sFontCmsc32;\r
+extern const tFont g_sFontCmsc34;\r
+extern const tFont g_sFontCmsc36;\r
+extern const tFont g_sFontCmsc38;\r
+extern const tFont g_sFontCmsc40;\r
+extern const tFont g_sFontCmsc42;\r
+extern const tFont g_sFontCmsc44;\r
+extern const tFont g_sFontCmsc46;\r
+extern const tFont g_sFontCmsc48;\r
+extern const tFont g_sFontCmss12;\r
+extern const tFont g_sFontCmss12b;\r
+extern const tFont g_sFontCmss12i;\r
+extern const tFont g_sFontCmss14;\r
+extern const tFont g_sFontCmss14b;\r
+extern const tFont g_sFontCmss14i;\r
+extern const tFont g_sFontCmss16;\r
+extern const tFont g_sFontCmss16b;\r
+extern const tFont g_sFontCmss16i;\r
+extern const tFont g_sFontCmss18;\r
+extern const tFont g_sFontCmss18b;\r
+extern const tFont g_sFontCmss18i;\r
+extern const tFont g_sFontCmss20;\r
+extern const tFont g_sFontCmss20b;\r
+extern const tFont g_sFontCmss20i;\r
+extern const tFont g_sFontCmss22;\r
+extern const tFont g_sFontCmss22b;\r
+extern const tFont g_sFontCmss22i;\r
+extern const tFont g_sFontCmss24;\r
+extern const tFont g_sFontCmss24b;\r
+extern const tFont g_sFontCmss24i;\r
+extern const tFont g_sFontCmss26;\r
+extern const tFont g_sFontCmss26b;\r
+extern const tFont g_sFontCmss26i;\r
+extern const tFont g_sFontCmss28;\r
+extern const tFont g_sFontCmss28b;\r
+extern const tFont g_sFontCmss28i;\r
+extern const tFont g_sFontCmss30;\r
+extern const tFont g_sFontCmss30b;\r
+extern const tFont g_sFontCmss30i;\r
+extern const tFont g_sFontCmss32;\r
+extern const tFont g_sFontCmss32b;\r
+extern const tFont g_sFontCmss32i;\r
+extern const tFont g_sFontCmss34;\r
+extern const tFont g_sFontCmss34b;\r
+extern const tFont g_sFontCmss34i;\r
+extern const tFont g_sFontCmss36;\r
+extern const tFont g_sFontCmss36b;\r
+extern const tFont g_sFontCmss36i;\r
+extern const tFont g_sFontCmss38;\r
+extern const tFont g_sFontCmss38b;\r
+extern const tFont g_sFontCmss38i;\r
+extern const tFont g_sFontCmss40;\r
+extern const tFont g_sFontCmss40b;\r
+extern const tFont g_sFontCmss40i;\r
+extern const tFont g_sFontCmss42;\r
+extern const tFont g_sFontCmss42b;\r
+extern const tFont g_sFontCmss42i;\r
+extern const tFont g_sFontCmss44;\r
+extern const tFont g_sFontCmss44b;\r
+extern const tFont g_sFontCmss44i;\r
+extern const tFont g_sFontCmss46;\r
+extern const tFont g_sFontCmss46b;\r
+extern const tFont g_sFontCmss46i;\r
+extern const tFont g_sFontCmss48;\r
+extern const tFont g_sFontCmss48b;\r
+extern const tFont g_sFontCmss48i;\r
+extern const tFont g_sFontFixed6x8;\r
+\r
+//*****************************************************************************\r
+//\r
+//! Translates a 24-bit RGB color to a display driver-specific color.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param ulValue is the 24-bit RGB color. The least-significant byte is the\r
+//! blue channel, the next byte is the green channel, and the third byte is the\r
+//! red channel.\r
+//!\r
+//! This function translates a 24-bit RGB color into a value that can be\r
+//! written into the display's frame buffer in order to reproduce that color,\r
+//! or the closest possible approximation of that color.\r
+//!\r
+//! \return Returns the display-driver specific color.\r
+//\r
+//*****************************************************************************\r
+#define DpyColorTranslate(pDisplay, ulValue) \\r
+ ((pDisplay)->pfnColorTranslate((pDisplay)->pvDisplayData, ulValue))\r
+\r
+//*****************************************************************************\r
+//\r
+//! Flushes cached drawing operations.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//!\r
+//! This function flushes any cached drawing operations on a display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyFlush(pDisplay) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnFlush(pD->pvDisplayData); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the height of the display.\r
+//!\r
+//! \param pDisplay is a pointer to the display driver structure for the\r
+//! display to query.\r
+//!\r
+//! This function determines the height of the display.\r
+//!\r
+//! \return Returns the height of the display in pixels.\r
+//\r
+//*****************************************************************************\r
+#define DpyHeightGet(pDisplay) \\r
+ ((pDisplay)->usHeight)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a horizontal line on a display.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param lX1 is the starting X coordinate of the line.\r
+//! \param lX2 is the ending X coordinate of the line.\r
+//! \param lY is the Y coordinate of the line.\r
+//! \param ulValue is the color to draw the line.\r
+//!\r
+//! This function draws a horizontal line on a display. This assumes that\r
+//! clipping has already been performed, and that both end points of the line\r
+//! are within the extents of the display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyLineDrawH(pDisplay, lX1, lX2, lY, ulValue) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnLineDrawH(pD->pvDisplayData, lX1, lX2, lY, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a vertical line on a display.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param lX is the X coordinate of the line.\r
+//! \param lY1 is the starting Y coordinate of the line.\r
+//! \param lY2 is the ending Y coordinate of the line.\r
+//! \param ulValue is the color to draw the line.\r
+//!\r
+//! This function draws a vertical line on a display. This assumes that\r
+//! clipping has already been performed, and that both end points of the line\r
+//! are within the extents of the display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyLineDrawV(pDisplay, lX, lY1, lY2, ulValue) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnLineDrawV(pD->pvDisplayData, lX, lY1, lY2, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a pixel on a display.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param lX is the X coordinate of the pixel.\r
+//! \param lY is the Y coordinate of the pixel.\r
+//! \param ulValue is the color to draw the pixel.\r
+//!\r
+//! This function draws a pixel on a display. This assumes that clipping has\r
+//! already been performed.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyPixelDraw(pDisplay, lX, lY, ulValue) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnPixelDraw(pD->pvDisplayData, lX, lY, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Draws a horizontal sequence of pixels on a display.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param lX is the X coordinate of the first pixel.\r
+//! \param lY is the Y coordinate of the first pixel.\r
+//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1\r
+//! or 4 bit per pixel formats.\r
+//! \param lCount is the number of pixels to draw.\r
+//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8.\r
+//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel\r
+//! formats, the most significant bit(s) represent the left-most pixel.\r
+//! \param pucPalette is a pointer to the palette used to draw the pixels.\r
+//!\r
+//! This function draws a horizontal sequence of pixels on a display, using the\r
+//! supplied palette. For 1 bit per pixel format, the palette contains\r
+//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette\r
+//! contains 24-bit RGB values that must be translated before being written to\r
+//! the display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyPixelDrawMultiple(pDisplay, lX, lY, lX0, lCount, lBPP, pucData, \\r
+ pucPalette) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnPixelDrawMultiple(pD->pvDisplayData, lX, lY, lX0, lCount, \\r
+ lBPP, pucData, pucPalette); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Fills a rectangle on a display.\r
+//!\r
+//! \param pDisplay is the pointer to the display driver structure for the\r
+//! display to operate upon.\r
+//! \param pRect is a pointer to the structure describing the rectangle to\r
+//! fill.\r
+//! \param ulValue is the color to fill the rectangle.\r
+//!\r
+//! This function fills a rectangle on the display. This assumes that clipping\r
+//! has already been performed, and that all sides of the rectangle are within\r
+//! the extents of the display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+#define DpyRectFill(pDisplay, pRect, ulValue) \\r
+ do \\r
+ { \\r
+ const tDisplay *pD = pDisplay; \\r
+ pD->pfnRectFill(pD->pvDisplayData, pRect, ulValue); \\r
+ } \\r
+ while(0)\r
+\r
+//*****************************************************************************\r
+//\r
+//! Gets the width of the display.\r
+//!\r
+//! \param pDisplay is a pointer to the display driver structure for the\r
+//! display to query.\r
+//!\r
+//! This function determines the width of the display.\r
+//!\r
+//! \return Returns the width of the display in pixels.\r
+//\r
+//*****************************************************************************\r
+#define DpyWidthGet(pDisplay) \\r
+ ((pDisplay)->usWidth)\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the graphics library functions.\r
+//\r
+//*****************************************************************************\r
+extern void GrCircleDraw(const tContext *pContext, long lX, long lY,\r
+ long lRadius);\r
+extern void GrCircleFill(const tContext *pContext, long lX, long lY,\r
+ long lRadius);\r
+extern void GrContextClipRegionSet(tContext *pContext, tRectangle *pRect);\r
+extern void GrContextInit(tContext *pContext, const tDisplay *pDisplay);\r
+extern void GrImageDraw(const tContext *pContext,\r
+ const unsigned char *pucImage, long lX, long lY);\r
+extern void GrLineDraw(const tContext *pContext, long lX1, long lY1, long lX2,\r
+ long lY2);\r
+extern void GrLineDrawH(const tContext *pContext, long lX1, long lX2, long lY);\r
+extern void GrLineDrawV(const tContext *pContext, long lX, long lY1, long lY2);\r
+extern void GrOffScreen1BPPInit(tDisplay *pDisplay, unsigned char *pucImage,\r
+ long lWidth, long lHeight);\r
+extern void GrOffScreen4BPPInit(tDisplay *pDisplay, unsigned char *pucImage,\r
+ long lWidth, long lHeight);\r
+extern void GrOffScreen4BPPPaletteSet(tDisplay *pDisplay,\r
+ unsigned long *pulPalette,\r
+ unsigned long ulOffset,\r
+ unsigned long ulCount);\r
+extern void GrOffScreen8BPPInit(tDisplay *pDisplay, unsigned char *pucImage,\r
+ long lWidth, long lHeight);\r
+extern void GrOffScreen8BPPPaletteSet(tDisplay *pDisplay,\r
+ unsigned long *pulPalette,\r
+ unsigned long ulOffset,\r
+ unsigned long ulCount);\r
+extern void GrRectDraw(const tContext *pContext, const tRectangle *pRect);\r
+extern void GrRectFill(const tContext *pContext, const tRectangle *pRect);\r
+extern void GrStringDraw(const tContext *pContext, const char *pcString,\r
+ long lLength, long lX, long lY,\r
+ unsigned long bOpaque);\r
+extern long GrStringWidthGet(const tContext *pContext, const char *pcString,\r
+ long lLength);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
+\r
+#endif // __GRLIB_H__\r
//\r
// hibernate.h - API definition for the Hibernation module.\r
//\r
-// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __HIBERNATE_H__\r
#define __HIBERNATE_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
HibernateEnableExpClk(a, SysCtlClockGet())\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// hw_adc.h - Macros used when accessing the ADC hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the ADC registers.\r
+// The following are defines for the ADC register offsets.\r
//\r
//*****************************************************************************\r
#define ADC_O_ACTSS 0x00000000 // Active sample register\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the ADC sequence registers.\r
-//\r
-//*****************************************************************************\r
-#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
-#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
-#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
-#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
-#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
-#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the ADC_ACTSS register.\r
+// The following are defines for the bit fields in the ADC_ACTSS register.\r
//\r
//*****************************************************************************\r
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_RIS register.\r
+// The following are defines for the bit fields in the ADC_RIS register.\r
//\r
//*****************************************************************************\r
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_IM register.\r
+// The following are defines for the bit fields in the ADC_IM register.\r
//\r
//*****************************************************************************\r
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_ISC register.\r
+// The following are defines for the bit fields in the ADC_ISC register.\r
//\r
//*****************************************************************************\r
-#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
-#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
-#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
-#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
+#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_OSTAT register.\r
+// The following are defines for the bit fields in the ADC_OSTAT register.\r
//\r
//*****************************************************************************\r
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_EMUX register.\r
+// The following are defines for the bit fields in the ADC_EMUX register.\r
//\r
//*****************************************************************************\r
-#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask\r
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event\r
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event\r
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event\r
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event\r
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event\r
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event\r
-#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask\r
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event\r
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event\r
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event\r
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event\r
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event\r
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event\r
-#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask\r
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event\r
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event\r
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event\r
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event\r
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event\r
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event\r
-#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask\r
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event\r
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event\r
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event\r
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event\r
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event\r
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event\r
-#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
-#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
-#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
-#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_USTAT register.\r
+// The following are defines for the bit fields in the ADC_USTAT register.\r
//\r
//*****************************************************************************\r
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SSPRI register.\r
+// The following are defines for the bit fields in the ADC_SSPRI register.\r
//\r
//*****************************************************************************\r
-#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask\r
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority\r
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority\r
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority\r
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority\r
-#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask\r
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority\r
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority\r
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority\r
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority\r
-#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask\r
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority\r
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority\r
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority\r
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority\r
-#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask\r
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority\r
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority\r
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_PSSI register.\r
+// The following are defines for the bit fields in the ADC_PSSI register.\r
//\r
//*****************************************************************************\r
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SAC register.\r
+// The following are defines for the bit fields in the ADC_SAC register.\r
//\r
//*****************************************************************************\r
-#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
-#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
-#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
-#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
-#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
-#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control.\r
#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling\r
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling\r
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling\r
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling\r
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling\r
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling\r
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter.\r
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator.\r
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator.\r
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator.\r
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator.\r
+#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
+#define ADC_TMLB_CNT_S 6 // Sample counter shift\r
+#define ADC_TMLB_MUX_S 0 // Input channel number shift\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select.\r
+#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select.\r
+#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select.\r
+#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select.\r
+#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select.\r
+#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select.\r
+#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select.\r
+#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select.\r
+#define ADC_SSMUX0_MUX7_S 28\r
+#define ADC_SSMUX0_MUX6_S 24\r
+#define ADC_SSMUX0_MUX5_S 20\r
+#define ADC_SSMUX0_MUX4_S 16\r
+#define ADC_SSMUX0_MUX3_S 12\r
+#define ADC_SSMUX0_MUX2_S 8\r
+#define ADC_SSMUX0_MUX1_S 4\r
+#define ADC_SSMUX0_MUX0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence.\r
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence.\r
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence.\r
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence.\r
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence.\r
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence.\r
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence.\r
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select.\r
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select.\r
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable.\r
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence.\r
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data.\r
+#define ADC_SSFIFO0_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full.\r
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty.\r
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer.\r
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer.\r
+#define ADC_SSFSTAT0_HPTR_S 4\r
+#define ADC_SSFSTAT0_TPTR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select.\r
+#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select.\r
+#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select.\r
+#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select.\r
+#define ADC_SSMUX1_MUX3_S 12\r
+#define ADC_SSMUX1_MUX2_S 8\r
+#define ADC_SSMUX1_MUX1_S 4\r
+#define ADC_SSMUX1_MUX0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select.\r
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable.\r
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence.\r
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select.\r
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select.\r
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable.\r
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence.\r
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select.\r
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select.\r
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable.\r
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence.\r
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select.\r
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select.\r
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable.\r
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence.\r
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data.\r
+#define ADC_SSFIFO1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full.\r
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty.\r
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer.\r
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer.\r
+#define ADC_SSFSTAT1_HPTR_S 4\r
+#define ADC_SSFSTAT1_TPTR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select.\r
+#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select.\r
+#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select.\r
+#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select.\r
+#define ADC_SSMUX2_MUX3_S 12\r
+#define ADC_SSMUX2_MUX2_S 8\r
+#define ADC_SSMUX2_MUX1_S 4\r
+#define ADC_SSMUX2_MUX0_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select.\r
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable.\r
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence.\r
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select.\r
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select.\r
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable.\r
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence.\r
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select.\r
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select.\r
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable.\r
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence.\r
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select.\r
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select.\r
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable.\r
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence.\r
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data.\r
+#define ADC_SSFIFO2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full.\r
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty.\r
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer.\r
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer.\r
+#define ADC_SSFSTAT2_HPTR_S 4\r
+#define ADC_SSFSTAT2_TPTR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select.\r
+#define ADC_SSMUX3_MUX0_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
-// ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present in all\r
-// registers.\r
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select.\r
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable.\r
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence.\r
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data.\r
+#define ADC_SSFIFO3_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full.\r
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty.\r
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer.\r
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer.\r
+#define ADC_SSFSTAT3_HPTR_S 4\r
+#define ADC_SSFSTAT3_TPTR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the ADC sequence register offsets.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence\r
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register\r
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register\r
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register\r
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the ADC_EMUX\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask\r
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask\r
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask\r
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask\r
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event\r
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event\r
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event\r
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the ADC_SSPRI\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the ADC_SSMUX0,\r
+// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present\r
+// in all registers.\r
//\r
//*****************************************************************************\r
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
-// ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present in all\r
-// registers.\r
+// The following are deprecated defines for the bit fields in the ADC_SSCTL0,\r
+// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present\r
+// in all registers.\r
//\r
//*****************************************************************************\r
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
-// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,\r
+// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
//\r
//*****************************************************************************\r
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
-// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,\r
+// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
//\r
//*****************************************************************************\r
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the ADC_TMLB register.\r
-//\r
-//*****************************************************************************\r
-#define ADC_TMLB_LB 0x00000001 // Loopback control signals\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the loopback ADC data.\r
+// The following are deprecated defines for the bit fields in the loopback ADC\r
+// data.\r
//\r
//*****************************************************************************\r
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask\r
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift\r
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift\r
\r
+#endif\r
+\r
#endif // __HW_ADC_H__\r
//\r
// hw_can.h - Defines and macros used when accessing the can.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the can registers.\r
+// The following are defines for the CAN register offsets.\r
//\r
//*****************************************************************************\r
#define CAN_O_CTL 0x00000000 // Control register\r
#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register\r
#define CAN_O_NWDA1 0x00000120 // New Data 1 register\r
#define CAN_O_NWDA2 0x00000124 // New Data 2 register\r
-#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
-#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
-#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
-#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the reset values of the can registers.\r
-//\r
-//*****************************************************************************\r
-#define CAN_RV_CTL 0x00000001\r
-#define CAN_RV_STS 0x00000000\r
-#define CAN_RV_ERR 0x00000000\r
-#define CAN_RV_BIT 0x00002301\r
-#define CAN_RV_INT 0x00000000\r
-#define CAN_RV_TST 0x00000000\r
-#define CAN_RV_BRPE 0x00000000\r
-#define CAN_RV_IF1CRQ 0x00000001\r
-#define CAN_RV_IF1CMSK 0x00000000\r
-#define CAN_RV_IF1MSK1 0x0000FFFF\r
-#define CAN_RV_IF1MSK2 0x0000FFFF\r
-#define CAN_RV_IF1ARB1 0x00000000\r
-#define CAN_RV_IF1ARB2 0x00000000\r
-#define CAN_RV_IF1MCTL 0x00000000\r
-#define CAN_RV_IF1DA1 0x00000000\r
-#define CAN_RV_IF1DA2 0x00000000\r
-#define CAN_RV_IF1DB1 0x00000000\r
-#define CAN_RV_IF1DB2 0x00000000\r
-#define CAN_RV_IF2CRQ 0x00000001\r
-#define CAN_RV_IF2CMSK 0x00000000\r
-#define CAN_RV_IF2MSK1 0x0000FFFF\r
-#define CAN_RV_IF2MSK2 0x0000FFFF\r
-#define CAN_RV_IF2ARB1 0x00000000\r
-#define CAN_RV_IF2ARB2 0x00000000\r
-#define CAN_RV_IF2MCTL 0x00000000\r
-#define CAN_RV_IF2DA1 0x00000000\r
-#define CAN_RV_IF2DA2 0x00000000\r
-#define CAN_RV_IF2DB1 0x00000000\r
-#define CAN_RV_IF2DB2 0x00000000\r
-#define CAN_RV_TXRQ1 0x00000000\r
-#define CAN_RV_TXRQ2 0x00000000\r
-#define CAN_RV_NWDA1 0x00000000\r
-#define CAN_RV_NWDA2 0x00000000\r
-#define CAN_RV_MSGINT1 0x00000000\r
-#define CAN_RV_MSGINT2 0x00000000\r
-#define CAN_RV_MSGVAL1 0x00000000\r
-#define CAN_RV_MSGVAL2 0x00000000\r
+#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending\r
+#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending\r
+#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid\r
+#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_CTL register.\r
+// The following are defines for the bit fields in the CAN_CTL register.\r
//\r
//*****************************************************************************\r
#define CAN_CTL_TEST 0x00000080 // Test mode enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_STS register.\r
+// The following are defines for the bit fields in the CAN_STS register.\r
//\r
//*****************************************************************************\r
#define CAN_STS_BOFF 0x00000080 // Bus Off status\r
#define CAN_STS_EPASS 0x00000020 // Error Passive status\r
#define CAN_STS_RXOK 0x00000010 // Received Message Successful\r
#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful\r
-#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code\r
#define CAN_STS_LEC_NONE 0x00000000 // No error\r
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error\r
#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error\r
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error\r
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error\r
#define CAN_STS_LEC_CRC 0x00000006 // CRC error\r
+#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_ERR register.\r
+// The following are defines for the bit fields in the CAN_ERR register.\r
//\r
//*****************************************************************************\r
#define CAN_ERR_RP 0x00008000 // Receive error passive status\r
-#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
-#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
-#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
-#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.\r
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.\r
+#define CAN_ERR_REC_S 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_BIT register.\r
+// The following are defines for the bit fields in the CAN_BIT register.\r
//\r
//*****************************************************************************\r
-#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
-#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
-#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
-#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.\r
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample\r
+ // Point.\r
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.\r
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.\r
+#define CAN_BIT_TSEG2_S 12\r
+#define CAN_BIT_TSEG1_S 8\r
+#define CAN_BIT_SJW_S 6\r
+#define CAN_BIT_BRP_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_INT register.\r
+// The following are defines for the bit fields in the CAN_INT register.\r
//\r
//*****************************************************************************\r
-#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.\r
#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending\r
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_TST register.\r
+// The following are defines for the bit fields in the CAN_TST register.\r
//\r
//*****************************************************************************\r
#define CAN_TST_RX 0x00000080 // CAN_RX pin status\r
-#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin\r
#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX\r
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX\r
#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_BRPE register.\r
+// The following are defines for the bit fields in the CAN_BRPE register.\r
//\r
//*****************************************************************************\r
-#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.\r
+#define CAN_BRPE_BRPE_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_TXRQ1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.\r
+#define CAN_TXRQ1_TXRQST_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_TXRQ2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.\r
+#define CAN_TXRQ2_TXRQST_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_NWDA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.\r
+#define CAN_NWDA1_NEWDAT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_NWDA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.\r
+#define CAN_NWDA2_NEWDAT_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1CRQ and CAN_IF1CRQ\r
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.\r
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.\r
+#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;\r
+ // it is interpreted as 0x20, or\r
+ // object 32.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.\r
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.\r
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.\r
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.\r
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.\r
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.\r
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.\r
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.\r
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.\r
+#define CAN_IF1MSK1_IDMSK_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.\r
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.\r
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.\r
+#define CAN_IF1MSK2_IDMSK_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.\r
+#define CAN_IF1ARB1_ID_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.\r
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.\r
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.\r
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.\r
+#define CAN_IF1ARB2_ID_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.\r
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.\r
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.\r
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.\r
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.\r
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.\r
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.\r
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.\r
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.\r
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.\r
+#define CAN_IF1MCTL_DLC_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF1DA1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF1DA2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF1DB1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF1DB2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.\r
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.\r
+#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;\r
+ // it is interpreted as 0x20, or\r
+ // object 32.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.\r
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.\r
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.\r
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.\r
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.\r
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.\r
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.\r
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.\r
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.\r
+#define CAN_IF2MSK1_IDMSK_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.\r
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.\r
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.\r
+#define CAN_IF2MSK2_IDMSK_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.\r
+#define CAN_IF2ARB1_ID_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.\r
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.\r
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.\r
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.\r
+#define CAN_IF2ARB2_ID_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.\r
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.\r
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.\r
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.\r
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.\r
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.\r
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.\r
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.\r
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.\r
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.\r
+#define CAN_IF2MCTL_DLC_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF2DA1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF2DA2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF2DB1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.\r
+#define CAN_IF2DB2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.\r
+#define CAN_MSG1INT_INTPND_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.\r
+#define CAN_MSG2INT_INTPND_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.\r
+#define CAN_MSG1VAL_MSGVAL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.\r
+#define CAN_MSG2VAL_MSGVAL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the CAN register offsets.\r
+//\r
+//*****************************************************************************\r
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.\r
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.\r
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.\r
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the reset values of the can\r
// registers.\r
-// Note: All bits may not be available in all registers\r
+//\r
+//*****************************************************************************\r
+#define CAN_RV_IF1MSK2 0x0000FFFF\r
+#define CAN_RV_IF1MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK1 0x0000FFFF\r
+#define CAN_RV_IF2MSK2 0x0000FFFF\r
+#define CAN_RV_BIT 0x00002301\r
+#define CAN_RV_CTL 0x00000001\r
+#define CAN_RV_IF1CRQ 0x00000001\r
+#define CAN_RV_IF2CRQ 0x00000001\r
+#define CAN_RV_TXRQ2 0x00000000\r
+#define CAN_RV_IF2DB1 0x00000000\r
+#define CAN_RV_INT 0x00000000\r
+#define CAN_RV_IF1DB2 0x00000000\r
+#define CAN_RV_BRPE 0x00000000\r
+#define CAN_RV_IF2DA2 0x00000000\r
+#define CAN_RV_MSGVAL2 0x00000000\r
+#define CAN_RV_TXRQ1 0x00000000\r
+#define CAN_RV_IF1MCTL 0x00000000\r
+#define CAN_RV_IF1DB1 0x00000000\r
+#define CAN_RV_STS 0x00000000\r
+#define CAN_RV_MSGINT1 0x00000000\r
+#define CAN_RV_IF1DA2 0x00000000\r
+#define CAN_RV_TST 0x00000000\r
+#define CAN_RV_IF1ARB1 0x00000000\r
+#define CAN_RV_IF1ARB2 0x00000000\r
+#define CAN_RV_NWDA2 0x00000000\r
+#define CAN_RV_IF2CMSK 0x00000000\r
+#define CAN_RV_NWDA1 0x00000000\r
+#define CAN_RV_IF1DA1 0x00000000\r
+#define CAN_RV_IF2DA1 0x00000000\r
+#define CAN_RV_IF2MCTL 0x00000000\r
+#define CAN_RV_MSGVAL1 0x00000000\r
+#define CAN_RV_IF1CMSK 0x00000000\r
+#define CAN_RV_ERR 0x00000000\r
+#define CAN_RV_IF2ARB2 0x00000000\r
+#define CAN_RV_MSGINT2 0x00000000\r
+#define CAN_RV_IF2ARB1 0x00000000\r
+#define CAN_RV_IF2DB2 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_STS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_ERR\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status\r
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status\r
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos\r
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_BIT\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point\r
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point\r
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width\r
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_INT\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_TST\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_BRPE\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the CAN_IF1CRQ\r
+// and CAN_IF1CRQ registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1CMSK and CAN_IF2CMSK\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1CMSK\r
+// and CAN_IF2CMSK registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1MSK1 and CAN_IF2MSK1\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK1\r
+// and CAN_IF2MSK1 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1MSK2 and CAN_IF2MSK2\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK2\r
+// and CAN_IF2MSK2 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1ARB1 and CAN_IF2ARB1\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB1\r
+// and CAN_IF2ARB1 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFARB1_ID 0x0000FFFF // Identifier\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1ARB2 and CAN_IF2ARB2\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB2\r
+// and CAN_IF2ARB2 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1MCTL and CAN_IF2MCTL\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1MCTL\r
+// and CAN_IF2MCTL registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1DA1 and CAN_IF2DA1\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1DA1\r
+// and CAN_IF2DA1 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1DA2 and CAN_IF2DA2\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1DA2\r
+// and CAN_IF2DA2 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1DB1 and CAN_IF2DB1\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1DB1\r
+// and CAN_IF2DB1 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_IF1DB2 and CAN_IF2DB2\r
-// registers.\r
-// Note: All bits may not be available in all registers\r
+// The following are deprecated defines for the bit fields in the CAN_IF1DB2\r
+// and CAN_IF2DB2 registers.\r
+// Note: All bits may not be available in all registers\r
//\r
//*****************************************************************************\r
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_TXRQ1 register.\r
+// The following are deprecated defines for the bit fields in the CAN_TXRQ1\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_TXRQ2 register.\r
+// The following are deprecated defines for the bit fields in the CAN_TXRQ2\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_NWDA1 register.\r
+// The following are deprecated defines for the bit fields in the CAN_NWDA1\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_NWDA2 register.\r
+// The following are deprecated defines for the bit fields in the CAN_NWDA2\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_MSGINT1 register.\r
+// The following are deprecated defines for the bit fields in the CAN_MSGINT1\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_MSGINT2 register.\r
+// The following are deprecated defines for the bit fields in the CAN_MSGINT2\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_MSGVAL1 register.\r
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL1\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the CAN_MSGVAL2 register.\r
+// The following are deprecated defines for the bit fields in the CAN_MSGVAL2\r
+// register.\r
//\r
//*****************************************************************************\r
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits\r
\r
+#endif\r
+\r
#endif // __HW_CAN_H__\r
//\r
// hw_comp.h - Macros used when accessing the comparator hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the comparator registers.\r
+// The following are defines for the comparator register offsets.\r
//\r
//*****************************************************************************\r
-#define COMP_O_MIS 0x00000000 // Interrupt status register\r
-#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
-#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
-#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked\r
+ // Interrupt Status\r
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt\r
+ // Status\r
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt\r
+ // Enable\r
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference\r
+ // Voltage Control\r
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register\r
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register\r
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
-// COMP_INTEN registers.\r
+// The following are defines for the bit fields in the COMP_O_ACMIS register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt\r
+ // Status.\r
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt\r
+ // Status.\r
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt\r
+ // Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACRIS register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status.\r
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status.\r
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable.\r
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable.\r
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACREFCTL\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable.\r
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range.\r
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref.\r
+#define COMP_ACREFCTL_VREF_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable.\r
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive.\r
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value\r
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+\r
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value.\r
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense.\r
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL\r
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge\r
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge\r
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge\r
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value.\r
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense.\r
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL\r
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge\r
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge\r
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge\r
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable.\r
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive.\r
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value\r
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+\r
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value.\r
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense.\r
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL\r
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge\r
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge\r
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge\r
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value.\r
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense.\r
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL\r
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge\r
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge\r
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge\r
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable.\r
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive.\r
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value\r
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+\r
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference\r
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value.\r
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense.\r
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL\r
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge\r
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge\r
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge\r
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value.\r
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense.\r
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL\r
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge\r
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge\r
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge\r
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the comparator register offsets.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS 0x00000000 // Interrupt status register\r
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register\r
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register\r
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the COMP_MIS,\r
+// COMP_RIS, and COMP_INTEN registers.\r
//\r
//*****************************************************************************\r
#define COMP_INT_2 0x00000004 // Comp2 interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the COMP_REFCTL register.\r
+// The following are deprecated defines for the bit fields in the COMP_REFCTL\r
+// register.\r
//\r
//*****************************************************************************\r
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
-// COMP_ACSTAT2 registers.\r
+// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,\r
+// COMP_ACSTAT1, and COMP_ACSTAT2 registers.\r
//\r
//*****************************************************************************\r
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
-// COMP_ACCTL2 registers.\r
+// The following are deprecated defines for the bit fields in the COMP_ACCTL0,\r
+// COMP_ACCTL1, and COMP_ACCTL2 registers.\r
//\r
//*****************************************************************************\r
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the reset values for the comparator registers.\r
+// The following are deprecated defines for the reset values for the comparator\r
+// registers.\r
//\r
//*****************************************************************************\r
-#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register\r
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register\r
-#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
-#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register\r
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+#define COMP_RV_MIS 0x00000000 // Interrupt status register\r
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register\r
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register\r
-#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register\r
-#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register\r
-#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register\r
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg.\r
+\r
+#endif\r
\r
#endif // __HW_COMP_H__\r
//*****************************************************************************\r
//\r
-// hw_ethernet.h - Macros used when accessing the ethernet hardware.\r
+// hw_ethernet.h - Macros used when accessing the Ethernet hardware.\r
//\r
-// Copyright (c) 2006-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the MAC registers in the Ethernet\r
+// The following are defines for the MAC register offsets in the Ethernet\r
// Controller.\r
//\r
//*****************************************************************************\r
-#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt\r
+ // Status\r
#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register\r
#define MAC_O_IM 0x00000004 // Interrupt Mask Register\r
#define MAC_O_RCTL 0x00000008 // Receive Control Register\r
#define MAC_O_THR 0x0000001C // Threshold Register\r
#define MAC_O_MCTL 0x00000020 // Management Control Register\r
#define MAC_O_MDV 0x00000024 // Management Divider Register\r
-#define MAC_O_MADD 0x00000028 // Management Address Register\r
#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg\r
#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg\r
#define MAC_O_NP 0x00000034 // Number of Packets Register\r
\r
//*****************************************************************************\r
//\r
-// The following define the reset values of the MAC registers.\r
-//\r
-//*****************************************************************************\r
-#define MAC_RV_IS 0x00000000\r
-#define MAC_RV_IACK 0x00000000\r
-#define MAC_RV_IM 0x0000007F\r
-#define MAC_RV_RCTL 0x00000008\r
-#define MAC_RV_TCTL 0x00000000\r
-#define MAC_RV_DATA 0x00000000\r
-#define MAC_RV_IA0 0x00000000\r
-#define MAC_RV_IA1 0x00000000\r
-#define MAC_RV_THR 0x0000003F\r
-#define MAC_RV_MCTL 0x00000000\r
-#define MAC_RV_MDV 0x00000080\r
-#define MAC_RV_MADD 0x00000000\r
-#define MAC_RV_MTXD 0x00000000\r
-#define MAC_RV_MRXD 0x00000000\r
-#define MAC_RV_NP 0x00000000\r
-#define MAC_RV_TR 0x00000000\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the MAC_IS register.\r
-//\r
-//*****************************************************************************\r
-#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
-#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
-#define MAC_IS_RXER 0x00000010 // RX Error\r
-#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
-#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
-#define MAC_IS_TXER 0x00000002 // TX Error\r
-#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the MAC_IACK register.\r
+// The following are defines for the bit fields in the MAC_IACK register.\r
//\r
//*****************************************************************************\r
#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_IM register.\r
+// The following are defines for the bit fields in the MAC_IM register.\r
//\r
//*****************************************************************************\r
#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_RCTL register.\r
+// The following are defines for the bit fields in the MAC_RCTL register.\r
//\r
//*****************************************************************************\r
#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_TCTL register.\r
+// The following are defines for the bit fields in the MAC_TCTL register.\r
//\r
//*****************************************************************************\r
#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_IA0 register.\r
+// The following are defines for the bit fields in the MAC_IA0 register.\r
//\r
//*****************************************************************************\r
-#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
-#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
-#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
-#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4.\r
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3.\r
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2.\r
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1.\r
+#define MAC_IA0_MACOCT4_S 24\r
+#define MAC_IA0_MACOCT3_S 16\r
+#define MAC_IA0_MACOCT2_S 8\r
+#define MAC_IA0_MACOCT1_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_IA1 register.\r
+// The following are defines for the bit fields in the MAC_IA1 register.\r
//\r
//*****************************************************************************\r
-#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
-#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6.\r
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5.\r
+#define MAC_IA1_MACOCT6_S 8\r
+#define MAC_IA1_MACOCT5_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_TXTH register.\r
+// The following are defines for the bit fields in the MAC_TXTH register.\r
//\r
//*****************************************************************************\r
-#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value.\r
+#define MAC_THR_THRESH_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_MCTL register.\r
+// The following are defines for the bit fields in the MAC_MCTL register.\r
//\r
//*****************************************************************************\r
-#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address.\r
#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write\r
#define MAC_MCTL_START 0x00000001 // Start MII Transaction\r
+#define MAC_MCTL_REGADR_S 3\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_MDV register.\r
+// The following are defines for the bit fields in the MAC_MDV register.\r
//\r
//*****************************************************************************\r
-#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider.\r
+#define MAC_MDV_DIV_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_MTXD register.\r
+// The following are defines for the bit fields in the MAC_MTXD register.\r
//\r
//*****************************************************************************\r
-#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data.\r
+#define MAC_MTXD_MDTX_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_MRXD register.\r
+// The following are defines for the bit fields in the MAC_MRXD register.\r
//\r
//*****************************************************************************\r
-#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data.\r
+#define MAC_MRXD_MDRX_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_NP register.\r
+// The following are defines for the bit fields in the MAC_NP register.\r
//\r
//*****************************************************************************\r
-#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive\r
+ // FIFO.\r
+#define MAC_NP_NPR_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_TXRQ register.\r
+// The following are defines for the bit fields in the MAC_TXRQ register.\r
//\r
//*****************************************************************************\r
#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the MAC_TS register.\r
+// The following are defines for the bit fields in the MAC_TS register.\r
//\r
//*****************************************************************************\r
#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic\r
\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the Ethernet Controller PHY registers.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24 0x00000018 // Ethernet PHY Management Register\r
+ // 24 -MDI/MDIX Control\r
+#define PHY_MR23 0x00000017 // Ethernet PHY Management Register\r
+ // 23 - LED Configuration\r
+#define PHY_MR19 0x00000013 // Ethernet PHY Management Register\r
+ // 19 - Transceiver Control\r
+#define PHY_MR18 0x00000012 // Ethernet PHY Management Register\r
+ // 18 - Diagnostic\r
+#define PHY_MR17 0x00000011 // Ethernet PHY Management Register\r
+ // 17 - Interrupt Control/Status\r
+#define PHY_MR16 0x00000010 // Ethernet PHY Management Register\r
+ // 16 - Vendor-Specific\r
+#define PHY_MR6 0x00000006 // Ethernet PHY Management Register\r
+ // 6 - Auto-Negotiation Expansion\r
+#define PHY_MR5 0x00000005 // Ethernet PHY Management Register\r
+ // 5 - Auto-Negotiation Link\r
+ // Partner Base Page Ability\r
+#define PHY_MR4 0x00000004 // Ethernet PHY Management Register\r
+ // 4 - Auto-Negotiation\r
+ // Advertisement\r
+#define PHY_MR3 0x00000003 // Ethernet PHY Management Register\r
+ // 3 - PHY Identifier 2\r
+#define PHY_MR2 0x00000002 // Ethernet PHY Management Register\r
+ // 2 - PHY Identifier 1\r
+#define PHY_MR1 0x00000001 // Ethernet PHY Management Register\r
+ // 1 - Status\r
+#define PHY_MR0 0x00000000 // Ethernet PHY Management Register\r
+ // 0 - Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR0 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR0_RESET 0x00008000 // Reset Registers.\r
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode.\r
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select.\r
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable.\r
+#define PHY_MR0_PWRDN 0x00000800 // Power Down.\r
+#define PHY_MR0_ISO 0x00000400 // Isolate.\r
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation.\r
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode.\r
+#define PHY_MR0_COLT 0x00000080 // Collision Test.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the MAC_O_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt.\r
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete.\r
+#define MAC_RIS_RXER 0x00000010 // Receive Error.\r
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun.\r
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty.\r
+#define MAC_RIS_TXER 0x00000002 // Transmit Error.\r
+#define MAC_RIS_RXINT 0x00000001 // Packet Received.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR1 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode.\r
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode.\r
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode.\r
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode.\r
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble\r
+ // Suppressed.\r
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete.\r
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault.\r
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation.\r
+#define PHY_MR1_LINK 0x00000004 // Link Made.\r
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition.\r
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR2 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique\r
+ // Identifier[21:6].\r
+#define PHY_MR2_OUI_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR3 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique\r
+ // Identifier[5:0].\r
+#define PHY_MR3_MN_M 0x000003F0 // Model Number.\r
+#define PHY_MR3_RN_M 0x0000000F // Revision Number.\r
+#define PHY_MR3_OUI_S 10\r
+#define PHY_MR3_MN_S 4\r
+#define PHY_MR3_RN_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR4 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR4_NP 0x00008000 // Next Page.\r
+#define PHY_MR4_RF 0x00002000 // Remote Fault.\r
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].\r
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].\r
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].\r
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].\r
+#define PHY_MR4_S_M 0x0000001F // Selector Field.\r
+#define PHY_MR4_S_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR5 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR5_NP 0x00008000 // Next Page.\r
+#define PHY_MR5_ACK 0x00004000 // Acknowledge.\r
+#define PHY_MR5_RF 0x00002000 // Remote Fault.\r
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.\r
+#define PHY_MR5_S_M 0x0000001F // Selector Field.\r
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3\r
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T\r
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5\r
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394\r
+#define PHY_MR5_A_S 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR6 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.\r
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.\r
+#define PHY_MR6_PRX 0x00000002 // New Page Received.\r
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation\r
+ // Able.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the MAC_O_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.\r
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.\r
+#define MAC_DATA_RXDATA_S 0\r
+#define MAC_DATA_TXDATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR16 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.\r
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.\r
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.\r
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.\r
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.\r
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.\r
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.\r
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.\r
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR17 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.\r
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.\r
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.\r
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault\r
+ // Interrupt Enable.\r
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.\r
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt\r
+ // Enable.\r
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.\r
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete\r
+ // Interrupt Enable.\r
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.\r
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.\r
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.\r
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault\r
+ // Interrupt.\r
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.\r
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.\r
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.\r
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete\r
+ // Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR18 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.\r
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.\r
+#define PHY_MR18_RATE 0x00000400 // Rate.\r
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection.\r
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR19 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.\r
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion\r
+ // loss\r
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion\r
+ // loss\r
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion\r
+ // loss\r
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion\r
+ // loss\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR23 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.\r
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK\r
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)\r
+#define PHY_MR23_LED1_TX 0x00000020 // TX Activity\r
+#define PHY_MR23_LED1_RX 0x00000030 // RX Activity\r
+#define PHY_MR23_LED1_COL 0x00000040 // Collision\r
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode\r
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode\r
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex\r
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX\r
+ // Activity\r
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.\r
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)\r
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity\r
+#define PHY_MR23_LED0_TX 0x00000002 // TX Activity\r
+#define PHY_MR23_LED0_RX 0x00000003 // RX Activity\r
+#define PHY_MR23_LED0_COL 0x00000004 // Collision\r
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode\r
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode\r
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex\r
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX\r
+ // Activity\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PHY_MR24 register.\r
+//\r
+//*****************************************************************************\r
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.\r
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.\r
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.\r
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.\r
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.\r
+#define PHY_MR24_MDIX_SD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the MAC register offsets in the\r
+// Ethernet Controller.\r
+//\r
+//*****************************************************************************\r
+#define MAC_O_IS 0x00000000 // Interrupt Status Register\r
+#define MAC_O_MADD 0x00000028 // Management Address Register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the reset values of the MAC\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define MAC_RV_MDV 0x00000080\r
+#define MAC_RV_IM 0x0000007F\r
+#define MAC_RV_THR 0x0000003F\r
+#define MAC_RV_RCTL 0x00000008\r
+#define MAC_RV_IA0 0x00000000\r
+#define MAC_RV_TCTL 0x00000000\r
+#define MAC_RV_DATA 0x00000000\r
+#define MAC_RV_MRXD 0x00000000\r
+#define MAC_RV_TR 0x00000000\r
+#define MAC_RV_IS 0x00000000\r
+#define MAC_RV_NP 0x00000000\r
+#define MAC_RV_MCTL 0x00000000\r
+#define MAC_RV_MTXD 0x00000000\r
+#define MAC_RV_IA1 0x00000000\r
+#define MAC_RV_IACK 0x00000000\r
+#define MAC_RV_MADD 0x00000000\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_IS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt\r
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete\r
+#define MAC_IS_RXER 0x00000010 // RX Error\r
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun\r
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy\r
+#define MAC_IS_TXER 0x00000002 // TX Error\r
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_IA0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address\r
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address\r
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address\r
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_IA1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address\r
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_TXTH\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_MCTL\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_MDV\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_MTXD\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_MRXD\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the MAC_NP\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO\r
+\r
+#endif\r
+\r
#endif // __HW_ETHERNET_H__\r
//\r
// hw_flash.h - Macros used when accessing the flash controller.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the FLASH registers.\r
+// The following are defines for the FLASH register offsets.\r
//\r
//*****************************************************************************\r
#define FLASH_FMA 0x400FD000 // Memory address register\r
#define FLASH_FMD 0x400FD004 // Memory data register\r
#define FLASH_FMC 0x400FD008 // Memory control register\r
-#define FLASH_FCRIS 0x400FD00c // Raw interrupt status register\r
+#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register\r
#define FLASH_FCIM 0x400FD010 // Interrupt mask register\r
#define FLASH_FCMISC 0x400FD014 // Interrupt status register\r
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control\r
+#define FLASH_RMVER 0x400FE0F4 // ROM Version Register\r
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register\r
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register\r
#define FLASH_USECRL 0x400FE140 // uSec reload register\r
+#define FLASH_USERDBG 0x400FE1D0 // User Debug\r
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0\r
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1\r
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2\r
+#define FLASH_USERREG3 0x400FE1EC // User Register 3\r
#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0\r
#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1\r
#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_FMC register.\r
+// The following are defines for the bit fields in the FLASH_FMC register.\r
//\r
//*****************************************************************************\r
-#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask\r
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key\r
#define FLASH_FMC_COMT 0x00000008 // Commit user register\r
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH\r
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page\r
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word\r
+#define FLASH_FMC_WRKEY_S 16\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_FCRIS register.\r
+// The following are defines for the bit fields in the FLASH_FCRIS register.\r
//\r
//*****************************************************************************\r
-#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
-#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt\r
+ // Status.\r
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_FCIM register.\r
+// The following are defines for the bit fields in the FLASH_FCIM register.\r
//\r
//*****************************************************************************\r
-#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
-#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask.\r
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_FMIS register.\r
+// The following are defines for the bit fields in the FLASH_FMIS register.\r
//\r
//*****************************************************************************\r
-#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
-#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt\r
+ // Status and Clear.\r
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status\r
+ // and Clear.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
-// registers.\r
+// The following are defines for the bit fields in the FLASH_FMPRE and\r
+// FLASH_FMPPE registers.\r
//\r
//*****************************************************************************\r
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the FLASH_USECRL register.\r
+// The following are defines for the bit fields in the FLASH_USECRL register.\r
//\r
//*****************************************************************************\r
-#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
-#define FLASH_USECRL_SHIFT 0\r
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value.\r
+#define FLASH_USECRL_S 0\r
\r
//*****************************************************************************\r
//\r
-// The erase size is the size of the FLASH block that is erased by an erase\r
-// operation, and the protect size is the size of the FLASH block that is\r
-// protected by each protection register.\r
+// The following are defines for the erase size of the FLASH block that is\r
+// erased by an erase operation, and the protect size is the size of the FLASH\r
+// block that is protected by each protection register.\r
//\r
//*****************************************************************************\r
-#define FLASH_ERASE_SIZE 0x00000400\r
#define FLASH_PROTECT_SIZE 0x00000800\r
+#define FLASH_ERASE_SIZE 0x00000400\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_FMA register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset.\r
+#define FLASH_FMA_OFFSET_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_FMD register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value.\r
+#define FLASH_FMD_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_USERDBG register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written.\r
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data.\r
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1.\r
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0.\r
+#define FLASH_USERDBG_DATA_S 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_USERREG0 register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USERREG0_NW 0x80000000 // Not Written.\r
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data.\r
+#define FLASH_USERREG0_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_USERREG1 register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USERREG1_NW 0x80000000 // Not Written.\r
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data.\r
+#define FLASH_USERREG1_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_RMCTL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_RMVER register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents.\r
+#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib\r
+#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size.\r
+#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size\r
+#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version.\r
+#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision.\r
+#define FLASH_RMVER_VER_S 8\r
+#define FLASH_RMVER_REV_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_USERREG2 register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USERREG2_NW 0x80000000 // Not Written.\r
+#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data.\r
+#define FLASH_USERREG2_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the FLASH_USERREG3 register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USERREG3_NW 0x80000000 // Not Written.\r
+#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data.\r
+#define FLASH_USERREG3_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the FLASH_FMC\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the FLASH_FCRIS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the FLASH_FCIM\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask\r
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the FLASH_FMIS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status\r
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the FLASH_USECRL\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec\r
+#define FLASH_USECRL_SHIFT 0\r
+\r
+#endif\r
\r
#endif // __HW_FLASH_H__\r
//\r
// hw_gpio.h - Defines and Macros for GPIO hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// GPIO Register Offsets.\r
+// The following are defines for the GPIO Register offsets.\r
//\r
//*****************************************************************************\r
#define GPIO_O_DATA 0x00000000 // Data register.\r
#define GPIO_O_DEN 0x0000051C // Digital input enable register.\r
#define GPIO_O_LOCK 0x00000520 // Lock register.\r
#define GPIO_O_CR 0x00000524 // Commit register.\r
-#define GPIO_O_PeriphID4 0x00000FD0 //\r
-#define GPIO_O_PeriphID5 0x00000FD4 //\r
-#define GPIO_O_PeriphID6 0x00000FD8 //\r
-#define GPIO_O_PeriphID7 0x00000FDC //\r
-#define GPIO_O_PeriphID0 0x00000FE0 //\r
-#define GPIO_O_PeriphID1 0x00000FE4 //\r
-#define GPIO_O_PeriphID2 0x00000FE8 //\r
-#define GPIO_O_PeriphID3 0x00000FEC //\r
-#define GPIO_O_PCellID0 0x00000FF0 //\r
-#define GPIO_O_PCellID1 0x00000FF4 //\r
-#define GPIO_O_PCellID2 0x00000FF8 //\r
-#define GPIO_O_PCellID3 0x00000FFC //\r
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the GPIO_LOCK register.\r
+// The following are defines for the bit fields in the GPIO_LOCK register.\r
//\r
//*****************************************************************************\r
-#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock.\r
#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked\r
+#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked\r
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register\r
+#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on\r
+ // DustDevil-class devices and\r
+ // later.\r
\r
//*****************************************************************************\r
//\r
-// GPIO Register reset values.\r
+// The following definitions are deprecated.\r
//\r
//*****************************************************************************\r
-#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
-#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
-#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the GPIO Register offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_PeriphID4 0x00000FD0\r
+#define GPIO_O_PeriphID5 0x00000FD4\r
+#define GPIO_O_PeriphID6 0x00000FD8\r
+#define GPIO_O_PeriphID7 0x00000FDC\r
+#define GPIO_O_PeriphID0 0x00000FE0\r
+#define GPIO_O_PeriphID1 0x00000FE4\r
+#define GPIO_O_PeriphID2 0x00000FE8\r
+#define GPIO_O_PeriphID3 0x00000FEC\r
+#define GPIO_O_PCellID0 0x00000FF0\r
+#define GPIO_O_PCellID1 0x00000FF4\r
+#define GPIO_O_PCellID2 0x00000FF8\r
+#define GPIO_O_PCellID3 0x00000FFC\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
+#define GPIO_RV_PCellID1 0x000000F0\r
+#define GPIO_RV_PCellID3 0x000000B1\r
+#define GPIO_RV_PeriphID0 0x00000061\r
+#define GPIO_RV_PeriphID1 0x00000010\r
+#define GPIO_RV_PCellID0 0x0000000D\r
+#define GPIO_RV_PCellID2 0x00000005\r
+#define GPIO_RV_PeriphID2 0x00000004\r
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
+#define GPIO_RV_PeriphID7 0x00000000\r
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV.\r
-#define GPIO_RV_IEV 0x00000000 // Interrupt event reg RV.\r
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV.\r
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV.\r
+#define GPIO_RV_PeriphID4 0x00000000\r
+#define GPIO_RV_PeriphID5 0x00000000\r
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV.\r
-#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
-#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV.\r
-#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV.\r
-#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV.\r
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV.\r
-#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV.\r
-#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV.\r
-#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV.\r
-#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV.\r
-#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV.\r
-#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV.\r
-#define GPIO_RV_LOCK 0x00000001 // Lock register RV.\r
-#define GPIO_RV_PeriphID4 0x00000000 //\r
-#define GPIO_RV_PeriphID5 0x00000000 //\r
-#define GPIO_RV_PeriphID6 0x00000000 //\r
-#define GPIO_RV_PeriphID7 0x00000000 //\r
-#define GPIO_RV_PeriphID0 0x00000061 //\r
-#define GPIO_RV_PeriphID1 0x00000010 //\r
-#define GPIO_RV_PeriphID2 0x00000004 //\r
-#define GPIO_RV_PeriphID3 0x00000000 //\r
-#define GPIO_RV_PCellID0 0x0000000D //\r
-#define GPIO_RV_PCellID1 0x000000F0 //\r
-#define GPIO_RV_PCellID2 0x00000005 //\r
-#define GPIO_RV_PCellID3 0x000000B1 //\r
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV.\r
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV.\r
+#define GPIO_RV_PeriphID6 0x00000000\r
+#define GPIO_RV_PeriphID3 0x00000000\r
+#define GPIO_RV_DATA 0x00000000 // Data register reset value.\r
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV.\r
+\r
+#endif\r
\r
-#endif // __HW_GPIO_H__\r
+#endif // __HW_GPIO_H__\r
//\r
// hw_hibernate.h - Defines and Macros for the Hibernation module.\r
//\r
-// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the addresses of the hibernation module registers.\r
+// The following are defines for the Hibernation module register addresses.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCC 0x400fc000 // Hibernate RTC counter\r
-#define HIB_RTCM0 0x400fc004 // Hibernate RTC match 0\r
-#define HIB_RTCM1 0x400fc008 // Hibernate RTC match 1\r
-#define HIB_RTCLD 0x400fc00C // Hibernate RTC load\r
-#define HIB_CTL 0x400fc010 // Hibernate RTC control\r
-#define HIB_IM 0x400fc014 // Hibernate interrupt mask\r
-#define HIB_RIS 0x400fc018 // Hibernate raw interrupt status\r
-#define HIB_MIS 0x400fc01C // Hibernate masked interrupt stat\r
-#define HIB_IC 0x400fc020 // Hibernate interrupt clear\r
-#define HIB_RTCT 0x400fc024 // Hibernate RTC trim\r
-#define HIB_DATA 0x400fc030 // Hibernate data area\r
-#define HIB_DATA_END 0x400fc130 // end of data area, exclusive\r
+#define HIB_RTCC 0x400FC000 // Hibernate RTC counter\r
+#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0\r
+#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1\r
+#define HIB_RTCLD 0x400FC00C // Hibernate RTC load\r
+#define HIB_CTL 0x400FC010 // Hibernate RTC control\r
+#define HIB_IM 0x400FC014 // Hibernate interrupt mask\r
+#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status\r
+#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat\r
+#define HIB_IC 0x400FC020 // Hibernate interrupt clear\r
+#define HIB_RTCT 0x400FC024 // Hibernate RTC trim\r
+#define HIB_DATA 0x400FC030 // Hibernate data area\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate RTC counter register.\r
+// The following are defines for the bit fields in the Hibernate RTC counter\r
+// register.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCC_MASK 0xffffffff // RTC counter mask\r
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter.\r
+#define HIB_RTCC_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate RTC match 0 register.\r
+// The following are defines for the bit fields in the Hibernate RTC match 0\r
+// register.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCM0_MASK 0xffffffff // RTC match 0 mask\r
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0.\r
+#define HIB_RTCM0_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate RTC match 1 register.\r
+// The following are defines for the bit fields in the Hibernate RTC match 1\r
+// register.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCM1_MASK 0xffffffff // RTC match 1 mask\r
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1.\r
+#define HIB_RTCM1_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate RTC load register.\r
+// The following are defines for the bit fields in the Hibernate RTC load\r
+// register.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCLD_MASK 0xffffffff // RTC load mask\r
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load.\r
+#define HIB_RTCLD_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate control register\r
+// The following are defines for the bit fields in the Hibernate control\r
+// register\r
//\r
//*****************************************************************************\r
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable.\r
#define HIB_CTL_VABORT 0x00000080 // low bat abort\r
#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator\r
#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate interrupt mask reg.\r
+// The following are defines for the bit fields in the Hibernate interrupt mask\r
+// reg.\r
//\r
//*****************************************************************************\r
#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate raw interrupt status.\r
+// The following are defines for the bit fields in the Hibernate raw interrupt\r
+// status.\r
//\r
//*****************************************************************************\r
#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt\r
#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt\r
#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
-#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate masked int status.\r
+// The following are defines for the bit fields in the Hibernate masked int\r
+// status.\r
//\r
//*****************************************************************************\r
#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt\r
#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt\r
#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt\r
-#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt\r
+ // Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate interrupt clear reg.\r
+// The following are defines for the bit fields in the Hibernate interrupt\r
+// clear reg.\r
//\r
//*****************************************************************************\r
#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate RTC trim register.\r
+// The following are defines for the bit fields in the Hibernate RTC trim\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value.\r
+#define HIB_RTCT_TRIM_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the Hibernate data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV\r
+ // Registers[63:0].\r
+#define HIB_DATA_RTD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Hibernation module register\r
+// addresses.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_END 0x400FC130 // end of data area, exclusive\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate RTC\r
+// counter register.\r
//\r
//*****************************************************************************\r
-#define HIB_RTCT_MASK 0x0000ffff // RTC trim mask\r
+#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the Hibernate data register.\r
+// The following are deprecated defines for the bit fields in the Hibernate RTC\r
+// match 0 register.\r
//\r
//*****************************************************************************\r
-#define HIB_DATA_MASK 0xffffffff // NV memory data mask\r
+#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate RTC\r
+// match 1 register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate RTC\r
+// load register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate raw\r
+// interrupt status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate\r
+// masked int status.\r
+//\r
+//*****************************************************************************\r
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate RTC\r
+// trim register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the Hibernate\r
+// data register.\r
+//\r
+//*****************************************************************************\r
+#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask\r
+\r
+#endif\r
\r
#endif // __HW_HIBERNATE_H__\r
//\r
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following defines the offset between the I2C master and slave registers.\r
+// The following are defines for the offsets between the I2C master and slave\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address\r
+#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address\r
+#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status\r
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status\r
+#define I2C_O_SDR 0x00000008 // I2C Slave Data\r
+#define I2C_O_MDR 0x00000008 // I2C Master Data\r
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period\r
+#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask\r
+#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status\r
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask\r
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status\r
+#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt\r
+ // Status\r
+#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear\r
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt\r
+ // Status\r
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear\r
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MSA register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address.\r
+#define I2C_MSA_RS 0x00000001 // Receive not Send\r
+#define I2C_MSA_SA_S 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SOAR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address.\r
+#define I2C_SOAR_OAR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SCSR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received.\r
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request.\r
+#define I2C_SCSR_DA 0x00000001 // Device Active.\r
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MCS register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy.\r
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle.\r
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost.\r
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable.\r
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data.\r
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address.\r
+#define I2C_MCS_STOP 0x00000004 // Generate STOP.\r
+#define I2C_MCS_START 0x00000002 // Generate START.\r
+#define I2C_MCS_ERROR 0x00000002 // Error.\r
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable.\r
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SDR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer.\r
+#define I2C_SDR_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MDR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred.\r
+#define I2C_MDR_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MTPR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period.\r
+#define I2C_MTPR_TPR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SIMR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask.\r
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask.\r
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SRIS register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt\r
+ // Status.\r
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt\r
+ // Status.\r
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MIMR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MRIS register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SMIS register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt\r
+ // Status.\r
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt\r
+ // Status.\r
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_SICR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear.\r
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear.\r
+#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MMIS register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MICR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the I2C_O_MCR register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable.\r
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable.\r
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the offsets between the I2C master\r
+// and slave registers.\r
//\r
//*****************************************************************************\r
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the I2C master registers.\r
+// The following are deprecated defines for the I2C master register offsets.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_O_SA 0x00000000 // Slave address register\r
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register\r
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register\r
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg\r
-#define I2C_MASTER_O_MICR 0x0000001c // Interrupt clear register\r
+#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register\r
#define I2C_MASTER_O_CR 0x00000020 // Configuration register\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the I2C slave registers.\r
+// The following are deprecated defines for the I2C slave register offsets.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
-#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
-#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
-#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
-#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
-#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register\r
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg\r
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register\r
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register\r
+#define I2C_SLAVE_O_DR 0x00000008 // Data register\r
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register\r
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register\r
\r
//*****************************************************************************\r
//\r
-// The followng define the bit fields in the I2C master slave address register.\r
+// The following are deprecated defines for the bit fields in the I2C master\r
+// slave address register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Control and Status\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Control and Status register.\r
//\r
//*****************************************************************************\r
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde\r
#define I2C_MASTER_CS_STOP 0x00000004 // Stop\r
#define I2C_MASTER_CS_START 0x00000002 // Start\r
#define I2C_MASTER_CS_RUN 0x00000001 // Run\r
-#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy\r
-#define I2C_MASTER_CS_IDLE 0x00000020 // Idle\r
-#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration\r
-#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged\r
-#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged\r
-#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred\r
-#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data\r
-#define I2C_MASTER_CS_ERR_MASK 0x0000001C\r
\r
//*****************************************************************************\r
//\r
-// The following define values used in determining the contents of the I2C\r
-// Master Timer Period register.\r
+// The following are deprecated defines for the values used in determining the\r
+// contents of the I2C Master Timer Period register.\r
//\r
//*****************************************************************************\r
-#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
+#define I2C_SCL_FAST 400000 // SCL fast frequency\r
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period\r
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period\r
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)\r
-#define I2C_SCL_STANDARD 100000 // SCL standard frequency\r
-#define I2C_SCL_FAST 400000 // SCL fast frequency\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Interrupt Mask\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Interrupt Mask register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Raw Interrupt Status\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Raw Interrupt Status register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Masked Interrupt\r
-// Status register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Masked Interrupt Status register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Interrupt Clear\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Interrupt Clear register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Master Configuration\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Master\r
+// Configuration register.\r
//\r
//*****************************************************************************\r
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Own Address register.\r
+// The following are deprecated defines for the bit fields in the I2C Slave Own\r
+// Address register.\r
//\r
//*****************************************************************************\r
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Control/Status\r
-// register.\r
+// The following are deprecated defines for the bit fields in the I2C Slave\r
+// Control/Status register.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
+#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master\r
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received\r
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device\r
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// The following are deprecated defines for the bit fields in the I2C Slave\r
+// Interrupt Mask register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the I2C Slave Raw\r
+// Interrupt Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the I2C Slave\r
+// Masked Interrupt Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the I2C Slave\r
+// Interrupt Clear register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR\r
// register.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask\r
+#define I2C_SIMR_IM 0x00000001 // Interrupt Mask.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS\r
// register.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status\r
+#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Masked Interrupt\r
-// Status register.\r
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS\r
+// register.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status\r
+#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// The following are deprecated defines for the bit fields in the I2C_O_SICR\r
// register.\r
//\r
//*****************************************************************************\r
-#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear\r
+#define I2C_SICR_IC 0x00000001 // Clear Interrupt.\r
+\r
+#endif\r
\r
#endif // __HW_I2C_H__\r
//\r
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the fault assignments.\r
+// The following are defines for the fault assignments.\r
//\r
//*****************************************************************************\r
#define FAULT_NMI 2 // NMI fault\r
\r
//*****************************************************************************\r
//\r
-// The following define the interrupt assignments.\r
+// The following are defines for the interrupt assignments.\r
//\r
//*****************************************************************************\r
#define INT_GPIOA 16 // GPIO Port A\r
#define INT_GPIOE 20 // GPIO Port E\r
#define INT_UART0 21 // UART0 Rx and Tx\r
#define INT_UART1 22 // UART1 Rx and Tx\r
-#define INT_SSI 23 // SSI Rx and Tx\r
#define INT_SSI0 23 // SSI0 Rx and Tx\r
-#define INT_I2C 24 // I2C Master and Slave\r
#define INT_I2C0 24 // I2C0 Master and Slave\r
#define INT_PWM_FAULT 25 // PWM Fault\r
#define INT_PWM0 26 // PWM Generator 0\r
#define INT_PWM1 27 // PWM Generator 1\r
#define INT_PWM2 28 // PWM Generator 2\r
-#define INT_QEI 29 // Quadrature Encoder\r
#define INT_QEI0 29 // Quadrature Encoder 0\r
#define INT_ADC0 30 // ADC Sequence 0\r
#define INT_ADC1 31 // ADC Sequence 1\r
#define INT_CAN2 57 // CAN2\r
#define INT_ETH 58 // Ethernet\r
#define INT_HIBERNATE 59 // Hibernation module\r
+#define INT_USB0 60 // USB 0 Controller\r
+#define INT_PWM3 61 // PWM Generator 3\r
+#define INT_UDMA 62 // uDMA controller\r
+#define INT_UDMAERR 63 // uDMA Error\r
\r
//*****************************************************************************\r
//\r
-// The total number of interrupts.\r
+// The following are defines for the total number of interrupts.\r
//\r
//*****************************************************************************\r
-#define NUM_INTERRUPTS 60\r
+#define NUM_INTERRUPTS 64\r
\r
//*****************************************************************************\r
//\r
-// The total number of priority levels.\r
+// The following are defines for the total number of priority levels.\r
//\r
//*****************************************************************************\r
#define NUM_PRIORITY 8\r
#define NUM_PRIORITY_BITS 3\r
\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_SSI 23 // SSI Rx and Tx\r
+#define INT_I2C 24 // I2C Master and Slave\r
+#define INT_QEI 29 // Quadrature Encoder\r
+\r
+#endif\r
+\r
#endif // __HW_INTS_H__\r
//\r
// hw_memmap.h - Macros defining the memory map of Stellaris.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the base address of the memories and peripherals.\r
+// The following are defines for the base address of the memories and\r
+// peripherals.\r
//\r
//*****************************************************************************\r
#define FLASH_BASE 0x00000000 // FLASH memory\r
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B\r
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C\r
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D\r
-#define SSI_BASE 0x40008000 // SSI\r
#define SSI0_BASE 0x40008000 // SSI0\r
#define SSI1_BASE 0x40009000 // SSI1\r
#define UART0_BASE 0x4000C000 // UART0\r
#define UART1_BASE 0x4000D000 // UART1\r
#define UART2_BASE 0x4000E000 // UART2\r
-#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
-#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master\r
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave\r
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master\r
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G\r
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H\r
#define PWM_BASE 0x40028000 // PWM\r
-#define QEI_BASE 0x4002C000 // QEI\r
#define QEI0_BASE 0x4002C000 // QEI0\r
#define QEI1_BASE 0x4002D000 // QEI1\r
#define TIMER0_BASE 0x40030000 // Timer0\r
#define CAN1_BASE 0x40041000 // CAN1\r
#define CAN2_BASE 0x40042000 // CAN2\r
#define ETH_BASE 0x40048000 // Ethernet\r
+#define MAC_BASE 0x40048000 // Ethernet\r
+#define USB0_BASE 0x40050000 // USB 0 Controller\r
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)\r
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)\r
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)\r
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)\r
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)\r
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)\r
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)\r
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)\r
+#define HIB_BASE 0x400FC000 // Hibernation Module\r
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller\r
#define SYSCTL_BASE 0x400FE000 // System Control\r
+#define UDMA_BASE 0x400FF000 // uDMA Controller\r
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell\r
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace\r
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint\r
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl\r
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit\r
\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the base address of the memories\r
+// and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define SSI_BASE 0x40008000 // SSI\r
+#define I2C_MASTER_BASE 0x40020000 // I2C Master\r
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave\r
+#define QEI_BASE 0x4002C000 // QEI\r
+\r
+#endif\r
+\r
#endif // __HW_MEMMAP_H__\r
//\r
// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the addresses of the NVIC registers.\r
+// The following are defines for the NVIC register addresses.\r
//\r
//*****************************************************************************\r
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg.\r
#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register\r
#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register\r
#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register\r
+#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register\r
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register\r
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register\r
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_INT_TYPE register.\r
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.\r
//\r
//*****************************************************************************\r
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ST_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.\r
//\r
//*****************************************************************************\r
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.\r
//\r
//*****************************************************************************\r
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+// The following are defines for the bit fields in the NVIC_ST_CURRENT\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ST_CAL register.\r
+// The following are defines for the bit fields in the NVIC_ST_CAL register.\r
//\r
//*****************************************************************************\r
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_EN0 register.\r
+// The following are defines for the bit fields in the NVIC_EN0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_EN1 register.\r
+// The following are defines for the bit fields in the NVIC_EN1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DIS0 register.\r
+// The following are defines for the bit fields in the NVIC_DIS0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DIS1 register.\r
+// The following are defines for the bit fields in the NVIC_DIS1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PEND0 register.\r
+// The following are defines for the bit fields in the NVIC_PEND0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PEND1 register.\r
+// The following are defines for the bit fields in the NVIC_PEND1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_UNPEND0 register.\r
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_UNPEND1 register.\r
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_ACTIVE1 register.\r
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI0 register.\r
+// The following are defines for the bit fields in the NVIC_PRI0 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI1 register.\r
+// The following are defines for the bit fields in the NVIC_PRI1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI2 register.\r
+// The following are defines for the bit fields in the NVIC_PRI2 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI3 register.\r
+// The following are defines for the bit fields in the NVIC_PRI3 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI4 register.\r
+// The following are defines for the bit fields in the NVIC_PRI4 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI5 register.\r
+// The following are defines for the bit fields in the NVIC_PRI5 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI6 register.\r
+// The following are defines for the bit fields in the NVIC_PRI6 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI7 register.\r
+// The following are defines for the bit fields in the NVIC_PRI7 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI8 register.\r
+// The following are defines for the bit fields in the NVIC_PRI8 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI9 register.\r
+// The following are defines for the bit fields in the NVIC_PRI9 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_PRI10 register.\r
+// The following are defines for the bit fields in the NVIC_PRI10 register.\r
//\r
//*****************************************************************************\r
#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_CPUID register.\r
+// The following are defines for the bit fields in the NVIC_CPUID register.\r
//\r
//*****************************************************************************\r
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_INT_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.\r
//\r
//*****************************************************************************\r
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_VTABLE register.\r
+// The following are defines for the bit fields in the NVIC_VTABLE register.\r
//\r
//*****************************************************************************\r
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_APINT register.\r
+// The following are defines for the bit fields in the NVIC_APINT register.\r
//\r
//*****************************************************************************\r
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask\r
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key\r
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess\r
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group\r
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split\r
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request\r
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info\r
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.\r
//\r
//*****************************************************************************\r
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.\r
//\r
//*****************************************************************************\r
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.\r
//\r
//*****************************************************************************\r
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.\r
//\r
//*****************************************************************************\r
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.\r
//\r
//*****************************************************************************\r
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+// The following are defines for the bit fields in the NVIC_FAULT_STAT\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_MM_ADDR register.\r
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.\r
//\r
//*****************************************************************************\r
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_EXC_STACK register.\r
-//\r
-//*****************************************************************************\r
-#define NVIC_EXC_STACK_DEEP 0x00000001 // Exception stack\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the NVIC_EXC_NUM register.\r
-//\r
-//*****************************************************************************\r
-#define NVIC_EXC_NUM_M 0x000003FF // Exception number\r
-#define NVIC_EXC_NUM_S 0\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the NVIC_COPRO register.\r
-//\r
-//*****************************************************************************\r
-#define NVIC_COPRO_15_M 0xC0000000 // Coprocessor 15 access mask\r
-#define NVIC_COPRO_15_DENIED 0x00000000 // Coprocessor 15 access denied\r
-#define NVIC_COPRO_15_PRIV 0x40000000 // Coprocessor 15 privileged addess\r
-#define NVIC_COPRO_15_FULL 0xC0000000 // Coprocessor 15 full access\r
-#define NVIC_COPRO_14_M 0x30000000 // Coprocessor 14 access mask\r
-#define NVIC_COPRO_14_DENIED 0x00000000 // Coprocessor 14 access denied\r
-#define NVIC_COPRO_14_PRIV 0x10000000 // Coprocessor 14 privileged addess\r
-#define NVIC_COPRO_14_FULL 0x30000000 // Coprocessor 14 full access\r
-#define NVIC_COPRO_13_M 0x0C000000 // Coprocessor 13 access mask\r
-#define NVIC_COPRO_13_DENIED 0x00000000 // Coprocessor 13 access denied\r
-#define NVIC_COPRO_13_PRIV 0x04000000 // Coprocessor 13 privileged addess\r
-#define NVIC_COPRO_13_FULL 0x0C000000 // Coprocessor 13 full access\r
-#define NVIC_COPRO_12_M 0x03000000 // Coprocessor 12 access mask\r
-#define NVIC_COPRO_12_DENIED 0x00000000 // Coprocessor 12 access denied\r
-#define NVIC_COPRO_12_PRIV 0x01000000 // Coprocessor 12 privileged addess\r
-#define NVIC_COPRO_12_FULL 0x03000000 // Coprocessor 12 full access\r
-#define NVIC_COPRO_11_M 0x00C00000 // Coprocessor 11 access mask\r
-#define NVIC_COPRO_11_DENIED 0x00000000 // Coprocessor 11 access denied\r
-#define NVIC_COPRO_11_PRIV 0x00400000 // Coprocessor 11 privileged addess\r
-#define NVIC_COPRO_11_FULL 0x00C00000 // Coprocessor 11 full access\r
-#define NVIC_COPRO_10_M 0x00300000 // Coprocessor 10 access mask\r
-#define NVIC_COPRO_10_DENIED 0x00000000 // Coprocessor 10 access denied\r
-#define NVIC_COPRO_10_PRIV 0x00100000 // Coprocessor 10 privileged addess\r
-#define NVIC_COPRO_10_FULL 0x00300000 // Coprocessor 10 full access\r
-#define NVIC_COPRO_9_M 0x000C0000 // Coprocessor 9 access mask\r
-#define NVIC_COPRO_9_DENIED 0x00000000 // Coprocessor 9 access denied\r
-#define NVIC_COPRO_9_PRIV 0x00040000 // Coprocessor 9 privileged addess\r
-#define NVIC_COPRO_9_FULL 0x000C0000 // Coprocessor 9 full access\r
-#define NVIC_COPRO_8_M 0x00030000 // Coprocessor 8 access mask\r
-#define NVIC_COPRO_8_DENIED 0x00000000 // Coprocessor 8 access denied\r
-#define NVIC_COPRO_8_PRIV 0x00010000 // Coprocessor 8 privileged addess\r
-#define NVIC_COPRO_8_FULL 0x00030000 // Coprocessor 8 full access\r
-#define NVIC_COPRO_7_M 0x0000C000 // Coprocessor 7 access mask\r
-#define NVIC_COPRO_7_DENIED 0x00000000 // Coprocessor 7 access denied\r
-#define NVIC_COPRO_7_PRIV 0x00004000 // Coprocessor 7 privileged addess\r
-#define NVIC_COPRO_7_FULL 0x0000C000 // Coprocessor 7 full access\r
-#define NVIC_COPRO_6_M 0x00003000 // Coprocessor 6 access mask\r
-#define NVIC_COPRO_6_DENIED 0x00000000 // Coprocessor 6 access denied\r
-#define NVIC_COPRO_6_PRIV 0x00001000 // Coprocessor 6 privileged addess\r
-#define NVIC_COPRO_6_FULL 0x00003000 // Coprocessor 6 full access\r
-#define NVIC_COPRO_5_M 0x00000C00 // Coprocessor 5 access mask\r
-#define NVIC_COPRO_5_DENIED 0x00000000 // Coprocessor 5 access denied\r
-#define NVIC_COPRO_5_PRIV 0x00000400 // Coprocessor 5 privileged addess\r
-#define NVIC_COPRO_5_FULL 0x00000C00 // Coprocessor 5 full access\r
-#define NVIC_COPRO_4_M 0x00000300 // Coprocessor 4 access mask\r
-#define NVIC_COPRO_4_DENIED 0x00000000 // Coprocessor 4 access denied\r
-#define NVIC_COPRO_4_PRIV 0x00000100 // Coprocessor 4 privileged addess\r
-#define NVIC_COPRO_4_FULL 0x00000300 // Coprocessor 4 full access\r
-#define NVIC_COPRO_3_M 0x000000C0 // Coprocessor 3 access mask\r
-#define NVIC_COPRO_3_DENIED 0x00000000 // Coprocessor 3 access denied\r
-#define NVIC_COPRO_3_PRIV 0x00000040 // Coprocessor 3 privileged addess\r
-#define NVIC_COPRO_3_FULL 0x000000C0 // Coprocessor 3 full access\r
-#define NVIC_COPRO_2_M 0x00000030 // Coprocessor 2 access mask\r
-#define NVIC_COPRO_2_DENIED 0x00000000 // Coprocessor 2 access denied\r
-#define NVIC_COPRO_2_PRIV 0x00000010 // Coprocessor 2 privileged addess\r
-#define NVIC_COPRO_2_FULL 0x00000030 // Coprocessor 2 full access\r
-#define NVIC_COPRO_1_M 0x0000000C // Coprocessor 1 access mask\r
-#define NVIC_COPRO_1_DENIED 0x00000000 // Coprocessor 1 access denied\r
-#define NVIC_COPRO_1_PRIV 0x00000004 // Coprocessor 1 privileged addess\r
-#define NVIC_COPRO_1_FULL 0x0000000C // Coprocessor 1 full access\r
-#define NVIC_COPRO_0_M 0x00000003 // Coprocessor 0 access mask\r
-#define NVIC_COPRO_0_DENIED 0x00000000 // Coprocessor 0 access denied\r
-#define NVIC_COPRO_0_PRIV 0x00000001 // Coprocessor 0 privileged addess\r
-#define NVIC_COPRO_0_FULL 0x00000003 // Coprocessor 0 full access\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.\r
//\r
//*****************************************************************************\r
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.\r
//\r
//*****************************************************************************\r
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode\r
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults\r
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER\r
+// register.\r
//\r
//*****************************************************************************\r
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_MPU_BASE register.\r
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.\r
//\r
//*****************************************************************************\r
-#define NVIC_MPU_BASE_ADDR_M 0xFFFFFF00 // Base address\r
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask\r
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid\r
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number\r
#define NVIC_MPU_BASE_ADDR_S 8\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_MPU_ATTR register.\r
-//\r
-//*****************************************************************************\r
-#define NVIC_MPU_ATTR_ATTRS 0xFFFF0000 // Attributes\r
-#define NVIC_MPU_ATTR_SRD 0x0000FF00 // Sub-region disable\r
-#define NVIC_MPU_ATTR_SZENABLE 0x000000FF // Region size\r
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes\r
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access\r
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable\r
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable\r
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable\r
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask\r
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none\r
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only\r
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw\r
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none\r
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro\r
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask\r
+#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable\r
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask\r
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable\r
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable\r
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable\r
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable\r
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable\r
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable\r
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable\r
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable\r
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask\r
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes\r
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes\r
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes\r
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes\r
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes\r
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes\r
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes\r
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes\r
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes\r
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes\r
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.\r
//\r
//*****************************************************************************\r
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DBG_XFER register.\r
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.\r
//\r
//*****************************************************************************\r
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read\r
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register\r
-#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
-#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
-#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
-#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
-#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
-#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
-#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
-#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
-#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
-#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
-#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
-#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
-#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
-#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
-#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
-#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
-#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
-#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
-#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask\r
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP\r
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP\r
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15\r
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14\r
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13\r
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12\r
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11\r
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10\r
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9\r
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8\r
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7\r
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6\r
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5\r
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4\r
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3\r
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2\r
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1\r
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DBG_DATA register.\r
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.\r
//\r
//*****************************************************************************\r
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_DBG_INT register.\r
+// The following are defines for the bit fields in the NVIC_DBG_INT register.\r
//\r
//*****************************************************************************\r
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the NVIC_SW_TRIG register.\r
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.\r
//\r
//*****************************************************************************\r
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger\r
//\r
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// PWM Module Register Offsets.\r
+// The following are defines for the PWM Module Register offsets.\r
//\r
//*****************************************************************************\r
#define PWM_O_CTL 0x00000000 // PWM Master Control register\r
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg.\r
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register\r
#define PWM_O_STATUS 0x00000020 // PWM Status register\r
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value\r
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control\r
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger\r
+ // Enable\r
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status\r
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear\r
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load\r
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter\r
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A\r
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B\r
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control\r
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control\r
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control\r
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay\r
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band\r
+ // Falling-Edge-Delay\r
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0\r
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period\r
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control\r
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable\r
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status\r
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear\r
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load\r
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter\r
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A\r
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B\r
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control\r
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control\r
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control\r
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay\r
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band\r
+ // Falling-Edge-Delay\r
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0\r
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period\r
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control\r
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable\r
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status\r
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear\r
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load\r
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter\r
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A\r
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B\r
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control\r
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control\r
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control\r
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay\r
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band\r
+ // Falling-Edge-Delay\r
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0\r
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period\r
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control\r
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger\r
+ // Enable\r
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status\r
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear\r
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load\r
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter\r
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A\r
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B\r
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control\r
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control\r
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control\r
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay\r
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band\r
+ // Falling-Edge-Delay\r
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0\r
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period\r
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense\r
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0\r
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense\r
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0\r
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense\r
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0\r
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense\r
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Master Control register.\r
+// The following are defines for the bit fields in the PWM Master Control\r
+// register.\r
//\r
//*****************************************************************************\r
-#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
-#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
-#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3.\r
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2.\r
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1.\r
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Time Base Sync register.\r
+// The following are defines for the bit fields in the PWM Time Base Sync\r
+// register.\r
//\r
//*****************************************************************************\r
+#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter\r
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter\r
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter\r
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Output Enable register.\r
+// The following are defines for the bit fields in the PWM Output Enable\r
+// register.\r
//\r
//*****************************************************************************\r
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable\r
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable\r
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable\r
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable\r
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Inversion register.\r
+// The following are defines for the bit fields in the PWM Inversion register.\r
//\r
//*****************************************************************************\r
+#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert\r
+#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert\r
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert\r
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert\r
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Fault register.\r
+// The following are defines for the bit fields in the PWM Fault register.\r
//\r
//*****************************************************************************\r
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault\r
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault\r
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault\r
-#define PWM_FAULT_FAULT4 0x00000010 // PWM5 pin fault\r
-#define PWM_FAULT_FAULT3 0x00000008 // PWM5 pin fault\r
-#define PWM_FAULT_FAULT2 0x00000004 // PWM5 pin fault\r
-#define PWM_FAULT_FAULT1 0x00000002 // PWM5 pin fault\r
-#define PWM_FAULT_FAULT0 0x00000001 // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault\r
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault\r
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault\r
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault\r
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault\r
\r
//*****************************************************************************\r
//\r
-// PWM Interrupt Register bit definitions.\r
+// The following are defines for the bit fields in the PWM Status register.\r
//\r
//*****************************************************************************\r
-#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status.\r
+#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status.\r
+#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status.\r
+#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the PWM Status register.\r
+// The following are defines for the PWM Generator standard offsets.\r
//\r
//*****************************************************************************\r
-#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
-\r
-//*****************************************************************************\r
-//\r
-// PWM Generator standard offsets.\r
-//\r
-//*****************************************************************************\r
-#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
-#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
-#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
-\r
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg\r
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg\r
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg\r
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg\r
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg\r
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg\r
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition\r
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension\r
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base\r
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base\r
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base\r
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Control Register bit definitions.\r
+// The following are defines for the PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input.\r
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled\r
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source.\r
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for\r
+ // the PWMnDBFALL register.\r
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate\r
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized\r
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized\r
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode.\r
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate\r
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized\r
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized\r
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode.\r
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate\r
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized\r
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized\r
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode.\r
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate\r
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized\r
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized\r
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode.\r
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate\r
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized\r
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized\r
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
+#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
+#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
+#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the PWM Generator extended offsets.\r
//\r
//*****************************************************************************\r
-#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block\r
-#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down\r
-#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode\r
-#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg\r
-#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg\r
-#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg\r
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense\r
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status\r
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base\r
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base\r
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base\r
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+// The following are defines for the PWM_X Interrupt/Trigger Enable Register\r
+// bit definitions.\r
//\r
//*****************************************************************************\r
-#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
-#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
-#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
-#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
-#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
-#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
-#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
-#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
-#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
-#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
-#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0\r
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Raw Interrupt Status Register bit definitions.\r
+// The following are defines for the PWM_X Raw Interrupt Status Register bit\r
+// definitions.\r
//\r
//*****************************************************************************\r
-#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
-#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
-#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
-#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
-#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int\r
+#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Interrupt Status Register bit definitions.\r
+// The following are defines for the bit fields in the PWM_O_INTEN register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3.\r
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2.\r
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1.\r
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable.\r
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0.\r
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable.\r
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable.\r
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable.\r
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3.\r
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2.\r
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1.\r
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0.\r
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted.\r
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted.\r
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted.\r
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted.\r
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted.\r
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted.\r
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted.\r
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted.\r
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted.\r
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status.\r
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status.\r
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status.\r
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt.\r
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt.\r
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt.\r
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt.\r
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt.\r
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value.\r
+#define PWM_X_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value.\r
+#define PWM_X_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value.\r
+#define PWM_X_CMPA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value.\r
+#define PWM_X_CMPB_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_GENA register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.\r
+#define PWM_X_GENA_ACTCMPBD_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal.\r
+#define PWM_X_GENA_ACTCMPBD_ZERO \\r
+ 0x00000800 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.\r
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.\r
+#define PWM_X_GENA_ACTCMPBU_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal.\r
+#define PWM_X_GENA_ACTCMPBU_ZERO \\r
+ 0x00000200 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.\r
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.\r
+#define PWM_X_GENA_ACTCMPAD_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal.\r
+#define PWM_X_GENA_ACTCMPAD_ZERO \\r
+ 0x00000080 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.\r
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.\r
+#define PWM_X_GENA_ACTCMPAU_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal.\r
+#define PWM_X_GENA_ACTCMPAU_ZERO \\r
+ 0x00000020 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.\r
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load.\r
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal.\r
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.\r
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0.\r
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing.\r
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal.\r
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.\r
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_GENB register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down.\r
+#define PWM_X_GENB_ACTCMPBD_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal.\r
+#define PWM_X_GENB_ACTCMPBD_ZERO \\r
+ 0x00000800 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1.\r
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up.\r
+#define PWM_X_GENB_ACTCMPBU_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal.\r
+#define PWM_X_GENB_ACTCMPBU_ZERO \\r
+ 0x00000200 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1.\r
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down.\r
+#define PWM_X_GENB_ACTCMPAD_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal.\r
+#define PWM_X_GENB_ACTCMPAD_ZERO \\r
+ 0x00000080 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1.\r
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up.\r
+#define PWM_X_GENB_ACTCMPAU_NONE \\r
+ 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal.\r
+#define PWM_X_GENB_ACTCMPAU_ZERO \\r
+ 0x00000020 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1.\r
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load.\r
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal.\r
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1.\r
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0.\r
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing.\r
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal.\r
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0.\r
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay.\r
+#define PWM_X_DBRISE_DELAY_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay.\r
+#define PWM_X_DBFALL_DELAY_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value.\r
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value.\r
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value.\r
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value.\r
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value.\r
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value.\r
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value.\r
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period.\r
+#define PWM_X_MINFLTPER_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense.\r
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense.\r
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense.\r
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3.\r
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2.\r
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1.\r
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3.\r
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2.\r
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1.\r
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the PWM Master\r
+// Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the PWM Interrupt Register bit\r
+// definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the PWM Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT 0x00000001 // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the PWM_X Interrupt Status Register\r
+// bit definitions.\r
//\r
//*****************************************************************************\r
-#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
-#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
-#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
-#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
-#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Generator A/B Control Register bit definitions.\r
+// The following are deprecated defines for the PWM_X Generator A/B Control\r
+// Register bit definitions.\r
//\r
//*****************************************************************************\r
-#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
-#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
-#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
-#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
-#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D\r
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Generator A/B Control Register action definitions.\r
+// The following are deprecated defines for the PWM_X Generator A/B Control\r
+// Register action definitions.\r
//\r
//*****************************************************************************\r
-#define PWM_GEN_ACT_NONE 0x0 // Do nothing\r
-#define PWM_GEN_ACT_INV 0x1 // Invert the output signal\r
-#define PWM_GEN_ACT_ZERO 0x2 // Set the output signal to zero\r
-#define PWM_GEN_ACT_ONE 0x3 // Set the output signal to one\r
-#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
-#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
-#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
-#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
-#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero\r
+#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal\r
+#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing\r
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action\r
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action\r
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action\r
\r
//*****************************************************************************\r
//\r
-// PWM_X Dead Band Control Register bit definitions.\r
+// The following are deprecated defines for the PWM_X Dead Band Control\r
+// Register bit definitions.\r
//\r
//*****************************************************************************\r
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion\r
\r
//*****************************************************************************\r
//\r
-// PWM Register reset values.\r
+// The following are deprecated defines for the PWM Register reset values.\r
//\r
//*****************************************************************************\r
-#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
-#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
-#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM\r
- // output pins\r
-#define PWM_RV_INVERT 0x00000000 // Inversion control for\r
- // PWM output pins\r
-#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
- // output pins\r
-#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
-#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
-#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
#define PWM_RV_STATUS 0x00000000 // Status\r
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM\r
// generator block\r
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators\r
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
+ // count\r
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable\r
-#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status\r
-#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing\r
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter\r
-#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
-#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
-#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A\r
-#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
-#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator\r
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module\r
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM\r
+ // output pins\r
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status\r
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value\r
+#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output\r
+ // pins\r
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay\r
// count\r
-#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay\r
- // count\r
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output\r
+ // pins\r
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B\r
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value\r
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing\r
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable\r
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value\r
+\r
+#endif\r
\r
-#endif // __HW_PWM_H__\r
+#endif // __HW_PWM_H__\r
//\r
// hw_qei.h - Macros used when accessing the QEI hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the QEI registers.\r
+// The following are defines for the QEI register offsets.\r
//\r
//*****************************************************************************\r
#define QEI_O_CTL 0x00000000 // Configuration and control reg.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_CTL register.\r
+// The following are defines for the bit fields in the QEI_CTL register.\r
//\r
//*****************************************************************************\r
#define QEI_CTL_STALLEN 0x00001000 // Stall enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_STAT register.\r
+// The following are defines for the bit fields in the QEI_STAT register.\r
//\r
//*****************************************************************************\r
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_POS register.\r
+// The following are defines for the bit fields in the QEI_POS register.\r
//\r
//*****************************************************************************\r
#define QEI_POS_M 0xFFFFFFFF // Current encoder position\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_MAXPOS register.\r
+// The following are defines for the bit fields in the QEI_MAXPOS register.\r
//\r
//*****************************************************************************\r
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_LOAD register.\r
+// The following are defines for the bit fields in the QEI_LOAD register.\r
//\r
//*****************************************************************************\r
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_TIME register.\r
+// The following are defines for the bit fields in the QEI_TIME register.\r
//\r
//*****************************************************************************\r
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_COUNT register.\r
+// The following are defines for the bit fields in the QEI_COUNT register.\r
//\r
//*****************************************************************************\r
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_SPEED register.\r
+// The following are defines for the bit fields in the QEI_SPEED register.\r
//\r
//*****************************************************************************\r
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_INTEN register.\r
+// The following are defines for the bit fields in the QEI_INTEN register.\r
//\r
//*****************************************************************************\r
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_RIS register.\r
+// The following are defines for the bit fields in the QEI_RIS register.\r
//\r
//*****************************************************************************\r
#define QEI_RIS_ERROR 0x00000008 // Phase error detected\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the QEI_ISC register.\r
+// The following are defines for the bit fields in the QEI_O_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt.\r
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt.\r
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired\r
+ // Interrupt.\r
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the QEI_ISC\r
+// register.\r
//\r
//*****************************************************************************\r
#define QEI_INT_ERROR 0x00000008 // Phase error detected\r
\r
//*****************************************************************************\r
//\r
-// The following define the reset values for the QEI registers.\r
+// The following are deprecated defines for the reset values for the QEI\r
+// registers.\r
//\r
//*****************************************************************************\r
-#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
-#define QEI_RV_STAT 0x00000000 // Status register\r
#define QEI_RV_POS 0x00000000 // Current position register\r
-#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register\r
-#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
-#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
-#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
-#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg.\r
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register\r
#define QEI_RV_ISC 0x00000000 // Interrupt status register\r
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register\r
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register\r
+#define QEI_RV_STAT 0x00000000 // Status register\r
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register\r
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register\r
+#define QEI_RV_TIME 0x00000000 // Velocity timer register\r
+\r
+#endif\r
\r
#endif // __HW_QEI_H__\r
//\r
// hw_ssi.h - Macros used when accessing the SSI hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the SSI registers.\r
+// The following are defines for the SSI register offsets.\r
//\r
//*****************************************************************************\r
#define SSI_O_CR0 0x00000000 // Control register 0\r
#define SSI_O_RIS 0x00000018 // Raw interrupt register\r
#define SSI_O_MIS 0x0000001C // Masked interrupt register\r
#define SSI_O_ICR 0x00000020 // Interrupt clear register\r
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SSI Control register 0.\r
+// The following are defines for the bit fields in the SSI Control register 0.\r
//\r
//*****************************************************************************\r
-#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.\r
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase\r
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity\r
-#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_FRF_M 0x00000030 // Frame format mask\r
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format\r
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format\r
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format\r
-#define SSI_CR0_DSS 0x0000000F // Data size select\r
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.\r
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data\r
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data\r
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data\r
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data\r
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data\r
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data\r
+#define SSI_CR0_SCR_S 8\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SSI Control register 1.\r
+// The following are defines for the bit fields in the SSI Control register 1.\r
//\r
//*****************************************************************************\r
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SSI Status register.\r
+// The following are defines for the bit fields in the SSI Status register.\r
//\r
//*****************************************************************************\r
#define SSI_SR_BSY 0x00000010 // SSI busy\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SSI clock prescale register.\r
+// The following are defines for the bit fields in the SSI clock prescale\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.\r
+#define SSI_CPSR_CPSDVSR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_DR register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.\r
+#define SSI_DR_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_IM register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt\r
+ // Mask.\r
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.\r
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt\r
+ // Mask.\r
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt\r
+ // Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt\r
+ // Status.\r
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt\r
+ // Status.\r
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw\r
+ // Interrupt Status.\r
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw\r
+ // Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked\r
+ // Interrupt Status.\r
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked\r
+ // Interrupt Status.\r
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked\r
+ // Interrupt Status.\r
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked\r
+ // Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt\r
+ // Clear.\r
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt\r
+ // Clear.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SSI_O_DMACTL register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.\r
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SSI Control\r
+// register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate\r
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask\r
+#define SSI_CR0_DSS 0x0000000F // Data size select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SSI clock\r
+// prescale register.\r
//\r
//*****************************************************************************\r
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale\r
\r
//*****************************************************************************\r
//\r
-// The following define information concerning the SSI Data register.\r
+// The following are deprecated defines for the SSI controller's FIFO size.\r
//\r
//*****************************************************************************\r
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the interrupt mask set and clear,\r
-// raw interrupt, masked interrupt, and interrupt clear registers.\r
+// The following are deprecated defines for the bit fields in the interrupt\r
+// mask set and clear, raw interrupt, masked interrupt, and interrupt clear\r
+// registers.\r
//\r
//*****************************************************************************\r
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt\r
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt\r
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt\r
\r
+#endif\r
+\r
#endif // __HW_SSI_H__\r
//\r
// hw_sysctl.h - Macros used when accessing the system control hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the addresses of the system control registers.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_DID0 0x400fe000 // Device identification register 0\r
-#define SYSCTL_DID1 0x400fe004 // Device identification register 1\r
-#define SYSCTL_DC0 0x400fe008 // Device capabilities register 0\r
-#define SYSCTL_DC1 0x400fe010 // Device capabilities register 1\r
-#define SYSCTL_DC2 0x400fe014 // Device capabilities register 2\r
-#define SYSCTL_DC3 0x400fe018 // Device capabilities register 3\r
-#define SYSCTL_DC4 0x400fe01C // Device capabilities register 4\r
-#define SYSCTL_PBORCTL 0x400fe030 // POR/BOR reset control register\r
-#define SYSCTL_LDOPCTL 0x400fe034 // LDO power control register\r
-#define SYSCTL_SRCR0 0x400fe040 // Software reset control reg 0\r
-#define SYSCTL_SRCR1 0x400fe044 // Software reset control reg 1\r
-#define SYSCTL_SRCR2 0x400fe048 // Software reset control reg 2\r
-#define SYSCTL_RIS 0x400fe050 // Raw interrupt status register\r
-#define SYSCTL_IMC 0x400fe054 // Interrupt mask/control register\r
-#define SYSCTL_MISC 0x400fe058 // Interrupt status register\r
-#define SYSCTL_RESC 0x400fe05c // Reset cause register\r
-#define SYSCTL_RCC 0x400fe060 // Run-mode clock config register\r
-#define SYSCTL_PLLCFG 0x400fe064 // PLL configuration register\r
-#define SYSCTL_RCC2 0x400fe070 // Run-mode clock config register 2\r
-#define SYSCTL_RCGC0 0x400fe100 // Run-mode clock gating register 0\r
-#define SYSCTL_RCGC1 0x400fe104 // Run-mode clock gating register 1\r
-#define SYSCTL_RCGC2 0x400fe108 // Run-mode clock gating register 2\r
-#define SYSCTL_SCGC0 0x400fe110 // Sleep-mode clock gating reg 0\r
-#define SYSCTL_SCGC1 0x400fe114 // Sleep-mode clock gating reg 1\r
-#define SYSCTL_SCGC2 0x400fe118 // Sleep-mode clock gating reg 2\r
-#define SYSCTL_DCGC0 0x400fe120 // Deep Sleep-mode clock gate reg 0\r
-#define SYSCTL_DCGC1 0x400fe124 // Deep Sleep-mode clock gate reg 1\r
-#define SYSCTL_DCGC2 0x400fe128 // Deep Sleep-mode clock gate reg 2\r
-#define SYSCTL_DSLPCLKCFG 0x400fe144 // Deep Sleep-mode clock config reg\r
-#define SYSCTL_CLKVCLR 0x400fe150 // Clock verifcation clear register\r
-#define SYSCTL_LDOARST 0x400fe160 // LDO reset control register\r
-#define SYSCTL_USER0 0x400fe1e0 // NV User Register 0\r
-#define SYSCTL_USER1 0x400fe1e4 // NV User Register 1\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_DID0 register.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
-#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
-#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
-#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
-#define SYSCTL_DID0_CLASS_SANDSTORM 0x00000000 // Sandstorm-class Device\r
-#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device\r
-#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
-#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
-#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
-#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
-#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
-#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
-#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
-#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
-#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
-#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
-#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_DID1 register.\r
+// The following are defines for the system control register addresses.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
-#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
-#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
-#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID0 0x400FE000 // Device identification register 0\r
+#define SYSCTL_DID1 0x400FE004 // Device identification register 1\r
+#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0\r
+#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1\r
+#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2\r
+#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3\r
+#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4\r
+#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5\r
+#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6\r
+#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7\r
+#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register\r
+#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0\r
+#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1\r
+#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2\r
+#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register\r
+#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register\r
+#define SYSCTL_MISC 0x400FE058 // Interrupt status register\r
+#define SYSCTL_RESC 0x400FE05C // Reset cause register\r
+#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register\r
+#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register\r
+#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control\r
+#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2\r
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control\r
+#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg\r
+#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register\r
+#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0\r
+#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1\r
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_CLASS_SANDSTORM \\r
+ 0x00000000 // Sandstorm-class Device\r
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device\r
+#define SYSCTL_DID0_CLASS_DUSTDEVIL \\r
+ 0x00030000 // DustDevil-class Device\r
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)\r
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer\r
+ // revision)\r
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer\r
+ // revision)\r
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1\r
+#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2\r
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3\r
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4\r
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version.\r
+#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format\r
+ // definition, indicating a\r
+ // Stellaris LM3Snnn device.\r
+#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1\r
+ // register format, indicating a\r
+ // Stellaris Fury-class device.\r
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family.\r
+#define SYSCTL_DID1_FAM_STELLARIS \\r
+ 0x00000000 // Stellaris family of\r
+ // microcontollers, that is, all\r
+ // devices with external part\r
+ // numbers starting with LM3S.\r
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask\r
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101\r
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102\r
+#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300\r
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301\r
+#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308\r
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310\r
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315\r
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316\r
#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317\r
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328\r
+#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600\r
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601\r
+#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608\r
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610\r
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611\r
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612\r
#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617\r
#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618\r
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628\r
+#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800\r
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801\r
+#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808\r
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811\r
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812\r
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815\r
#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439\r
#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512\r
#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538\r
+#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601\r
+#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607\r
+#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608\r
#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620\r
+#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625\r
+#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626\r
+#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627\r
#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635\r
#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637\r
#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751\r
+#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776\r
#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850\r
+#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911\r
+#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918\r
#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937\r
#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958\r
#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960\r
#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968\r
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110\r
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139\r
+#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276\r
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410\r
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412\r
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432\r
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533\r
+#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601\r
+#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608\r
+#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616\r
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620\r
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637\r
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651\r
+#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671\r
+#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678\r
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730\r
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739\r
+#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776\r
+#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911\r
+#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918\r
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939\r
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948\r
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950\r
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965\r
+#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651\r
+#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739\r
+#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748\r
+#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749\r
+#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759\r
+#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768\r
+#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632\r
+#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652\r
+#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662\r
+#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732\r
+#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737\r
+#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739\r
+#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747\r
+#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749\r
+#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752\r
+#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757\r
+#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762\r
+#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767\r
+#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768\r
+#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769\r
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100\r
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110\r
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420\r
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432\r
#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537\r
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610\r
+#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611\r
+#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618\r
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633\r
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637\r
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730\r
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753\r
+#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911\r
+#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918\r
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938\r
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950\r
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952\r
#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938\r
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962\r
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970\r
-#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971\r
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count.\r
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package\r
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package\r
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package\r
-#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package\r
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask\r
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C)\r
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C)\r
-#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C\r
+ // to 105C)\r
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type.\r
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package\r
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC\r
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP\r
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant\r
-#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask\r
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified)\r
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified)\r
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified\r
-#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+#define SYSCTL_DID1_PRTNO_S 16 // Part number shift\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DC0 register.\r
+// The following are defines for the bit fields in the SYSCTL_DC0 register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask\r
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM\r
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM\r
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM\r
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM\r
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM\r
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM\r
-#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask\r
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash\r
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash\r
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash\r
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash\r
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash\r
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash\r
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift\r
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DC1 register.\r
+// The following are defines for the bit fields in the SYSCTL_DC1 register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present\r
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present\r
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present\r
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present\r
-#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
-#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
-#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
-#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
-#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider.\r
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock\r
+ // with a PLL divider of 4.\r
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a\r
+ // PLL divider of 8.\r
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a\r
+ // PLL divider of 10.\r
+#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask\r
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC\r
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present\r
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present\r
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present\r
#define SYSCTL_DC1_PLL 0x00000010 // PLL present\r
-#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present.\r
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present\r
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present\r
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DC2 register.\r
+// The following are defines for the bit fields in the SYSCTL_DC2 register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present\r
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present\r
#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present\r
#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present\r
-#ifndef DEPRECATED\r
-#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
-#endif\r
#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present\r
#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present\r
-#ifndef DEPRECATED\r
-#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
-#endif\r
#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present\r
#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present\r
-#ifndef DEPRECATED\r
-#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
-#endif\r
#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present\r
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present\r
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DC3 register.\r
+// The following are defines for the bit fields in the SYSCTL_DC3 register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_DC3_32KHZ 0x80000000 // 32kHz pin present\r
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present.\r
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present\r
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present\r
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present\r
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present\r
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present\r
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present\r
-#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present.\r
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present\r
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present\r
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DC4 register.\r
+// The following are defines for the bit fields in the SYSCTL_DC4 register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present\r
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present.\r
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present.\r
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable.\r
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present.\r
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present.\r
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present.\r
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present.\r
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present\r
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present\r
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay.\r
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset\r
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise\r
-#define SYSCTL_PBORCTL_BOR_SH 2\r
+#define SYSCTL_PBORCTL_BORTIM_S 2\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage.\r
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V\r
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V\r
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V\r
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V\r
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V\r
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V\r
-#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V\r
-#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V\r
-#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V\r
-#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V\r
-#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
-// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_SET0_CAN2 0x04000000 // CAN2 module\r
-#define SYSCTL_SET0_CAN1 0x02000000 // CAN1 module\r
-#define SYSCTL_SET0_CAN0 0x01000000 // CAN0 module\r
-#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
-#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
-#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
-#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
-#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
-#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
-#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
-#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
-#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
-// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
-#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
-#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
-#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
-#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
-#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
-#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
-#define SYSCTL_SET1_I2C1 0x00004000 // I2C module 1\r
-#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
-#ifndef DEPRECATED\r
-#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
-#endif\r
-#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
-#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
-#ifndef DEPRECATED\r
-#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
-#endif\r
-#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
-#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
-#ifndef DEPRECATED\r
-#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
-#endif\r
-#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
-#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
-#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
-// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
-#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
-#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
-#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
-#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
-#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
-#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
-#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
-#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
-// SYSCTL_IMS registers.\r
-//\r
-//*****************************************************************************\r
-#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
-#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
-#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
-#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
-#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
-#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
-#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the SYSCTL_RESC register.\r
+// The following are defines for the bit fields in the SYSCTL_RESC register.\r
//\r
//*****************************************************************************\r
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset.\r
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset\r
#define SYSCTL_RESC_SW 0x00000010 // Software reset\r
-#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset.\r
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset\r
#define SYSCTL_RESC_POR 0x00000002 // Power on reset\r
#define SYSCTL_RESC_EXT 0x00000001 // External reset\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_RCC register.\r
+// The following are defines for the bit fields in the SYSCTL_RCC register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating\r
-#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor.\r
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2\r
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3\r
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4\r
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14\r
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15\r
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16\r
-#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
-#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
-#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider.\r
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor.\r
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider\r
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2\r
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4\r
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8\r
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32\r
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64\r
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down\r
-#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable.\r
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass\r
-#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
-#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc\r
#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal\r
#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal\r
#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal\r
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal\r
#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal\r
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal\r
-#ifdef DEPRECATED\r
-#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864MHz crystal\r
-#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4MHz crystal\r
-#endif\r
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal\r
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal\r
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal\r
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal\r
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal\r
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal\r
-#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB)\r
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB)\r
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz\r
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz\r
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz\r
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB)\r
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz\r
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable\r
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select\r
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator\r
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator\r
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator\r
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en\r
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en\r
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable\r
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable\r
-#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
-#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
-#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
-#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider\r
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1\r
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2\r
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4\r
-#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
-#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
-#define SYSCTL_PLLCFG_F_SHIFT 5\r
-#define SYSCTL_PLLCFG_R_SHIFT 0\r
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value.\r
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value.\r
+#define SYSCTL_PLLCFG_F_S 5\r
+#define SYSCTL_PLLCFG_R_S 0\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_RCC2 register.\r
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2\r
-#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider\r
#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2\r
#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3\r
#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4\r
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62\r
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63\r
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64\r
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL.\r
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down\r
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass\r
-#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source.\r
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator\r
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator\r
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4\r
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc.\r
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc.\r
+#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_DSLPCLKCFG register.\r
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG\r
+// register.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_DSLPCLKCFG_D_MSK 0x1f800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override.\r
#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2\r
#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3\r
#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4\r
#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62\r
#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63\r
#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64\r
-#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source.\r
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override\r
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator\r
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc.\r
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc.\r
+#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source.\r
+#define SYSCTL_DSLPCLKCFG_D_S 23\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control.\r
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control.\r
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control.\r
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control.\r
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control.\r
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control.\r
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control.\r
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control.\r
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control.\r
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control.\r
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control.\r
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control.\r
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control.\r
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control.\r
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control.\r
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control.\r
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control.\r
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control.\r
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control.\r
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control.\r
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control.\r
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control.\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control.\r
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control.\r
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control.\r
+#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control.\r
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control.\r
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control.\r
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control.\r
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control.\r
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control.\r
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control.\r
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control.\r
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt\r
+ // Status.\r
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt\r
+ // Status.\r
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status.\r
+#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt\r
+ // Status.\r
+#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw\r
+ // Interrupt Status.\r
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw\r
+ // Interrupt Status.\r
+#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw\r
+ // Interrupt Status.\r
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt\r
+ // Status.\r
+#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_IMC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask.\r
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask.\r
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask.\r
+#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask.\r
+#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault\r
+ // Interrupt Mask.\r
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt\r
+ // Mask.\r
+#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt\r
+ // Mask.\r
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask.\r
+#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_MISC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt\r
+ // Status.\r
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt\r
+ // Status.\r
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt\r
+ // Status.\r
+#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt\r
+ // Status.\r
+#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked\r
+ // Interrupt Status.\r
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked\r
+ // Interrupt Status.\r
+#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked\r
+ // Interrupt Status.\r
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.\r
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.\r
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.\r
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control.\r
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.\r
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.\r
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second\r
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second\r
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second\r
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second\r
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control.\r
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock\r
+ // Gating.\r
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock\r
+ // Gating.\r
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock\r
+ // Gating.\r
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.\r
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.\r
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.\r
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.\r
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.\r
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.\r
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.\r
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.\r
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.\r
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.\r
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control.\r
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control.\r
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.\r
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.\r
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control.\r
+#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.\r
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.\r
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.\r
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.\r
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control.\r
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.\r
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.\r
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second\r
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second\r
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second\r
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second\r
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control.\r
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock\r
+ // Gating.\r
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock\r
+ // Gating.\r
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock\r
+ // Gating.\r
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.\r
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.\r
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.\r
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.\r
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.\r
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.\r
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.\r
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.\r
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.\r
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.\r
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control.\r
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control.\r
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.\r
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.\r
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control.\r
+#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.\r
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control.\r
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control.\r
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control.\r
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control.\r
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control.\r
+#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed.\r
+#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second\r
+#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second\r
+#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second\r
+#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second\r
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control.\r
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock\r
+ // Gating.\r
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock\r
+ // Gating.\r
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock\r
+ // Gating.\r
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control.\r
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control.\r
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control.\r
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control.\r
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control.\r
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control.\r
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control.\r
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control.\r
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control.\r
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control.\r
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control.\r
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control.\r
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control.\r
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control.\r
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control.\r
+#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control.\r
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DC5 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present.\r
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present.\r
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present.\r
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present.\r
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is\r
+ // active.\r
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is\r
+ // active.\r
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present.\r
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present.\r
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present.\r
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present.\r
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present.\r
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present.\r
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present.\r
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DC6 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is\r
+ // present and its capability.\r
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST\r
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed.\r
+#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the SYSCTL_DC7 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25.\r
+#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24.\r
+#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23.\r
+#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22.\r
+#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11.\r
+#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10.\r
+#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9.\r
+#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8.\r
+#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5.\r
+#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4.\r
+#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3.\r
+#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2.\r
+#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1.\r
+#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the system control register\r
+// addresses.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0\r
+#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask\r
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class\r
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A\r
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B\r
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C\r
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DID1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask\r
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask\r
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count\r
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask\r
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask\r
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DC0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DC1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DC2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present\r
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present\r
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_DC3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the\r
+// SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer\r
+#define SYSCTL_PBORCTL_BOR_SH 2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the\r
+// SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,\r
+// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module\r
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module\r
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module\r
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module\r
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module\r
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask\r
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC\r
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC\r
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module\r
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,\r
+// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3\r
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2\r
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1\r
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0\r
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1\r
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0\r
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module\r
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1\r
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module\r
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0\r
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1\r
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0\r
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module\r
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2\r
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1\r
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,\r
+// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module\r
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module\r
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module\r
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module\r
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module\r
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module\r
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module\r
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module\r
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_RIS,\r
+// SYSCTL_IMC, and SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int\r
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt\r
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider\r
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider\r
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal\r
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc\r
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider\r
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT 5\r
+#define SYSCTL_PLLCFG_R_SHIFT 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider\r
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the\r
+// SYSCTL_DSLPCLKCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override\r
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the\r
+// SYSCTL_CLKVCLR register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the SYSCTL_LDOARST register.\r
+// The following are deprecated defines for the bit fields in the\r
+// SYSCTL_LDOARST register.\r
//\r
//*****************************************************************************\r
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device\r
\r
+#endif\r
+\r
#endif // __HW_SYSCTL_H__\r
//\r
// hw_timer.h - Defines and macros used when accessing the timer.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the timer registers.\r
+// The following are defines for the timer register offsets.\r
//\r
//*****************************************************************************\r
#define TIMER_O_CFG 0x00000000 // Configuration register\r
\r
//*****************************************************************************\r
//\r
-// The following define the reset values of the timer registers.\r
+// The following are defines for the bit fields in the TIMER_CFG register.\r
//\r
//*****************************************************************************\r
-#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
-#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
-#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
-#define TIMER_RV_CTL 0x00000000 // Control register RV\r
-#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
-#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
-#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
-#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
-#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
-#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
-#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
-#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
-#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
-#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
-#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
-#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
-#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
-#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the TIMER_CFG register.\r
-//\r
-//*****************************************************************************\r
-#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration.\r
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers\r
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC\r
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_TnMR register.\r
-//\r
-//*****************************************************************************\r
-#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
-#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
-#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
-#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
-#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
-#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the TIMER_CTL register.\r
+// The following are defines for the bit fields in the TIMER_CTL register.\r
//\r
//*****************************************************************************\r
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert\r
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable\r
-#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
-#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
-#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode.\r
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable\r
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable\r
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert\r
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable\r
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable\r
-#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
-#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
-#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode.\r
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge\r
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges\r
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable\r
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_IMR register.\r
+// The following are defines for the bit fields in the TIMER_IMR register.\r
//\r
//*****************************************************************************\r
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_RIS register.\r
+// The following are defines for the bit fields in the TIMER_RIS register.\r
//\r
//*****************************************************************************\r
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_MIS register.\r
-//\r
-//*****************************************************************************\r
-#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
-#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
-#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
-#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
-#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
-#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
-#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
-\r
-//*****************************************************************************\r
-//\r
-// The following define the bit fields in the TIMER_ICR register.\r
+// The following are defines for the bit fields in the TIMER_ICR register.\r
//\r
//*****************************************************************************\r
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_TAILR register.\r
+// The following are defines for the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load\r
+ // Register High.\r
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load\r
+ // Register Low.\r
+#define TIMER_TAILR_TAILRH_S 16\r
+#define TIMER_TAILR_TAILRL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load\r
+ // Register.\r
+#define TIMER_TBILR_TBILRL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High.\r
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low.\r
+#define TIMER_TAMATCHR_TAMRH_S 16\r
+#define TIMER_TAMATCHR_TAMRL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low.\r
+#define TIMER_TBMATCHR_TBMRL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High.\r
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low.\r
+#define TIMER_TAR_TARH_S 16\r
+#define TIMER_TAR_TARL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB.\r
+#define TIMER_TBR_TBRL_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TAMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode\r
+ // Select.\r
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode.\r
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode.\r
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode.\r
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode.\r
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TBMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode\r
+ // Select.\r
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode.\r
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode.\r
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode.\r
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode.\r
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked\r
+ // Interrupt.\r
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked\r
+ // Interrupt.\r
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked\r
+ // Interrupt.\r
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt.\r
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked\r
+ // Interrupt.\r
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked\r
+ // Interrupt.\r
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked\r
+ // Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TAPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale.\r
+#define TIMER_TAPR_TAPSR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TBPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale.\r
+#define TIMER_TBPR_TBPSR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match.\r
+#define TIMER_TAPMR_TAPSMR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match.\r
+#define TIMER_TBPMR_TBPSMR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the reset values of the timer\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV\r
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV\r
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV\r
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV\r
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV\r
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV\r
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV\r
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV\r
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV\r
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV\r
+#define TIMER_RV_CTL 0x00000000 // Control register RV\r
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV\r
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV\r
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV\r
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV\r
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV\r
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV\r
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the TIMER_CFG\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the TIMER_TnMR\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select\r
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the TIMER_CTL\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask\r
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the TIMER_MIS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status\r
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the TIMER_TAILR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode\r
\r
//*****************************************************************************\r
//\r
-// The following defines the bit fields in the TIMER_TBILR register.\r
+// The following are deprecated defines for the bit fields in the TIMER_TBILR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_TAMATCHR register.\r
+// The following are deprecated defines for the bit fields in the\r
+// TIMER_TAMATCHR register.\r
//\r
//*****************************************************************************\r
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode\r
\r
//*****************************************************************************\r
//\r
-// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+// The following are deprecated defines for the bit fields in the\r
+// TIMER_TBMATCHR register.\r
//\r
//*****************************************************************************\r
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value\r
\r
//*****************************************************************************\r
//\r
-// The following defines the bit fields in the TIMER_TnPR register.\r
+// The following are deprecated defines for the bit fields in the TIMER_TnPR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value\r
\r
//*****************************************************************************\r
//\r
-// The following defines the bit fields in the TIMER_TnPMR register.\r
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the TIMER_TAR register.\r
+// The following are deprecated defines for the bit fields in the TIMER_TAR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode\r
\r
//*****************************************************************************\r
//\r
-// The following defines the bit fields in the TIMER_TBR register.\r
+// The following are deprecated defines for the bit fields in the TIMER_TBR\r
+// register.\r
//\r
//*****************************************************************************\r
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value\r
\r
+#endif\r
+\r
#endif // __HW_TIMER_H__\r
//\r
// hw_types.h - Common types and macros.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
// conditional code blocks that will allow a single version of the Driverlib\r
// "binary" code to support multiple(all) Stellaris silicon revisions.\r
//\r
-// It is expected that these macros will be used inside of a standard 'C' \r
+// It is expected that these macros will be used inside of a standard 'C'\r
// conditional block of code, e.g.\r
//\r
-// if(DEVICE_IS_SANDSTORM())\r
+// if(CLASS_IS_SANDSTORM)\r
// {\r
-// do some Sandstorm specific code here.\r
+// do some Sandstorm-class specific code here.\r
// }\r
//\r
// By default, these macros will be defined as run-time checks of the\r
// However, if code-space optimization is required, these macros can be "hard-\r
// coded" for a specific version of Stellaris silicon. Many compilers will\r
// then detect the "hard-coded" conditionals, and appropriately optimize the\r
-// code blocks, eliminating any "unreachable" code. This would result in \r
+// code blocks, eliminating any "unreachable" code. This would result in\r
// a smaller Driverlib, thus producing a smaller final application size, but\r
// at the cost of limiting the Driverlib binary to a specific Stellaris\r
// silicon revision.\r
//\r
//*****************************************************************************\r
-#ifndef DEVICE_IS_SANDSTORM\r
-#define DEVICE_IS_SANDSTORM \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_0) || \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
- ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
- SYSCTL_DID0_CLASS_SANDSTORM)))\r
+#ifndef CLASS_IS_SANDSTORM\r
+#define CLASS_IS_SANDSTORM \\r
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \\r
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))\r
#endif\r
\r
-#ifndef DEVICE_IS_FURY\r
-#define DEVICE_IS_FURY \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_MASK) == SYSCTL_DID0_VER_1) && \\r
- ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_CLASS_MASK) == \\r
- SYSCTL_DID0_CLASS_FURY))\r
+#ifndef CLASS_IS_FURY\r
+#define CLASS_IS_FURY \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \\r
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))\r
#endif\r
\r
-#ifndef DEVICE_IS_REVA2\r
-#define DEVICE_IS_REVA2 \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_A) && \\r
- ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#ifndef CLASS_IS_DUSTDEVIL\r
+#define CLASS_IS_DUSTDEVIL \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \\r
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))\r
#endif\r
\r
-#ifndef DEVICE_IS_REVC1\r
-#define DEVICE_IS_REVC1 \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
- ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_1))\r
+#ifndef REVISION_IS_A0\r
+#define REVISION_IS_A0 \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \\r
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))\r
#endif\r
\r
-#ifndef DEVICE_IS_REVC2\r
-#define DEVICE_IS_REVC2 \\r
- (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MAJ_MASK) == SYSCTL_DID0_MAJ_C) && \\r
- ((HWREG(SYSCTL_DID0) & SYSCTL_DID0_MIN_MASK) == SYSCTL_DID0_MIN_2))\r
+#ifndef REVISION_IS_A2\r
+#define REVISION_IS_A2 \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \\r
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+#ifndef REVISION_IS_C1\r
+#define REVISION_IS_C1 \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \\r
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))\r
+#endif\r
+\r
+#ifndef REVISION_IS_C2\r
+#define REVISION_IS_C2 \\r
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \\r
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Deprecated silicon class and revision detection macros.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM\r
+#define DEVICE_IS_FURY CLASS_IS_FURY\r
+#define DEVICE_IS_REVA2 REVISION_IS_A2\r
+#define DEVICE_IS_REVC1 REVISION_IS_C1\r
+#define DEVICE_IS_REVC2 REVISION_IS_C2\r
#endif\r
\r
#endif // __HW_TYPES_H__\r
//\r
// hw_uart.h - Macros and defines used when accessing the UART hardware\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// UART Register Offsets.\r
+// The following are defines for the UART Register offsets.\r
//\r
//*****************************************************************************\r
#define UART_O_DR 0x00000000 // Data Register\r
#define UART_O_RSR 0x00000004 // Receive Status Register (read)\r
#define UART_O_ECR 0x00000004 // Error Clear Register (write)\r
#define UART_O_FR 0x00000018 // Flag Register (read only)\r
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register\r
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg\r
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg\r
-#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_LCRH 0x0000002C // UART Line Control\r
#define UART_O_CTL 0x00000030 // Control Register\r
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg\r
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg\r
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register\r
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register\r
#define UART_O_ICR 0x00000044 // Interrupt Clear Register\r
-#define UART_O_PeriphID4 0x00000FD0 //\r
-#define UART_O_PeriphID5 0x00000FD4 //\r
-#define UART_O_PeriphID6 0x00000FD8 //\r
-#define UART_O_PeriphID7 0x00000FDC //\r
-#define UART_O_PeriphID0 0x00000FE0 //\r
-#define UART_O_PeriphID1 0x00000FE4 //\r
-#define UART_O_PeriphID2 0x00000FE8 //\r
-#define UART_O_PeriphID3 0x00000FEC //\r
-#define UART_O_PCellID0 0x00000FF0 //\r
-#define UART_O_PCellID1 0x00000FF4 //\r
-#define UART_O_PCellID2 0x00000FF8 //\r
-#define UART_O_PCellID3 0x00000FFC //\r
+#define UART_O_DMACTL 0x00000048 // UART DMA Control\r
\r
//*****************************************************************************\r
//\r
-// Data Register bits\r
+// The following are defines for the Data Register bits\r
//\r
//*****************************************************************************\r
#define UART_DR_OE 0x00000800 // Overrun Error\r
#define UART_DR_BE 0x00000400 // Break Error\r
#define UART_DR_PE 0x00000200 // Parity Error\r
#define UART_DR_FE 0x00000100 // Framing Error\r
-#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received.\r
+#define UART_DR_DATA_S 0\r
\r
//*****************************************************************************\r
//\r
-// Receive Status Register bits\r
+// The following are defines for the Receive Status Register bits\r
//\r
//*****************************************************************************\r
#define UART_RSR_OE 0x00000008 // Overrun Error\r
\r
//*****************************************************************************\r
//\r
-// Flag Register bits\r
+// The following are defines for the Flag Register bits\r
//\r
//*****************************************************************************\r
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty\r
\r
//*****************************************************************************\r
//\r
-// Integer baud-rate divisor\r
+// The following are defines for the Integer baud-rate divisor\r
//\r
//*****************************************************************************\r
-#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
-\r
-//*****************************************************************************\r
-//\r
-// Fractional baud-rate divisor\r
-//\r
-//*****************************************************************************\r
-#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor.\r
+#define UART_IBRD_DIVINT_S 0\r
\r
//*****************************************************************************\r
//\r
-// Line Control Register High bits\r
+// The following are defines for the Fractional baud-rate divisor\r
//\r
//*****************************************************************************\r
-#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
-#define UART_LCR_H_WLEN 0x00000060 // Word length\r
-#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
-#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
-#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
-#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
-#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
-#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
-#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
-#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
-#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor.\r
+#define UART_FBRD_DIVFRAC_S 0\r
\r
//*****************************************************************************\r
//\r
-// Control Register bits\r
+// The following are defines for the Control Register bits\r
//\r
//*****************************************************************************\r
#define UART_CTL_RXE 0x00000200 // Receive Enable\r
\r
//*****************************************************************************\r
//\r
-// Interrupt FIFO Level Select Register bits\r
+// The following are defines for the Interrupt FIFO Level Select Register bits\r
//\r
//*****************************************************************************\r
-#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask\r
+#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask\r
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full\r
#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full\r
#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full\r
#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full\r
#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full\r
-#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask\r
+#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask\r
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full\r
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full\r
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full\r
\r
//*****************************************************************************\r
//\r
-// Interrupt Mask Set/Clear Register bits\r
+// The following are defines for the Interrupt Mask Set/Clear Register bits\r
//\r
//*****************************************************************************\r
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask\r
\r
//*****************************************************************************\r
//\r
-// Raw Interrupt Status Register\r
+// The following are defines for the Raw Interrupt Status Register\r
//\r
//*****************************************************************************\r
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status\r
\r
//*****************************************************************************\r
//\r
-// Masked Interrupt Status Register\r
+// The following are defines for the Masked Interrupt Status Register\r
//\r
//*****************************************************************************\r
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status\r
\r
//*****************************************************************************\r
//\r
-// Interrupt Clear Register bits\r
+// The following are defines for the Interrupt Clear Register bits\r
//\r
//*****************************************************************************\r
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear\r
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear\r
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear\r
\r
-#define UART_RSR_ANY (UART_RSR_OE | \\r
- UART_RSR_BE | \\r
- UART_RSR_PE | \\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UART_O_ECR register.\r
+//\r
+//*****************************************************************************\r
+#define UART_ECR_DATA_M 0x000000FF // Error Clear.\r
+#define UART_ECR_DATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UART_O_LCRH register.\r
+//\r
+//*****************************************************************************\r
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select.\r
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length.\r
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)\r
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits\r
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits\r
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits\r
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs.\r
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select.\r
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select.\r
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable.\r
+#define UART_LCRH_BRK 0x00000001 // UART Send Break.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UART_O_ILPR register.\r
+//\r
+//*****************************************************************************\r
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor.\r
+#define UART_ILPR_ILPDVSR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UART_O_DMACTL register.\r
+//\r
+//*****************************************************************************\r
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error.\r
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.\r
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the UART Register offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte\r
+#define UART_O_PeriphID4 0x00000FD0\r
+#define UART_O_PeriphID5 0x00000FD4\r
+#define UART_O_PeriphID6 0x00000FD8\r
+#define UART_O_PeriphID7 0x00000FDC\r
+#define UART_O_PeriphID0 0x00000FE0\r
+#define UART_O_PeriphID1 0x00000FE4\r
+#define UART_O_PeriphID2 0x00000FE8\r
+#define UART_O_PeriphID3 0x00000FEC\r
+#define UART_O_PCellID0 0x00000FF0\r
+#define UART_O_PCellID1 0x00000FF4\r
+#define UART_O_PCellID2 0x00000FF8\r
+#define UART_O_PCellID3 0x00000FFC\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_DATA_MASK 0x000000FF // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select\r
+#define UART_LCR_H_WLEN 0x00000060 // Word length\r
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data\r
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data\r
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data\r
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO\r
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select\r
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select\r
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable\r
+#define UART_LCR_H_BRK 0x00000001 // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Interrupt FIFO Level Select\r
+// Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask\r
+#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \\r
UART_RSR_FE)\r
\r
//*****************************************************************************\r
//\r
-// Reset Values for UART Registers.\r
+// The following are deprecated defines for the Reset Values for UART\r
+// Registers.\r
//\r
//*****************************************************************************\r
+#define UART_RV_CTL 0x00000300\r
+#define UART_RV_PCellID1 0x000000F0\r
+#define UART_RV_PCellID3 0x000000B1\r
+#define UART_RV_FR 0x00000090\r
+#define UART_RV_PeriphID2 0x00000018\r
+#define UART_RV_IFLS 0x00000012\r
+#define UART_RV_PeriphID0 0x00000011\r
+#define UART_RV_PCellID0 0x0000000D\r
+#define UART_RV_PCellID2 0x00000005\r
+#define UART_RV_PeriphID3 0x00000001\r
+#define UART_RV_PeriphID4 0x00000000\r
+#define UART_RV_LCR_H 0x00000000\r
+#define UART_RV_PeriphID6 0x00000000\r
#define UART_RV_DR 0x00000000\r
#define UART_RV_RSR 0x00000000\r
#define UART_RV_ECR 0x00000000\r
-#define UART_RV_FR 0x00000090\r
-#define UART_RV_IBRD 0x00000000\r
+#define UART_RV_PeriphID5 0x00000000\r
+#define UART_RV_RIS 0x00000000\r
#define UART_RV_FBRD 0x00000000\r
-#define UART_RV_LCR_H 0x00000000\r
-#define UART_RV_CTL 0x00000300\r
-#define UART_RV_IFLS 0x00000012\r
#define UART_RV_IM 0x00000000\r
-#define UART_RV_RIS 0x00000000\r
#define UART_RV_MIS 0x00000000\r
#define UART_RV_ICR 0x00000000\r
-#define UART_RV_PeriphID4 0x00000000\r
-#define UART_RV_PeriphID5 0x00000000\r
-#define UART_RV_PeriphID6 0x00000000\r
-#define UART_RV_PeriphID7 0x00000000\r
-#define UART_RV_PeriphID0 0x00000011\r
#define UART_RV_PeriphID1 0x00000000\r
-#define UART_RV_PeriphID2 0x00000018\r
-#define UART_RV_PeriphID3 0x00000001\r
-#define UART_RV_PCellID0 0x0000000D\r
-#define UART_RV_PCellID1 0x000000F0\r
-#define UART_RV_PCellID2 0x00000005\r
-#define UART_RV_PCellID3 0x000000B1\r
+#define UART_RV_PeriphID7 0x00000000\r
+#define UART_RV_IBRD 0x00000000\r
+\r
+#endif\r
\r
#endif // __HW_UART_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_udma.h - Macros for use in accessing the UDMA registers.\r
+//\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UDMA_H__\r
+#define __HW_UDMA_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_STAT 0x400FF000 // DMA Status\r
+#define UDMA_CFG 0x400FF004 // DMA Configuration\r
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer\r
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control\r
+ // Base Pointer\r
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request\r
+ // Status\r
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request\r
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set\r
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear\r
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set\r
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear\r
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set\r
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear\r
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate\r
+ // Set\r
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate\r
+ // Clear\r
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set\r
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear\r
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear\r
+\r
+//*****************************************************************************\r
+//\r
+// Micro Direct Memory Access (uDMA) offsets.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End\r
+ // Pointer\r
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address\r
+ // End Pointer\r
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer.\r
+#define UDMA_SRCENDP_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1.\r
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State.\r
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle\r
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data\r
+#define UDMA_STAT_STATE_RD_SRCENDP \\r
+ 0x00000020 // Reading source end pointer\r
+#define UDMA_STAT_STATE_RD_DSTENDP \\r
+ 0x00000030 // Reading destination end pointer\r
+#define UDMA_STAT_STATE_RD_SRCDAT \\r
+ 0x00000040 // Reading source data\r
+#define UDMA_STAT_STATE_WR_DSTDAT \\r
+ 0x00000050 // Writing destination data\r
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear\r
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data\r
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled\r
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done\r
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined\r
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable.\r
+#define UDMA_STAT_DMACHANS_S 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer.\r
+#define UDMA_DSTENDP_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_CTLBASE register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address.\r
+#define UDMA_CTLBASE_ADDR_S 10\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment.\r
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte\r
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word\r
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word\r
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment\r
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size.\r
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte\r
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word\r
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word\r
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment.\r
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte\r
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word\r
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word\r
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment\r
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size.\r
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte\r
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word\r
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word\r
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size.\r
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer\r
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers\r
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers\r
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1).\r
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst.\r
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode.\r
+#define UDMA_CHCTL_XFERMODE_STOP \\r
+ 0x00000000 // Stop\r
+#define UDMA_CHCTL_XFERMODE_BASIC \\r
+ 0x00000001 // Basic\r
+#define UDMA_CHCTL_XFERMODE_AUTO \\r
+ 0x00000002 // Auto-Request\r
+#define UDMA_CHCTL_XFERMODE_PINGPONG \\r
+ 0x00000003 // Ping-Pong\r
+#define UDMA_CHCTL_XFERMODE_MEM_SG \\r
+ 0x00000004 // Memory Scatter-Gather\r
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \\r
+ 0x00000005 // Alternate Memory Scatter-Gather\r
+#define UDMA_CHCTL_XFERMODE_PER_SG \\r
+ 0x00000006 // Peripheral Scatter-Gather\r
+#define UDMA_CHCTL_XFERMODE_PER_SGA \\r
+ 0x00000007 // Alternate Peripheral\r
+ // Scatter-Gather\r
+#define UDMA_CHCTL_XFERSIZE_S 4\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ALTBASE register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address\r
+ // Pointer.\r
+#define UDMA_ALTBASE_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status.\r
+#define UDMA_WAITSTAT_WAITREQ_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_SWREQ register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request.\r
+#define UDMA_SWREQ_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_USEBURSTSET\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set.\r
+#define UDMA_USEBURSTSET_SET__0 0x00000000 // No Effect\r
+#define UDMA_USEBURSTSET_SET__1 0x00000001 // Burst Only\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear.\r
+#define UDMA_USEBURSTCLR_CLR__0 0x00000000 // No Effect\r
+#define UDMA_USEBURSTCLR_CLR__1 0x00000001 // Single and Burst\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_REQMASKSET\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set.\r
+#define UDMA_REQMASKSET_SET__0 0x00000000 // No Effect\r
+#define UDMA_REQMASKSET_SET__1 0x00000001 // Masked\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_REQMASKCLR\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear.\r
+#define UDMA_REQMASKCLR_CLR__0 0x00000000 // No Effect\r
+#define UDMA_REQMASKCLR_CLR__1 0x00000001 // Clear Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ENASET register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set.\r
+#define UDMA_ENASET_SET__0 0x00000000 // Disabled\r
+#define UDMA_ENASET_SET__1 0x00000001 // Enabled\r
+#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set.\r
+#define UDMA_ENASET_CHENSET__0 0x00000000 // No Effect\r
+#define UDMA_ENASET_CHENSET__1 0x00000001 // Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ENACLR register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable.\r
+#define UDMA_ENACLR_CLR__0 0x00000000 // No Effect\r
+#define UDMA_ENACLR_CLR__1 0x00000001 // Disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ALTSET register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set.\r
+#define UDMA_ALTSET_SET__0 0x00000000 // No Effect\r
+#define UDMA_ALTSET_SET__1 0x00000001 // Alternate\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ALTCLR register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear.\r
+#define UDMA_ALTCLR_CLR__0 0x00000000 // No Effect\r
+#define UDMA_ALTCLR_CLR__1 0x00000001 // Primary\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_PRIOSET register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set.\r
+#define UDMA_PRIOSET_SET__0 0x00000000 // No Effect\r
+#define UDMA_PRIOSET_SET__1 0x00000001 // High Priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear.\r
+#define UDMA_PRIOCLR_CLR__0 0x00000000 // No Effect\r
+#define UDMA_PRIOCLR_CLR__1 0x00000001 // Default Priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the UDMA_ERRCLR register.\r
+//\r
+//*****************************************************************************\r
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status.\r
+\r
+#endif // __HW_UDMA_H__\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// hw_usb.h - Macros for use in accessing the USB registers.\r
+//\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_USB_H__\r
+#define __HW_USB_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the Univeral Serial Bus (USB) Controller\r
+// offsets.\r
+//\r
+//*****************************************************************************\r
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address\r
+#define USB_O_POWER 0x00000001 // USB Power\r
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status\r
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status\r
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable\r
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable\r
+#define USB_O_IS 0x0000000A // USB General Interrupt Status\r
+#define USB_O_IE 0x0000000B // USB Interrupt Enable\r
+#define USB_O_FRAME 0x0000000C // USB Frame Value\r
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index\r
+#define USB_O_TEST 0x0000000F // USB Test Mode\r
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0\r
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1\r
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2\r
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3\r
+#define USB_O_DEVCTL 0x00000060 // USB Device Control\r
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing\r
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing\r
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address\r
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address\r
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing\r
+#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing\r
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction\r
+ // to End of Frame Timing\r
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction\r
+ // to End of Frame Timing\r
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address\r
+ // Endpoint 0\r
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address\r
+ // Endpoint 0\r
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0\r
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address\r
+ // Endpoint 1\r
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address\r
+ // Endpoint 1\r
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1\r
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address\r
+ // Endpoint 1\r
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint\r
+ // 1\r
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1\r
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address\r
+ // Endpoint 2\r
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address\r
+ // Endpoint 2\r
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2\r
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address\r
+ // Endpoint 2\r
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint\r
+ // 2\r
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2\r
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address\r
+ // Endpoint 3\r
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address\r
+ // Endpoint 3\r
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3\r
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address\r
+ // Endpoint 3\r
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint\r
+ // 3\r
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3\r
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint\r
+ // 0 Low\r
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint\r
+ // 0 High\r
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint\r
+ // 0\r
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0\r
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit\r
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data\r
+ // Endpoint 1\r
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status\r
+ // Endpoint 1 Low\r
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status\r
+ // Endpoint 1 High\r
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data\r
+ // Endpoint 1\r
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status\r
+ // Endpoint 1 Low\r
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status\r
+ // Endpoint 1 High\r
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint\r
+ // 1\r
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type\r
+ // Endpoint 1\r
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval\r
+ // Endpoint 1\r
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type\r
+ // Endpoint 1\r
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling\r
+ // Interval Endpoint 1\r
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data\r
+ // Endpoint 2\r
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status\r
+ // Endpoint 2 Low\r
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status\r
+ // Endpoint 2 High\r
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data\r
+ // Endpoint 2\r
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status\r
+ // Endpoint 2 Low\r
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status\r
+ // Endpoint 2 High\r
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint\r
+ // 2\r
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type\r
+ // Endpoint 2\r
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval\r
+ // Endpoint 2\r
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type\r
+ // Endpoint 2\r
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling\r
+ // Interval Endpoint 2\r
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data\r
+ // Endpoint 3\r
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status\r
+ // Endpoint 3 Low\r
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status\r
+ // Endpoint 3 High\r
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data\r
+ // Endpoint 3\r
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status\r
+ // Endpoint 3 Low\r
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status\r
+ // Endpoint 3 High\r
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint\r
+ // 3\r
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type\r
+ // Endpoint 3\r
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval\r
+ // Endpoint 3\r
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type\r
+ // Endpoint 3\r
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling\r
+ // Interval Endpoint 3\r
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in\r
+ // Block Transfer Endpoint 1\r
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in\r
+ // Block Transfer Endpoint 2\r
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in\r
+ // Block Transfer Endpoint 3\r
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer\r
+ // Disable\r
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet\r
+ // Buffer Disable\r
+#define USB_O_EPC 0x00000400 // USB External Power Control\r
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw\r
+ // Interrupt Status\r
+#define USB_O_EPCIM 0x00000408 // USB External Power Control\r
+ // Interrupt Mask\r
+#define USB_O_EPCISC 0x0000040C // USB External Power Control\r
+ // Interrupt Status and Clear\r
+#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt\r
+ // Status\r
+#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask\r
+#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt\r
+ // Status and Clear\r
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and\r
+ // Status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FADDR register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FADDR_M 0x0000007F // Function Address.\r
+#define USB_FADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_POWER register.\r
+//\r
+//*****************************************************************************\r
+#define USB_POWER_ISOUP 0x00000080 // ISO Update.\r
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect.\r
+#define USB_POWER_RESET 0x00000008 // Reset.\r
+#define USB_POWER_RESUME 0x00000004 // Resume Signaling.\r
+#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode.\r
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXIS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt.\r
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt.\r
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt.\r
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXIS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt.\r
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt.\r
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXIE register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable.\r
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable.\r
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable.\r
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt\r
+ // Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXIE register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable.\r
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable.\r
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_IS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_IS_VBUSERR 0x00000080 // VBus Error.\r
+#define USB_IS_SESREQ 0x00000040 // Session Request.\r
+#define USB_IS_DISCON 0x00000020 // Session Disconnect.\r
+#define USB_IS_CONN 0x00000010 // Session Connect.\r
+#define USB_IS_SOF 0x00000008 // Start of Frame.\r
+#define USB_IS_BABBLE 0x00000004 // Babble Detected.\r
+#define USB_IS_RESET 0x00000004 // Reset Signal Detected.\r
+#define USB_IS_RESUME 0x00000002 // Resume Signal Detected.\r
+#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_IE register.\r
+//\r
+//*****************************************************************************\r
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt.\r
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request\r
+ // Interrupt.\r
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt.\r
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt.\r
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt.\r
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt.\r
+#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt.\r
+#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt.\r
+#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FRAME register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FRAME_M 0x000007FF // Frame Number.\r
+#define USB_FRAME_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_EPIDX register.\r
+//\r
+//*****************************************************************************\r
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index.\r
+#define USB_EPIDX_EPIDX_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode.\r
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access.\r
+#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FIFO0 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data.\r
+#define USB_FIFO0_EPDATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FIFO1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data.\r
+#define USB_FIFO1_EPDATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FIFO2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data.\r
+#define USB_FIFO2_EPDATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FIFO3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data.\r
+#define USB_FIFO3_EPDATA_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_DEVCTL register.\r
+//\r
+//*****************************************************************************\r
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode.\r
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected.\r
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected.\r
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level.\r
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd\r
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid\r
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid\r
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid\r
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode.\r
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request.\r
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.\r
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.\r
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8\r
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16\r
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32\r
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64\r
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128\r
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256\r
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512\r
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024\r
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support.\r
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size.\r
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8\r
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16\r
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32\r
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64\r
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128\r
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256\r
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512\r
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024\r
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFIFOADD\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.\r
+#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0\r
+#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8\r
+#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16\r
+#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32\r
+#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64\r
+#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128\r
+#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256\r
+#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512\r
+#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024\r
+#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXFIFOADD\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address.\r
+#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0\r
+#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8\r
+#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16\r
+#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32\r
+#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64\r
+#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128\r
+#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256\r
+#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512\r
+#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024\r
+#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_CONTIM register.\r
+//\r
+//*****************************************************************************\r
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait.\r
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID.\r
+#define USB_CONTIM_WTCON_S 4\r
+#define USB_CONTIM_WTID_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_FSEOF register.\r
+//\r
+//*****************************************************************************\r
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap.\r
+#define USB_FSEOF_FSEOFG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_LSEOF register.\r
+//\r
+//*****************************************************************************\r
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap.\r
+#define USB_LSEOF_LSEOFG_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address.\r
+#define USB_TXFUNCADDR0_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_TXHUBADDR0_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port.\r
+#define USB_TXHUBPORT0_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address.\r
+#define USB_TXFUNCADDR1_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_TXHUBADDR1_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port.\r
+#define USB_TXHUBPORT1_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address.\r
+#define USB_RXFUNCADDR1_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_RXHUBADDR1_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port.\r
+#define USB_RXHUBPORT1_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address.\r
+#define USB_TXFUNCADDR2_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_TXHUBADDR2_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port.\r
+#define USB_TXHUBPORT2_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address.\r
+#define USB_RXFUNCADDR2_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_RXHUBADDR2_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port.\r
+#define USB_RXHUBPORT2_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address.\r
+#define USB_TXFUNCADDR3_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_TXHUBADDR3_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port.\r
+#define USB_TXHUBPORT3_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address.\r
+#define USB_RXFUNCADDR3_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators.\r
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address.\r
+#define USB_RXHUBADDR3_ADDR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port.\r
+#define USB_RXHUBPORT3_PORT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_CSRL0 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout.\r
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear.\r
+#define USB_CSRL0_STATUS 0x00000040 // Status Packet.\r
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear.\r
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet.\r
+#define USB_CSRL0_STALL 0x00000020 // Send Stall.\r
+#define USB_CSRL0_SETEND 0x00000010 // Setup End.\r
+#define USB_CSRL0_ERROR 0x00000010 // Error.\r
+#define USB_CSRL0_DATAEND 0x00000008 // Data End.\r
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet.\r
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled.\r
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready.\r
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_CSRH0 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable.\r
+#define USB_CSRH0_DT 0x00000002 // Data Toggle.\r
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_COUNT0 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_COUNT0_COUNT_M 0x0000007F // Count.\r
+#define USB_COUNT0_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TYPE0 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full\r
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_NAKLMT register.\r
+//\r
+//*****************************************************************************\r
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit.\r
+#define USB_NAKLMT_NAKLMT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_TXMAXP1_MULT_S 11\r
+#define USB_TXMAXP1_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout\r
+#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit.\r
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle.\r
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled.\r
+#define USB_TXCSRL1_STALL 0x00000010 // Send Stall.\r
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet.\r
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO.\r
+#define USB_TXCSRL1_ERROR 0x00000004 // Error.\r
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun.\r
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty.\r
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set.\r
+#define USB_TXCSRH1_ISO 0x00000040 // ISO.\r
+#define USB_TXCSRH1_MODE 0x00000020 // Mode.\r
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable.\r
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle.\r
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode.\r
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable.\r
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_RXMAXP1_MULT_S 11\r
+#define USB_RXMAXP1_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle.\r
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled.\r
+#define USB_RXCSRL1_STALL 0x00000020 // Send Stall.\r
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet.\r
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO.\r
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error.\r
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout.\r
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun.\r
+#define USB_RXCSRL1_ERROR 0x00000004 // Error.\r
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full.\r
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear.\r
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request.\r
+#define USB_RXCSRH1_ISO 0x00000040 // ISO.\r
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable.\r
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET\r
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error.\r
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode.\r
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable.\r
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle.\r
+#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count.\r
+#define USB_RXCOUNT1_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default\r
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full\r
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low\r
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol.\r
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control\r
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_TXTYPE1_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXINTERVAL1_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_TXINTERVAL1_TXPOLL_M \\r
+ 0x000000FF // TX Polling\r
+#define USB_TXINTERVAL1_TXPOLL_S \\r
+ 0\r
+#define USB_TXINTERVAL1_NAKLMT_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default\r
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full\r
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low\r
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol.\r
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control\r
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_RXTYPE1_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXINTERVAL1_TXPOLL_M \\r
+ 0x000000FF // RX Polling\r
+#define USB_RXINTERVAL1_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_RXINTERVAL1_TXPOLL_S \\r
+ 0\r
+#define USB_RXINTERVAL1_NAKLMT_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_TXMAXP2_MULT_S 11\r
+#define USB_TXMAXP2_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit.\r
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout\r
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle.\r
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled.\r
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet.\r
+#define USB_TXCSRL2_STALL 0x00000010 // Send Stall.\r
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO.\r
+#define USB_TXCSRL2_ERROR 0x00000004 // Error.\r
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun.\r
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty.\r
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set.\r
+#define USB_TXCSRH2_ISO 0x00000040 // ISO.\r
+#define USB_TXCSRH2_MODE 0x00000020 // Mode.\r
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable.\r
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle.\r
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode.\r
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable.\r
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_RXMAXP2_MULT_S 11\r
+#define USB_RXMAXP2_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle.\r
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled.\r
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet.\r
+#define USB_RXCSRL2_STALL 0x00000020 // Send Stall.\r
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO.\r
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error.\r
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout.\r
+#define USB_RXCSRL2_ERROR 0x00000004 // Error.\r
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun.\r
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full.\r
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear.\r
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request.\r
+#define USB_RXCSRH2_ISO 0x00000040 // ISO.\r
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable.\r
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET\r
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error.\r
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode.\r
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable.\r
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle.\r
+#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count.\r
+#define USB_RXCOUNT2_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default\r
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full\r
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low\r
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol.\r
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control\r
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_TXTYPE2_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXINTERVAL2_TXPOLL_M \\r
+ 0x000000FF // TX Polling\r
+#define USB_TXINTERVAL2_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_TXINTERVAL2_NAKLMT_S \\r
+ 0\r
+#define USB_TXINTERVAL2_TXPOLL_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default\r
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full\r
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low\r
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol.\r
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control\r
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_RXTYPE2_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXINTERVAL2_TXPOLL_M \\r
+ 0x000000FF // RX Polling\r
+#define USB_RXINTERVAL2_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_RXINTERVAL2_TXPOLL_S \\r
+ 0\r
+#define USB_RXINTERVAL2_NAKLMT_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_TXMAXP3_MULT_S 11\r
+#define USB_TXMAXP3_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit.\r
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout\r
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle.\r
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled.\r
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet.\r
+#define USB_TXCSRL3_STALL 0x00000010 // Send Stall.\r
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO.\r
+#define USB_TXCSRL3_ERROR 0x00000004 // Error.\r
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun.\r
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty.\r
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set.\r
+#define USB_TXCSRH3_ISO 0x00000040 // ISO.\r
+#define USB_TXCSRH3_MODE 0x00000020 // Mode.\r
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable.\r
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle.\r
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode.\r
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable.\r
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier.\r
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload.\r
+#define USB_RXMAXP3_MULT_S 11\r
+#define USB_RXMAXP3_MAXLOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle.\r
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled.\r
+#define USB_RXCSRL3_STALL 0x00000020 // Send Stall.\r
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet.\r
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO.\r
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error.\r
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout.\r
+#define USB_RXCSRL3_ERROR 0x00000004 // Error.\r
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun.\r
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full.\r
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear.\r
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request.\r
+#define USB_RXCSRH3_ISO 0x00000040 // ISO.\r
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable.\r
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET\r
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error.\r
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode.\r
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable.\r
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle.\r
+#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count.\r
+#define USB_RXCOUNT3_COUNT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default\r
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full\r
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low\r
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol.\r
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control\r
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_TXTYPE3_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXINTERVAL3_TXPOLL_M \\r
+ 0x000000FF // TX Polling\r
+#define USB_TXINTERVAL3_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_TXINTERVAL3_TXPOLL_S \\r
+ 0\r
+#define USB_TXINTERVAL3_NAKLMT_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed.\r
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default\r
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full\r
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low\r
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol.\r
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control\r
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous\r
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk\r
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt\r
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number.\r
+#define USB_RXTYPE3_TEP_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXINTERVAL3_TXPOLL_M \\r
+ 0x000000FF // RX Polling\r
+#define USB_RXINTERVAL3_NAKLMT_M \\r
+ 0x000000FF // NAK Limit.\r
+#define USB_RXINTERVAL3_TXPOLL_S \\r
+ 0\r
+#define USB_RXINTERVAL3_NAKLMT_S \\r
+ 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count.\r
+#define USB_RQPKTCOUNT1_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count.\r
+#define USB_RQPKTCOUNT2_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count.\r
+#define USB_RQPKTCOUNT3_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer\r
+ // Disable.\r
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer\r
+ // Disable.\r
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer\r
+ // Disable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer\r
+ // Disable.\r
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer\r
+ // Disable.\r
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer\r
+ // Disable.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_EPC register.\r
+//\r
+//*****************************************************************************\r
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action.\r
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged\r
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate\r
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low\r
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High\r
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable.\r
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense.\r
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable.\r
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable.\r
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable\r
+ // Configuration.\r
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low\r
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High\r
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low\r
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_EPCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt\r
+ // Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_EPCIM register.\r
+//\r
+//*****************************************************************************\r
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_EPCISC register.\r
+//\r
+//*****************************************************************************\r
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status\r
+ // and Clear.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_DRRIS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_DRIM register.\r
+//\r
+//*****************************************************************************\r
+#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_DRISC register.\r
+//\r
+//*****************************************************************************\r
+#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and\r
+ // Clear.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_GPCS register.\r
+//\r
+//*****************************************************************************\r
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the USB_O_VPLEN register.\r
+//\r
+//*****************************************************************************\r
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length.\r
+#define USB_VPLEN_VPLEN_S 0\r
+\r
+#endif // __HW_USB_H__\r
//\r
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
\r
//*****************************************************************************\r
//\r
-// The following define the offsets of the Watchdog Timer registers.\r
+// The following are defines for the Watchdog Timer register offsets.\r
//\r
//*****************************************************************************\r
#define WDT_O_LOAD 0x00000000 // Load register\r
#define WDT_O_MIS 0x00000014 // Masked interrupt status register\r
#define WDT_O_TEST 0x00000418 // Test register\r
#define WDT_O_LOCK 0x00000C00 // Lock register\r
-#define WDT_O_PeriphID4 0x00000FD0 //\r
-#define WDT_O_PeriphID5 0x00000FD4 //\r
-#define WDT_O_PeriphID6 0x00000FD8 //\r
-#define WDT_O_PeriphID7 0x00000FDC //\r
-#define WDT_O_PeriphID0 0x00000FE0 //\r
-#define WDT_O_PeriphID1 0x00000FE4 //\r
-#define WDT_O_PeriphID2 0x00000FE8 //\r
-#define WDT_O_PeriphID3 0x00000FEC //\r
-#define WDT_O_PCellID0 0x00000FF0 //\r
-#define WDT_O_PCellID1 0x00000FF4 //\r
-#define WDT_O_PCellID2 0x00000FF8 //\r
-#define WDT_O_PCellID3 0x00000FFC //\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the WDT_CTL register.\r
+// The following are defines for the bit fields in the WDT_CTL register.\r
//\r
//*****************************************************************************\r
#define WDT_CTL_RESEN 0x00000002 // Enable reset output\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
-// registers.\r
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and\r
+// WDT_MIS registers.\r
//\r
//*****************************************************************************\r
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the WDT_TEST register.\r
+// The following are defines for the bit fields in the WDT_TEST register.\r
//\r
//*****************************************************************************\r
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable\r
-#ifndef DEPRECATED\r
-#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
-#endif\r
\r
//*****************************************************************************\r
//\r
-// The following define the bit fields in the WDT_LOCK register.\r
+// The following are defines for the bit fields in the WDT_LOCK register.\r
//\r
//*****************************************************************************\r
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock.\r
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked\r
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked\r
-#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer\r
\r
//*****************************************************************************\r
//\r
-// The following define the reset values for the WDT registers.\r
+// The following are defines for the bit fields in the WDT_O_LOAD register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value.\r
+#define WDT_LOAD_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the WDT_O_VALUE register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value.\r
+#define WDT_VALUE_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the WDT_O_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear.\r
+#define WDT_ICR_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the WDT_O_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are defines for the bit fields in the WDT_O_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt\r
+ // Status.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following definitions are deprecated.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the Watchdog Timer register\r
+// offsets.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_PeriphID4 0x00000FD0\r
+#define WDT_O_PeriphID5 0x00000FD4\r
+#define WDT_O_PeriphID6 0x00000FD8\r
+#define WDT_O_PeriphID7 0x00000FDC\r
+#define WDT_O_PeriphID0 0x00000FE0\r
+#define WDT_O_PeriphID1 0x00000FE4\r
+#define WDT_O_PeriphID2 0x00000FE8\r
+#define WDT_O_PeriphID3 0x00000FEC\r
+#define WDT_O_PCellID0 0x00000FF0\r
+#define WDT_O_PCellID1 0x00000FF4\r
+#define WDT_O_PCellID2 0x00000FF8\r
+#define WDT_O_PCellID3 0x00000FFC\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the bit fields in the WDT_TEST\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are deprecated defines for the reset values for the WDT\r
+// registers.\r
//\r
//*****************************************************************************\r
-#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register\r
-#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register\r
+#define WDT_RV_PCellID1 0x000000F0\r
+#define WDT_RV_PCellID3 0x000000B1\r
+#define WDT_RV_PeriphID1 0x00000018\r
+#define WDT_RV_PeriphID2 0x00000018\r
+#define WDT_RV_PCellID0 0x0000000D\r
+#define WDT_RV_PCellID2 0x00000005\r
+#define WDT_RV_PeriphID0 0x00000005\r
+#define WDT_RV_PeriphID3 0x00000001\r
+#define WDT_RV_PeriphID5 0x00000000\r
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register\r
-#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+#define WDT_RV_CTL 0x00000000 // Control register\r
+#define WDT_RV_PeriphID4 0x00000000\r
+#define WDT_RV_PeriphID6 0x00000000\r
+#define WDT_RV_PeriphID7 0x00000000\r
#define WDT_RV_LOCK 0x00000000 // Lock register\r
-#define WDT_RV_PeriphID4 0x00000000 //\r
-#define WDT_RV_PeriphID5 0x00000000 //\r
-#define WDT_RV_PeriphID6 0x00000000 //\r
-#define WDT_RV_PeriphID7 0x00000000 //\r
-#define WDT_RV_PeriphID0 0x00000005 //\r
-#define WDT_RV_PeriphID1 0x00000018 //\r
-#define WDT_RV_PeriphID2 0x00000018 //\r
-#define WDT_RV_PeriphID3 0x00000001 //\r
-#define WDT_RV_PCellID0 0x0000000D //\r
-#define WDT_RV_PCellID1 0x000000F0 //\r
-#define WDT_RV_PCellID2 0x00000005 //\r
-#define WDT_RV_PCellID3 0x000000B1 //\r
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register\r
+\r
+#endif\r
\r
#endif // __HW_WATCHDOG_H__\r
//\r
// i2c.h - Prototypes for the I2C Driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __I2C_H__\r
#define __I2C_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#define I2C_SLAVE_ACT_NONE 0\r
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data\r
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data\r
+#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte\r
\r
//*****************************************************************************\r
//\r
I2CMasterInitExpClk(a, SysCtlClockGet(), b)\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __INTERRUPT_H__\r
#define __INTERRUPT_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Macro to generate an interrupt priority mask based on the number of bits\r
+// of priority supported by the hardware.\r
+//\r
+//*****************************************************************************\r
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)\r
+\r
//*****************************************************************************\r
//\r
// Prototypes for the APIs.\r
//\r
//*****************************************************************************\r
-extern void IntMasterEnable(void);\r
-extern void IntMasterDisable(void);\r
+extern tBoolean IntMasterEnable(void);\r
+extern tBoolean IntMasterDisable(void);\r
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
extern void IntUnregister(unsigned long ulInterrupt);\r
extern void IntPriorityGroupingSet(unsigned long ulBits);\r
extern void IntEnable(unsigned long ulInterrupt);\r
extern void IntDisable(unsigned long ulInterrupt);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// mpu.h - Defines and Macros for the memory protection unit.\r
+//\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __MPU_H__\r
+#define __MPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags that can be passed to MPUEnable..\r
+//\r
+//*****************************************************************************\r
+#define MPU_CONFIG_PRIV_DEFAULT 4\r
+#define MPU_CONFIG_HARDFLT_NMI 2\r
+#define MPU_CONFIG_NONE 0\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags for the region size to be passed to MPURegionSet.\r
+//\r
+//*****************************************************************************\r
+#define MPU_RGN_SIZE_32B (4 << 1)\r
+#define MPU_RGN_SIZE_64B (5 << 1)\r
+#define MPU_RGN_SIZE_128B (6 << 1)\r
+#define MPU_RGN_SIZE_256B (7 << 1)\r
+#define MPU_RGN_SIZE_512B (8 << 1)\r
+\r
+#define MPU_RGN_SIZE_1K (9 << 1)\r
+#define MPU_RGN_SIZE_2K (10 << 1)\r
+#define MPU_RGN_SIZE_4K (11 << 1)\r
+#define MPU_RGN_SIZE_8K (12 << 1)\r
+#define MPU_RGN_SIZE_16K (13 << 1)\r
+#define MPU_RGN_SIZE_32K (14 << 1)\r
+#define MPU_RGN_SIZE_64K (15 << 1)\r
+#define MPU_RGN_SIZE_128K (16 << 1)\r
+#define MPU_RGN_SIZE_256K (17 << 1)\r
+#define MPU_RGN_SIZE_512K (18 << 1)\r
+\r
+#define MPU_RGN_SIZE_1M (19 << 1)\r
+#define MPU_RGN_SIZE_2M (20 << 1)\r
+#define MPU_RGN_SIZE_4M (21 << 1)\r
+#define MPU_RGN_SIZE_8M (22 << 1)\r
+#define MPU_RGN_SIZE_16M (23 << 1)\r
+#define MPU_RGN_SIZE_32M (24 << 1)\r
+#define MPU_RGN_SIZE_64M (25 << 1)\r
+#define MPU_RGN_SIZE_128M (26 << 1)\r
+#define MPU_RGN_SIZE_256M (27 << 1)\r
+#define MPU_RGN_SIZE_512M (28 << 1)\r
+\r
+#define MPU_RGN_SIZE_1G (29 << 1)\r
+#define MPU_RGN_SIZE_2G (30 << 1)\r
+#define MPU_RGN_SIZE_4G (31 << 1)\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags for the permissions to be passed to MPURegionSet.\r
+//\r
+//*****************************************************************************\r
+#define MPU_RGN_PERM_EXEC 0x00000000\r
+#define MPU_RGN_PERM_NOEXEC 0x10000000\r
+#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000\r
+#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000\r
+#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000\r
+#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000\r
+#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000\r
+#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags for the sub-region to be passed to MPURegionSet.\r
+//\r
+//*****************************************************************************\r
+#define MPU_SUB_RGN_DISABLE_0 0x00000100\r
+#define MPU_SUB_RGN_DISABLE_1 0x00000200\r
+#define MPU_SUB_RGN_DISABLE_2 0x00000400\r
+#define MPU_SUB_RGN_DISABLE_3 0x00000800\r
+#define MPU_SUB_RGN_DISABLE_4 0x00001000\r
+#define MPU_SUB_RGN_DISABLE_5 0x00002000\r
+#define MPU_SUB_RGN_DISABLE_6 0x00004000\r
+#define MPU_SUB_RGN_DISABLE_7 0x00008000\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags to enable or disable a region, to be passed to MPURegionSet.\r
+//\r
+//*****************************************************************************\r
+#define MPU_RGN_ENABLE 1\r
+#define MPU_RGN_DISABLE 0\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void MPUEnable(unsigned long ulMPUConfig);\r
+extern void MPUDisable(void);\r
+extern unsigned long MPURegionCountGet(void);\r
+extern void MPURegionEnable(unsigned long ulRegion);\r
+extern void MPURegionDisable(unsigned long ulRegion);\r
+extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,\r
+ unsigned long ulFlags);\r
+extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,\r
+ unsigned long *pulFlags);\r
+extern void MPUIntRegister(void (*pfnHandler)(void));\r
+extern void MPUIntUnregister(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __MPU_H__\r
//\r
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __PWM_H__\r
#define __PWM_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates\r
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode\r
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode\r
+#define PWM_GEN_MODE_FAULT_LATCHED \\r
+ 0x00040000 // Fault is latched\r
+#define PWM_GEN_MODE_FAULT_UNLATCHED \\r
+ 0x00000000 // Fault is not latched\r
+#define PWM_GEN_MODE_FAULT_MINPER \\r
+ 0x00020000 // Enable min fault period\r
+#define PWM_GEN_MODE_FAULT_NO_MINPER \\r
+ 0x00000000 // Disable min fault period\r
+#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support\r
+#define PWM_GEN_MODE_FAULT_LEGACY \\r
+ 0x00000000 // Disable extended fault support\r
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur\r
+ // immediately\r
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \\r
+ 0x0000A800 // Deadband updates locally\r
+ // synchronized\r
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \\r
+ 0x0000FC00 // Deadband updates globally\r
+ // synchronized\r
+#define PWM_GEN_MODE_GEN_NO_SYNC \\r
+ 0x00000000 // Generator mode updates occur\r
+ // immediately\r
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \\r
+ 0x00000280 // Generator mode updates locally\r
+ // synchronized\r
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \\r
+ 0x000003C0 // Generator mode updates globally\r
+ // synchronized\r
\r
//*****************************************************************************\r
//\r
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt\r
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt\r
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt\r
+#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt\r
+#ifndef DEPRECATED\r
#define PWM_INT_FAULT 0x00010000 // Fault interrupt\r
+#endif\r
+#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt\r
+#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt\r
+#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt\r
+#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt\r
+#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask\r
\r
//*****************************************************************************\r
//\r
#define PWM_GEN_0 0x00000040 // Offset address of Gen0\r
#define PWM_GEN_1 0x00000080 // Offset address of Gen1\r
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2\r
+#define PWM_GEN_3 0x00000100 // Offset address of Gen3\r
\r
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0\r
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1\r
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2\r
+#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3\r
+\r
+#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range\r
+#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range\r
+#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range\r
+#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range\r
\r
//*****************************************************************************\r
//\r
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3\r
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4\r
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5\r
+#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6\r
+#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7\r
\r
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0\r
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1\r
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3\r
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4\r
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5\r
+#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6\r
+#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify each of the possible fault trigger conditions in\r
+// PWM_FAULT_GROUP_0\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_GROUP_0 0\r
+\r
+#define PWM_FAULT_FAULT0 0x00000001\r
+#define PWM_FAULT_FAULT1 0x00000002\r
+#define PWM_FAULT_FAULT2 0x00000004\r
+#define PWM_FAULT_FAULT3 0x00000008\r
+#define PWM_FAULT_ACMP0 0x00010000\r
+#define PWM_FAULT_ACMP1 0x00020000\r
+#define PWM_FAULT_ACMP2 0x00040000\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the sense of each of the external FAULTn signals\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT0_SENSE_HIGH 0x00000000\r
+#define PWM_FAULT0_SENSE_LOW 0x00000001\r
+#define PWM_FAULT1_SENSE_HIGH 0x00000000\r
+#define PWM_FAULT1_SENSE_LOW 0x00000002\r
+#define PWM_FAULT2_SENSE_HIGH 0x00000000\r
+#define PWM_FAULT2_SENSE_LOW 0x00000004\r
+#define PWM_FAULT3_SENSE_HIGH 0x00000000\r
+#define PWM_FAULT3_SENSE_LOW 0x00000008\r
\r
//*****************************************************************************\r
//\r
tBoolean bEnable);\r
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
tBoolean bInvert);\r
+extern void PWMOutputFaultLevel(unsigned long ulBase,\r
+ unsigned long ulPWMOutBits,\r
+ tBoolean bDriveHigh);\r
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
- tBoolean bFaultKill);\r
+ tBoolean bFaultSuppress);\r
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
void (*pfnIntHandler)(void));\r
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
extern void PWMFaultIntClear(unsigned long ulBase);\r
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void PWMFaultIntClearExt(unsigned long ulBase,\r
+ unsigned long ulFaultInts);\r
+extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulMinFaultPeriod,\r
+ unsigned long ulFaultSenses);\r
+extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulGroup,\r
+ unsigned long ulFaultTriggers);\r
+extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,\r
+ unsigned long ulGen,\r
+ unsigned long ulGroup);\r
+extern unsigned long PWMGenFaultStatus(unsigned long ulBase,\r
+ unsigned long ulGen,\r
+ unsigned long ulGroup);\r
+extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,\r
+ unsigned long ulGroup,\r
+ unsigned long ulFaultTriggers);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// qei.h - Prototypes for the Quadrature Encoder Driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __QEI_H__\r
#define __QEI_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
--- /dev/null
+//*****************************************************************************\r
+//\r
+// rom.h - Macros to facilitate calling functions in the ROM.\r
+//\r
+// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved.\r
+// \r
+// Software License Agreement\r
+// \r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's microcontroller products.\r
+// \r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
+// \r
+// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+// \r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ROM_H__\r
+#define __ROM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Pointers to the main API tables.\r
+//\r
+//*****************************************************************************\r
+#define ROM_APITABLE ((unsigned long *)0x01000010)\r
+#define ROM_VERSION (ROM_APITABLE[0])\r
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))\r
+#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2]))\r
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3]))\r
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4]))\r
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5]))\r
+#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6]))\r
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7]))\r
+#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8]))\r
+#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9]))\r
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10]))\r
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11]))\r
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12]))\r
+#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13]))\r
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14]))\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the ADC API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceDataGet \\r
+ ((long (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum, \\r
+ unsigned long *pulBuffer))ROM_ADCTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum, \\r
+ tBoolean bMasked))ROM_ADCTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum, \\r
+ unsigned long ulTrigger, \\r
+ unsigned long ulPriority))ROM_ADCTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceStepConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum, \\r
+ unsigned long ulStep, \\r
+ unsigned long ulConfig))ROM_ADCTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceOverflow \\r
+ ((long (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceOverflowClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceUnderflow \\r
+ ((long (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCSequenceUnderflowClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCProcessorTrigger \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSequenceNum))ROM_ADCTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ADCHardwareOversampleConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulFactor))ROM_ADCTABLE[14])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the Comparator API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulComp))ROM_COMPARATORTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulComp, \\r
+ unsigned long ulConfig))ROM_COMPARATORTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorRefSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulRef))ROM_COMPARATORTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorValueGet \\r
+ ((tBoolean (*)(unsigned long ulBase, \\r
+ unsigned long ulComp))ROM_COMPARATORTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulComp))ROM_COMPARATORTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulComp))ROM_COMPARATORTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_ComparatorIntStatus \\r
+ ((tBoolean (*)(unsigned long ulBase, \\r
+ unsigned long ulComp, \\r
+ tBoolean bMasked))ROM_COMPARATORTABLE[6])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the Flash API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashProgram \\r
+ ((long (*)(unsigned long *pulData, \\r
+ unsigned long ulAddress, \\r
+ unsigned long ulCount))ROM_FLASHTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashUsecGet \\r
+ ((unsigned long (*)(void))ROM_FLASHTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashUsecSet \\r
+ ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashErase \\r
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashProtectGet \\r
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashProtectSet \\r
+ ((long (*)(unsigned long ulAddress, \\r
+ tFlashProtection eProtect))ROM_FLASHTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashProtectSave \\r
+ ((long (*)(void))ROM_FLASHTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashUserGet \\r
+ ((long (*)(unsigned long *pulUser0, \\r
+ unsigned long *pulUser1))ROM_FLASHTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashUserSet \\r
+ ((long (*)(unsigned long ulUser0, \\r
+ unsigned long ulUser1))ROM_FLASHTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashUserSave \\r
+ ((long (*)(void))ROM_FLASHTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashIntEnable \\r
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashIntDisable \\r
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashIntGetStatus \\r
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_FlashIntClear \\r
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the GPIO API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinWrite \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins, \\r
+ unsigned char ucVal))ROM_GPIOTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIODirModeSet \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins, \\r
+ unsigned long ulPinIO))ROM_GPIOTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIODirModeGet \\r
+ ((unsigned long (*)(unsigned long ulPort, \\r
+ unsigned char ucPin))ROM_GPIOTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOIntTypeSet \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins, \\r
+ unsigned long ulIntType))ROM_GPIOTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOIntTypeGet \\r
+ ((unsigned long (*)(unsigned long ulPort, \\r
+ unsigned char ucPin))ROM_GPIOTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPadConfigSet \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins, \\r
+ unsigned long ulStrength, \\r
+ unsigned long ulPadType))ROM_GPIOTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPadConfigGet \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPin, \\r
+ unsigned long *pulStrength, \\r
+ unsigned long *pulPadType))ROM_GPIOTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinIntEnable \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinIntDisable \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinIntStatus \\r
+ ((long (*)(unsigned long ulPort, \\r
+ tBoolean bMasked))ROM_GPIOTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinIntClear \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinRead \\r
+ ((long (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeCAN \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeComparator \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeGPIOInput \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeGPIOOutput \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeI2C \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypePWM \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeQEI \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeSSI \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeTimer \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeUART \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[21])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_GPIOPinTypeGPIOOutputOD \\r
+ ((void (*)(unsigned long ulPort, \\r
+ unsigned char ucPins))ROM_GPIOTABLE[22])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the I2C API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterDataPut \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned char ucData))ROM_I2CTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterInitExpClk \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulI2CClk, \\r
+ tBoolean bFast))ROM_I2CTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveInit \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned char ucSlaveAddr))ROM_I2CTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterIntEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveIntEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterIntDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveIntDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterIntStatus \\r
+ ((tBoolean (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_I2CTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveIntStatus \\r
+ ((tBoolean (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_I2CTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterIntClear \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveIntClear \\r
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterSlaveAddrSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned char ucSlaveAddr, \\r
+ tBoolean bReceive))ROM_I2CTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterBusy \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterBusBusy \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterControl \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulCmd))ROM_I2CTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterErr \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CMasterDataGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveStatus \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveDataPut \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned char ucData))ROM_I2CTABLE[22])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_I2CSlaveDataGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UpdateI2C \\r
+ ((void (*)(void))ROM_I2CTABLE[24])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the Interrupt API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntEnable \\r
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntDisable \\r
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntPriorityGroupingSet \\r
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntPriorityGroupingGet \\r
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntPrioritySet \\r
+ ((void (*)(unsigned long ulInterrupt, \\r
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_IntPriorityGet \\r
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the PWM API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMPulseWidthSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPWMOut, \\r
+ unsigned long ulWidth))ROM_PWMTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned long ulConfig))ROM_PWMTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenPeriodSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned long ulPeriod))ROM_PWMTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenPeriodGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulGen))ROM_PWMTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen))ROM_PWMTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen))ROM_PWMTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMPulseWidthGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulPWMOut))ROM_PWMTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMDeadBandEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned short usRise, \\r
+ unsigned short usFall))ROM_PWMTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMDeadBandDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen))ROM_PWMTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMSyncUpdate \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGenBits))ROM_PWMTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMSyncTimeBase \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGenBits))ROM_PWMTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMOutputState \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPWMOutBits, \\r
+ tBoolean bEnable))ROM_PWMTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMOutputInvert \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPWMOutBits, \\r
+ tBoolean bInvert))ROM_PWMTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMOutputFault \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPWMOutBits, \\r
+ tBoolean bFaultSuppress))ROM_PWMTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenIntTrigEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned long ulIntTrig))ROM_PWMTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenIntTrigDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned long ulIntTrig))ROM_PWMTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ tBoolean bMasked))ROM_PWMTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMGenIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGen, \\r
+ unsigned long ulInts))ROM_PWMTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGenFault))ROM_PWMTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulGenFault))ROM_PWMTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMFaultIntClear \\r
+ ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_PWMIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_PWMTABLE[21])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the QEI API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIPositionGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulConfig, \\r
+ unsigned long ulMaxPosition))ROM_QEITABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIPositionSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPosition))ROM_QEITABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIDirectionGet \\r
+ ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIErrorGet \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIVelocityEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIVelocityDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIVelocityConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulPreDiv, \\r
+ unsigned long ulPeriod))ROM_QEITABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIVelocityGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_QEITABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_QEITABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_QEITABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_QEIIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_QEITABLE[14])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the SSI API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIDataPut \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulData))ROM_SSITABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIConfigSetExpClk \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulSSIClk, \\r
+ unsigned long ulProtocol, \\r
+ unsigned long ulMode, \\r
+ unsigned long ulBitRate, \\r
+ unsigned long ulDataWidth))ROM_SSITABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_SSITABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_SSITABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_SSITABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_SSITABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIDataPutNonBlocking \\r
+ ((long (*)(unsigned long ulBase, \\r
+ unsigned long ulData))ROM_SSITABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIDataGet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long *pulData))ROM_SSITABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SSIDataGetNonBlocking \\r
+ ((long (*)(unsigned long ulBase, \\r
+ unsigned long *pulData))ROM_SSITABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UpdateSSI \\r
+ ((void (*)(void))ROM_SSITABLE[11])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the SysCtl API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlSleep \\r
+ ((void (*)(void))ROM_SYSCTLTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlSRAMSizeGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlFlashSizeGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPinPresent \\r
+ ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralPresent \\r
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralReset \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralEnable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralDisable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralSleepEnable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralSleepDisable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralDeepSleepEnable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralDeepSleepDisable \\r
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPeripheralClockGating \\r
+ ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlIntEnable \\r
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlIntDisable \\r
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlIntClear \\r
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlIntStatus \\r
+ ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlLDOSet \\r
+ ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlLDOGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlReset \\r
+ ((void (*)(void))ROM_SYSCTLTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlDeepSleep \\r
+ ((void (*)(void))ROM_SYSCTLTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlResetCauseGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlResetCauseClear \\r
+ ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlClockSet \\r
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlClockGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPWMClockSet \\r
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlPWMClockGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlADCSpeedSet \\r
+ ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlADCSpeedGet \\r
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlGPIOAHBEnable \\r
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysCtlGPIOAHBDisable \\r
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the SysTick API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickValueGet \\r
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickEnable \\r
+ ((void (*)(void))ROM_SYSTICKTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickDisable \\r
+ ((void (*)(void))ROM_SYSTICKTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickIntEnable \\r
+ ((void (*)(void))ROM_SYSTICKTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickIntDisable \\r
+ ((void (*)(void))ROM_SYSTICKTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickPeriodSet \\r
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_SysTickPeriodGet \\r
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the Timer API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_TIMERTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerConfigure \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulConfig))ROM_TIMERTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerControlLevel \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ tBoolean bInvert))ROM_TIMERTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerControlTrigger \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ tBoolean bEnable))ROM_TIMERTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerControlEvent \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ unsigned long ulEvent))ROM_TIMERTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerControlStall \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ tBoolean bStall))ROM_TIMERTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerRTCEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerRTCDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerPrescaleSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ unsigned long ulValue))ROM_TIMERTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerPrescaleGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerLoadSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ unsigned long ulValue))ROM_TIMERTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerLoadGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerValueGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerMatchSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer, \\r
+ unsigned long ulValue))ROM_TIMERTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerMatchGet \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ unsigned long ulTimer))ROM_TIMERTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_TIMERTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_TimerIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_TIMERTABLE[21])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the UART API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTCharPut \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned char ucData))ROM_UARTTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTParityModeSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulParity))ROM_UARTTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTParityModeGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTFIFOLevelSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulTxLevel, \\r
+ unsigned long ulRxLevel))ROM_UARTTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTFIFOLevelGet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long *pulTxLevel, \\r
+ unsigned long *pulRxLevel))ROM_UARTTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTConfigSetExpClk \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulUARTClk, \\r
+ unsigned long ulBaud, \\r
+ unsigned long ulConfig))ROM_UARTTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTConfigGetExpClk \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulUARTClk, \\r
+ unsigned long *pulBaud, \\r
+ unsigned long *pulConfig))ROM_UARTTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTEnableSIR \\r
+ ((void (*)(unsigned long ulBase, \\r
+ tBoolean bLowPower))ROM_UARTTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTDisableSIR \\r
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTCharsAvail \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTSpaceAvail \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTCharGetNonBlocking \\r
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTCharGet \\r
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTCharPutNonBlocking \\r
+ ((tBoolean (*)(unsigned long ulBase, \\r
+ unsigned char ucData))ROM_UARTTABLE[15])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTBreakCtl \\r
+ ((void (*)(unsigned long ulBase, \\r
+ tBoolean bBreakState))ROM_UARTTABLE[16])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTIntEnable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_UARTTABLE[17])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTIntDisable \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_UARTTABLE[18])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_UARTTABLE[19])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UARTIntClear \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_UpdateUART \\r
+ ((void (*)(void))ROM_UARTTABLE[21])\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for calling ROM functions in the Watchdog API.\r
+//\r
+//*****************************************************************************\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogIntClear \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogRunning \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogResetEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogResetDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogLock \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogUnlock \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogLockState \\r
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogReloadSet \\r
+ ((void (*)(unsigned long ulBase, \\r
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogReloadGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogValueGet \\r
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogIntEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogIntStatus \\r
+ ((unsigned long (*)(unsigned long ulBase, \\r
+ tBoolean bMasked))ROM_WATCHDOGTABLE[12])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogStallEnable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])\r
+#endif\r
+#if defined(TARGET_IS_DUSTDEVIL_RA0)\r
+#define ROM_WatchdogStallDisable \\r
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])\r
+#endif\r
+\r
+#endif // __ROM_H__\r
//\r
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __SSI_H__\r
#define __SSI_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
#define SSI_MODE_SLAVE 0x00000001 // SSI slave\r
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled\r
\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().\r
+//\r
+//*****************************************************************************\r
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit\r
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive\r
+\r
//*****************************************************************************\r
//\r
// Prototypes for the APIs.\r
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
extern void SSIIntUnregister(unsigned long ulBase);\r
+extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);\r
+extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);\r
\r
//*****************************************************************************\r
//\r
SSIDataPutNonBlocking(a, b)\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// sysctl.h - Prototypes for the system control driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __SYSCTL_H__\r
#define __SYSCTL_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
//\r
//*****************************************************************************\r
-#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
-#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
-#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog\r
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module\r
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC\r
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM\r
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0\r
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1\r
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2\r
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0\r
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1\r
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2\r
+#ifndef DEPRECATED\r
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI\r
+#endif\r
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0\r
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1\r
+#ifndef DEPRECATED\r
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI\r
+#endif\r
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0\r
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1\r
+#ifndef DEPRECATED\r
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C\r
+#endif\r
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0\r
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1\r
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0\r
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F\r
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G\r
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H\r
+#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA\r
+#define SYSCTL_PERIPH_USB0 0x20100001 // USB0\r
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH\r
-#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
-#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588\r
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL\r
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor\r
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU\r
\r
//*****************************************************************************\r
//\r
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin\r
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin\r
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin\r
+#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin\r
+#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin\r
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin\r
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin\r
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin\r
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14\r
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15\r
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16\r
+#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17\r
+#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18\r
+#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19\r
+#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20\r
+#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21\r
+#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22\r
+#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23\r
+#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24\r
+#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25\r
+#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26\r
+#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27\r
+#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28\r
+#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29\r
+#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30\r
+#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31\r
+#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32\r
+#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33\r
+#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34\r
+#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35\r
+#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36\r
+#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37\r
+#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38\r
+#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39\r
+#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40\r
+#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41\r
+#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42\r
+#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43\r
+#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44\r
+#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45\r
+#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46\r
+#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47\r
+#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48\r
+#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49\r
+#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50\r
+#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51\r
+#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52\r
+#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53\r
+#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54\r
+#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55\r
+#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56\r
+#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57\r
+#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58\r
+#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59\r
+#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60\r
+#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61\r
+#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62\r
+#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63\r
+#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64\r
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock\r
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock\r
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz\r
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz\r
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz\r
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz\r
+#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz\r
+#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz\r
+#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz\r
+#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz\r
+#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz\r
+#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz\r
+#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz\r
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc\r
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc\r
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4\r
+#define SYSCTL_OSC_INT30 0x80000030 // Oscillator source is int. 30 KHz\r
+#define SYSCTL_OSC_EXT32 0x80000038 // Oscillator source is ext. 32 KHz\r
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator\r
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator\r
\r
extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
unsigned long ulDelay);\r
+extern void SysCtlDelay(unsigned long ulCount);\r
extern void SysCtlClockSet(unsigned long ulConfig);\r
extern unsigned long SysCtlClockGet(void);\r
extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
extern void SysCtlClkVerificationClear(void);\r
+extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);\r
+extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);\r
+extern void SysCtlUSBPLLEnable(void);\r
+extern void SysCtlUSBPLLDisable(void);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// systick.h - Prototypes for the SysTick driver.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __SYSTICK_H__\r
#define __SYSTICK_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
extern unsigned long SysTickPeriodGet(void);\r
extern unsigned long SysTickValueGet(void);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// timer.h - Prototypes for the timer module\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __TIMER_H__\r
#define __TIMER_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
unsigned long ulValue);\r
extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
unsigned long ulTimer);\r
-extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
- unsigned long ulValue);\r
-extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
- unsigned long ulTimer);\r
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
unsigned long ulValue);\r
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+//*****************************************************************************\r
+//\r
+// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used\r
+// instead to return the timer to its reset state.\r
+//\r
+//*****************************************************************************\r
+#ifndef DEPRECATED\r
extern void TimerQuiesce(unsigned long ulBase);\r
+#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// uart.h - Defines and Macros for the UART.\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __UART_H__\r
#define __UART_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
// UARTParityModeGet.\r
//\r
//*****************************************************************************\r
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length\r
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data\r
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data\r
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data\r
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data\r
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits\r
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit\r
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits\r
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity\r
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity\r
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity\r
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity\r
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full\r
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full\r
\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().\r
+//\r
+//*****************************************************************************\r
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error\r
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit\r
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive\r
+\r
//*****************************************************************************\r
//\r
// API Function prototypes\r
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);\r
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);\r
\r
//*****************************************************************************\r
//\r
UARTCharPutNonBlocking(a, b)\r
#endif\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
//\r
// watchdog.h - Prototypes for the Watchdog Timer API\r
//\r
-// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.\r
+// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.\r
// \r
// Software License Agreement\r
// \r
// exclusively on LMI's microcontroller products.\r
// \r
// The software is owned by LMI and/or its suppliers, and is protected under\r
-// applicable copyright laws. All rights are reserved. Any use in violation\r
-// of the foregoing restrictions may subject the user to criminal sanctions\r
-// under applicable laws, as well as to civil liability for the breach of the\r
-// terms and conditions of this license.\r
+// applicable copyright laws. All rights are reserved. You may not combine\r
+// this software with "viral" open-source software in order to form a larger\r
+// program. Any use in violation of the foregoing restrictions may subject\r
+// the user to criminal sanctions under applicable laws, as well as to civil\r
+// liability for the breach of the terms and conditions of this license.\r
// \r
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
// \r
-// This is part of revision 1582 of the Stellaris Peripheral Driver Library.\r
+// This is part of revision 2523 of the Stellaris Peripheral Driver Library.\r
//\r
//*****************************************************************************\r
\r
#ifndef __WATCHDOG_H__\r
#define __WATCHDOG_H__\r
\r
+//*****************************************************************************\r
+//\r
+// If building with a C++ compiler, make all of the definitions in this header\r
+// have a C binding.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
extern "C"\r
{\r
extern void WatchdogStallEnable(unsigned long ulBase);\r
extern void WatchdogStallDisable(unsigned long ulBase);\r
\r
+//*****************************************************************************\r
+//\r
+// Mark the end of the C bindings section for C++ compilers.\r
+//\r
+//*****************************************************************************\r
#ifdef __cplusplus\r
}\r
#endif\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
/*\r
- FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
+ FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.\r
\r
This file is part of the FreeRTOS.org distribution.\r
\r
projects / freertos / commitdiff