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<projectStorage><?xml version="1.0" encoding="UTF-8"?> \r
<TargetConfig> \r
<Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/> \r
-<infoList vendor="NXP"><info chip="LPC1768" match_id="0x00013f37,0x26013F37" name="LPC1768" package="lpc17_lqfp100.xml"><chip><name>LPC1768</name> \r
+<infoList vendor="NXP"> \r
+<info chip="LPC1768" match_id="0x00013f37,0x26013F37" name="LPC1768" package="lpc17_lqfp100.xml"> \r
+<chip> \r
+<name>LPC1768</name> \r
<family>LPC17xx</family> \r
<vendor>NXP (formerly Philips)</vendor> \r
<reset board="None" core="Real" sys="Real"/> \r
<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/> \r
<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/> \r
<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> \r
-<peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> \r
+<peripheralInstance derived_from="SVD_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> \r
<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/> \r
<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/> \r
<peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/> \r
<peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/> \r
<peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/> \r
<peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/> \r
-<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> \r
-<peripheralInstance derived_from="LPC1xxx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> \r
-<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> \r
-<peripheralInstance derived_from="LPC1xxx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCAURT3&amp;0x1" id="UART3" location="0x4009C000"/> \r
+<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> \r
+<peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> \r
+<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> \r
+<peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/> \r
<peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/> \r
<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/> \r
<peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/> \r
<peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/> \r
<peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/> \r
<peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/> \r
+<peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/> \r
+<peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/> \r
+<memoryInstance derived_from="RAM" id="CANAccFilterRAM" location="0x40038000" size="0x800"/> \r
+<peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/> \r
+<peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/> \r
+<peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/> \r
+<peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/> \r
+<peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/> \r
</chip> \r
-<processor><name gcc_name="cortex-m3">Cortex-M3</name> \r
+<processor> \r
+<name gcc_name="cortex-m3">Cortex-M3</name> \r
<family>Cortex-M</family> \r
</processor> \r
<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> \r
*-----------------------------------------------------------*/\r
extern void vConfigureTimerForRunTimeStats( void );\r
#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
-#define portGET_RUN_TIME_COUNTER_VALUE() TIM0->TC\r
+#define portGET_RUN_TIME_COUNTER_VALUE() LPC_TIM0->TC\r
\r
\r
#endif /* FREERTOS_CONFIG_H */\r
static void Wait4DevInt(unsigned long dwIntr)\r
{\r
// wait for specific interrupt\r
- while ((USB->USBDevIntSt & dwIntr) != dwIntr);\r
+ while ((LPC_USB->USBDevIntSt & dwIntr) != dwIntr);\r
// clear the interrupt bits\r
- USB->USBDevIntClr = dwIntr;\r
+ LPC_USB->USBDevIntClr = dwIntr;\r
}\r
\r
\r
static void USBHwCmd(unsigned char bCmd)\r
{\r
// clear CDFULL/CCEMTY\r
- USB->USBDevIntClr = CDFULL | CCEMTY;\r
+ LPC_USB->USBDevIntClr = CDFULL | CCEMTY;\r
// write command code\r
- USB->USBCmdCode = 0x00000500 | (bCmd << 16);\r
+ LPC_USB->USBCmdCode = 0x00000500 | (bCmd << 16);\r
Wait4DevInt(CCEMTY);\r
}\r
\r
USBHwCmd(bCmd);\r
\r
// write command data\r
- USB->USBCmdCode = 0x00000100 | (bData << 16);\r
+ LPC_USB->USBCmdCode = 0x00000100 | (bData << 16);\r
Wait4DevInt(CCEMTY);\r
}\r
\r
USBHwCmd(bCmd);\r
\r
// get data\r
- USB->USBCmdCode = 0x00000200 | (bCmd << 16);\r
+ LPC_USB->USBCmdCode = 0x00000200 | (bCmd << 16);\r
Wait4DevInt(CDFULL);\r
- return USB->USBCmdData;\r
+ return LPC_USB->USBCmdData;\r
}\r
\r
\r
*/\r
static void USBHwEPRealize(int idx, unsigned short wMaxPSize)\r
{\r
- USB->USBReEP |= (1 << idx);\r
- USB->USBEpInd = idx;\r
- USB->USBMaxPSize = wMaxPSize;\r
+ LPC_USB->USBReEP |= (1 << idx);\r
+ LPC_USB->USBEpInd = idx;\r
+ LPC_USB->USBMaxPSize = wMaxPSize;\r
Wait4DevInt(EP_RLZED);\r
}\r
\r
_apfnEPIntHandlers[idx / 2] = pfnHandler;\r
\r
/* enable EP interrupt */\r
- USB->USBEpIntEn |= (1 << idx);\r
- USB->USBDevIntEn |= EP_SLOW;\r
+ LPC_USB->USBEpIntEn |= (1 << idx);\r
+ LPC_USB->USBDevIntEn |= EP_SLOW;\r
\r
DBG("Registered handler for EP 0x%x\n", bEP);\r
}\r
_pfnDevIntHandler = pfnHandler;\r
\r
// enable device interrupt\r
- USB->USBDevIntEn |= DEV_STAT;\r
+ LPC_USB->USBDevIntEn |= DEV_STAT;\r
\r
DBG("Registered handler for device status\n");\r
}\r
_pfnFrameHandler = pfnHandler;\r
\r
// enable device interrupt\r
- USB->USBDevIntEn |= FRAME;\r
+ LPC_USB->USBDevIntEn |= FRAME;\r
\r
DBG("Registered handler for frame\n");\r
}\r
idx = EP2IDX(bEP);\r
\r
// set write enable for specific endpoint\r
- USB->USBCtrl = WR_EN | ((bEP & 0xF) << 2);\r
+ LPC_USB->USBCtrl = WR_EN | ((bEP & 0xF) << 2);\r
\r
// set packet length\r
- USB->USBTxPLen = iLen;\r
+ LPC_USB->USBTxPLen = iLen;\r
\r
// write data\r
- while (USB->USBCtrl & WR_EN) {\r
- USB->USBTxData = (pbBuf[3] << 24) | (pbBuf[2] << 16) | (pbBuf[1] << 8) | pbBuf[0];\r
+ while (LPC_USB->USBCtrl & WR_EN) {\r
+ LPC_USB->USBTxData = (pbBuf[3] << 24) | (pbBuf[2] << 16) | (pbBuf[1] << 8) | pbBuf[0];\r
pbBuf += 4;\r
}\r
\r
idx = EP2IDX(bEP);\r
\r
// set read enable bit for specific endpoint\r
- USB->USBCtrl = RD_EN | ((bEP & 0xF) << 2);\r
+ LPC_USB->USBCtrl = RD_EN | ((bEP & 0xF) << 2);\r
\r
// wait for PKT_RDY\r
do {\r
- dwLen = USB->USBRxPLen;\r
+ dwLen = LPC_USB->USBRxPLen;\r
} while ((dwLen & PKT_RDY) == 0);\r
\r
// packet valid?\r
dwData = 0;\r
for (i = 0; i < dwLen; i++) {\r
if ((i % 4) == 0) {\r
- dwData = USB->USBRxData;\r
+ dwData = LPC_USB->USBRxData;\r
}\r
if ((pbBuf != NULL) && (i < iMaxLen)) {\r
pbBuf[i] = dwData & 0xFF;\r
}\r
\r
// make sure RD_EN is clear\r
- USB->USBCtrl = 0;\r
+ LPC_USB->USBCtrl = 0;\r
\r
// select endpoint and clear buffer\r
USBHwCmd(CMD_EP_SELECT | idx);\r
unsigned short wFrame;\r
\r
// handle device interrupts\r
- dwStatus = USB->USBDevIntSt;\r
+ dwStatus = LPC_USB->USBDevIntSt;\r
\r
// frame interrupt\r
if (dwStatus & FRAME) {\r
// clear int\r
- USB->USBDevIntClr = FRAME;\r
+ LPC_USB->USBDevIntClr = FRAME;\r
// call handler\r
if (_pfnFrameHandler != NULL) {\r
wFrame = USBHwCmdRead(CMD_DEV_READ_CUR_FRAME_NR);\r
This prevents corrupted device status reads, see\r
LPC2148 User manual revision 2, 25 july 2006.\r
*/\r
- USB->USBDevIntClr = DEV_STAT;\r
+ LPC_USB->USBDevIntClr = DEV_STAT;\r
bDevStat = USBHwCmdRead(CMD_DEV_STATUS);\r
if (bDevStat & (CON_CH | SUS_CH | RST)) {\r
// convert device status into something HW independent\r
// endpoint interrupt\r
if (dwStatus & EP_SLOW) {\r
// clear EP_SLOW\r
- USB->USBDevIntClr = EP_SLOW;\r
+ LPC_USB->USBDevIntClr = EP_SLOW;\r
// check all endpoints\r
for (i = 0; i < 32; i++) {\r
dwIntBit = (1 << i);\r
- if (USB->USBEpIntSt & dwIntBit) {\r
+ if (LPC_USB->USBEpIntSt & dwIntBit) {\r
// clear int (and retrieve status)\r
- USB->USBEpIntClr = dwIntBit;\r
+ LPC_USB->USBEpIntClr = dwIntBit;\r
Wait4DevInt(CDFULL);\r
- bEPStat = USB->USBCmdData;\r
+ bEPStat = LPC_USB->USBCmdData;\r
// convert EP pipe stat into something HW independent\r
bStat = ((bEPStat & EPSTAT_FE) ? EP_STATUS_DATA : 0) |\r
((bEPStat & EPSTAT_ST) ? EP_STATUS_STALLED : 0) |\r
BOOL USBHwInit(void)\r
{\r
// P2.9 -> USB_CONNECT\r
- PINCON->PINSEL4 &= ~0x000C0000;\r
- PINCON->PINSEL4 |= 0x00040000;\r
+ LPC_PINCON->PINSEL4 &= ~0x000C0000;\r
+ LPC_PINCON->PINSEL4 |= 0x00040000;\r
\r
// P1.18 -> USB_UP_LED\r
// P1.30 -> VBUS\r
- PINCON->PINSEL3 &= ~0x30000030;\r
- PINCON->PINSEL3 |= 0x20000010;\r
+ LPC_PINCON->PINSEL3 &= ~0x30000030;\r
+ LPC_PINCON->PINSEL3 |= 0x20000010;\r
\r
// P0.29 -> USB_D+\r
// P0.30 -> USB_D-\r
- PINCON->PINSEL1 &= ~0x3C000000;\r
- PINCON->PINSEL1 |= 0x14000000; \r
+ LPC_PINCON->PINSEL1 &= ~0x3C000000;\r
+ LPC_PINCON->PINSEL1 |= 0x14000000;\r
\r
// enable PUSB\r
- SC->PCONP |= (1 << 31);\r
+ LPC_SC->PCONP |= (1 << 31);\r
\r
- USB->OTGClkCtrl = 0x12; /* Dev clock, AHB clock enable */\r
- while ((USB->OTGClkSt & 0x12) != 0x12);\r
+ LPC_USB->OTGClkCtrl = 0x12; /* Dev clock, AHB clock enable */\r
+ while ((LPC_USB->OTGClkSt & 0x12) != 0x12);\r
\r
// disable/clear all interrupts for now\r
- USB->USBDevIntEn = 0;\r
- USB->USBDevIntClr = 0xFFFFFFFF;\r
- USB->USBDevIntPri = 0;\r
+ LPC_USB->USBDevIntEn = 0;\r
+ LPC_USB->USBDevIntClr = 0xFFFFFFFF;\r
+ LPC_USB->USBDevIntPri = 0;\r
\r
- USB->USBEpIntEn = 0;\r
- USB->USBEpIntClr = 0xFFFFFFFF;\r
- USB->USBEpIntPri = 0;\r
+ LPC_USB->USBEpIntEn = 0;\r
+ LPC_USB->USBEpIntClr = 0xFFFFFFFF;\r
+ LPC_USB->USBEpIntPri = 0;\r
\r
// by default, only ACKs generate interrupts\r
USBHwNakIntEnable(0);\r
void vParTestInitialise( void )\r
{\r
/* LEDs on port 1. */\r
- GPIO1->FIODIR = partstFIO1_BITS;\r
+ LPC_GPIO1->FIODIR = partstFIO1_BITS;\r
\r
/* Start will all LEDs off. */\r
- GPIO1->FIOCLR = partstFIO1_BITS;\r
+ LPC_GPIO1->FIOCLR = partstFIO1_BITS;\r
}\r
/*-----------------------------------------------------------*/\r
\r
/* Set of clear the output. */\r
if( xValue )\r
{\r
- GPIO1->FIOCLR = ulLEDs[ uxLED ];\r
+ LPC_GPIO1->FIOCLR = ulLEDs[ uxLED ];\r
}\r
else\r
{\r
- GPIO1->FIOSET = ulLEDs[ uxLED ];\r
+ LPC_GPIO1->FIOSET = ulLEDs[ uxLED ];\r
}\r
}\r
}\r
{\r
if( uxLED < partstNUM_LEDS )\r
{\r
- if( GPIO1->FIOPIN & ulLEDs[ uxLED ] )\r
+ if( LPC_GPIO1->FIOPIN & ulLEDs[ uxLED ] )\r
{\r
- GPIO1->FIOCLR = ulLEDs[ uxLED ];\r
+ LPC_GPIO1->FIOCLR = ulLEDs[ uxLED ];\r
}\r
else\r
{\r
- GPIO1->FIOSET = ulLEDs[ uxLED ];\r
+ LPC_GPIO1->FIOSET = ulLEDs[ uxLED ];\r
}\r
}\r
}\r
{\r
if( uxLED < partstNUM_LEDS )\r
{\r
- return ( GPIO1->FIOPIN & ulLEDs[ uxLED ] );\r
+ return ( LPC_GPIO1->FIOPIN & ulLEDs[ uxLED ] );\r
}\r
else\r
{\r
// library.\r
//\r
//*****************************************************************************\r
-void Reset_Handler(void)\r
+void\r
ResetISR(void) {\r
unsigned long *pulSrc, *pulDest;\r
\r
without an error being reported. */\r
#define mainPASS_STATUS_MESSAGE "All tasks are executing without error."\r
\r
+/* Bit definitions. */\r
+#define PCONP_PCGPIO 0x00008000\r
+#define PLLFEED_FEED1 0x000000AA\r
+#define PLLFEED_FEED2 0x00000055\r
/*-----------------------------------------------------------*/\r
\r
/*\r
void prvSetupHardware( void )\r
{\r
/* Disable peripherals power. */\r
- SC->PCONP = 0;\r
+ LPC_SC->PCONP = 0;\r
\r
/* Enable GPIO power. */\r
- SC->PCONP = PCONP_PCGPIO;\r
+ LPC_SC->PCONP = PCONP_PCGPIO;\r
\r
/* Disable TPIU. */\r
- PINCON->PINSEL10 = 0;\r
+ LPC_PINCON->PINSEL10 = 0;\r
\r
- if ( SC->PLL0STAT & ( 1 << 25 ) )\r
+ if ( LPC_SC->PLL0STAT & ( 1 << 25 ) )\r
{\r
/* Enable PLL, disconnected. */\r
- SC->PLL0CON = 1; \r
- SC->PLL0FEED = PLLFEED_FEED1;\r
- SC->PLL0FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL0CON = 1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED2;\r
}\r
\r
/* Disable PLL, disconnected. */\r
- SC->PLL0CON = 0; \r
- SC->PLL0FEED = PLLFEED_FEED1;\r
- SC->PLL0FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL0CON = 0;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED2;\r
\r
/* Enable main OSC. */\r
- SC->SCS |= 0x20; \r
- while( !( SC->SCS & 0x40 ) );\r
+ LPC_SC->SCS |= 0x20;\r
+ while( !( LPC_SC->SCS & 0x40 ) );\r
\r
/* select main OSC, 12MHz, as the PLL clock source. */\r
- SC->CLKSRCSEL = 0x1; \r
+ LPC_SC->CLKSRCSEL = 0x1;\r
\r
- SC->PLL0CFG = 0x20031;\r
- SC->PLL0FEED = PLLFEED_FEED1;\r
- SC->PLL0FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL0CFG = 0x20031;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED2;\r
\r
/* Enable PLL, disconnected. */\r
- SC->PLL0CON = 1; \r
- SC->PLL0FEED = PLLFEED_FEED1;\r
- SC->PLL0FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL0CON = 1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED2;\r
\r
/* Set clock divider. */\r
- SC->CCLKCFG = 0x03;\r
+ LPC_SC->CCLKCFG = 0x03;\r
\r
/* Configure flash accelerator. */\r
- SC->FLASHCFG = 0x403a;\r
+ LPC_SC->FLASHCFG = 0x403a;\r
\r
/* Check lock bit status. */\r
- while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) ); \r
+ while( ( ( LPC_SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) );\r
\r
/* Enable and connect. */\r
- SC->PLL0CON = 3; \r
- SC->PLL0FEED = PLLFEED_FEED1;\r
- SC->PLL0FEED = PLLFEED_FEED2;\r
- while( ( ( SC->PLL0STAT & ( 1 << 25 ) ) == 0 ) ); \r
+ LPC_SC->PLL0CON = 3;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL0FEED = PLLFEED_FEED2;\r
+ while( ( ( LPC_SC->PLL0STAT & ( 1 << 25 ) ) == 0 ) );\r
\r
\r
\r
\r
/* Configure the clock for the USB. */\r
\r
- if( SC->PLL1STAT & ( 1 << 9 ) )\r
+ if( LPC_SC->PLL1STAT & ( 1 << 9 ) )\r
{\r
/* Enable PLL, disconnected. */\r
- SC->PLL1CON = 1; \r
- SC->PLL1FEED = PLLFEED_FEED1;\r
- SC->PLL1FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL1CON = 1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED2;\r
}\r
\r
/* Disable PLL, disconnected. */\r
- SC->PLL1CON = 0; \r
- SC->PLL1FEED = PLLFEED_FEED1;\r
- SC->PLL1FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL1CON = 0;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED2;\r
\r
- SC->PLL1CFG = 0x23;\r
- SC->PLL1FEED = PLLFEED_FEED1;\r
- SC->PLL1FEED = PLLFEED_FEED2;\r
+ LPC_SC->PLL1CFG = 0x23;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED2;\r
\r
/* Enable PLL, disconnected. */\r
- SC->PLL1CON = 1; \r
- SC->PLL1FEED = PLLFEED_FEED1;\r
- SC->PLL1FEED = PLLFEED_FEED2;\r
- while( ( ( SC->PLL1STAT & ( 1 << 10 ) ) == 0 ) );\r
+ LPC_SC->PLL1CON = 1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED2;\r
+ while( ( ( LPC_SC->PLL1STAT & ( 1 << 10 ) ) == 0 ) );\r
\r
/* Enable and connect. */\r
- SC->PLL1CON = 3; \r
- SC->PLL1FEED = PLLFEED_FEED1;\r
- SC->PLL1FEED = PLLFEED_FEED2;\r
- while( ( ( SC->PLL1STAT & ( 1 << 9 ) ) == 0 ) );\r
+ LPC_SC->PLL1CON = 3;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED1;\r
+ LPC_SC->PLL1FEED = PLLFEED_FEED2;\r
+ while( ( ( LPC_SC->PLL1STAT & ( 1 << 9 ) ) == 0 ) );\r
\r
/* Setup the peripheral bus to be the same as the PLL output (64 MHz). */\r
- SC->PCLKSEL0 = 0x05555555;\r
+ LPC_SC->PCLKSEL0 = 0x05555555;\r
\r
/* Configure the LEDs. */\r
vParTestInitialise();\r
to 1). */\r
\r
/* Power up and feed the timer. */\r
- SC->PCONP |= 0x02UL;\r
- SC->PCLKSEL0 = (SC->PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);\r
+ LPC_SC->PCONP |= 0x02UL;\r
+ LPC_SC->PCLKSEL0 = (LPC_SC->PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);\r
\r
/* Reset Timer 0 */\r
- TIM0->TCR = TCR_COUNT_RESET;\r
+ LPC_TIM0->TCR = TCR_COUNT_RESET;\r
\r
/* Just count up. */\r
- TIM0->CTCR = CTCR_CTM_TIMER;\r
+ LPC_TIM0->CTCR = CTCR_CTM_TIMER;\r
\r
/* Prescale to a frequency that is good enough to get a decent resolution,\r
but not too fast so as to overflow all the time. */\r
- TIM0->PR = ( configCPU_CLOCK_HZ / 10000UL ) - 1UL;\r
+ LPC_TIM0->PR = ( configCPU_CLOCK_HZ / 10000UL ) - 1UL;\r
\r
/* Start the counter. */\r
- TIM0->TCR = TCR_COUNT_ENABLE;\r
+ LPC_TIM0->TCR = TCR_COUNT_ENABLE;\r
}\r
/*-----------------------------------------------------------*/\r
\r
descriptor is then used to re-send in order to speed up the uIP Tx process. */\r
#define emacTX_DESC_INDEX ( 0 )\r
\r
+#define PCONP_PCENET 0x40000000\r
/*-----------------------------------------------------------*/\r
\r
/*\r
if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFF0UL ) ) == DP83848C_ID )\r
{\r
/* Set the Ethernet MAC Address registers */\r
- EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
- EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
- EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
+ LPC_EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
+ LPC_EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
+ LPC_EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
\r
/* Initialize Tx and Rx DMA Descriptors */\r
prvInitDescriptors();\r
\r
/* Receive broadcast and perfect match packets */\r
- EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+ LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
\r
/* Setup the PHY. */\r
prvConfigurePHY();\r
uip_buf = prvGetNextBuffer();\r
\r
/* Reset all interrupts */\r
- EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );\r
+ LPC_EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );\r
\r
/* Enable receive and transmit mode of MAC Ethernet core */\r
- EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
- EMAC->MAC1 |= MAC1_REC_EN;\r
+ LPC_EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+ LPC_EMAC->MAC1 |= MAC1_REC_EN;\r
}\r
\r
return lReturn;\r
}\r
\r
/* Set EMAC Receive Descriptor Registers. */\r
- EMAC->RxDescriptor = RX_DESC_BASE;\r
- EMAC->RxStatus = RX_STAT_BASE;\r
- EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;\r
+ LPC_EMAC->RxDescriptor = RX_DESC_BASE;\r
+ LPC_EMAC->RxStatus = RX_STAT_BASE;\r
+ LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;\r
\r
/* Rx Descriptors Point to 0 */\r
- EMAC->RxConsumeIndex = 0;\r
+ LPC_EMAC->RxConsumeIndex = 0;\r
\r
/* A buffer is not allocated to the Tx descriptors until they are actually\r
used. */\r
}\r
\r
/* Set EMAC Transmit Descriptor Registers. */\r
- EMAC->TxDescriptor = TX_DESC_BASE;\r
- EMAC->TxStatus = TX_STAT_BASE;\r
- EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;\r
+ LPC_EMAC->TxDescriptor = TX_DESC_BASE;\r
+ LPC_EMAC->TxStatus = TX_STAT_BASE;\r
+ LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;\r
\r
/* Tx Descriptors Point to 0 */\r
- EMAC->TxProduceIndex = 0;\r
+ LPC_EMAC->TxProduceIndex = 0;\r
}\r
/*-----------------------------------------------------------*/\r
\r
long x, lDummy;\r
\r
/* Enable P1 Ethernet Pins. */\r
- PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
- PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
+ LPC_PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
+ LPC_PINCON->PINSEL3 = ( LPC_PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
\r
/* Power Up the EMAC controller. */\r
- SC->PCONP |= PCONP_PCENET;\r
+ LPC_SC->PCONP |= PCONP_PCENET;\r
vTaskDelay( emacSHORT_DELAY );\r
\r
/* Reset all EMAC internal modules. */\r
- EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
- EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
+ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+ LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
\r
/* A short delay after reset. */\r
vTaskDelay( emacSHORT_DELAY );\r
\r
/* Initialize MAC control registers. */\r
- EMAC->MAC1 = MAC1_PASS_ALL;\r
- EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
- EMAC->MAXF = ETH_MAX_FLEN;\r
- EMAC->CLRT = CLRT_DEF;\r
- EMAC->IPGR = IPGR_DEF;\r
+ LPC_EMAC->MAC1 = MAC1_PASS_ALL;\r
+ LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+ LPC_EMAC->MAXF = ETH_MAX_FLEN;\r
+ LPC_EMAC->CLRT = CLRT_DEF;\r
+ LPC_EMAC->IPGR = IPGR_DEF;\r
\r
/* Enable Reduced MII interface. */\r
- EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;\r
+ LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;\r
\r
/* Reset Reduced MII Logic. */\r
- EMAC->SUPP = SUPP_RES_RMII;\r
+ LPC_EMAC->SUPP = SUPP_RES_RMII;\r
vTaskDelay( emacSHORT_DELAY );\r
- EMAC->SUPP = 0;\r
+ LPC_EMAC->SUPP = 0;\r
\r
/* Put the PHY in reset mode */\r
prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
{\r
/* Full duplex is enabled. */\r
- EMAC->MAC2 |= MAC2_FULL_DUP;\r
- EMAC->Command |= CR_FULL_DUP;\r
- EMAC->IPGT = IPGT_FULL_DUP;\r
+ LPC_EMAC->MAC2 |= MAC2_FULL_DUP;\r
+ LPC_EMAC->Command |= CR_FULL_DUP;\r
+ LPC_EMAC->IPGT = IPGT_FULL_DUP;\r
}\r
else\r
{\r
/* Half duplex mode. */\r
- EMAC->IPGT = IPGT_HALF_DUP;\r
+ LPC_EMAC->IPGT = IPGT_HALF_DUP;\r
}\r
\r
/* Configure 100MBit/10MBit mode. */\r
if( usLinkStatus & emac10BASE_T_MODE )\r
{\r
/* 10MBit mode. */\r
- EMAC->SUPP = 0;\r
+ LPC_EMAC->SUPP = 0;\r
}\r
else\r
{\r
/* 100MBit mode. */\r
- EMAC->SUPP = SUPP_SPEED;\r
+ LPC_EMAC->SUPP = SUPP_SPEED;\r
}\r
}\r
\r
unsigned long ulLen = 0;\r
long lIndex;\r
\r
- if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )\r
+ if( LPC_EMAC->RxProduceIndex != LPC_EMAC->RxConsumeIndex )\r
{\r
/* Mark the current buffer as free as uip_buf is going to be set to\r
the buffer that contains the received data. */\r
prvReturnBuffer( uip_buf );\r
\r
- ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;\r
- uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );\r
+ ulLen = ( RX_STAT_INFO( LPC_EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;\r
+ uip_buf = ( unsigned char * ) RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex );\r
\r
/* Allocate a new buffer to the descriptor. */\r
- RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();\r
+ RX_DESC_PACKET( LPC_EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();\r
\r
/* Move the consume index onto the next position, ensuring it wraps to\r
the beginning at the appropriate place. */\r
- lIndex = EMAC->RxConsumeIndex;\r
+ lIndex = LPC_EMAC->RxConsumeIndex;\r
\r
lIndex++;\r
if( lIndex >= NUM_RX_FRAG )\r
lIndex = 0;\r
}\r
\r
- EMAC->RxConsumeIndex = lIndex;\r
+ LPC_EMAC->RxConsumeIndex = lIndex;\r
}\r
\r
return ulLen;\r
usSendLen = usTxDataLen;\r
TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;\r
TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );\r
- EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );\r
+ LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );\r
\r
/* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */\r
uip_buf = prvGetNextBuffer();\r
const long lMaxTime = 10;\r
long x;\r
\r
- EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;\r
- EMAC->MWTD = lValue;\r
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | lPhyReg;\r
+ LPC_EMAC->MWTD = lValue;\r
\r
x = 0;\r
for( x = 0; x < lMaxTime; x++ )\r
{\r
- if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
+ if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
{\r
/* Operation has finished. */\r
break;\r
long x;\r
const long lMaxTime = 10;\r
\r
- EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;\r
- EMAC->MCMD = MCMD_READ;\r
+ LPC_EMAC->MADR = DP83848C_DEF_ADR | ucPhyReg;\r
+ LPC_EMAC->MCMD = MCMD_READ;\r
\r
for( x = 0; x < lMaxTime; x++ )\r
{\r
/* Operation has finished. */\r
- if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
+ if( ( LPC_EMAC->MIND & MIND_BUSY ) == 0 )\r
{\r
break;\r
}\r
vTaskDelay( emacSHORT_DELAY );\r
}\r
\r
- EMAC->MCMD = 0;\r
+ LPC_EMAC->MCMD = 0;\r
\r
if( x >= lMaxTime )\r
{\r
*plStatus = pdFAIL;\r
}\r
\r
- return( EMAC->MRDD );\r
+ return( LPC_EMAC->MRDD );\r
}\r
/*-----------------------------------------------------------*/\r
\r
unsigned long ulStatus;\r
long lHigherPriorityTaskWoken = pdFALSE;\r
\r
- ulStatus = EMAC->IntStatus;\r
+ ulStatus = LPC_EMAC->IntStatus;\r
\r
/* Clear the interrupt. */\r
- EMAC->IntClear = ulStatus;\r
+ LPC_EMAC->IntClear = ulStatus;\r
\r
if( ulStatus & INT_RX_DONE )\r
{\r
only two descriptors the index is set back to 0. */\r
TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );\r
TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );\r
- EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );\r
+ LPC_EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );\r
\r
/* This is the second Tx so set usSendLen to 0 to indicate that the\r
Tx descriptors will be free again. */\r
\r
portENTER_CRITICAL();\r
{\r
- EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
+ LPC_EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
\r
/* Set the interrupt priority to the max permissible to cause some\r
interrupt nesting. */\r
projects / freertos / commitdiff