--- /dev/null
+\r
+Microsoft Visual Studio Solution File, Format Version 11.00\r
+# Atmel Studio Solution File, Format Version 11.00\r
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{3D8959CD-73CA-4147-9C1B-CFCF2EE40326}"\r
+EndProject\r
+Global\r
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution\r
+ Debug|ARM = Debug|ARM\r
+ Release|ARM = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution\r
+ {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Debug|ARM.ActiveCfg = Debug|ARM\r
+ {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Debug|ARM.Build.0 = Debug|ARM\r
+ {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Release|ARM.ActiveCfg = Release|ARM\r
+ {3D8959CD-73CA-4147-9C1B-CFCF2EE40326}.Release|ARM.Build.0 = Release|ARM\r
+ EndGlobalSection\r
+ GlobalSection(SolutionProperties) = preSolution\r
+ HideSolutionNode = FALSE\r
+ EndGlobalSection\r
+EndGlobal\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003" DefaultTargets="Build">\r
+ <PropertyGroup>\r
+ <SchemaVersion>2.0</SchemaVersion>\r
+ <ProjectVersion>6.0</ProjectVersion>\r
+ <ProjectGuid>{3d8959cd-73ca-4147-9c1b-cfcf2ee40326}</ProjectGuid>\r
+ <Name>$(MSBuildProjectName)</Name>\r
+ <AssemblyName>$(MSBuildProjectName)</AssemblyName>\r
+ <RootNamespace>$(MSBuildProjectName)</RootNamespace>\r
+ <AsfVersion>3.1.3</AsfVersion>\r
+ <AsfFrameworkConfig>\r
+ <framework-data>\r
+ <options>\r
+ <option id="common.applications.user_application" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.boards" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="common.services.basic.gpio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.drivers.pio" value="Add" config="" content-id="Atmel.ASF" />\r
+ <option id="sam.utils.cmsis.sam4s.source.template" value="Add" config="" content-id="Atmel.ASF" />\r
+ </options>\r
+ <configurations />\r
+ <files>\r
+ <file framework="" version="3.1.3" path="src/asf.h" source="./common/applications/user_application/sam4s16c_sam4s_ek/as5_arm_template/asf.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/main.c" source="common/applications/user_application/main.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/config/conf_board.h" source="common/applications/user_application/sam4s16c_sam4s_ek/conf_board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/boards/board.h" source="common/boards/board.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/services/gpio/gpio.h" source="common/services/gpio/gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/services/gpio/sam_ioport/sam_gpio.h" source="common/services/gpio/sam_ioport/sam_gpio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt.h" source="common/utils/interrupt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt/interrupt_sam_nvic.c" source="common/utils/interrupt/interrupt_sam_nvic.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/common/utils/interrupt/interrupt_sam_nvic.h" source="common/utils/interrupt/interrupt_sam_nvic.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/boards/sam4s_ek/init.c" source="sam/boards/sam4s_ek/init.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/boards/sam4s_ek/sam4s_ek.h" source="sam/boards/sam4s_ek/sam4s_ek.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio.c" source="sam/drivers/pio/pio.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio.h" source="sam/drivers/pio/pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio_handler.c" source="sam/drivers/pio/pio_handler.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/drivers/pio/pio_handler.h" source="sam/drivers/pio/pio_handler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_acc.h" source="sam/utils/cmsis/sam4s/include/component/component_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_adc.h" source="sam/utils/cmsis/sam4s/include/component/component_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_chipid.h" source="sam/utils/cmsis/sam4s/include/component/component_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_crccu.h" source="sam/utils/cmsis/sam4s/include/component/component_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_dacc.h" source="sam/utils/cmsis/sam4s/include/component/component_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_efc.h" source="sam/utils/cmsis/sam4s/include/component/component_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_gpbr.h" source="sam/utils/cmsis/sam4s/include/component/component_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_hsmci.h" source="sam/utils/cmsis/sam4s/include/component/component_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_matrix.h" source="sam/utils/cmsis/sam4s/include/component/component_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pdc.h" source="sam/utils/cmsis/sam4s/include/component/component_pdc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pio.h" source="sam/utils/cmsis/sam4s/include/component/component_pio.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pmc.h" source="sam/utils/cmsis/sam4s/include/component/component_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_pwm.h" source="sam/utils/cmsis/sam4s/include/component/component_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rstc.h" source="sam/utils/cmsis/sam4s/include/component/component_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtc.h" source="sam/utils/cmsis/sam4s/include/component/component_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_rtt.h" source="sam/utils/cmsis/sam4s/include/component/component_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_smc.h" source="sam/utils/cmsis/sam4s/include/component/component_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_spi.h" source="sam/utils/cmsis/sam4s/include/component/component_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_ssc.h" source="sam/utils/cmsis/sam4s/include/component/component_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_supc.h" source="sam/utils/cmsis/sam4s/include/component/component_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_tc.h" source="sam/utils/cmsis/sam4s/include/component/component_tc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_twi.h" source="sam/utils/cmsis/sam4s/include/component/component_twi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_uart.h" source="sam/utils/cmsis/sam4s/include/component/component_uart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_udp.h" source="sam/utils/cmsis/sam4s/include/component/component_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_usart.h" source="sam/utils/cmsis/sam4s/include/component/component_usart.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/component/component_wdt.h" source="sam/utils/cmsis/sam4s/include/component/component_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_acc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_acc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_adc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_adc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" source="sam/utils/cmsis/sam4s/include/instance/instance_chipid.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" source="sam/utils/cmsis/sam4s/include/instance/instance_crccu.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_dacc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_efc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_efc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" source="sam/utils/cmsis/sam4s/include/instance/instance_gpbr.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" source="sam/utils/cmsis/sam4s/include/instance/instance_hsmci.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" source="sam/utils/cmsis/sam4s/include/instance/instance_matrix.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pioa.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_piob.h" source="sam/utils/cmsis/sam4s/include/instance/instance_piob.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pioc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pmc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" source="sam/utils/cmsis/sam4s/include/instance/instance_pwm.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rstc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rtc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" source="sam/utils/cmsis/sam4s/include/instance/instance_rtt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_smc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_smc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_spi.h" source="sam/utils/cmsis/sam4s/include/instance/instance_spi.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_ssc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_supc.h" source="sam/utils/cmsis/sam4s/include/instance/instance_supc.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_tc0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_tc1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_twi0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_twi1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_uart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_uart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_udp.h" source="sam/utils/cmsis/sam4s/include/instance/instance_udp.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" source="sam/utils/cmsis/sam4s/include/instance/instance_usart0.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" source="sam/utils/cmsis/sam4s/include/instance/instance_usart1.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" source="sam/utils/cmsis/sam4s/include/instance/instance_wdt.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/pio/pio_sam4s16c.h" source="sam/utils/cmsis/sam4s/include/pio/pio_sam4s16c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/sam4s.h" source="sam/utils/cmsis/sam4s/include/sam4s.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/include/sam4s16c.h" source="sam/utils/cmsis/sam4s/include/sam4s16c.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.c" source="sam/utils/cmsis/sam4s/source/templates/exceptions.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/exceptions.h" source="sam/utils/cmsis/sam4s/source/templates/exceptions.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" source="sam/utils/cmsis/sam4s/source/templates/gcc/startup_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.c" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" source="sam/utils/cmsis/sam4s/source/templates/system_sam4s.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/compiler.h" source="sam/utils/compiler.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/header_files/io.h" source="sam/utils/header_files/io.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" source="sam/utils/linker_scripts/sam4s/sam4s16/gcc/flash.ld" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/make/Makefile.in" source="sam/utils/make/Makefile.in" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/parts.h" source="sam/utils/parts.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/mrepeat.h" source="sam/utils/preprocessor/mrepeat.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/preprocessor.h" source="sam/utils/preprocessor/preprocessor.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/stringz.h" source="sam/utils/preprocessor/stringz.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/preprocessor/tpaste.h" source="sam/utils/preprocessor/tpaste.h" changed="False" content-id="Atmel.ASF" />\r
+ <file framework="" version="3.1.3" path="src/asf/sam/utils/status_codes.h" source="sam/utils/status_codes.h" changed="False" content-id="Atmel.ASF" />\r
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+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_dacc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_efc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_gpbr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_hsmci.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_matrix.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_pdc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_pio.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_pwm.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_rstc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_rtt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_smc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_spi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_ssc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_supc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_tc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_twi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_uart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_udp.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_usart.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\component\component_wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_acc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_adc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_chipid.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_crccu.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_dacc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_efc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_gpbr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_hsmci.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_matrix.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_pioa.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_piob.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_pioc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_pmc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_pwm.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_rstc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_rtc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_rtt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_smc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_spi.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_ssc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_supc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_tc0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_tc1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_twi0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_twi1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_uart0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_uart1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_udp.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_usart0.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_usart1.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\instance\instance_wdt.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\pio\pio_sam4s16c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\sam4s.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\include\sam4s16c.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\source\templates\exceptions.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\cmsis\sam4s\source\templates\system_sam4s.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\compiler.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\header_files\io.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\linker_scripts\sam4s\sam4s16\gcc\flash.ld">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\make\Makefile.in">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\parts.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\mrepeat.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\preprocessor.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\stringz.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\preprocessor\tpaste.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\sam\utils\status_codes.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\CMSIS END USER LICENCE AGREEMENT.pdf">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\arm_math.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cm4.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cm4_simd.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmFunc.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Include\core_cmInstr.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\Lib\GCC\libarm_cortexM4l_math.a">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\README.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\asf\thirdparty\CMSIS\license.txt">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ <None Include="src\config\conf_board.h">\r
+ <SubType>compile</SubType>\r
+ </None>\r
+ </ItemGroup>\r
+ <ItemGroup>\r
+ <Folder Include="src\" />\r
+ <Folder Include="src\asf\" />\r
+ <Folder Include="src\asf\common\" />\r
+ <Folder Include="src\asf\common\boards\" />\r
+ <Folder Include="src\asf\common\services\" />\r
+ <Folder Include="src\asf\common\services\gpio\" />\r
+ <Folder Include="src\asf\common\services\gpio\sam_ioport\" />\r
+ <Folder Include="src\asf\common\utils\" />\r
+ <Folder Include="src\asf\common\utils\interrupt\" />\r
+ <Folder Include="src\asf\sam\" />\r
+ <Folder Include="src\asf\sam\boards\" />\r
+ <Folder Include="src\asf\sam\boards\sam4s_ek\" />\r
+ <Folder Include="src\asf\sam\drivers\" />\r
+ <Folder Include="src\asf\sam\drivers\pio\" />\r
+ <Folder Include="src\asf\sam\utils\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\include\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\include\component\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\include\instance\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\include\pio\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\source\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\source\templates\" />\r
+ <Folder Include="src\asf\sam\utils\cmsis\sam4s\source\templates\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\header_files\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam4s\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam4s\sam4s16\" />\r
+ <Folder Include="src\asf\sam\utils\linker_scripts\sam4s\sam4s16\gcc\" />\r
+ <Folder Include="src\asf\sam\utils\make\" />\r
+ <Folder Include="src\asf\sam\utils\preprocessor\" />\r
+ <Folder Include="src\asf\thirdparty\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\Include\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\Lib\" />\r
+ <Folder Include="src\asf\thirdparty\CMSIS\Lib\GCC\" />\r
+ <Folder Include="src\Common-Demo-Source\include" />\r
+ <Folder Include="src\config\" />\r
+ <Folder Include="src\FreeRTOS-Source" />\r
+ <Folder Include="src\FreeRTOS-Source\include" />\r
+ <Folder Include="src\FreeRTOS-Source\portable" />\r
+ <Folder Include="src\FreeRTOS-Source\portable\GCC" />\r
+ <Folder Include="src\FreeRTOS-Source\portable\GCC\ARM_CM3" />\r
+ <Folder Include="src\Common-Demo-Source" />\r
+ <Folder Include="src\FreeRTOS-Source\portable\MemMang" />\r
+ </ItemGroup>\r
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />\r
+</Project>
\ No newline at end of file
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * Creates six tasks that operate on three queues as follows:\r
+ *\r
+ * The first two tasks send and receive an incrementing number to/from a queue.\r
+ * One task acts as a producer and the other as the consumer. The consumer is a\r
+ * higher priority than the producer and is set to block on queue reads. The queue\r
+ * only has space for one item - as soon as the producer posts a message on the\r
+ * queue the consumer will unblock, pre-empt the producer, and remove the item.\r
+ *\r
+ * The second two tasks work the other way around. Again the queue used only has\r
+ * enough space for one item. This time the consumer has a lower priority than the\r
+ * producer. The producer will try to post on the queue blocking when the queue is\r
+ * full. When the consumer wakes it will remove the item from the queue, causing\r
+ * the producer to unblock, pre-empt the consumer, and immediately re-fill the\r
+ * queue.\r
+ *\r
+ * The last two tasks use the same queue producer and consumer functions. This time the queue has\r
+ * enough space for lots of items and the tasks operate at the same priority. The\r
+ * producer will execute, placing items into the queue. The consumer will start\r
+ * executing when either the queue becomes full (causing the producer to block) or\r
+ * a context switch occurs (tasks of the same priority will time slice).\r
+ *\r
+ */\r
+\r
+/*\r
+\r
+Changes from V4.1.1\r
+\r
+ + The second set of tasks were created the wrong way around. This has been\r
+ corrected.\r
+*/\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "BlockQ.h"\r
+\r
+#define blckqSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define blckqNUM_TASK_SETS ( 3 )\r
+\r
+/* Structure used to pass parameters to the blocking queue tasks. */\r
+typedef struct BLOCKING_QUEUE_PARAMETERS\r
+{\r
+ xQueueHandle xQueue; /*< The queue to be used by the task. */\r
+ portTickType xBlockTime; /*< The block time to use on queue reads/writes. */\r
+ volatile short *psCheckVariable; /*< Incremented on each successful cycle to check the task is still running. */\r
+} xBlockingQueueParameters;\r
+\r
+/* Task function that creates an incrementing number and posts it on a queue. */\r
+static portTASK_FUNCTION_PROTO( vBlockingQueueProducer, pvParameters );\r
+\r
+/* Task function that removes the incrementing number from a queue and checks that\r
+it is the expected number. */\r
+static portTASK_FUNCTION_PROTO( vBlockingQueueConsumer, pvParameters );\r
+\r
+/* Variables which are incremented each time an item is removed from a queue, and\r
+found to be the expected value.\r
+These are used to check that the tasks are still running. */\r
+static volatile short sBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 };\r
+\r
+/* Variable which are incremented each time an item is posted on a queue. These\r
+are used to check that the tasks are still running. */\r
+static volatile short sBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xBlockingQueueParameters *pxQueueParameters1, *pxQueueParameters2;\r
+xBlockingQueueParameters *pxQueueParameters3, *pxQueueParameters4;\r
+xBlockingQueueParameters *pxQueueParameters5, *pxQueueParameters6;\r
+const unsigned portBASE_TYPE uxQueueSize1 = 1, uxQueueSize5 = 5;\r
+const portTickType xBlockTime = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+const portTickType xDontBlock = ( portTickType ) 0;\r
+\r
+ /* Create the first two tasks as described at the top of the file. */\r
+ \r
+ /* First create the structure used to pass parameters to the consumer tasks. */\r
+ pxQueueParameters1 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Create the queue used by the first two tasks to pass the incrementing number.\r
+ Pass a pointer to the queue in the parameter structure. */\r
+ pxQueueParameters1->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );\r
+\r
+ /* The consumer is created first so gets a block time as described above. */\r
+ pxQueueParameters1->xBlockTime = xBlockTime;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check it\r
+ is still running. */\r
+ pxQueueParameters1->psCheckVariable = &( sBlockingConsumerCount[ 0 ] );\r
+ \r
+ /* Create the structure used to pass parameters to the producer task. */\r
+ pxQueueParameters2 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+\r
+ /* Pass the queue to this task also, using the parameter structure. */\r
+ pxQueueParameters2->xQueue = pxQueueParameters1->xQueue;\r
+\r
+ /* The producer is not going to block - as soon as it posts the consumer will\r
+ wake and remove the item so the producer should always have room to post. */\r
+ pxQueueParameters2->xBlockTime = xDontBlock;\r
+\r
+ /* Pass in the variable that this task is going to increment so we can check\r
+ it is still running. */\r
+ pxQueueParameters2->psCheckVariable = &( sBlockingProducerCount[ 0 ] );\r
+\r
+\r
+ /* Note the producer has a lower priority than the consumer when the tasks are\r
+ spawned. */\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB1", blckqSTACK_SIZE, ( void * ) pxQueueParameters1, uxPriority, NULL );\r
+ xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB2", blckqSTACK_SIZE, ( void * ) pxQueueParameters2, tskIDLE_PRIORITY, NULL );\r
+\r
+ \r
+\r
+ /* Create the second two tasks as described at the top of the file. This uses\r
+ the same mechanism but reverses the task priorities. */\r
+\r
+ pxQueueParameters3 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters3->xQueue = xQueueCreate( uxQueueSize1, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );\r
+ pxQueueParameters3->xBlockTime = xDontBlock;\r
+ pxQueueParameters3->psCheckVariable = &( sBlockingProducerCount[ 1 ] );\r
+\r
+ pxQueueParameters4 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters4->xQueue = pxQueueParameters3->xQueue;\r
+ pxQueueParameters4->xBlockTime = xBlockTime;\r
+ pxQueueParameters4->psCheckVariable = &( sBlockingConsumerCount[ 1 ] );\r
+\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB3", blckqSTACK_SIZE, ( void * ) pxQueueParameters3, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB4", blckqSTACK_SIZE, ( void * ) pxQueueParameters4, uxPriority, NULL );\r
+\r
+\r
+\r
+ /* Create the last two tasks as described above. The mechanism is again just\r
+ the same. This time both parameter structures are given a block time. */\r
+ pxQueueParameters5 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters5->xQueue = xQueueCreate( uxQueueSize5, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );\r
+ pxQueueParameters5->xBlockTime = xBlockTime;\r
+ pxQueueParameters5->psCheckVariable = &( sBlockingProducerCount[ 2 ] );\r
+\r
+ pxQueueParameters6 = ( xBlockingQueueParameters * ) pvPortMalloc( sizeof( xBlockingQueueParameters ) );\r
+ pxQueueParameters6->xQueue = pxQueueParameters5->xQueue;\r
+ pxQueueParameters6->xBlockTime = xBlockTime;\r
+ pxQueueParameters6->psCheckVariable = &( sBlockingConsumerCount[ 2 ] ); \r
+\r
+ xTaskCreate( vBlockingQueueProducer, ( signed char * ) "QProdB5", blckqSTACK_SIZE, ( void * ) pxQueueParameters5, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vBlockingQueueConsumer, ( signed char * ) "QConsB6", blckqSTACK_SIZE, ( void * ) pxQueueParameters6, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vBlockingQueueProducer, pvParameters )\r
+{\r
+unsigned short usValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+short sErrorEverOccurred = pdFALSE;\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueSend( pxQueueParameters->xQueue, ( void * ) &usValue, pxQueueParameters->xBlockTime ) != pdPASS )\r
+ {\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully posted a message, so increment the variable\r
+ used to check we are still running. */\r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+\r
+ /* Increment the variable we are going to post next time round. The\r
+ consumer will expect the numbers to follow in numerical order. */\r
+ ++usValue;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vBlockingQueueConsumer, pvParameters )\r
+{\r
+unsigned short usData, usExpectedValue = 0;\r
+xBlockingQueueParameters *pxQueueParameters;\r
+short sErrorEverOccurred = pdFALSE;\r
+\r
+ pxQueueParameters = ( xBlockingQueueParameters * ) pvParameters;\r
+\r
+ for( ;; )\r
+ { \r
+ if( xQueueReceive( pxQueueParameters->xQueue, &usData, pxQueueParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ /* Catch-up. */\r
+ usExpectedValue = usData;\r
+\r
+ sErrorEverOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* We have successfully received a message, so increment the\r
+ variable used to check we are still running. */ \r
+ if( sErrorEverOccurred == pdFALSE )\r
+ {\r
+ ( *pxQueueParameters->psCheckVariable )++;\r
+ }\r
+ \r
+ /* Increment the value we expect to remove from the queue next time\r
+ round. */\r
+ ++usExpectedValue;\r
+ } \r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreBlockingQueuesStillRunning( void )\r
+{\r
+static short sLastBlockingConsumerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 };\r
+static short sLastBlockingProducerCount[ blckqNUM_TASK_SETS ] = { ( unsigned short ) 0, ( unsigned short ) 0, ( unsigned short ) 0 };\r
+portBASE_TYPE xReturn = pdPASS, xTasks;\r
+\r
+ /* Not too worried about mutual exclusion on these variables as they are 16\r
+ bits and we are only reading them. We also only care to see if they have\r
+ changed or not.\r
+ \r
+ Loop through each check variable to and return pdFALSE if any are found not\r
+ to have changed since the last call. */\r
+\r
+ for( xTasks = 0; xTasks < blckqNUM_TASK_SETS; xTasks++ )\r
+ {\r
+ if( sBlockingConsumerCount[ xTasks ] == sLastBlockingConsumerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingConsumerCount[ xTasks ] = sBlockingConsumerCount[ xTasks ];\r
+\r
+\r
+ if( sBlockingProducerCount[ xTasks ] == sLastBlockingProducerCount[ xTasks ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ sLastBlockingProducerCount[ xTasks ] = sBlockingProducerCount[ xTasks ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+/* \r
+ * Tests the extra queue functionality introduced in FreeRTOS.org V4.5.0 - \r
+ * including xQueueSendToFront(), xQueueSendToBack(), xQueuePeek() and \r
+ * mutex behaviour. \r
+ *\r
+ * See the comments above the prvSendFrontAndBackTest() and \r
+ * prvLowPriorityMutexTask() prototypes below for more information.\r
+ */\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "semphr.h"\r
+\r
+/* Demo program include files. */\r
+#include "GenQTest.h"\r
+\r
+#define genqQUEUE_LENGTH ( 5 )\r
+#define genqNO_BLOCK ( 0 )\r
+\r
+#define genqMUTEX_LOW_PRIORITY ( tskIDLE_PRIORITY )\r
+#define genqMUTEX_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define genqMUTEX_MEDIUM_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define genqMUTEX_HIGH_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Tests the behaviour of the xQueueSendToFront() and xQueueSendToBack()\r
+ * macros by using both to fill a queue, then reading from the queue to\r
+ * check the resultant queue order is as expected. Queue data is also\r
+ * peeked.\r
+ */\r
+static void prvSendFrontAndBackTest( void *pvParameters );\r
+\r
+/*\r
+ * The following three tasks are used to demonstrate the mutex behaviour.\r
+ * Each task is given a different priority to demonstrate the priority\r
+ * inheritance mechanism.\r
+ *\r
+ * The low priority task obtains a mutex. After this a high priority task\r
+ * attempts to obtain the same mutex, causing its priority to be inherited\r
+ * by the low priority task. The task with the inherited high priority then\r
+ * resumes a medium priority task to ensure it is not blocked by the medium\r
+ * priority task while it holds the inherited high priority. Once the mutex\r
+ * is returned the task with the inherited priority returns to its original\r
+ * low priority, and is therefore immediately preempted by first the high\r
+ * priority task and then the medium prioroity task before it can continue.\r
+ */\r
+static void prvLowPriorityMutexTask( void *pvParameters );\r
+static void prvMediumPriorityMutexTask( void *pvParameters );\r
+static void prvHighPriorityMutexTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be\r
+detected in any of the tasks. */\r
+static portBASE_TYPE xErrorDetected = pdFALSE;\r
+\r
+/* Counters that are incremented on each cycle of a test. This is used to\r
+detect a stalled task - a test that is no longer running. */\r
+static volatile unsigned portLONG ulLoopCounter = 0;\r
+static volatile unsigned portLONG ulLoopCounter2 = 0;\r
+\r
+/* The variable that is guarded by the mutex in the mutex demo tasks. */\r
+static volatile unsigned portLONG ulGuardedVariable = 0;\r
+\r
+/* Handles used in the mutext test to suspend and resume the high and medium\r
+priority mutex test tasks. */\r
+static xTaskHandle xHighPriorityMutexTask, xMediumPriorityMutexTask;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xQueueHandle xQueue;\r
+xSemaphoreHandle xMutex;\r
+\r
+ /* Create the queue that we are going to use for the\r
+ prvSendFrontAndBackTest demo. */\r
+ xQueue = xQueueCreate( genqQUEUE_LENGTH, sizeof( unsigned portLONG ) );\r
+\r
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is\r
+ in use. The queue registry is provided as a means for kernel aware \r
+ debuggers to locate queues and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( xQueue, ( signed portCHAR * ) "Gen_Queue_Test" );\r
+\r
+ /* Create the demo task and pass it the queue just created. We are\r
+ passing the queue handle by value so it does not matter that it is\r
+ declared on the stack here. */\r
+ xTaskCreate( prvSendFrontAndBackTest, ( signed portCHAR * )"GenQ", configMINIMAL_STACK_SIZE, ( void * ) xQueue, uxPriority, NULL );\r
+\r
+ /* Create the mutex used by the prvMutexTest task. */\r
+ xMutex = xSemaphoreCreateMutex();\r
+\r
+ /* vQueueAddToRegistry() adds the mutex to the registry, if one is\r
+ in use. The registry is provided as a means for kernel aware \r
+ debuggers to locate mutexes and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Gen_Queue_Mutex" );\r
+\r
+ /* Create the mutex demo tasks and pass it the mutex just created. We are\r
+ passing the mutex handle by value so it does not matter that it is declared\r
+ on the stack here. */\r
+ xTaskCreate( prvLowPriorityMutexTask, ( signed portCHAR * )"MuLow", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_LOW_PRIORITY, NULL );\r
+ xTaskCreate( prvMediumPriorityMutexTask, ( signed portCHAR * )"MuMed", configMINIMAL_STACK_SIZE, NULL, genqMUTEX_MEDIUM_PRIORITY, &xMediumPriorityMutexTask );\r
+ xTaskCreate( prvHighPriorityMutexTask, ( signed portCHAR * )"MuHigh", configMINIMAL_STACK_SIZE, ( void * ) xMutex, genqMUTEX_HIGH_PRIORITY, &xHighPriorityMutexTask );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSendFrontAndBackTest( void *pvParameters )\r
+{\r
+unsigned portLONG ulData, ulData2;\r
+xQueueHandle xQueue;\r
+\r
+ #ifdef USE_STDIO\r
+ void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );\r
+ \r
+ const portCHAR * const pcTaskStartMsg = "Queue SendToFront/SendToBack/Peek test started.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+ #endif\r
+\r
+ xQueue = ( xQueueHandle ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The queue is empty, so sending an item to the back of the queue\r
+ should have the same efect as sending it to the front of the queue.\r
+\r
+ First send to the front and check everything is as expected. */\r
+ xQueueSendToFront( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );\r
+\r
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* The data we sent to the queue should equal the data we just received\r
+ from the queue. */\r
+ if( ulLoopCounter != ulData )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Then do the same, sending the data to the back, checking everything\r
+ is as expected. */\r
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ xQueueSendToBack( xQueue, ( void * ) &ulLoopCounter, genqNO_BLOCK );\r
+\r
+ if( uxQueueMessagesWaiting( xQueue ) != 1 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueReceive( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* The data we sent to the queue should equal the data we just received\r
+ from the queue. */\r
+ if( ulLoopCounter != ulData )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+\r
+\r
+ /* Place 2, 3, 4 into the queue, adding items to the back of the queue. */\r
+ for( ulData = 2; ulData < 5; ulData++ )\r
+ {\r
+ xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK );\r
+ }\r
+\r
+ /* Now the order in the queue should be 2, 3, 4, with 2 being the first\r
+ thing to be read out. Now add 1 then 0 to the front of the queue. */\r
+ if( uxQueueMessagesWaiting( xQueue ) != 3 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ ulData = 1;\r
+ xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );\r
+ ulData = 0;\r
+ xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK );\r
+\r
+ /* Now the queue should be full, and when we read the data out we\r
+ should receive 0, 1, 2, 3, 4. */\r
+ if( uxQueueMessagesWaiting( xQueue ) != 5 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ /* Check the data we read out is in the expected order. */\r
+ for( ulData = 0; ulData < genqQUEUE_LENGTH; ulData++ )\r
+ {\r
+ /* Try peeking the data first. */\r
+ if( xQueuePeek( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( ulData != ulData2 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ \r
+\r
+ /* Now try receiving the data for real. The value should be the\r
+ same. Clobber the value first so we know we really received it. */\r
+ ulData2 = ~ulData2;\r
+ if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( ulData != ulData2 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* The queue should now be empty again. */\r
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+\r
+ /* Our queue is empty once more, add 10, 11 to the back. */\r
+ ulData = 10;\r
+ if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ ulData = 11;\r
+ if( xQueueSend( xQueue, &ulData, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( uxQueueMessagesWaiting( xQueue ) != 2 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Now we should have 10, 11 in the queue. Add 7, 8, 9 to the\r
+ front. */\r
+ for( ulData = 9; ulData >= 7; ulData-- )\r
+ {\r
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Now check that the queue is full, and that receiving data provides\r
+ the expected sequence of 7, 8, 9, 10, 11. */\r
+ if( uxQueueMessagesWaiting( xQueue ) != 5 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueSendToFront( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( xQueueSendToBack( xQueue, ( void * ) &ulData, genqNO_BLOCK ) != errQUEUE_FULL )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ /* Check the data we read out is in the expected order. */\r
+ for( ulData = 7; ulData < ( 7 + genqQUEUE_LENGTH ); ulData++ )\r
+ {\r
+ if( xQueueReceive( xQueue, &ulData2, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( ulData != ulData2 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+ }\r
+\r
+ if( uxQueueMessagesWaiting( xQueue ) != 0 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ ulLoopCounter++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLowPriorityMutexTask( void *pvParameters )\r
+{\r
+xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;\r
+\r
+ #ifdef USE_STDIO\r
+ void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );\r
+ \r
+ const portCHAR * const pcTaskStartMsg = "Mutex with priority inheritance test started.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+ #endif\r
+\r
+ for( ;; )\r
+ {\r
+ /* Take the mutex. It should be available now. */\r
+ if( xSemaphoreTake( xMutex, genqNO_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Set our guarded variable to a known start value. */\r
+ ulGuardedVariable = 0;\r
+\r
+ /* Our priority should be as per that assigned when the task was\r
+ created. */\r
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_LOW_PRIORITY )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Now unsuspend the high priority task. This will attempt to take the\r
+ mutex, and block when it finds it cannot obtain it. */\r
+ vTaskResume( xHighPriorityMutexTask );\r
+\r
+ /* We should now have inherited the prioritoy of the high priority task,\r
+ as by now it will have attempted to get the mutex. */\r
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* We can attempt to set our priority to the test priority - between the\r
+ idle priority and the medium/high test priorities, but our actual\r
+ prioroity should remain at the high priority. */\r
+ vTaskPrioritySet( NULL, genqMUTEX_TEST_PRIORITY );\r
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_HIGH_PRIORITY )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Now unsuspend the medium priority task. This should not run as our\r
+ inherited priority is above that of the medium priority task. */\r
+ vTaskResume( xMediumPriorityMutexTask );\r
+\r
+ /* If the did run then it will have incremented our guarded variable. */\r
+ if( ulGuardedVariable != 0 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* When we give back the semaphore our priority should be disinherited\r
+ back to the priority to which we attempted to set ourselves. This means\r
+ that when the high priority task next blocks, the medium priority task\r
+ should execute and increment the guarded variable. When we next run\r
+ both the high and medium priority tasks will have been suspended again. */\r
+ if( xSemaphoreGive( xMutex ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Check that the guarded variable did indeed increment... */\r
+ if( ulGuardedVariable != 1 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* ... and that our priority has been disinherited to\r
+ genqMUTEX_TEST_PRIORITY. */\r
+ if( uxTaskPriorityGet( NULL ) != genqMUTEX_TEST_PRIORITY )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* Set our priority back to our original priority ready for the next\r
+ loop around this test. */\r
+ vTaskPrioritySet( NULL, genqMUTEX_LOW_PRIORITY );\r
+\r
+ /* Just to show we are still running. */\r
+ ulLoopCounter2++;\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvMediumPriorityMutexTask( void *pvParameters )\r
+{\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The medium priority task starts by suspending itself. The low\r
+ priority task will unsuspend this task when required. */\r
+ vTaskSuspend( NULL );\r
+\r
+ /* When this task unsuspends all it does is increment the guarded\r
+ variable, this is so the low priority task knows that it has\r
+ executed. */\r
+ ulGuardedVariable++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvHighPriorityMutexTask( void *pvParameters )\r
+{\r
+xSemaphoreHandle xMutex = ( xSemaphoreHandle ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* The high priority task starts by suspending itself. The low\r
+ priority task will unsuspend this task when required. */\r
+ vTaskSuspend( NULL );\r
+\r
+ /* When this task unsuspends all it does is attempt to obtain\r
+ the mutex. It should find the mutex is not available so a\r
+ block time is specified. */\r
+ if( xSemaphoreTake( xMutex, portMAX_DELAY ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* When we eventually obtain the mutex we just give it back then\r
+ return to suspend ready for the next test. */\r
+ if( xSemaphoreGive( xMutex ) != pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreGenericQueueTasksStillRunning( void )\r
+{\r
+static unsigned portLONG ulLastLoopCounter = 0, ulLastLoopCounter2 = 0;\r
+\r
+ /* If the demo task is still running then we expect the loopcounters to\r
+ have incremented since this function was last called. */\r
+ if( ulLastLoopCounter == ulLoopCounter )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ if( ulLastLoopCounter2 == ulLoopCounter2 )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ ulLastLoopCounter = ulLoopCounter;\r
+ ulLastLoopCounter2 = ulLoopCounter2; \r
+\r
+ /* Errors detected in the task itself will have latched xErrorDetected\r
+ to true. */\r
+\r
+ return !xErrorDetected;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * This version of PollQ. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * Creates two tasks that communicate over a single queue. One task acts as a\r
+ * producer, the other a consumer.\r
+ *\r
+ * The producer loops for three iteration, posting an incrementing number onto the\r
+ * queue each cycle. It then delays for a fixed period before doing exactly the\r
+ * same again.\r
+ *\r
+ * The consumer loops emptying the queue. Each item removed from the queue is\r
+ * checked to ensure it contains the expected value. When the queue is empty it\r
+ * blocks for a fixed period, then does the same again.\r
+ *\r
+ * All queue access is performed without blocking. The consumer completely empties\r
+ * the queue each time it runs so the producer should never find the queue full.\r
+ *\r
+ * An error is flagged if the consumer obtains an unexpected value or the producer\r
+ * find the queue is full.\r
+ */\r
+\r
+/*\r
+Changes from V2.0.0\r
+\r
+ + Delay periods are now specified using variables and constants of\r
+ portTickType rather than unsigned long.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo program include files. */\r
+#include "PollQ.h"\r
+\r
+#define pollqSTACK_SIZE configMINIMAL_STACK_SIZE\r
+#define pollqQUEUE_SIZE ( 10 )\r
+#define pollqPRODUCER_DELAY ( ( portTickType ) 200 / portTICK_RATE_MS )\r
+#define pollqCONSUMER_DELAY ( pollqPRODUCER_DELAY - ( portTickType ) ( 20 / portTICK_RATE_MS ) )\r
+#define pollqNO_DELAY ( ( portTickType ) 0 )\r
+#define pollqVALUES_TO_PRODUCE ( ( signed portBASE_TYPE ) 3 )\r
+#define pollqINITIAL_VALUE ( ( signed portBASE_TYPE ) 0 )\r
+\r
+/* The task that posts the incrementing number onto the queue. */\r
+static portTASK_FUNCTION_PROTO( vPolledQueueProducer, pvParameters );\r
+\r
+/* The task that empties the queue. */\r
+static portTASK_FUNCTION_PROTO( vPolledQueueConsumer, pvParameters );\r
+\r
+/* Variables that are used to check that the tasks are still running with no\r
+errors. */\r
+static volatile signed portBASE_TYPE xPollingConsumerCount = pollqINITIAL_VALUE, xPollingProducerCount = pollqINITIAL_VALUE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+static xQueueHandle xPolledQueue;\r
+\r
+ /* Create the queue used by the producer and consumer. */\r
+ xPolledQueue = xQueueCreate( pollqQUEUE_SIZE, ( unsigned portBASE_TYPE ) sizeof( unsigned short ) );\r
+\r
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is\r
+ in use. The queue registry is provided as a means for kernel aware \r
+ debuggers to locate queues and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( xPolledQueue, ( signed char * ) "Poll_Test_Queue" );\r
+\r
+ /* Spawn the producer and consumer. */\r
+ xTaskCreate( vPolledQueueConsumer, ( signed char * ) "QConsNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( vPolledQueueProducer, ( signed char * ) "QProdNB", pollqSTACK_SIZE, ( void * ) &xPolledQueue, uxPriority, ( xTaskHandle * ) NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vPolledQueueProducer, pvParameters )\r
+{\r
+unsigned short usValue = ( unsigned short ) 0;\r
+signed portBASE_TYPE xError = pdFALSE, xLoop;\r
+\r
+ for( ;; )\r
+ { \r
+ for( xLoop = 0; xLoop < pollqVALUES_TO_PRODUCE; xLoop++ )\r
+ {\r
+ /* Send an incrementing number on the queue without blocking. */\r
+ if( xQueueSend( *( ( xQueueHandle * ) pvParameters ), ( void * ) &usValue, pollqNO_DELAY ) != pdPASS )\r
+ {\r
+ /* We should never find the queue full so if we get here there\r
+ has been an error. */\r
+ xError = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ if( xError == pdFALSE )\r
+ {\r
+ /* If an error has ever been recorded we stop incrementing the\r
+ check variable. */\r
+ portENTER_CRITICAL();\r
+ xPollingProducerCount++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Update the value we are going to post next time around. */\r
+ usValue++;\r
+ }\r
+ }\r
+\r
+ /* Wait before we start posting again to ensure the consumer runs and\r
+ empties the queue. */\r
+ vTaskDelay( pollqPRODUCER_DELAY );\r
+ }\r
+} /*lint !e818 Function prototype must conform to API. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vPolledQueueConsumer, pvParameters )\r
+{\r
+unsigned short usData, usExpectedValue = ( unsigned short ) 0;\r
+signed portBASE_TYPE xError = pdFALSE;\r
+\r
+ for( ;; )\r
+ { \r
+ /* Loop until the queue is empty. */\r
+ while( uxQueueMessagesWaiting( *( ( xQueueHandle * ) pvParameters ) ) )\r
+ {\r
+ if( xQueueReceive( *( ( xQueueHandle * ) pvParameters ), &usData, pollqNO_DELAY ) == pdPASS )\r
+ {\r
+ if( usData != usExpectedValue )\r
+ {\r
+ /* This is not what we expected to receive so an error has\r
+ occurred. */\r
+ xError = pdTRUE;\r
+\r
+ /* Catch-up to the value we received so our next expected\r
+ value should again be correct. */\r
+ usExpectedValue = usData;\r
+ }\r
+ else\r
+ {\r
+ if( xError == pdFALSE )\r
+ {\r
+ /* Only increment the check variable if no errors have\r
+ occurred. */\r
+ portENTER_CRITICAL();\r
+ xPollingConsumerCount++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+ /* Next time round we would expect the number to be one higher. */\r
+ usExpectedValue++;\r
+ }\r
+ }\r
+\r
+ /* Now the queue is empty we block, allowing the producer to place more\r
+ items in the queue. */\r
+ vTaskDelay( pollqCONSUMER_DELAY );\r
+ }\r
+} /*lint !e818 Function prototype must conform to API. */\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running with no errors. */\r
+portBASE_TYPE xArePollingQueuesStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Check both the consumer and producer poll count to check they have both\r
+ been changed since out last trip round. We do not need a critical section\r
+ around the check variables as this is called from a higher priority than\r
+ the other tasks that access the same variables. */\r
+ if( ( xPollingConsumerCount == pollqINITIAL_VALUE ) ||\r
+ ( xPollingProducerCount == pollqINITIAL_VALUE )\r
+ )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ /* Set the check variables back down so we know if they have been\r
+ incremented the next time around. */\r
+ xPollingConsumerCount = pollqINITIAL_VALUE;\r
+ xPollingProducerCount = pollqINITIAL_VALUE;\r
+\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * This file contains some test scenarios that ensure tasks do not exit queue\r
+ * send or receive functions prematurely. A description of the tests is\r
+ * included within the code.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo includes. */\r
+#include "blocktim.h"\r
+\r
+/* Task priorities. Allow these to be overridden. */\r
+#ifndef bktPRIMARY_PRIORITY\r
+ #define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 )\r
+#endif\r
+\r
+#ifndef bktSECONDARY_PRIORITY\r
+ #define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 )\r
+#endif\r
+\r
+/* Task behaviour. */\r
+#define bktQUEUE_LENGTH ( 5 )\r
+#define bktSHORT_WAIT ( ( ( portTickType ) 20 ) / portTICK_RATE_MS )\r
+#define bktPRIMARY_BLOCK_TIME ( 10 )\r
+#define bktALLOWABLE_MARGIN ( 15 )\r
+#define bktTIME_TO_BLOCK ( 175 )\r
+#define bktDONT_BLOCK ( ( portTickType ) 0 )\r
+#define bktRUN_INDICATOR ( ( unsigned portBASE_TYPE ) 0x55 )\r
+\r
+/* The queue on which the tasks block. */\r
+static xQueueHandle xTestQueue;\r
+\r
+/* Handle to the secondary task is required by the primary task for calls\r
+to vTaskSuspend/Resume(). */\r
+static xTaskHandle xSecondary;\r
+\r
+/* Used to ensure that tasks are still executing without error. */\r
+static volatile portBASE_TYPE xPrimaryCycles = 0, xSecondaryCycles = 0;\r
+static volatile portBASE_TYPE xErrorOccurred = pdFALSE;\r
+\r
+/* Provides a simple mechanism for the primary task to know when the\r
+secondary task has executed. */\r
+static volatile unsigned portBASE_TYPE xRunIndicator;\r
+\r
+/* The two test tasks. Their behaviour is commented within the files. */\r
+static void vPrimaryBlockTimeTestTask( void *pvParameters );\r
+static void vSecondaryBlockTimeTestTask( void *pvParameters );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateBlockTimeTasks( void )\r
+{\r
+ /* Create the queue on which the two tasks block. */\r
+ xTestQueue = xQueueCreate( bktQUEUE_LENGTH, sizeof( portBASE_TYPE ) );\r
+\r
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is\r
+ in use. The queue registry is provided as a means for kernel aware\r
+ debuggers to locate queues and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is\r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( xTestQueue, ( signed char * ) "Block_Time_Queue" );\r
+\r
+ /* Create the two test tasks. */\r
+ xTaskCreate( vPrimaryBlockTimeTestTask, ( signed char * )"BTest1", configMINIMAL_STACK_SIZE, NULL, bktPRIMARY_PRIORITY, NULL );\r
+ xTaskCreate( vSecondaryBlockTimeTestTask, ( signed char * )"BTest2", configMINIMAL_STACK_SIZE, NULL, bktSECONDARY_PRIORITY, &xSecondary );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vPrimaryBlockTimeTestTask( void *pvParameters )\r
+{\r
+portBASE_TYPE xItem, xData;\r
+portTickType xTimeWhenBlocking;\r
+portTickType xTimeToBlock, xBlockedTime;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /*********************************************************************\r
+ Test 1\r
+\r
+ Simple block time wakeup test on queue receives. */\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ /* The queue is empty. Attempt to read from the queue using a block\r
+ time. When we wake, ensure the delta in time is as expected. */\r
+ xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;\r
+\r
+ xTimeWhenBlocking = xTaskGetTickCount();\r
+\r
+ /* We should unblock after xTimeToBlock having not received\r
+ anything on the queue. */\r
+ if( xQueueReceive( xTestQueue, &xData, xTimeToBlock ) != errQUEUE_EMPTY )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* How long were we blocked for? */\r
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;\r
+\r
+ if( xBlockedTime < xTimeToBlock )\r
+ {\r
+ /* Should not have blocked for less than we requested. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )\r
+ {\r
+ /* Should not have blocked for longer than we requested,\r
+ although we would not necessarily run as soon as we were\r
+ unblocked so a margin is allowed. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /*********************************************************************\r
+ Test 2\r
+\r
+ Simple block time wakeup test on queue sends.\r
+\r
+ First fill the queue. It should be empty so all sends should pass. */\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+ }\r
+\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ /* The queue is full. Attempt to write to the queue using a block\r
+ time. When we wake, ensure the delta in time is as expected. */\r
+ xTimeToBlock = bktPRIMARY_BLOCK_TIME << xItem;\r
+\r
+ xTimeWhenBlocking = xTaskGetTickCount();\r
+\r
+ /* We should unblock after xTimeToBlock having not received\r
+ anything on the queue. */\r
+ if( xQueueSend( xTestQueue, &xItem, xTimeToBlock ) != errQUEUE_FULL )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* How long were we blocked for? */\r
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;\r
+\r
+ if( xBlockedTime < xTimeToBlock )\r
+ {\r
+ /* Should not have blocked for less than we requested. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xBlockedTime > ( xTimeToBlock + bktALLOWABLE_MARGIN ) )\r
+ {\r
+ /* Should not have blocked for longer than we requested,\r
+ although we would not necessarily run as soon as we were\r
+ unblocked so a margin is allowed. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /*********************************************************************\r
+ Test 3\r
+\r
+ Wake the other task, it will block attempting to post to the queue.\r
+ When we read from the queue the other task will wake, but before it\r
+ can run we will post to the queue again. When the other task runs it\r
+ will find the queue still full, even though it was woken. It should\r
+ recognise that its block time has not expired and return to block for\r
+ the remains of its block time.\r
+\r
+ Wake the other task so it blocks attempting to post to the already\r
+ full queue. */\r
+ xRunIndicator = 0;\r
+ vTaskResume( xSecondary );\r
+\r
+ /* We need to wait a little to ensure the other task executes. */\r
+ while( xRunIndicator != bktRUN_INDICATOR )\r
+ {\r
+ /* The other task has not yet executed. */\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ }\r
+ /* Make sure the other task is blocked on the queue. */\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ xRunIndicator = 0;\r
+\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ /* Now when we make space on the queue the other task should wake\r
+ but not execute as this task has higher priority. */\r
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Now fill the queue again before the other task gets a chance to\r
+ execute. If the other task had executed we would find the queue\r
+ full ourselves, and the other task have set xRunIndicator. */\r
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xRunIndicator == bktRUN_INDICATOR )\r
+ {\r
+ /* The other task should not have executed. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Raise the priority of the other task so it executes and blocks\r
+ on the queue again. */\r
+ vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );\r
+\r
+ /* The other task should now have re-blocked without exiting the\r
+ queue function. */\r
+ if( xRunIndicator == bktRUN_INDICATOR )\r
+ {\r
+ /* The other task should not have executed outside of the\r
+ queue function. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Set the priority back down. */\r
+ vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );\r
+ }\r
+\r
+ /* Let the other task timeout. When it unblockes it will check that it\r
+ unblocked at the correct time, then suspend itself. */\r
+ while( xRunIndicator != bktRUN_INDICATOR )\r
+ {\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ }\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ xRunIndicator = 0;\r
+\r
+\r
+ /*********************************************************************\r
+ Test 4\r
+\r
+ As per test 3 - but with the send and receive the other way around.\r
+ The other task blocks attempting to read from the queue.\r
+\r
+ Empty the queue. We should find that it is full. */\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Wake the other task so it blocks attempting to read from the\r
+ already empty queue. */\r
+ vTaskResume( xSecondary );\r
+\r
+ /* We need to wait a little to ensure the other task executes. */\r
+ while( xRunIndicator != bktRUN_INDICATOR )\r
+ {\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ }\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ xRunIndicator = 0;\r
+\r
+ for( xItem = 0; xItem < bktQUEUE_LENGTH; xItem++ )\r
+ {\r
+ /* Now when we place an item on the queue the other task should\r
+ wake but not execute as this task has higher priority. */\r
+ if( xQueueSend( xTestQueue, &xItem, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Now empty the queue again before the other task gets a chance to\r
+ execute. If the other task had executed we would find the queue\r
+ empty ourselves, and the other task would be suspended. */\r
+ if( xQueueReceive( xTestQueue, &xData, bktDONT_BLOCK ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ if( xRunIndicator == bktRUN_INDICATOR )\r
+ {\r
+ /* The other task should not have executed. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Raise the priority of the other task so it executes and blocks\r
+ on the queue again. */\r
+ vTaskPrioritySet( xSecondary, bktPRIMARY_PRIORITY + 2 );\r
+\r
+ /* The other task should now have re-blocked without exiting the\r
+ queue function. */\r
+ if( xRunIndicator == bktRUN_INDICATOR )\r
+ {\r
+ /* The other task should not have executed outside of the\r
+ queue function. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ vTaskPrioritySet( xSecondary, bktSECONDARY_PRIORITY );\r
+ }\r
+\r
+ /* Let the other task timeout. When it unblockes it will check that it\r
+ unblocked at the correct time, then suspend itself. */\r
+ while( xRunIndicator != bktRUN_INDICATOR )\r
+ {\r
+ vTaskDelay( bktSHORT_WAIT );\r
+ }\r
+ vTaskDelay( bktSHORT_WAIT );\r
+\r
+ xPrimaryCycles++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void vSecondaryBlockTimeTestTask( void *pvParameters )\r
+{\r
+portTickType xTimeWhenBlocking, xBlockedTime;\r
+portBASE_TYPE xData;\r
+\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /*********************************************************************\r
+ Test 1 and 2\r
+\r
+ This task does does not participate in these tests. */\r
+ vTaskSuspend( NULL );\r
+\r
+ /*********************************************************************\r
+ Test 3\r
+\r
+ The first thing we do is attempt to read from the queue. It should be\r
+ full so we block. Note the time before we block so we can check the\r
+ wake time is as per that expected. */\r
+ xTimeWhenBlocking = xTaskGetTickCount();\r
+\r
+ /* We should unblock after bktTIME_TO_BLOCK having not sent\r
+ anything to the queue. */\r
+ xData = 0;\r
+ xRunIndicator = bktRUN_INDICATOR;\r
+ if( xQueueSend( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_FULL )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* How long were we inside the send function? */\r
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;\r
+\r
+ /* We should not have blocked for less time than bktTIME_TO_BLOCK. */\r
+ if( xBlockedTime < bktTIME_TO_BLOCK )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* We should of not blocked for much longer than bktALLOWABLE_MARGIN\r
+ either. A margin is permitted as we would not necessarily run as\r
+ soon as we unblocked. */\r
+ if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Suspend ready for test 3. */\r
+ xRunIndicator = bktRUN_INDICATOR;\r
+ vTaskSuspend( NULL );\r
+\r
+ /*********************************************************************\r
+ Test 4\r
+\r
+ As per test three, but with the send and receive reversed. */\r
+ xTimeWhenBlocking = xTaskGetTickCount();\r
+\r
+ /* We should unblock after bktTIME_TO_BLOCK having not received\r
+ anything on the queue. */\r
+ xRunIndicator = bktRUN_INDICATOR;\r
+ if( xQueueReceive( xTestQueue, &xData, bktTIME_TO_BLOCK ) != errQUEUE_EMPTY )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ xBlockedTime = xTaskGetTickCount() - xTimeWhenBlocking;\r
+\r
+ /* We should not have blocked for less time than bktTIME_TO_BLOCK. */\r
+ if( xBlockedTime < bktTIME_TO_BLOCK )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* We should of not blocked for much longer than bktALLOWABLE_MARGIN\r
+ either. A margin is permitted as we would not necessarily run as soon\r
+ as we unblocked. */\r
+ if( xBlockedTime > ( bktTIME_TO_BLOCK + bktALLOWABLE_MARGIN ) )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ xRunIndicator = bktRUN_INDICATOR;\r
+\r
+ xSecondaryCycles++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void )\r
+{\r
+static portBASE_TYPE xLastPrimaryCycleCount = 0, xLastSecondaryCycleCount = 0;\r
+portBASE_TYPE xReturn = pdPASS;\r
+\r
+ /* Have both tasks performed at least one cycle since this function was\r
+ last called? */\r
+ if( xPrimaryCycles == xLastPrimaryCycleCount )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ if( xSecondaryCycles == xLastSecondaryCycleCount )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ if( xErrorOccurred == pdTRUE )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ xLastSecondaryCycleCount = xSecondaryCycles;\r
+ xLastPrimaryCycleCount = xPrimaryCycles;\r
+\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+/* \r
+ * Simple demonstration of the usage of counting semaphore.\r
+ */\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo program include files. */\r
+#include "countsem.h"\r
+\r
+/* The maximum count value that the semaphore used for the demo can hold. */\r
+#define countMAX_COUNT_VALUE ( 200 )\r
+\r
+/* Constants used to indicate whether or not the semaphore should have been\r
+created with its maximum count value, or its minimum count value. These \r
+numbers are used to ensure that the pointers passed in as the task parameters\r
+are valid. */\r
+#define countSTART_AT_MAX_COUNT ( 0xaa )\r
+#define countSTART_AT_ZERO ( 0x55 )\r
+\r
+/* Two tasks are created for the test. One uses a semaphore created with its\r
+count value set to the maximum, and one with the count value set to zero. */\r
+#define countNUM_TEST_TASKS ( 2 )\r
+#define countDONT_BLOCK ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Flag that will be latched to pdTRUE should any unexpected behaviour be\r
+detected in any of the tasks. */\r
+static volatile portBASE_TYPE xErrorDetected = pdFALSE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The demo task. This simply counts the semaphore up to its maximum value,\r
+ * the counts it back down again. The result of each semaphore 'give' and\r
+ * 'take' is inspected, with an error being flagged if it is found not to be\r
+ * the expected result.\r
+ */\r
+static void prvCountingSemaphoreTask( void *pvParameters );\r
+\r
+/*\r
+ * Utility function to increment the semaphore count value up from zero to\r
+ * countMAX_COUNT_VALUE.\r
+ */\r
+static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter );\r
+\r
+/*\r
+ * Utility function to decrement the semaphore count value up from \r
+ * countMAX_COUNT_VALUE to zero.\r
+ */\r
+static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The structure that is passed into the task as the task parameter. */\r
+typedef struct COUNT_SEM_STRUCT\r
+{\r
+ /* The semaphore to be used for the demo. */\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ /* Set to countSTART_AT_MAX_COUNT if the semaphore should be created with\r
+ its count value set to its max count value, or countSTART_AT_ZERO if it\r
+ should have been created with its count value set to 0. */\r
+ unsigned portBASE_TYPE uxExpectedStartCount; \r
+\r
+ /* Incremented on each cycle of the demo task. Used to detect a stalled\r
+ task. */\r
+ unsigned portBASE_TYPE uxLoopCounter; \r
+} xCountSemStruct;\r
+\r
+/* Two structures are defined, one is passed to each test task. */\r
+static volatile xCountSemStruct xParameters[ countNUM_TEST_TASKS ];\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartCountingSemaphoreTasks( void )\r
+{\r
+ /* Create the semaphores that we are going to use for the test/demo. The\r
+ first should be created such that it starts at its maximum count value,\r
+ the second should be created such that it starts with a count value of zero. */\r
+ xParameters[ 0 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, countMAX_COUNT_VALUE );\r
+ xParameters[ 0 ].uxExpectedStartCount = countSTART_AT_MAX_COUNT;\r
+ xParameters[ 0 ].uxLoopCounter = 0;\r
+\r
+ xParameters[ 1 ].xSemaphore = xSemaphoreCreateCounting( countMAX_COUNT_VALUE, 0 );\r
+ xParameters[ 1 ].uxExpectedStartCount = 0;\r
+ xParameters[ 1 ].uxLoopCounter = 0;\r
+\r
+ /* vQueueAddToRegistry() adds the semaphore to the registry, if one is\r
+ in use. The registry is provided as a means for kernel aware \r
+ debuggers to locate semaphores and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( ( xQueueHandle ) xParameters[ 0 ].xSemaphore, ( signed portCHAR * ) "Counting_Sem_1" );\r
+ vQueueAddToRegistry( ( xQueueHandle ) xParameters[ 1 ].xSemaphore, ( signed portCHAR * ) "Counting_Sem_2" );\r
+\r
+\r
+ /* Were the semaphores created? */\r
+ if( ( xParameters[ 0 ].xSemaphore != NULL ) || ( xParameters[ 1 ].xSemaphore != NULL ) )\r
+ {\r
+ /* Create the demo tasks, passing in the semaphore to use as the parameter. */\r
+ xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT1", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 0 ] ), tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( prvCountingSemaphoreTask, ( signed portCHAR * ) "CNT2", configMINIMAL_STACK_SIZE, ( void * ) &( xParameters[ 1 ] ), tskIDLE_PRIORITY, NULL ); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvDecrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter )\r
+{\r
+unsigned portBASE_TYPE ux;\r
+\r
+ /* If the semaphore count is at its maximum then we should not be able to\r
+ 'give' the semaphore. */\r
+ if( xSemaphoreGive( xSemaphore ) == pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* We should be able to 'take' the semaphore countMAX_COUNT_VALUE times. */\r
+ for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )\r
+ {\r
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) != pdPASS )\r
+ {\r
+ /* We expected to be able to take the semaphore. */\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ ( *puxLoopCounter )++;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ /* If the semaphore count is zero then we should not be able to 'take' \r
+ the semaphore. */\r
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvIncrementSemaphoreCount( xSemaphoreHandle xSemaphore, unsigned portBASE_TYPE *puxLoopCounter )\r
+{\r
+unsigned portBASE_TYPE ux;\r
+\r
+ /* If the semaphore count is zero then we should not be able to 'take' \r
+ the semaphore. */\r
+ if( xSemaphoreTake( xSemaphore, countDONT_BLOCK ) == pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ /* We should be able to 'give' the semaphore countMAX_COUNT_VALUE times. */\r
+ for( ux = 0; ux < countMAX_COUNT_VALUE; ux++ )\r
+ {\r
+ if( xSemaphoreGive( xSemaphore ) != pdPASS )\r
+ {\r
+ /* We expected to be able to take the semaphore. */\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ ( *puxLoopCounter )++;\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ taskYIELD();\r
+ #endif\r
+\r
+ /* If the semaphore count is at its maximum then we should not be able to\r
+ 'give' the semaphore. */\r
+ if( xSemaphoreGive( xSemaphore ) == pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCountingSemaphoreTask( void *pvParameters )\r
+{\r
+xCountSemStruct *pxParameter;\r
+\r
+ #ifdef USE_STDIO\r
+ void vPrintDisplayMessage( const portCHAR * const * ppcMessageToSend );\r
+ \r
+ const portCHAR * const pcTaskStartMsg = "Counting semaphore demo started.\r\n";\r
+\r
+ /* Queue a message for printing to say the task has started. */\r
+ vPrintDisplayMessage( &pcTaskStartMsg );\r
+ #endif\r
+\r
+ /* The semaphore to be used was passed as the parameter. */\r
+ pxParameter = ( xCountSemStruct * ) pvParameters;\r
+\r
+ /* Did we expect to find the semaphore already at its max count value, or\r
+ at zero? */\r
+ if( pxParameter->uxExpectedStartCount == countSTART_AT_MAX_COUNT )\r
+ {\r
+ prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );\r
+ }\r
+\r
+ /* Now we expect the semaphore count to be 0, so this time there is an\r
+ error if we can take the semaphore. */\r
+ if( xSemaphoreTake( pxParameter->xSemaphore, 0 ) == pdPASS )\r
+ {\r
+ xErrorDetected = pdTRUE;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ prvIncrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );\r
+ prvDecrementSemaphoreCount( pxParameter->xSemaphore, &( pxParameter->uxLoopCounter ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void )\r
+{\r
+static unsigned portBASE_TYPE uxLastCount0 = 0, uxLastCount1 = 0;\r
+portBASE_TYPE xReturn = pdPASS;\r
+\r
+ /* Return fail if any 'give' or 'take' did not result in the expected\r
+ behaviour. */\r
+ if( xErrorDetected != pdFALSE )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ /* Return fail if either task is not still incrementing its loop counter. */\r
+ if( uxLastCount0 == xParameters[ 0 ].uxLoopCounter )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ uxLastCount0 = xParameters[ 0 ].uxLoopCounter;\r
+ }\r
+\r
+ if( uxLastCount1 == xParameters[ 1 ].uxLoopCounter )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ uxLastCount1 = xParameters[ 1 ].uxLoopCounter;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/**\r
+ * Create a single persistent task which periodically dynamically creates another\r
+ * two tasks. The original task is called the creator task, the two tasks it\r
+ * creates are called suicidal tasks.\r
+ *\r
+ * One of the created suicidal tasks kill one other suicidal task before killing\r
+ * itself - leaving just the original task remaining.\r
+ *\r
+ * The creator task must be spawned after all of the other demo application tasks\r
+ * as it keeps a check on the number of tasks under the scheduler control. The\r
+ * number of tasks it expects to see running should never be greater than the\r
+ * number of tasks that were in existence when the creator task was spawned, plus\r
+ * one set of four suicidal tasks. If this number is exceeded an error is flagged.\r
+ *\r
+ * \page DeathC death.c\r
+ * \ingroup DemoFiles\r
+ * <HR>\r
+ */\r
+\r
+/*\r
+Changes from V3.0.0\r
+ + CreationCount sizes changed from unsigned portBASE_TYPE to\r
+ unsigned short to minimize the risk of overflowing.\r
+ \r
+ + Reset of usLastCreationCount added\r
+ \r
+Changes from V3.1.0\r
+ + Changed the dummy calculation to use variables of type long, rather than\r
+ float. This allows the file to be used with ports that do not support\r
+ floating point.\r
+\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "death.h"\r
+\r
+#define deathSTACK_SIZE ( configMINIMAL_STACK_SIZE + 60 )\r
+\r
+/* The task originally created which is responsible for periodically dynamically\r
+creating another four tasks. */\r
+static portTASK_FUNCTION_PROTO( vCreateTasks, pvParameters );\r
+\r
+/* The task function of the dynamically created tasks. */\r
+static portTASK_FUNCTION_PROTO( vSuicidalTask, pvParameters );\r
+\r
+/* A variable which is incremented every time the dynamic tasks are created. This\r
+is used to check that the task is still running. */\r
+static volatile unsigned short usCreationCount = 0;\r
+\r
+/* Used to store the number of tasks that were originally running so the creator\r
+task can tell if any of the suicidal tasks have failed to die.\r
+*/\r
+static volatile unsigned portBASE_TYPE uxTasksRunningAtStart = 0;\r
+\r
+/* Tasks are deleted by the idle task. Under heavy load the idle task might\r
+not get much processing time, so it would be legitimate for several tasks to\r
+remain undeleted for a short period. */\r
+static const unsigned portBASE_TYPE uxMaxNumberOfExtraTasksRunning = 2;\r
+\r
+/* Used to store a handle to the task that should be killed by a suicidal task,\r
+before it kills itself. */\r
+xTaskHandle xCreatedTask;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+unsigned portBASE_TYPE *puxPriority;\r
+\r
+ /* Create the Creator tasks - passing in as a parameter the priority at which\r
+ the suicidal tasks should be created. */\r
+ puxPriority = ( unsigned portBASE_TYPE * ) pvPortMalloc( sizeof( unsigned portBASE_TYPE ) );\r
+ *puxPriority = uxPriority;\r
+\r
+ xTaskCreate( vCreateTasks, ( signed char * ) "CREATOR", deathSTACK_SIZE, ( void * ) puxPriority, uxPriority, NULL );\r
+\r
+ /* Record the number of tasks that are running now so we know if any of the\r
+ suicidal tasks have failed to be killed. */\r
+ uxTasksRunningAtStart = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();\r
+ \r
+ /* FreeRTOS.org versions before V3.0 started the idle-task as the very\r
+ first task. The idle task was then already included in uxTasksRunningAtStart.\r
+ From FreeRTOS V3.0 on, the idle task is started when the scheduler is\r
+ started. Therefore the idle task is not yet accounted for. We correct\r
+ this by increasing uxTasksRunningAtStart by 1. */\r
+ uxTasksRunningAtStart++;\r
+ \r
+ /* From FreeRTOS version 7.0.0 can optionally create a timer service task. \r
+ If this is done, then uxTasksRunningAtStart needs incrementing again as that\r
+ too is created when the scheduler is started. */\r
+ #if configUSE_TIMERS == 1\r
+ uxTasksRunningAtStart++;\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+ \r
+static portTASK_FUNCTION( vSuicidalTask, pvParameters )\r
+{\r
+volatile long l1, l2;\r
+xTaskHandle xTaskToKill;\r
+const portTickType xDelay = ( portTickType ) 200 / portTICK_RATE_MS;\r
+\r
+ if( pvParameters != NULL )\r
+ {\r
+ /* This task is periodically created four times. Two created tasks are\r
+ passed a handle to the other task so it can kill it before killing itself.\r
+ The other task is passed in null. */\r
+ xTaskToKill = *( xTaskHandle* )pvParameters;\r
+ }\r
+ else\r
+ {\r
+ xTaskToKill = NULL;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Do something random just to use some stack and registers. */\r
+ l1 = 2;\r
+ l2 = 89;\r
+ l2 *= l1;\r
+ vTaskDelay( xDelay );\r
+\r
+ if( xTaskToKill != NULL )\r
+ {\r
+ /* Make sure the other task has a go before we delete it. */\r
+ vTaskDelay( ( portTickType ) 0 );\r
+\r
+ /* Kill the other task that was created by vCreateTasks(). */\r
+ vTaskDelete( xTaskToKill );\r
+\r
+ /* Kill ourselves. */\r
+ vTaskDelete( NULL );\r
+ }\r
+ }\r
+}/*lint !e818 !e550 Function prototype must be as per standard for task functions. */\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCreateTasks, pvParameters )\r
+{\r
+const portTickType xDelay = ( portTickType ) 1000 / portTICK_RATE_MS;\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ uxPriority = *( unsigned portBASE_TYPE * ) pvParameters;\r
+ vPortFree( pvParameters );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just loop round, delaying then creating the four suicidal tasks. */\r
+ vTaskDelay( xDelay );\r
+\r
+ xCreatedTask = NULL;\r
+\r
+ xTaskCreate( vSuicidalTask, ( signed char * ) "SUICID1", configMINIMAL_STACK_SIZE, NULL, uxPriority, &xCreatedTask );\r
+ xTaskCreate( vSuicidalTask, ( signed char * ) "SUICID2", configMINIMAL_STACK_SIZE, &xCreatedTask, uxPriority, NULL );\r
+\r
+ ++usCreationCount;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that the creator task is still running and that there\r
+are not any more than four extra tasks. */\r
+portBASE_TYPE xIsCreateTaskStillRunning( void )\r
+{\r
+static unsigned short usLastCreationCount = 0xfff;\r
+portBASE_TYPE xReturn = pdTRUE;\r
+static unsigned portBASE_TYPE uxTasksRunningNow;\r
+\r
+ if( usLastCreationCount == usCreationCount )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ usLastCreationCount = usCreationCount;\r
+ }\r
+ \r
+ uxTasksRunningNow = ( unsigned portBASE_TYPE ) uxTaskGetNumberOfTasks();\r
+\r
+ if( uxTasksRunningNow < uxTasksRunningAtStart )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else if( ( uxTasksRunningNow - uxTasksRunningAtStart ) > uxMaxNumberOfExtraTasksRunning )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ /* Everything is okay. */\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * The first test creates three tasks - two counter tasks (one continuous count \r
+ * and one limited count) and one controller. A "count" variable is shared \r
+ * between all three tasks. The two counter tasks should never be in a "ready" \r
+ * state at the same time. The controller task runs at the same priority as \r
+ * the continuous count task, and at a lower priority than the limited count \r
+ * task.\r
+ *\r
+ * One counter task loops indefinitely, incrementing the shared count variable\r
+ * on each iteration. To ensure it has exclusive access to the variable it\r
+ * raises it's priority above that of the controller task before each \r
+ * increment, lowering it again to it's original priority before starting the\r
+ * next iteration.\r
+ *\r
+ * The other counter task increments the shared count variable on each\r
+ * iteration of it's loop until the count has reached a limit of 0xff - at\r
+ * which point it suspends itself. It will not start a new loop until the \r
+ * controller task has made it "ready" again by calling vTaskResume (). \r
+ * This second counter task operates at a higher priority than controller \r
+ * task so does not need to worry about mutual exclusion of the counter \r
+ * variable.\r
+ *\r
+ * The controller task is in two sections. The first section controls and\r
+ * monitors the continuous count task. When this section is operational the \r
+ * limited count task is suspended. Likewise, the second section controls \r
+ * and monitors the limited count task. When this section is operational the \r
+ * continuous count task is suspended.\r
+ *\r
+ * In the first section the controller task first takes a copy of the shared\r
+ * count variable. To ensure mutual exclusion on the count variable it\r
+ * suspends the continuous count task, resuming it again when the copy has been\r
+ * taken. The controller task then sleeps for a fixed period - during which\r
+ * the continuous count task will execute and increment the shared variable.\r
+ * When the controller task wakes it checks that the continuous count task\r
+ * has executed by comparing the copy of the shared variable with its current\r
+ * value. This time, to ensure mutual exclusion, the scheduler itself is \r
+ * suspended with a call to vTaskSuspendAll (). This is for demonstration \r
+ * purposes only and is not a recommended technique due to its inefficiency.\r
+ *\r
+ * After a fixed number of iterations the controller task suspends the \r
+ * continuous count task, and moves on to its second section.\r
+ *\r
+ * At the start of the second section the shared variable is cleared to zero.\r
+ * The limited count task is then woken from it's suspension by a call to\r
+ * vTaskResume (). As this counter task operates at a higher priority than\r
+ * the controller task the controller task should not run again until the\r
+ * shared variable has been counted up to the limited value causing the counter\r
+ * task to suspend itself. The next line after vTaskResume () is therefore\r
+ * a check on the shared variable to ensure everything is as expected.\r
+ *\r
+ *\r
+ * The second test consists of a couple of very simple tasks that post onto a \r
+ * queue while the scheduler is suspended. This test was added to test parts\r
+ * of the scheduler not exercised by the first test.\r
+ *\r
+ */\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "dynamic.h"\r
+\r
+/* Function that implements the "limited count" task as described above. */\r
+static portTASK_FUNCTION_PROTO( vLimitedIncrementTask, pvParameters );\r
+\r
+/* Function that implements the "continuous count" task as described above. */\r
+static portTASK_FUNCTION_PROTO( vContinuousIncrementTask, pvParameters );\r
+\r
+/* Function that implements the controller task as described above. */\r
+static portTASK_FUNCTION_PROTO( vCounterControlTask, pvParameters );\r
+\r
+static portTASK_FUNCTION_PROTO( vQueueReceiveWhenSuspendedTask, pvParameters );\r
+static portTASK_FUNCTION_PROTO( vQueueSendWhenSuspendedTask, pvParameters );\r
+\r
+/* Demo task specific constants. */\r
+#define priSTACK_SIZE ( configMINIMAL_STACK_SIZE )\r
+#define priSLEEP_TIME ( ( portTickType ) 128 / portTICK_RATE_MS )\r
+#define priLOOPS ( 5 )\r
+#define priMAX_COUNT ( ( unsigned long ) 0xff )\r
+#define priNO_BLOCK ( ( portTickType ) 0 )\r
+#define priSUSPENDED_QUEUE_LENGTH ( 1 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Handles to the two counter tasks. These could be passed in as parameters\r
+to the controller task to prevent them having to be file scope. */\r
+static xTaskHandle xContinousIncrementHandle, xLimitedIncrementHandle;\r
+\r
+/* The shared counter variable. This is passed in as a parameter to the two \r
+counter variables for demonstration purposes. */\r
+static unsigned long ulCounter;\r
+\r
+/* Variables used to check that the tasks are still operating without error.\r
+Each complete iteration of the controller task increments this variable\r
+provided no errors have been found. The variable maintaining the same value\r
+is therefore indication of an error. */\r
+static volatile unsigned short usCheckVariable = ( unsigned short ) 0;\r
+static volatile portBASE_TYPE xSuspendedQueueSendError = pdFALSE;\r
+static volatile portBASE_TYPE xSuspendedQueueReceiveError = pdFALSE;\r
+\r
+/* Queue used by the second test. */\r
+xQueueHandle xSuspendedTestQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+/*\r
+ * Start the three tasks as described at the top of the file.\r
+ * Note that the limited count task is given a higher priority.\r
+ */\r
+void vStartDynamicPriorityTasks( void )\r
+{\r
+ xSuspendedTestQueue = xQueueCreate( priSUSPENDED_QUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ /* vQueueAddToRegistry() adds the queue to the queue registry, if one is\r
+ in use. The queue registry is provided as a means for kernel aware \r
+ debuggers to locate queues and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( xSuspendedTestQueue, ( signed char * ) "Suspended_Test_Queue" );\r
+\r
+ xTaskCreate( vContinuousIncrementTask, ( signed char * ) "CNT_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY, &xContinousIncrementHandle );\r
+ xTaskCreate( vLimitedIncrementTask, ( signed char * ) "LIM_INC", priSTACK_SIZE, ( void * ) &ulCounter, tskIDLE_PRIORITY + 1, &xLimitedIncrementHandle );\r
+ xTaskCreate( vCounterControlTask, ( signed char * ) "C_CTRL", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueSendWhenSuspendedTask, ( signed char * ) "SUSP_TX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+ xTaskCreate( vQueueReceiveWhenSuspendedTask, ( signed char * ) "SUSP_RX", priSTACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just loops around incrementing the shared variable until the limit has been\r
+ * reached. Once the limit has been reached it suspends itself. \r
+ */\r
+static portTASK_FUNCTION( vLimitedIncrementTask, pvParameters )\r
+{\r
+unsigned long *pulCounter;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned long * ) pvParameters;\r
+\r
+ /* This will run before the control task, so the first thing it does is\r
+ suspend - the control task will resume it when ready. */\r
+ vTaskSuspend( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Just count up to a value then suspend. */\r
+ ( *pulCounter )++; \r
+ \r
+ if( *pulCounter >= priMAX_COUNT )\r
+ {\r
+ vTaskSuspend( NULL );\r
+ } \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Just keep counting the shared variable up. The control task will suspend\r
+ * this task when it wants.\r
+ */\r
+static portTASK_FUNCTION( vContinuousIncrementTask, pvParameters )\r
+{\r
+unsigned long *pulCounter;\r
+unsigned portBASE_TYPE uxOurPriority;\r
+\r
+ /* Take a pointer to the shared variable from the parameters passed into\r
+ the task. */\r
+ pulCounter = ( unsigned long * ) pvParameters;\r
+\r
+ /* Query our priority so we can raise it when exclusive access to the \r
+ shared variable is required. */\r
+ uxOurPriority = uxTaskPriorityGet( NULL );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Raise our priority above the controller task to ensure a context\r
+ switch does not occur while we are accessing this variable. */\r
+ vTaskPrioritySet( NULL, uxOurPriority + 1 );\r
+ ( *pulCounter )++; \r
+ vTaskPrioritySet( NULL, uxOurPriority );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Controller task as described above.\r
+ */\r
+static portTASK_FUNCTION( vCounterControlTask, pvParameters )\r
+{\r
+unsigned long ulLastCounter;\r
+short sLoops;\r
+short sError = pdFALSE;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Start with the counter at zero. */\r
+ ulCounter = ( unsigned long ) 0;\r
+\r
+ /* First section : */\r
+\r
+ /* Check the continuous count task is running. */\r
+ for( sLoops = 0; sLoops < priLOOPS; sLoops++ )\r
+ {\r
+ /* Suspend the continuous count task so we can take a mirror of the\r
+ shared variable without risk of corruption. */\r
+ vTaskSuspend( xContinousIncrementHandle );\r
+ ulLastCounter = ulCounter;\r
+ vTaskResume( xContinousIncrementHandle );\r
+ \r
+ /* Now delay to ensure the other task has processor time. */\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ /* Check the shared variable again. This time to ensure mutual \r
+ exclusion the whole scheduler will be locked. This is just for\r
+ demo purposes! */\r
+ vTaskSuspendAll();\r
+ {\r
+ if( ulLastCounter == ulCounter )\r
+ {\r
+ /* The shared variable has not changed. There is a problem\r
+ with the continuous count task so flag an error. */\r
+ sError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+\r
+ /* Second section: */\r
+\r
+ /* Suspend the continuous counter task so it stops accessing the shared variable. */\r
+ vTaskSuspend( xContinousIncrementHandle );\r
+\r
+ /* Reset the variable. */\r
+ ulCounter = ( unsigned long ) 0;\r
+\r
+ /* Resume the limited count task which has a higher priority than us.\r
+ We should therefore not return from this call until the limited count\r
+ task has suspended itself with a known value in the counter variable. */\r
+ vTaskResume( xLimitedIncrementHandle );\r
+\r
+ /* Does the counter variable have the expected value? */\r
+ if( ulCounter != priMAX_COUNT )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* If no errors have occurred then increment the check variable. */\r
+ portENTER_CRITICAL();\r
+ usCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Resume the continuous count task and do it all again. */\r
+ vTaskResume( xContinousIncrementHandle );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vQueueSendWhenSuspendedTask, pvParameters )\r
+{\r
+static unsigned long ulValueToSend = ( unsigned long ) 0;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ /* We must not block while the scheduler is suspended! */\r
+ if( xQueueSend( xSuspendedTestQueue, ( void * ) &ulValueToSend, priNO_BLOCK ) != pdTRUE )\r
+ {\r
+ xSuspendedQueueSendError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ vTaskDelay( priSLEEP_TIME );\r
+\r
+ ++ulValueToSend;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vQueueReceiveWhenSuspendedTask, pvParameters )\r
+{\r
+static unsigned long ulExpectedValue = ( unsigned long ) 0, ulReceivedValue;\r
+portBASE_TYPE xGotValue;\r
+\r
+ /* Just to stop warning messages. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ do\r
+ {\r
+ /* Suspending the scheduler here is fairly pointless and \r
+ undesirable for a normal application. It is done here purely\r
+ to test the scheduler. The inner xTaskResumeAll() should\r
+ never return pdTRUE as the scheduler is still locked by the\r
+ outer call. */\r
+ vTaskSuspendAll();\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ xGotValue = xQueueReceive( xSuspendedTestQueue, ( void * ) &ulReceivedValue, priNO_BLOCK );\r
+ }\r
+ if( xTaskResumeAll() )\r
+ {\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ } while( xGotValue == pdFALSE );\r
+\r
+ if( ulReceivedValue != ulExpectedValue )\r
+ {\r
+ xSuspendedQueueReceiveError = pdTRUE;\r
+ }\r
+\r
+ ++ulExpectedValue;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Called to check that all the created tasks are still running without error. */\r
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void )\r
+{\r
+/* Keep a history of the check variables so we know if it has been incremented \r
+since the last call. */\r
+static unsigned short usLastTaskCheck = ( unsigned short ) 0;\r
+portBASE_TYPE xReturn = pdTRUE;\r
+\r
+ /* Check the tasks are still running by ensuring the check variable\r
+ is still incrementing. */\r
+\r
+ if( usCheckVariable == usLastTaskCheck )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueSendError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ if( xSuspendedQueueReceiveError == pdTRUE )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ usLastTaskCheck = usCheckVariable;\r
+ return xReturn;\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef BLOCK_Q_H\r
+#define BLOCK_Q_H\r
+\r
+void vStartBlockingQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreBlockingQueuesStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef GEN_Q_TEST_H\r
+#define GEN_Q_TEST_H\r
+\r
+void vStartGenericQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreGenericQueueTasksStillRunning( void );\r
+\r
+#endif /* GEN_Q_TEST_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef POLLED_Q_H\r
+#define POLLED_Q_H\r
+\r
+void vStartPolledQueueTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xArePollingQueuesStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef BLOCK_TIME_TEST_H\r
+#define BLOCK_TIME_TEST_H\r
+\r
+void vCreateBlockTimeTasks( void );\r
+portBASE_TYPE xAreBlockTimeTestTasksStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef COUNT_SEMAPHORE_TEST_H\r
+#define COUNT_SEMAPHORE_TEST_H\r
+\r
+void vStartCountingSemaphoreTasks( void );\r
+portBASE_TYPE xAreCountingSemaphoreTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SUICIDE_TASK_H\r
+#define SUICIDE_TASK_H\r
+\r
+void vCreateSuicidalTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xIsCreateTaskStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef DYNAMIC_MANIPULATION_H\r
+#define DYNAMIC_MANIPULATION_H\r
+\r
+void vStartDynamicPriorityTasks( void );\r
+portBASE_TYPE xAreDynamicPriorityTasksStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef INTEGER_TASKS_H\r
+#define INTEGER_TASKS_H\r
+\r
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef RECURSIVE_MUTEX_TEST_H\r
+#define RECURSIVE_MUTEX_TEST_H\r
+\r
+void vStartRecursiveMutexTasks( void );\r
+portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SEMAPHORE_TEST_H\r
+#define SEMAPHORE_TEST_H\r
+\r
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority );\r
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void );\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * This version of integer. c is for use on systems that have limited stack\r
+ * space and no display facilities. The complete version can be found in\r
+ * the Demo/Common/Full directory.\r
+ *\r
+ * As with the full version, the tasks created in this file are a good test \r
+ * of the scheduler context switch mechanism. The processor has to access \r
+ * 32bit variables in two or four chunks (depending on the processor). The low \r
+ * priority of these tasks means there is a high probability that a context \r
+ * switch will occur mid calculation. See flop. c documentation for \r
+ * more information.\r
+ *\r
+ */\r
+\r
+/*\r
+Changes from V1.2.1\r
+\r
+ + The constants used in the calculations are larger to ensure the\r
+ optimiser does not truncate them to 16 bits.\r
+\r
+Changes from V1.2.3\r
+\r
+ + uxTaskCheck is now just used as a boolean. Instead of incrementing\r
+ the variable each cycle of the task, the variable is simply set to\r
+ true. sAreIntegerMathsTaskStillRunning() sets it back to false and\r
+ expects it to have been set back to true by the time it is called\r
+ again.\r
+ + A division has been included in the calculation.\r
+*/\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo program include files. */\r
+#include "integer.h"\r
+\r
+/* The constants used in the calculation. */\r
+#define intgCONST1 ( ( long ) 123 )\r
+#define intgCONST2 ( ( long ) 234567 )\r
+#define intgCONST3 ( ( long ) -3 )\r
+#define intgCONST4 ( ( long ) 7 )\r
+#define intgEXPECTED_ANSWER ( ( ( intgCONST1 + intgCONST2 ) * intgCONST3 ) / intgCONST4 )\r
+\r
+#define intgSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+/* As this is the minimal version, we will only create one task. */\r
+#define intgNUMBER_OF_TASKS ( 1 )\r
+\r
+/* The task function. Repeatedly performs a 32 bit calculation, checking the\r
+result against the expected result. If the result is incorrect then the\r
+context switch must have caused some corruption. */\r
+static portTASK_FUNCTION_PROTO( vCompeteingIntMathTask, pvParameters );\r
+\r
+/* Variables that are set to true within the calculation task to indicate\r
+that the task is still executing. The check task sets the variable back to\r
+false, flagging an error if the variable is still false the next time it\r
+is called. */\r
+static volatile signed portBASE_TYPE xTaskCheck[ intgNUMBER_OF_TASKS ] = { ( signed portBASE_TYPE ) pdFALSE };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartIntegerMathTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+short sTask;\r
+\r
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )\r
+ {\r
+ xTaskCreate( vCompeteingIntMathTask, ( signed char * ) "IntMath", intgSTACK_SIZE, ( void * ) &( xTaskCheck[ sTask ] ), uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( vCompeteingIntMathTask, pvParameters )\r
+{\r
+/* These variables are all effectively set to constants so they are volatile to\r
+ensure the compiler does not just get rid of them. */\r
+volatile long lValue;\r
+short sError = pdFALSE;\r
+volatile signed portBASE_TYPE *pxTaskHasExecuted;\r
+\r
+ /* Set a pointer to the variable we are going to set to true each\r
+ iteration. This is also a good test of the parameter passing mechanism\r
+ within each port. */\r
+ pxTaskHasExecuted = ( volatile signed portBASE_TYPE * ) pvParameters;\r
+\r
+ /* Keep performing a calculation and checking the result against a constant. */\r
+ for( ;; )\r
+ {\r
+ /* Perform the calculation. This will store partial value in\r
+ registers, resulting in a good test of the context switch mechanism. */\r
+ lValue = intgCONST1;\r
+ lValue += intgCONST2;\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ /* Finish off the calculation. */\r
+ lValue *= intgCONST3;\r
+ lValue /= intgCONST4;\r
+\r
+ /* If the calculation is found to be incorrect we stop setting the \r
+ TaskHasExecuted variable so the check task can see an error has \r
+ occurred. */\r
+ if( lValue != intgEXPECTED_ANSWER ) /*lint !e774 volatile used to prevent this being optimised out. */\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ /* We have not encountered any errors, so set the flag that show\r
+ we are still executing. This will be periodically cleared by\r
+ the check task. */\r
+ portENTER_CRITICAL();\r
+ *pxTaskHasExecuted = pdTRUE;\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ /* Yield in case cooperative scheduling is being used. */\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreIntegerMathsTaskStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn = pdTRUE;\r
+short sTask;\r
+\r
+ /* Check the maths tasks are still running by ensuring their check variables \r
+ are still being set to true. */\r
+ for( sTask = 0; sTask < intgNUMBER_OF_TASKS; sTask++ )\r
+ {\r
+ if( xTaskCheck[ sTask ] == pdFALSE )\r
+ {\r
+ /* The check has not incremented so an error exists. */\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ /* Reset the check variable so we can tell if it has been set by\r
+ the next time around. */\r
+ xTaskCheck[ sTask ] = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ The tasks defined on this page demonstrate the use of recursive mutexes.\r
+\r
+ For recursive mutex functionality the created mutex should be created using\r
+ xSemaphoreCreateRecursiveMutex(), then be manipulated\r
+ using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API\r
+ functions.\r
+\r
+ This demo creates three tasks all of which access the same recursive mutex:\r
+\r
+ prvRecursiveMutexControllingTask() has the highest priority so executes \r
+ first and grabs the mutex. It then performs some recursive accesses - \r
+ between each of which it sleeps for a short period to let the lower \r
+ priority tasks execute. When it has completed its demo functionality\r
+ it gives the mutex back before suspending itself.\r
+\r
+ prvRecursiveMutexBlockingTask() attempts to access the mutex by performing\r
+ a blocking 'take'. The blocking task has a lower priority than the \r
+ controlling task so by the time it executes the mutex has already been\r
+ taken by the controlling task, causing the blocking task to block. It \r
+ does not unblock until the controlling task has given the mutex back, \r
+ and it does not actually run until the controlling task has suspended \r
+ itself (due to the relative priorities). When it eventually does obtain\r
+ the mutex all it does is give the mutex back prior to also suspending \r
+ itself. At this point both the controlling task and the blocking task are \r
+ suspended.\r
+\r
+ prvRecursiveMutexPollingTask() runs at the idle priority. It spins round\r
+ a tight loop attempting to obtain the mutex with a non-blocking call. As\r
+ the lowest priority task it will not successfully obtain the mutex until\r
+ both the controlling and blocking tasks are suspended. Once it eventually \r
+ does obtain the mutex it first unsuspends both the controlling task and\r
+ blocking task prior to giving the mutex back - resulting in the polling\r
+ task temporarily inheriting the controlling tasks priority.\r
+*/\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "recmutex.h"\r
+\r
+/* Priorities assigned to the three tasks. */\r
+#define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 )\r
+\r
+/* The recursive call depth. */\r
+#define recmuMAX_COUNT ( 10 )\r
+\r
+/* Misc. */\r
+#define recmuSHORT_DELAY ( 20 / portTICK_RATE_MS )\r
+#define recmuNO_DELAY ( ( portTickType ) 0 )\r
+#define recmuTWO_TICK_DELAY ( ( portTickType ) 2 )\r
+\r
+/* The three tasks as described at the top of this file. */\r
+static void prvRecursiveMutexControllingTask( void *pvParameters );\r
+static void prvRecursiveMutexBlockingTask( void *pvParameters );\r
+static void prvRecursiveMutexPollingTask( void *pvParameters );\r
+\r
+/* The mutex used by the demo. */\r
+static xSemaphoreHandle xMutex;\r
+\r
+/* Variables used to detect and latch errors. */\r
+static volatile portBASE_TYPE xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE;\r
+static volatile unsigned portBASE_TYPE uxControllingCycles = 0, uxBlockingCycles = 0, uxPollingCycles = 0;\r
+\r
+/* Handles of the two higher priority tasks, required so they can be resumed \r
+(unsuspended). */\r
+static xTaskHandle xControllingTaskHandle, xBlockingTaskHandle;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartRecursiveMutexTasks( void )\r
+{\r
+ /* Just creates the mutex and the three tasks. */\r
+\r
+ xMutex = xSemaphoreCreateRecursiveMutex();\r
+\r
+ /* vQueueAddToRegistry() adds the mutex to the registry, if one is\r
+ in use. The registry is provided as a means for kernel aware \r
+ debuggers to locate mutex and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( ( xQueueHandle ) xMutex, ( signed portCHAR * ) "Recursive_Mutex" );\r
+\r
+\r
+ if( xMutex != NULL )\r
+ {\r
+ xTaskCreate( prvRecursiveMutexControllingTask, ( signed portCHAR * ) "Rec1", configMINIMAL_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle );\r
+ xTaskCreate( prvRecursiveMutexBlockingTask, ( signed portCHAR * ) "Rec2", configMINIMAL_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle );\r
+ xTaskCreate( prvRecursiveMutexPollingTask, ( signed portCHAR * ) "Rec3", configMINIMAL_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRecursiveMutexControllingTask( void *pvParameters )\r
+{\r
+unsigned portBASE_TYPE ux;\r
+\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Should not be able to 'give' the mutex, as we have not yet 'taken'\r
+ it. The first time through, the mutex will not have been used yet,\r
+ subsequent times through, at this point the mutex will be held by the\r
+ polling task. */\r
+ if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ for( ux = 0; ux < recmuMAX_COUNT; ux++ )\r
+ {\r
+ /* We should now be able to take the mutex as many times as\r
+ we like.\r
+ \r
+ The first time through the mutex will be immediately available, on\r
+ subsequent times through the mutex will be held by the polling task\r
+ at this point and this Take will cause the polling task to inherit\r
+ the priority of this task. In this case the block time must be\r
+ long enough to ensure the polling task will execute again before the\r
+ block time expires. If the block time does expire then the error\r
+ flag will be set here. */\r
+ if( xSemaphoreTakeRecursive( xMutex, recmuTWO_TICK_DELAY ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Ensure the other task attempting to access the mutex (and the\r
+ other demo tasks) are able to execute to ensure they either block\r
+ (where a block time is specified) or return an error (where no \r
+ block time is specified) as the mutex is held by this task. */\r
+ vTaskDelay( recmuSHORT_DELAY );\r
+ }\r
+\r
+ /* For each time we took the mutex, give it back. */\r
+ for( ux = 0; ux < recmuMAX_COUNT; ux++ )\r
+ {\r
+ /* Ensure the other task attempting to access the mutex (and the\r
+ other demo tasks) are able to execute. */\r
+ vTaskDelay( recmuSHORT_DELAY );\r
+\r
+ /* We should now be able to give the mutex as many times as we\r
+ took it. When the mutex is available again the Blocking task\r
+ should be unblocked but not run because it has a lower priority\r
+ than this task. The polling task should also not run at this point\r
+ as it too has a lower priority than this task. */\r
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Having given it back the same number of times as it was taken, we\r
+ should no longer be the mutex owner, so the next give sh ould fail. */\r
+ if( xSemaphoreGiveRecursive( xMutex ) == pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Keep count of the number of cycles this task has performed so a \r
+ stall can be detected. */\r
+ uxControllingCycles++;\r
+\r
+ /* Suspend ourselves to the blocking task can execute. */\r
+ xControllingIsSuspended = pdTRUE;\r
+ vTaskSuspend( NULL );\r
+ xControllingIsSuspended = pdFALSE;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRecursiveMutexBlockingTask( void *pvParameters )\r
+{\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* This task will run while the controlling task is blocked, and the\r
+ controlling task will block only once it has the mutex - therefore\r
+ this call should block until the controlling task has given up the \r
+ mutex, and not actually execute past this call until the controlling \r
+ task is suspended. */\r
+ if( xSemaphoreTakeRecursive( xMutex, portMAX_DELAY ) == pdPASS )\r
+ {\r
+ if( xControllingIsSuspended != pdTRUE )\r
+ {\r
+ /* Did not expect to execute until the controlling task was\r
+ suspended. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* Give the mutex back before suspending ourselves to allow\r
+ the polling task to obtain the mutex. */\r
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ xBlockingIsSuspended = pdTRUE;\r
+ vTaskSuspend( NULL );\r
+ xBlockingIsSuspended = pdFALSE;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We should not leave the xSemaphoreTakeRecursive() function\r
+ until the mutex was obtained. */\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* The controlling and blocking tasks should be in lock step. */\r
+ if( uxControllingCycles != ( uxBlockingCycles + 1 ) )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+\r
+ /* Keep count of the number of cycles this task has performed so a \r
+ stall can be detected. */\r
+ uxBlockingCycles++;\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvRecursiveMutexPollingTask( void *pvParameters )\r
+{\r
+ /* Just to remove compiler warning. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Keep attempting to obtain the mutex. We should only obtain it when\r
+ the blocking task has suspended itself, which in turn should only\r
+ happen when the controlling task is also suspended. */\r
+ if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS )\r
+ {\r
+ /* Is the blocking task suspended? */\r
+ if( ( xBlockingIsSuspended != pdTRUE ) || ( xControllingIsSuspended != pdTRUE ) )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ /* Keep count of the number of cycles this task has performed \r
+ so a stall can be detected. */\r
+ uxPollingCycles++;\r
+\r
+ /* We can resume the other tasks here even though they have a\r
+ higher priority than the polling task. When they execute they\r
+ will attempt to obtain the mutex but fail because the polling\r
+ task is still the mutex holder. The polling task (this task)\r
+ will then inherit the higher priority. The Blocking task will\r
+ block indefinitely when it attempts to obtain the mutex, the\r
+ Controlling task will only block for a fixed period and an\r
+ error will be latched if the polling task has not returned the\r
+ mutex by the time this fixed period has expired. */\r
+ vTaskResume( xBlockingTaskHandle );\r
+ vTaskResume( xControllingTaskHandle );\r
+ \r
+ /* The other two tasks should now have executed and no longer\r
+ be suspended. */\r
+ if( ( xBlockingIsSuspended == pdTRUE ) || ( xControllingIsSuspended == pdTRUE ) )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ } \r
+ \r
+ /* Release the mutex, disinheriting the higher priority again. */\r
+ if( xSemaphoreGiveRecursive( xMutex ) != pdPASS )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ #if configUSE_PREEMPTION == 0\r
+ {\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+static unsigned portBASE_TYPE uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0;\r
+\r
+ /* Is the controlling task still cycling? */\r
+ if( uxLastControllingCycles == uxControllingCycles )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ uxLastControllingCycles = uxControllingCycles;\r
+ }\r
+\r
+ /* Is the blocking task still cycling? */\r
+ if( uxLastBlockingCycles == uxBlockingCycles )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ uxLastBlockingCycles = uxBlockingCycles;\r
+ }\r
+\r
+ /* Is the polling task still cycling? */\r
+ if( uxLastPollingCycles == uxPollingCycles )\r
+ {\r
+ xErrorOccurred = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ uxLastPollingCycles = uxPollingCycles;\r
+ }\r
+\r
+ if( xErrorOccurred == pdTRUE )\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * Creates two sets of two tasks. The tasks within a set share a variable, access \r
+ * to which is guarded by a semaphore.\r
+ * \r
+ * Each task starts by attempting to obtain the semaphore. On obtaining a \r
+ * semaphore a task checks to ensure that the guarded variable has an expected \r
+ * value. It then clears the variable to zero before counting it back up to the \r
+ * expected value in increments of 1. After each increment the variable is checked \r
+ * to ensure it contains the value to which it was just set. When the starting \r
+ * value is again reached the task releases the semaphore giving the other task in \r
+ * the set a chance to do exactly the same thing. The starting value is high \r
+ * enough to ensure that a tick is likely to occur during the incrementing loop.\r
+ *\r
+ * An error is flagged if at any time during the process a shared variable is \r
+ * found to have a value other than that expected. Such an occurrence would \r
+ * suggest an error in the mutual exclusion mechanism by which access to the \r
+ * variable is restricted.\r
+ *\r
+ * The first set of two tasks poll their semaphore. The second set use blocking \r
+ * calls.\r
+ *\r
+ */\r
+\r
+\r
+#include <stdlib.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Demo app include files. */\r
+#include "semtest.h"\r
+\r
+/* The value to which the shared variables are counted. */\r
+#define semtstBLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xfff )\r
+#define semtstNON_BLOCKING_EXPECTED_VALUE ( ( unsigned long ) 0xff )\r
+\r
+#define semtstSTACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+#define semtstNUM_TASKS ( 4 )\r
+\r
+#define semtstDELAY_FACTOR ( ( portTickType ) 10 )\r
+\r
+/* The task function as described at the top of the file. */\r
+static portTASK_FUNCTION_PROTO( prvSemaphoreTest, pvParameters );\r
+\r
+/* Structure used to pass parameters to each task. */\r
+typedef struct SEMAPHORE_PARAMETERS\r
+{\r
+ xSemaphoreHandle xSemaphore;\r
+ volatile unsigned long *pulSharedVariable;\r
+ portTickType xBlockTime;\r
+} xSemaphoreParameters;\r
+\r
+/* Variables used to check that all the tasks are still running without errors. */\r
+static volatile short sCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+static volatile short sNextCheckVariable = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vStartSemaphoreTasks( unsigned portBASE_TYPE uxPriority )\r
+{\r
+xSemaphoreParameters *pxFirstSemaphoreParameters, *pxSecondSemaphoreParameters;\r
+const portTickType xBlockTime = ( portTickType ) 100;\r
+\r
+ /* Create the structure used to pass parameters to the first two tasks. */\r
+ pxFirstSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+\r
+ if( pxFirstSemaphoreParameters != NULL )\r
+ {\r
+ /* Create the semaphore used by the first two tasks. */\r
+ vSemaphoreCreateBinary( pxFirstSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxFirstSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ /* Create the variable which is to be shared by the first two tasks. */\r
+ pxFirstSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );\r
+\r
+ /* Initialise the share variable to the value the tasks expect. */\r
+ *( pxFirstSemaphoreParameters->pulSharedVariable ) = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+\r
+ /* The first two tasks do not block on semaphore calls. */\r
+ pxFirstSemaphoreParameters->xBlockTime = ( portTickType ) 0;\r
+\r
+ /* Spawn the first two tasks. As they poll they operate at the idle priority. */\r
+ xTaskCreate( prvSemaphoreTest, ( signed char * ) "PolSEM1", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, ( signed char * ) "PolSEM2", semtstSTACK_SIZE, ( void * ) pxFirstSemaphoreParameters, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+\r
+ /* Do exactly the same to create the second set of tasks, only this time \r
+ provide a block time for the semaphore calls. */\r
+ pxSecondSemaphoreParameters = ( xSemaphoreParameters * ) pvPortMalloc( sizeof( xSemaphoreParameters ) );\r
+ if( pxSecondSemaphoreParameters != NULL )\r
+ {\r
+ vSemaphoreCreateBinary( pxSecondSemaphoreParameters->xSemaphore );\r
+\r
+ if( pxSecondSemaphoreParameters->xSemaphore != NULL )\r
+ {\r
+ pxSecondSemaphoreParameters->pulSharedVariable = ( unsigned long * ) pvPortMalloc( sizeof( unsigned long ) );\r
+ *( pxSecondSemaphoreParameters->pulSharedVariable ) = semtstBLOCKING_EXPECTED_VALUE;\r
+ pxSecondSemaphoreParameters->xBlockTime = xBlockTime / portTICK_RATE_MS;\r
+\r
+ xTaskCreate( prvSemaphoreTest, ( signed char * ) "BlkSEM1", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ xTaskCreate( prvSemaphoreTest, ( signed char * ) "BlkSEM2", semtstSTACK_SIZE, ( void * ) pxSecondSemaphoreParameters, uxPriority, ( xTaskHandle * ) NULL );\r
+ }\r
+ }\r
+\r
+ /* vQueueAddToRegistry() adds the semaphore to the registry, if one is\r
+ in use. The registry is provided as a means for kernel aware \r
+ debuggers to locate semaphores and has no purpose if a kernel aware debugger\r
+ is not being used. The call to vQueueAddToRegistry() will be removed\r
+ by the pre-processor if configQUEUE_REGISTRY_SIZE is not defined or is \r
+ defined to be less than 1. */\r
+ vQueueAddToRegistry( ( xQueueHandle ) pxFirstSemaphoreParameters->xSemaphore, ( signed char * ) "Counting_Sem_1" );\r
+ vQueueAddToRegistry( ( xQueueHandle ) pxSecondSemaphoreParameters->xSemaphore, ( signed char * ) "Counting_Sem_2" );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTASK_FUNCTION( prvSemaphoreTest, pvParameters )\r
+{\r
+xSemaphoreParameters *pxParameters;\r
+volatile unsigned long *pulSharedVariable, ulExpectedValue;\r
+unsigned long ulCounter;\r
+short sError = pdFALSE, sCheckVariableToUse;\r
+\r
+ /* See which check variable to use. sNextCheckVariable is not semaphore \r
+ protected! */\r
+ portENTER_CRITICAL();\r
+ sCheckVariableToUse = sNextCheckVariable;\r
+ sNextCheckVariable++;\r
+ portEXIT_CRITICAL();\r
+\r
+ /* A structure is passed in as the parameter. This contains the shared \r
+ variable being guarded. */\r
+ pxParameters = ( xSemaphoreParameters * ) pvParameters;\r
+ pulSharedVariable = pxParameters->pulSharedVariable;\r
+\r
+ /* If we are blocking we use a much higher count to ensure loads of context\r
+ switches occur during the count. */\r
+ if( pxParameters->xBlockTime > ( portTickType ) 0 )\r
+ {\r
+ ulExpectedValue = semtstBLOCKING_EXPECTED_VALUE;\r
+ }\r
+ else\r
+ {\r
+ ulExpectedValue = semtstNON_BLOCKING_EXPECTED_VALUE;\r
+ }\r
+\r
+ for( ;; )\r
+ {\r
+ /* Try to obtain the semaphore. */\r
+ if( xSemaphoreTake( pxParameters->xSemaphore, pxParameters->xBlockTime ) == pdPASS )\r
+ {\r
+ /* We have the semaphore and so expect any other tasks using the\r
+ shared variable to have left it in the state we expect to find\r
+ it. */\r
+ if( *pulSharedVariable != ulExpectedValue )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+ \r
+ /* Clear the variable, then count it back up to the expected value\r
+ before releasing the semaphore. Would expect a context switch or\r
+ two during this time. */\r
+ for( ulCounter = ( unsigned long ) 0; ulCounter <= ulExpectedValue; ulCounter++ )\r
+ {\r
+ *pulSharedVariable = ulCounter;\r
+ if( *pulSharedVariable != ulCounter )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Release the semaphore, and if no errors have occurred increment the check\r
+ variable. */\r
+ if( xSemaphoreGive( pxParameters->xSemaphore ) == pdFALSE )\r
+ {\r
+ sError = pdTRUE;\r
+ }\r
+\r
+ if( sError == pdFALSE )\r
+ {\r
+ if( sCheckVariableToUse < semtstNUM_TASKS )\r
+ {\r
+ ( sCheckVariables[ sCheckVariableToUse ] )++;\r
+ }\r
+ }\r
+\r
+ /* If we have a block time then we are running at a priority higher\r
+ than the idle priority. This task takes a long time to complete\r
+ a cycle (deliberately so to test the guarding) so will be starving\r
+ out lower priority tasks. Block for some time to allow give lower\r
+ priority tasks some processor time. */\r
+ vTaskDelay( pxParameters->xBlockTime * semtstDELAY_FACTOR );\r
+ }\r
+ else\r
+ {\r
+ if( pxParameters->xBlockTime == ( portTickType ) 0 )\r
+ {\r
+ /* We have not got the semaphore yet, so no point using the\r
+ processor. We are not blocking when attempting to obtain the\r
+ semaphore. */\r
+ taskYIELD();\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This is called to check that all the created tasks are still running. */\r
+portBASE_TYPE xAreSemaphoreTasksStillRunning( void )\r
+{\r
+static short sLastCheckVariables[ semtstNUM_TASKS ] = { 0 };\r
+portBASE_TYPE xTask, xReturn = pdTRUE;\r
+\r
+ for( xTask = 0; xTask < semtstNUM_TASKS; xTask++ )\r
+ {\r
+ if( sLastCheckVariables[ xTask ] == sCheckVariables[ xTask ] )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ sLastCheckVariables[ xTask ] = sCheckVariables[ xTask ];\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef INC_FREERTOS_H\r
+#define INC_FREERTOS_H\r
+\r
+\r
+/*\r
+ * Include the generic headers required for the FreeRTOS port being used.\r
+ */\r
+#include <stddef.h>\r
+\r
+/* Basic FreeRTOS definitions. */\r
+#include "projdefs.h"\r
+\r
+/* Application specific configuration options. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/* Definitions specific to the port being used. */\r
+#include "portable.h"\r
+\r
+\r
+/* Defines the prototype to which the application task hook function must\r
+conform. */\r
+typedef portBASE_TYPE (*pdTASK_HOOK_CODE)( void * );\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Check all the required application specific macros have been defined.\r
+ * These macros are application specific and (as downloaded) are defined\r
+ * within FreeRTOSConfig.h.\r
+ */\r
+\r
+#ifndef configUSE_PREEMPTION\r
+ #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_IDLE_HOOK\r
+ #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_TICK_HOOK\r
+ #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_CO_ROUTINES\r
+ #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskPrioritySet\r
+ #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_uxTaskPriorityGet\r
+ #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelete \r
+ #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskSuspend \r
+ #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelayUntil\r
+ #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelay\r
+ #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_16_BIT_TICKS\r
+ #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskGetIdleTaskHandle\r
+ #define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#endif\r
+\r
+#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle\r
+ #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0\r
+#endif\r
+\r
+#ifndef INCLUDE_xQueueGetMutexHolder\r
+ #define INCLUDE_xQueueGetMutexHolder 0\r
+#endif\r
+\r
+#ifndef INCLUDE_pcTaskGetTaskName\r
+ #define INCLUDE_pcTaskGetTaskName 0\r
+#endif\r
+\r
+#ifndef configUSE_APPLICATION_TASK_TAG\r
+ #define configUSE_APPLICATION_TASK_TAG 0\r
+#endif\r
+\r
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark\r
+ #define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#endif\r
+\r
+#ifndef configUSE_RECURSIVE_MUTEXES\r
+ #define configUSE_RECURSIVE_MUTEXES 0\r
+#endif\r
+\r
+#ifndef configUSE_MUTEXES\r
+ #define configUSE_MUTEXES 0\r
+#endif\r
+\r
+#ifndef configUSE_TIMERS\r
+ #define configUSE_TIMERS 0\r
+#endif\r
+\r
+#ifndef configUSE_COUNTING_SEMAPHORES\r
+ #define configUSE_COUNTING_SEMAPHORES 0\r
+#endif\r
+\r
+#ifndef configUSE_ALTERNATIVE_API\r
+ #define configUSE_ALTERNATIVE_API 0\r
+#endif\r
+\r
+#ifndef portCRITICAL_NESTING_IN_TCB\r
+ #define portCRITICAL_NESTING_IN_TCB 0\r
+#endif\r
+\r
+#ifndef configMAX_TASK_NAME_LEN\r
+ #define configMAX_TASK_NAME_LEN 16\r
+#endif\r
+\r
+#ifndef configIDLE_SHOULD_YIELD\r
+ #define configIDLE_SHOULD_YIELD 1\r
+#endif\r
+\r
+#if configMAX_TASK_NAME_LEN < 1\r
+ #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskResumeFromISR\r
+ #define INCLUDE_xTaskResumeFromISR 1\r
+#endif\r
+\r
+#ifndef configASSERT\r
+ #define configASSERT( x )\r
+#endif\r
+\r
+#ifndef portALIGNMENT_ASSERT_pxCurrentTCB\r
+ #define portALIGNMENT_ASSERT_pxCurrentTCB configASSERT\r
+#endif\r
+\r
+/* The timers module relies on xTaskGetSchedulerState(). */\r
+#if configUSE_TIMERS == 1\r
+\r
+ #ifndef configTIMER_TASK_PRIORITY\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\r
+ #endif /* configTIMER_TASK_PRIORITY */\r
+\r
+ #ifndef configTIMER_QUEUE_LENGTH\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\r
+ #endif /* configTIMER_QUEUE_LENGTH */\r
+\r
+ #ifndef configTIMER_TASK_STACK_DEPTH\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\r
+ #endif /* configTIMER_TASK_STACK_DEPTH */\r
+\r
+#endif /* configUSE_TIMERS */\r
+\r
+#ifndef INCLUDE_xTaskGetSchedulerState\r
+ #define INCLUDE_xTaskGetSchedulerState 0\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle\r
+ #define INCLUDE_xTaskGetCurrentTaskHandle 0\r
+#endif\r
+\r
+\r
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR\r
+ #define portSET_INTERRUPT_MASK_FROM_ISR() 0\r
+#endif\r
+\r
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\r
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\r
+#endif\r
+\r
+#ifndef portCLEAN_UP_TCB\r
+ #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB\r
+#endif\r
+\r
+#ifndef portSETUP_TCB\r
+ #define portSETUP_TCB( pxTCB ) ( void ) pxTCB\r
+#endif\r
+\r
+#ifndef configQUEUE_REGISTRY_SIZE\r
+ #define configQUEUE_REGISTRY_SIZE 0U\r
+#endif\r
+\r
+#if ( configQUEUE_REGISTRY_SIZE < 1 )\r
+ #define vQueueAddToRegistry( xQueue, pcName )\r
+ #define vQueueUnregisterQueue( xQueue )\r
+#endif\r
+\r
+#ifndef portPOINTER_SIZE_TYPE\r
+ #define portPOINTER_SIZE_TYPE unsigned long\r
+#endif\r
+\r
+/* Remove any unused trace macros. */\r
+#ifndef traceSTART\r
+ /* Used to perform any necessary initialisation - for example, open a file\r
+ into which trace is to be written. */\r
+ #define traceSTART()\r
+#endif\r
+\r
+#ifndef traceEND\r
+ /* Use to close a trace, for example close a file into which trace has been\r
+ written. */\r
+ #define traceEND()\r
+#endif\r
+\r
+#ifndef traceTASK_SWITCHED_IN\r
+ /* Called after a task has been selected to run. pxCurrentTCB holds a pointer\r
+ to the task control block of the selected task. */\r
+ #define traceTASK_SWITCHED_IN()\r
+#endif\r
+\r
+#ifndef traceTASK_SWITCHED_OUT\r
+ /* Called before a task has been selected to run. pxCurrentTCB holds a pointer\r
+ to the task control block of the task being switched out. */\r
+ #define traceTASK_SWITCHED_OUT()\r
+#endif\r
+\r
+#ifndef traceTASK_PRIORITY_INHERIT\r
+ /* Called when a task attempts to take a mutex that is already held by a\r
+ lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task\r
+ that holds the mutex. uxInheritedPriority is the priority the mutex holder\r
+ will inherit (the priority of the task that is attempting to obtain the\r
+ muted. */\r
+ #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )\r
+#endif\r
+\r
+#ifndef traceTASK_PRIORITY_DISINHERIT\r
+ /* Called when a task releases a mutex, the holding of which had resulted in\r
+ the task inheriting the priority of a higher priority task. \r
+ pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the\r
+ mutex. uxOriginalPriority is the task's configured (base) priority. */\r
+ #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )\r
+#endif\r
+\r
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\r
+ /* Task is about to block because it cannot read from a\r
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore\r
+ upon which the read was attempted. pxCurrentTCB points to the TCB of the\r
+ task that attempted the read. */\r
+ #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceBLOCKING_ON_QUEUE_SEND\r
+ /* Task is about to block because it cannot write to a\r
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore\r
+ upon which the write was attempted. pxCurrentTCB points to the TCB of the\r
+ task that attempted the write. */\r
+ #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\r
+#endif\r
+\r
+#ifndef configCHECK_FOR_STACK_OVERFLOW\r
+ #define configCHECK_FOR_STACK_OVERFLOW 0\r
+#endif\r
+\r
+/* The following event macros are embedded in the kernel API calls. */\r
+\r
+#ifndef traceMOVED_TASK_TO_READY_STATE\r
+ #define traceMOVED_TASK_TO_READY_STATE( pxTCB )\r
+#endif\r
+\r
+#ifndef traceQUEUE_CREATE \r
+ #define traceQUEUE_CREATE( pxNewQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_CREATE_FAILED\r
+ #define traceQUEUE_CREATE_FAILED( ucQueueType )\r
+#endif\r
+\r
+#ifndef traceCREATE_MUTEX\r
+ #define traceCREATE_MUTEX( pxNewQueue )\r
+#endif\r
+\r
+#ifndef traceCREATE_MUTEX_FAILED\r
+ #define traceCREATE_MUTEX_FAILED()\r
+#endif\r
+\r
+#ifndef traceGIVE_MUTEX_RECURSIVE\r
+ #define traceGIVE_MUTEX_RECURSIVE( pxMutex )\r
+#endif\r
+\r
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\r
+ #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\r
+#endif\r
+\r
+#ifndef traceTAKE_MUTEX_RECURSIVE\r
+ #define traceTAKE_MUTEX_RECURSIVE( pxMutex )\r
+#endif\r
+\r
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\r
+ #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\r
+#endif\r
+\r
+#ifndef traceCREATE_COUNTING_SEMAPHORE\r
+ #define traceCREATE_COUNTING_SEMAPHORE()\r
+#endif\r
+\r
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\r
+ #define traceCREATE_COUNTING_SEMAPHORE_FAILED()\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND\r
+ #define traceQUEUE_SEND( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FAILED\r
+ #define traceQUEUE_SEND_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE\r
+ #define traceQUEUE_RECEIVE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_PEEK\r
+ #define traceQUEUE_PEEK( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FAILED\r
+ #define traceQUEUE_RECEIVE_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FROM_ISR\r
+ #define traceQUEUE_SEND_FROM_ISR( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\r
+ #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FROM_ISR\r
+ #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\r
+ #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_DELETE\r
+ #define traceQUEUE_DELETE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceTASK_CREATE\r
+ #define traceTASK_CREATE( pxNewTCB )\r
+#endif\r
+\r
+#ifndef traceTASK_CREATE_FAILED\r
+ #define traceTASK_CREATE_FAILED()\r
+#endif\r
+\r
+#ifndef traceTASK_DELETE\r
+ #define traceTASK_DELETE( pxTaskToDelete )\r
+#endif\r
+\r
+#ifndef traceTASK_DELAY_UNTIL\r
+ #define traceTASK_DELAY_UNTIL()\r
+#endif\r
+\r
+#ifndef traceTASK_DELAY\r
+ #define traceTASK_DELAY()\r
+#endif\r
+\r
+#ifndef traceTASK_PRIORITY_SET\r
+ #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\r
+#endif\r
+\r
+#ifndef traceTASK_SUSPEND\r
+ #define traceTASK_SUSPEND( pxTaskToSuspend )\r
+#endif\r
+\r
+#ifndef traceTASK_RESUME\r
+ #define traceTASK_RESUME( pxTaskToResume )\r
+#endif\r
+\r
+#ifndef traceTASK_RESUME_FROM_ISR\r
+ #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\r
+#endif\r
+\r
+#ifndef traceTASK_INCREMENT_TICK\r
+ #define traceTASK_INCREMENT_TICK( xTickCount )\r
+#endif\r
+\r
+#ifndef traceTIMER_CREATE\r
+ #define traceTIMER_CREATE( pxNewTimer )\r
+#endif\r
+\r
+#ifndef traceTIMER_CREATE_FAILED\r
+ #define traceTIMER_CREATE_FAILED()\r
+#endif\r
+\r
+#ifndef traceTIMER_COMMAND_SEND\r
+ #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\r
+#endif\r
+\r
+#ifndef traceTIMER_EXPIRED\r
+ #define traceTIMER_EXPIRED( pxTimer )\r
+#endif\r
+\r
+#ifndef traceTIMER_COMMAND_RECEIVED\r
+ #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\r
+#endif\r
+\r
+#ifndef configGENERATE_RUN_TIME_STATS\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+#endif\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r
+ #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\r
+ #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\r
+\r
+ #ifndef portGET_RUN_TIME_COUNTER_VALUE\r
+ #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information.\r
+ #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\r
+ #endif /* portGET_RUN_TIME_COUNTER_VALUE */\r
+\r
+#endif /* configGENERATE_RUN_TIME_STATS */\r
+\r
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#endif\r
+\r
+#ifndef configUSE_MALLOC_FAILED_HOOK\r
+ #define configUSE_MALLOC_FAILED_HOOK 0\r
+#endif\r
+\r
+#ifndef portPRIVILEGE_BIT\r
+ #define portPRIVILEGE_BIT ( ( unsigned portBASE_TYPE ) 0x00 )\r
+#endif\r
+\r
+#ifndef portYIELD_WITHIN_API\r
+ #define portYIELD_WITHIN_API portYIELD\r
+#endif\r
+\r
+#ifndef pvPortMallocAligned\r
+ #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )\r
+#endif\r
+\r
+#ifndef vPortFreeAligned\r
+ #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )\r
+#endif\r
+\r
+#endif /* INC_FREERTOS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef STACK_MACROS_H\r
+#define STACK_MACROS_H\r
+\r
+/*\r
+ * Call the stack overflow hook function if the stack of the task being swapped\r
+ * out is currently overflowed, or looks like it might have overflowed in the\r
+ * past.\r
+ *\r
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\r
+ * the current stack state only - comparing the current top of stack value to\r
+ * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\r
+ * will also cause the last few stack bytes to be checked to ensure the value\r
+ * to which the bytes were set when the task was created have not been\r
+ * overwritten. Note this second test does not guarantee that an overflowed\r
+ * stack will always be recognised.\r
+ */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configCHECK_FOR_STACK_OVERFLOW == 0 )\r
+\r
+ /* FreeRTOSConfig.h is not set to check for stack overflows. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configCHECK_FOR_STACK_OVERFLOW == 1 )\r
+\r
+ /* FreeRTOSConfig.h is only set to use the first method of\r
+ overflow checking. */\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )\r
+\r
+ /* Only the current stack state is to be checked. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ /* Is the currently saved stack pointer within the stack limit? */ \\r
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )\r
+\r
+ /* Only the current stack state is to be checked. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ \\r
+ /* Is the currently saved stack pointer within the stack limit? */ \\r
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\r
+\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \\r
+ \\r
+ \\r
+ /* Has the extremity of the task stack ever been written over? */ \\r
+ if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\r
+\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ char *pcEndOfStack = ( char * ) pxCurrentTCB->pxEndOfStack; \\r
+ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \\r
+ \\r
+ \\r
+ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \\r
+ \\r
+ /* Has the extremity of the task stack ever been written over? */ \\r
+ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r
+/*-----------------------------------------------------------*/\r
+\r
+#endif /* STACK_MACROS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef CO_ROUTINE_H\r
+#define CO_ROUTINE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include croutine.h"\r
+#endif\r
+\r
+#include "list.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Used to hide the implementation of the co-routine control block. The\r
+control block structure however has to be included in the header due to\r
+the macro implementation of the co-routine functionality. */\r
+typedef void * xCoRoutineHandle;\r
+\r
+/* Defines the prototype to which co-routine functions must conform. */\r
+typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE );\r
+\r
+typedef struct corCoRoutineControlBlock\r
+{\r
+ crCOROUTINE_CODE pxCoRoutineFunction;\r
+ xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */\r
+ unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\r
+ unsigned short uxState; /*< Used internally by the co-routine implementation. */\r
+} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ portBASE_TYPE xCoRoutineCreate(\r
+ crCOROUTINE_CODE pxCoRoutineCode,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ unsigned portBASE_TYPE uxIndex\r
+ );</pre>\r
+ *\r
+ * Create a new co-routine and add it to the list of co-routines that are\r
+ * ready to run.\r
+ *\r
+ * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine\r
+ * functions require special syntax - see the co-routine section of the WEB\r
+ * documentation for more information.\r
+ *\r
+ * @param uxPriority The priority with respect to other co-routines at which\r
+ * the co-routine will run.\r
+ *\r
+ * @param uxIndex Used to distinguish between different co-routines that\r
+ * execute the same function. See the example below and the co-routine section\r
+ * of the WEB documentation for further information.\r
+ *\r
+ * @return pdPASS if the co-routine was successfully created and added to a ready\r
+ * list, otherwise an error code defined with ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ static const char cLedToFlash[ 2 ] = { 5, 6 };\r
+ static const portTickType uxFlashRates[ 2 ] = { 200, 400 };\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This co-routine just delays for a fixed period, then toggles\r
+ // an LED. Two co-routines are created using this function, so\r
+ // the uxIndex parameter is used to tell the co-routine which\r
+ // LED to flash and how long to delay. This assumes xQueue has\r
+ // already been created.\r
+ vParTestToggleLED( cLedToFlash[ uxIndex ] );\r
+ crDELAY( xHandle, uxFlashRates[ uxIndex ] );\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }\r
+\r
+ // Function that creates two co-routines.\r
+ void vOtherFunction( void )\r
+ {\r
+ unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create two co-routines at priority 0. The first is given index 0\r
+ // so (from the code above) toggles LED 5 every 200 ticks. The second\r
+ // is given index 1 so toggles LED 6 every 400 ticks.\r
+ for( uxIndex = 0; uxIndex < 2; uxIndex++ )\r
+ {\r
+ xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xCoRoutineCreate xCoRoutineCreate\r
+ * \ingroup Tasks\r
+ */\r
+signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex );\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ void vCoRoutineSchedule( void );</pre>\r
+ *\r
+ * Run a co-routine.\r
+ *\r
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able\r
+ * to run. The co-routine will execute until it either blocks, yields or is\r
+ * preempted by a task. Co-routines execute cooperatively so one\r
+ * co-routine cannot be preempted by another, but can be preempted by a task.\r
+ *\r
+ * If an application comprises of both tasks and co-routines then\r
+ * vCoRoutineSchedule should be called from the idle task (in an idle task\r
+ * hook).\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // This idle task hook will schedule a co-routine each time it is called.\r
+ // The rest of the idle task will execute between co-routine calls.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+\r
+ // Alternatively, if you do not require any other part of the idle task to\r
+ // execute, the idle task hook can call vCoRoutineScheduler() within an\r
+ // infinite loop.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ for( ;; )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule\r
+ * \ingroup Tasks\r
+ */\r
+void vCoRoutineSchedule( void );\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crSTART( xCoRoutineHandle xHandle );</pre>\r
+ *\r
+ * This macro MUST always be called at the start of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static long ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crSTART( pxCRCB ) switch( ( ( corCRCB * )( pxCRCB ) )->uxState ) { case 0:\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crEND();</pre>\r
+ *\r
+ * This macro MUST always be called at the end of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static long ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crEND() }\r
+\r
+/*\r
+ * These macros are intended for internal use by the co-routine implementation\r
+ * only. The macros should not be used directly by application writers.\r
+ */\r
+#define crSET_STATE0( xHandle ) ( ( corCRCB * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\r
+#define crSET_STATE1( xHandle ) ( ( corCRCB * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a co-routine for a fixed period of time.\r
+ *\r
+ * crDELAY can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * @param xHandle The handle of the co-routine to delay. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should delay\r
+ * for. The actual amount of time this equates to is defined by\r
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS\r
+ * can be used to convert ticks to milliseconds.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ // We are to delay for 200ms.\r
+ static const xTickType xDelayTime = 200 / portTICK_RATE_MS;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Delay for 200ms.\r
+ crDELAY( xHandle, xDelayTime );\r
+\r
+ // Do something here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crDELAY crDELAY\r
+ * \ingroup Tasks\r
+ */\r
+#define crDELAY( xHandle, xTicksToDelay ) \\r
+ if( ( xTicksToDelay ) > 0 ) \\r
+ { \\r
+ vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \\r
+ } \\r
+ crSET_STATE0( ( xHandle ) );\r
+\r
+/**\r
+ * <pre>\r
+ crQUEUE_SEND(\r
+ xCoRoutineHandle xHandle,\r
+ xQueueHandle pxQueue,\r
+ void *pvItemToQueue,\r
+ portTickType xTicksToWait,\r
+ portBASE_TYPE *pxResult\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_SEND can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue on which the data will be posted.\r
+ * The handle is obtained as the return value when the queue is created using\r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied from pvItemToQueue into the queue\r
+ * itself.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block\r
+ * to wait for space to become available on the queue, should space not be\r
+ * available immediately. The actual amount of time this equates to is defined\r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant\r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example\r
+ * below).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully posted onto the queue, otherwise it will be set to an\r
+ * error defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine function that blocks for a fixed period then posts a number onto\r
+ // a queue.\r
+ static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xNumberToPost = 0;\r
+ static portBASE_TYPE xResult;\r
+\r
+ // Co-routines must begin with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This assumes the queue has already been created.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\r
+\r
+ if( xResult != pdPASS )\r
+ {\r
+ // The message was not posted!\r
+ }\r
+\r
+ // Increment the number to be posted onto the queue.\r
+ xNumberToPost++;\r
+\r
+ // Delay for 100 ticks.\r
+ crDELAY( xHandle, 100 );\r
+ }\r
+\r
+ // Co-routines must end with a call to crEND().\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND crQUEUE_SEND\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \\r
+{ \\r
+ *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \\r
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( ( xHandle ) ); \\r
+ *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \\r
+ } \\r
+ if( *pxResult == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( ( xHandle ) ); \\r
+ *pxResult = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_RECEIVE(\r
+ xCoRoutineHandle xHandle,\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait,\r
+ portBASE_TYPE *pxResult\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue from which the data will be received.\r
+ * The handle is obtained as the return value when the queue is created using\r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvBuffer The buffer into which the received item is to be copied.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied into pvBuffer.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block\r
+ * to wait for data to become available from the queue, should data not be\r
+ * available immediately. The actual amount of time this equates to is defined\r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant\r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the\r
+ * crQUEUE_SEND example).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully retrieved from the queue, otherwise it will be set to\r
+ * an error code as defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine receives the number of an LED to flash from a queue. It\r
+ // blocks on the queue until the number is received.\r
+ static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xResult;\r
+ static unsigned portBASE_TYPE uxLEDToFlash;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue.\r
+ crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+\r
+ if( xResult == pdPASS )\r
+ {\r
+ // We received the LED to flash - flash it!\r
+ vParTestToggleLED( uxLEDToFlash );\r
+ }\r
+ }\r
+\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \\r
+{ \\r
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \\r
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( ( xHandle ) ); \\r
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \\r
+ } \\r
+ if( *( pxResult ) == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( ( xHandle ) ); \\r
+ *( pxResult ) = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvItemToQueue,\r
+ portBASE_TYPE xCoRoutinePreviouslyWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r
+ * functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\r
+ * that is being used from within a co-routine.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\r
+ * the same queue multiple times from a single interrupt. The first call\r
+ * should always pass in pdFALSE. Subsequent calls should pass in\r
+ * the value returned from the previous call.\r
+ *\r
+ * @return pdTRUE if a co-routine was woken by posting onto the queue. This is\r
+ * used by the ISR to determine if a context switch may be required following\r
+ * the ISR.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that blocks on a queue waiting for characters to be received.\r
+ static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ char cRxedChar;\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue. This assumes the\r
+ // queue xCommsRxQueue has already been created!\r
+ crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+\r
+ // Was a character received?\r
+ if( xResult == pdPASS )\r
+ {\r
+ // Process the character here.\r
+ }\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to send characters received on a serial port to\r
+ // a co-routine.\r
+ void vUART_ISR( void )\r
+ {\r
+ char cRxedChar;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ // We loop around reading characters until there are none left in the UART.\r
+ while( UART_RX_REG_NOT_EMPTY() )\r
+ {\r
+ // Obtain the character from the UART.\r
+ cRxedChar = UART_RX_REG;\r
+\r
+ // Post the character onto a queue. xCRWokenByPost will be pdFALSE\r
+ // the first time around the loop. If the post causes a co-routine\r
+ // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\r
+ // In this manner we can ensure that if more than one co-routine is\r
+ // blocked on the queue only one is woken by this ISR no matter how\r
+ // many characters are posted to the queue.\r
+ xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portBASE_TYPE * pxCoRoutineWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r
+ * functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\r
+ * from a queue that is being used from within a co-routine (a co-routine\r
+ * posted to the queue).\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvBuffer A pointer to a buffer into which the received item will be\r
+ * placed. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from the queue into\r
+ * pvBuffer.\r
+ *\r
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\r
+ * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a\r
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\r
+ * *pxCoRoutineWoken will remain unchanged.\r
+ *\r
+ * @return pdTRUE an item was successfully received from the queue, otherwise\r
+ * pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that posts a character to a queue then blocks for a fixed\r
+ // period. The character is incremented each time.\r
+ static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // cChar holds its value while this co-routine is blocked and must therefore\r
+ // be declared static.\r
+ static char cCharToTx = 'a';\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Send the next character to the queue.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\r
+\r
+ if( xResult == pdPASS )\r
+ {\r
+ // The character was successfully posted to the queue.\r
+ }\r
+ else\r
+ {\r
+ // Could not post the character to the queue.\r
+ }\r
+\r
+ // Enable the UART Tx interrupt to cause an interrupt in this\r
+ // hypothetical UART. The interrupt will obtain the character\r
+ // from the queue and send it.\r
+ ENABLE_RX_INTERRUPT();\r
+\r
+ // Increment to the next character then block for a fixed period.\r
+ // cCharToTx will maintain its value across the delay as it is\r
+ // declared static.\r
+ cCharToTx++;\r
+ if( cCharToTx > 'x' )\r
+ {\r
+ cCharToTx = 'a';\r
+ }\r
+ crDELAY( 100 );\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to receive characters to send on a UART.\r
+ void vUART_ISR( void )\r
+ {\r
+ char cCharToTx;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ while( UART_TX_REG_EMPTY() )\r
+ {\r
+ // Are there any characters in the queue waiting to be sent?\r
+ // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\r
+ // is woken by the post - ensuring that only a single co-routine is\r
+ // woken no matter how many times we go around this loop.\r
+ if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\r
+ {\r
+ SEND_CHARACTER( cCharToTx );\r
+ }\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\r
+\r
+/*\r
+ * This function is intended for internal use by the co-routine macros only.\r
+ * The macro nature of the co-routine implementation requires that the\r
+ * prototype appears here. The function should not be used by application\r
+ * writers.\r
+ *\r
+ * Removes the current co-routine from its ready list and places it in the\r
+ * appropriate delayed list.\r
+ */\r
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList );\r
+\r
+/*\r
+ * This function is intended for internal use by the queue implementation only.\r
+ * The function should not be used by application writers.\r
+ *\r
+ * Removes the highest priority co-routine from the event list and places it in\r
+ * the pending ready list.\r
+ */\r
+signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList );\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* CO_ROUTINE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * This is the list implementation used by the scheduler. While it is tailored\r
+ * heavily for the schedulers needs, it is also available for use by\r
+ * application code.\r
+ *\r
+ * xLists can only store pointers to xListItems. Each xListItem contains a\r
+ * numeric value (xItemValue). Most of the time the lists are sorted in\r
+ * descending item value order.\r
+ *\r
+ * Lists are created already containing one list item. The value of this\r
+ * item is the maximum possible that can be stored, it is therefore always at\r
+ * the end of the list and acts as a marker. The list member pxHead always\r
+ * points to this marker - even though it is at the tail of the list. This\r
+ * is because the tail contains a wrap back pointer to the true head of\r
+ * the list.\r
+ *\r
+ * In addition to it's value, each list item contains a pointer to the next\r
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)\r
+ * and a pointer to back to the object that contains it. These later two\r
+ * pointers are included for efficiency of list manipulation. There is\r
+ * effectively a two way link between the object containing the list item and\r
+ * the list item itself.\r
+ *\r
+ *\r
+ * \page ListIntroduction List Implementation\r
+ * \ingroup FreeRTOSIntro\r
+ */\r
+\r
+\r
+#ifndef LIST_H\r
+#define LIST_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/*\r
+ * Definition of the only type of object that a list can contain.\r
+ */\r
+struct xLIST_ITEM\r
+{\r
+ portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */\r
+ volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */\r
+ volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */\r
+ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */\r
+ void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */\r
+};\r
+typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */\r
+\r
+struct xMINI_LIST_ITEM\r
+{\r
+ portTickType xItemValue;\r
+ volatile struct xLIST_ITEM *pxNext;\r
+ volatile struct xLIST_ITEM *pxPrevious;\r
+};\r
+typedef struct xMINI_LIST_ITEM xMiniListItem;\r
+\r
+/*\r
+ * Definition of the type of queue used by the scheduler.\r
+ */\r
+typedef struct xLIST\r
+{\r
+ volatile unsigned portBASE_TYPE uxNumberOfItems;\r
+ volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */\r
+ volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\r
+} xList;\r
+\r
+/*\r
+ * Access macro to set the owner of a list item. The owner of a list item\r
+ * is the object (usually a TCB) that contains the list item.\r
+ *\r
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) ( pxOwner )\r
+\r
+/*\r
+ * Access macro to get the owner of a list item. The owner of a list item\r
+ * is the object (usually a TCB) that contains the list item.\r
+ *\r
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_LIST_ITEM_OWNER( pxListItem ) ( pxListItem )->pvOwner\r
+\r
+/*\r
+ * Access macro to set the value of the list item. In most cases the value is\r
+ * used to sort the list in descending order.\r
+ *\r
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = ( xValue )\r
+\r
+/*\r
+ * Access macro to retrieve the value of the list item. The value can\r
+ * represent anything - for example a the priority of a task, or the time at\r
+ * which a task should be unblocked.\r
+ *\r
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )\r
+\r
+/*\r
+ * Access macro the retrieve the value of the list item at the head of a given\r
+ * list.\r
+ *\r
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->xItemValue )\r
+\r
+/*\r
+ * Access macro to determine if a list contains any items. The macro will\r
+ * only have the value true if the list is empty.\r
+ *\r
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 )\r
+\r
+/*\r
+ * Access macro to return the number of items in the list.\r
+ */\r
+#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )\r
+\r
+/*\r
+ * Access function to obtain the owner of the next entry in a list.\r
+ *\r
+ * The list member pxIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\r
+ * and returns that entries pxOwner parameter. Using multiple calls to this\r
+ * function it is therefore possible to move through every item contained in\r
+ * a list.\r
+ *\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the next item owner is to be returned.\r
+ *\r
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \\r
+{ \\r
+xList * const pxConstList = ( pxList ); \\r
+ /* Increment the index to the next item and return the item, ensuring */ \\r
+ /* we don't return the marker used at the end of the list. */ \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
+ if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \\r
+ { \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
+ } \\r
+ ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \\r
+}\r
+\r
+\r
+/*\r
+ * Access function to obtain the owner of the first entry in a list. Lists\r
+ * are normally sorted in ascending item value order.\r
+ *\r
+ * This function returns the pxOwner member of the first item in the list.\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the owner of the head item is to be\r
+ * returned.\r
+ *\r
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )\r
+\r
+/*\r
+ * Check to see if a list item is within a list. The list item maintains a\r
+ * "container" pointer that points to the list it is in. All this macro does\r
+ * is check to see if the container and the list match.\r
+ *\r
+ * @param pxList The list we want to know if the list item is within.\r
+ * @param pxListItem The list item we want to know if is in the list.\r
+ * @return pdTRUE is the list item is in the list, otherwise pdFALSE.\r
+ * pointer against\r
+ */\r
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) )\r
+\r
+/*\r
+ * This provides a crude means of knowing if a list has been initialised, as\r
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()\r
+ * function.\r
+ */\r
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )\r
+\r
+/*\r
+ * Must be called before a list is used! This initialises all the members\r
+ * of the list structure and inserts the xListEnd item into the list as a\r
+ * marker to the back of the list.\r
+ *\r
+ * @param pxList Pointer to the list being initialised.\r
+ *\r
+ * \page vListInitialise vListInitialise\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialise( xList *pxList );\r
+\r
+/*\r
+ * Must be called before a list item is used. This sets the list container to\r
+ * null so the item does not think that it is already contained in a list.\r
+ *\r
+ * @param pxItem Pointer to the list item being initialised.\r
+ *\r
+ * \page vListInitialiseItem vListInitialiseItem\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialiseItem( xListItem *pxItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted into the list in\r
+ * a position determined by its item value (descending item value order).\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The item to that is to be placed in the list.\r
+ *\r
+ * \page vListInsert vListInsert\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted in a position\r
+ * such that it will be the last item within the list returned by multiple\r
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.\r
+ *\r
+ * The list member pvIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.\r
+ * Placing an item in a list using vListInsertEnd effectively places the item\r
+ * in the list position pointed to by pvIndex. This means that every other\r
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\r
+ * the pvIndex parameter again points to the item being inserted.\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The list item to be inserted into the list.\r
+ *\r
+ * \page vListInsertEnd vListInsertEnd\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Remove an item from a list. The list item has a pointer to the list that\r
+ * it is in, so only the list item need be passed into the function.\r
+ *\r
+ * @param vListRemove The item to be removed. The item will remove itself from\r
+ * the list pointed to by it's pxContainer parameter.\r
+ *\r
+ * \page vListRemove vListRemove\r
+ * \ingroup LinkedList\r
+ */\r
+void vListRemove( xListItem *pxItemToRemove );\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef MPU_WRAPPERS_H\r
+#define MPU_WRAPPERS_H\r
+\r
+/* This file redefines API functions to be called through a wrapper macro, but\r
+only for ports that are using the MPU. */\r
+#ifdef portUSING_MPU_WRAPPERS\r
+\r
+ /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\r
+ included from queue.c or task.c to prevent it from having an effect within\r
+ those files. */\r
+ #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+ #define xTaskGenericCreate MPU_xTaskGenericCreate\r
+ #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions\r
+ #define vTaskDelete MPU_vTaskDelete\r
+ #define vTaskDelayUntil MPU_vTaskDelayUntil\r
+ #define vTaskDelay MPU_vTaskDelay\r
+ #define uxTaskPriorityGet MPU_uxTaskPriorityGet\r
+ #define vTaskPrioritySet MPU_vTaskPrioritySet\r
+ #define vTaskSuspend MPU_vTaskSuspend\r
+ #define xTaskIsTaskSuspended MPU_xTaskIsTaskSuspended\r
+ #define vTaskResume MPU_vTaskResume\r
+ #define vTaskSuspendAll MPU_vTaskSuspendAll\r
+ #define xTaskResumeAll MPU_xTaskResumeAll\r
+ #define xTaskGetTickCount MPU_xTaskGetTickCount\r
+ #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks\r
+ #define vTaskList MPU_vTaskList\r
+ #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats\r
+ #define vTaskStartTrace MPU_vTaskStartTrace\r
+ #define ulTaskEndTrace MPU_ulTaskEndTrace\r
+ #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag\r
+ #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag\r
+ #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook\r
+ #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark\r
+ #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle\r
+ #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState\r
+\r
+ #define xQueueGenericCreate MPU_xQueueGenericCreate\r
+ #define xQueueCreateMutex MPU_xQueueCreateMutex\r
+ #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive\r
+ #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive\r
+ #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore\r
+ #define xQueueGenericSend MPU_xQueueGenericSend\r
+ #define xQueueAltGenericSend MPU_xQueueAltGenericSend\r
+ #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive\r
+ #define xQueueGenericReceive MPU_xQueueGenericReceive\r
+ #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting\r
+ #define vQueueDelete MPU_vQueueDelete\r
+\r
+ #define pvPortMalloc MPU_pvPortMalloc\r
+ #define vPortFree MPU_vPortFree\r
+ #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize\r
+ #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks\r
+\r
+ #if configQUEUE_REGISTRY_SIZE > 0\r
+ #define vQueueAddToRegistry MPU_vQueueAddToRegistry\r
+ #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue\r
+ #endif\r
+\r
+ /* Remove the privileged function macro. */\r
+ #define PRIVILEGED_FUNCTION\r
+\r
+ #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
+\r
+ /* Ensure API functions go in the privileged execution section. */\r
+ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))\r
+ #define PRIVILEGED_DATA __attribute__((section("privileged_data")))\r
+ //#define PRIVILEGED_DATA\r
+\r
+ #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
+\r
+#else /* portUSING_MPU_WRAPPERS */\r
+\r
+ #define PRIVILEGED_FUNCTION\r
+ #define PRIVILEGED_DATA\r
+ #define portUSING_MPU_WRAPPERS 0\r
+\r
+#endif /* portUSING_MPU_WRAPPERS */\r
+\r
+\r
+#endif /* MPU_WRAPPERS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Portable layer API. Each function must be defined for each port.\r
+ *----------------------------------------------------------*/\r
+\r
+#ifndef PORTABLE_H\r
+#define PORTABLE_H\r
+\r
+/* Include the macro file relevant to the port being used. */\r
+\r
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\r
+ #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\r
+ #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef GCC_MEGA_AVR\r
+ #include "../portable/GCC/ATMega323/portmacro.h"\r
+#endif\r
+\r
+#ifdef IAR_MEGA_AVR\r
+ #include "../portable/IAR/ATMega323/portmacro.h"\r
+#endif\r
+\r
+#ifdef MPLAB_PIC24_PORT\r
+ #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h"\r
+#endif\r
+\r
+#ifdef MPLAB_DSPIC_PORT\r
+ #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h"\r
+#endif\r
+\r
+#ifdef MPLAB_PIC18F_PORT\r
+ #include "..\..\Source\portable\MPLAB\PIC18F\portmacro.h"\r
+#endif\r
+\r
+#ifdef MPLAB_PIC32MX_PORT\r
+ #include "..\..\Source\portable\MPLAB\PIC32MX\portmacro.h"\r
+#endif\r
+\r
+#ifdef _FEDPICC\r
+ #include "libFreeRTOS/Include/portmacro.h"\r
+#endif\r
+\r
+#ifdef SDCC_CYGNAL\r
+ #include "../../Source/portable/SDCC/Cygnal/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARM7\r
+ #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARM7_ECLIPSE\r
+ #include "portmacro.h"\r
+#endif\r
+\r
+#ifdef ROWLEY_LPC23xx\r
+ #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"\r
+#endif\r
+\r
+#ifdef IAR_MSP430\r
+ #include "..\..\Source\portable\IAR\MSP430\portmacro.h" \r
+#endif\r
+ \r
+#ifdef GCC_MSP430\r
+ #include "../../Source/portable/GCC/MSP430F449/portmacro.h"\r
+#endif\r
+\r
+#ifdef ROWLEY_MSP430\r
+ #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"\r
+#endif\r
+\r
+#ifdef ARM7_LPC21xx_KEIL_RVDS\r
+ #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"\r
+#endif\r
+\r
+#ifdef SAM7_GCC\r
+ #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"\r
+#endif\r
+\r
+#ifdef SAM7_IAR\r
+ #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"\r
+#endif\r
+\r
+#ifdef SAM9XE_IAR\r
+ #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"\r
+#endif\r
+\r
+#ifdef LPC2000_IAR\r
+ #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"\r
+#endif\r
+\r
+#ifdef STR71X_IAR\r
+ #include "..\..\Source\portable\IAR\STR71x\portmacro.h"\r
+#endif\r
+\r
+#ifdef STR75X_IAR\r
+ #include "..\..\Source\portable\IAR\STR75x\portmacro.h"\r
+#endif\r
+ \r
+#ifdef STR75X_GCC\r
+ #include "..\..\Source\portable\GCC\STR75x\portmacro.h"\r
+#endif\r
+\r
+#ifdef STR91X_IAR\r
+ #include "..\..\Source\portable\IAR\STR91x\portmacro.h"\r
+#endif\r
+ \r
+#ifdef GCC_H8S\r
+ #include "../../Source/portable/GCC/H8S2329/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_AT91FR40008\r
+ #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"\r
+#endif\r
+\r
+#ifdef RVDS_ARMCM3_LM3S102\r
+ #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARMCM3_LM3S102\r
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_ARMCM3\r
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef IAR_ARM_CM3\r
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"\r
+#endif\r
+\r
+#ifdef IAR_ARMCM3_LM\r
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"\r
+#endif\r
+ \r
+#ifdef HCS12_CODE_WARRIOR\r
+ #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"\r
+#endif \r
+\r
+#ifdef MICROBLAZE_GCC\r
+ #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"\r
+#endif\r
+\r
+#ifdef TERN_EE\r
+ #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_HCS12\r
+ #include "../../Source/portable/GCC/HCS12/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_MCF5235\r
+ #include "../../Source/portable/GCC/MCF5235/portmacro.h"\r
+#endif\r
+\r
+#ifdef COLDFIRE_V2_GCC\r
+ #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"\r
+#endif\r
+\r
+#ifdef COLDFIRE_V2_CODEWARRIOR\r
+ #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_PPC405\r
+ #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"\r
+#endif\r
+\r
+#ifdef GCC_PPC440\r
+ #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"\r
+#endif\r
+\r
+#ifdef _16FX_SOFTUNE\r
+ #include "..\..\Source\portable\Softune\MB96340\portmacro.h"\r
+#endif\r
+\r
+#ifdef BCC_INDUSTRIAL_PC_PORT\r
+ /* A short file name has to be used in place of the normal\r
+ FreeRTOSConfig.h when using the Borland compiler. */\r
+ #include "frconfig.h"\r
+ #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef BCC_FLASH_LITE_186_PORT\r
+ /* A short file name has to be used in place of the normal\r
+ FreeRTOSConfig.h when using the Borland compiler. */\r
+ #include "frconfig.h"\r
+ #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"\r
+ typedef void ( __interrupt __far *pxISR )();\r
+#endif\r
+\r
+#ifdef __GNUC__\r
+ #ifdef __AVR32_AVR32A__\r
+ #include "portmacro.h"\r
+ #endif\r
+#endif\r
+\r
+#ifdef __ICCAVR32__\r
+ #ifdef __CORE__\r
+ #if __CORE__ == __AVR32A__\r
+ #include "portmacro.h"\r
+ #endif\r
+ #endif\r
+#endif\r
+\r
+#ifdef __91467D\r
+ #include "portmacro.h"\r
+#endif\r
+\r
+#ifdef __96340\r
+ #include "portmacro.h"\r
+#endif\r
+\r
+\r
+#ifdef __IAR_V850ES_Fx3__\r
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"\r
+#endif\r
+\r
+#ifdef __IAR_V850ES_Jx3__\r
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"\r
+#endif\r
+\r
+#ifdef __IAR_V850ES_Jx3_L__\r
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"\r
+#endif\r
+\r
+#ifdef __IAR_V850ES_Jx2__\r
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"\r
+#endif\r
+\r
+#ifdef __IAR_V850ES_Hx2__\r
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"\r
+#endif\r
+\r
+#ifdef __IAR_78K0R_Kx3__\r
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"\r
+#endif\r
+ \r
+#ifdef __IAR_78K0R_Kx3L__\r
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"\r
+#endif\r
+ \r
+/* Catch all to ensure portmacro.h is included in the build. Newer demos\r
+have the path as part of the project options, rather than as relative from\r
+the project location. If portENTER_CRITICAL() has not been defined then\r
+portmacro.h has not yet been included - as every portmacro.h provides a\r
+portENTER_CRITICAL() definition. Check the demo application for your demo\r
+to find the path to the correct portmacro.h file. */\r
+#ifndef portENTER_CRITICAL\r
+ #include "portmacro.h" \r
+#endif\r
+ \r
+#if portBYTE_ALIGNMENT == 8\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 4\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0003 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 2\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0001 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 1\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0000 )\r
+#endif\r
+\r
+#ifndef portBYTE_ALIGNMENT_MASK\r
+ #error "Invalid portBYTE_ALIGNMENT definition"\r
+#endif\r
+\r
+#ifndef portNUM_CONFIGURABLE_REGIONS\r
+ #define portNUM_CONFIGURABLE_REGIONS 1\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "mpu_wrappers.h"\r
+\r
+/*\r
+ * Setup the stack of a new task so it is ready to be placed under the\r
+ * scheduler control. The registers have to be placed on the stack in\r
+ * the order that the port expects to find them.\r
+ *\r
+ */\r
+#if( portUSING_MPU_WRAPPERS == 1 )\r
+ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) PRIVILEGED_FUNCTION;\r
+#else\r
+ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );\r
+#endif\r
+\r
+/*\r
+ * Map to the memory management routines required for the port.\r
+ */\r
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\r
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;\r
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\r
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Setup the hardware ready for the scheduler to take control. This generally\r
+ * sets up a tick interrupt and sets timers for the correct tick frequency.\r
+ */\r
+portBASE_TYPE xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\r
+ * the hardware is left in its original condition after the scheduler stops\r
+ * executing.\r
+ */\r
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The structures and methods of manipulating the MPU are contained within the\r
+ * port layer.\r
+ *\r
+ * Fills the xMPUSettings structure with the memory region information\r
+ * contained in xRegions.\r
+ */\r
+#if( portUSING_MPU_WRAPPERS == 1 ) \r
+ struct xMEMORY_REGION;\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTABLE_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef PROJDEFS_H\r
+#define PROJDEFS_H\r
+\r
+/* Defines the prototype to which task functions must conform. */\r
+typedef void (*pdTASK_CODE)( void * );\r
+\r
+#define pdTRUE ( 1 )\r
+#define pdFALSE ( 0 )\r
+\r
+#define pdPASS ( 1 )\r
+#define pdFAIL ( 0 )\r
+#define errQUEUE_EMPTY ( 0 )\r
+#define errQUEUE_FULL ( 0 )\r
+\r
+/* Error definitions. */\r
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )\r
+#define errNO_TASK_TO_RUN ( -2 )\r
+#define errQUEUE_BLOCKED ( -4 )\r
+#define errQUEUE_YIELD ( -5 )\r
+\r
+#endif /* PROJDEFS_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef QUEUE_H\r
+#define QUEUE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h" must appear in source files before "include queue.h"\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+#include "mpu_wrappers.h"\r
+\r
+/**\r
+ * Type by which queues are referenced. For example, a call to xQueueCreate\r
+ * returns (via a pointer parameter) an xQueueHandle variable that can then\r
+ * be used as a parameter to xQueueSend(), xQueueReceive(), etc.\r
+ */\r
+typedef void * xQueueHandle;\r
+\r
+\r
+/* For internal use only. */\r
+#define queueSEND_TO_BACK ( 0 )\r
+#define queueSEND_TO_FRONT ( 1 )\r
+\r
+/* For internal use only. These definitions *must* match those in queue.c. */\r
+#define queueQUEUE_TYPE_BASE ( 0U )\r
+#define queueQUEUE_TYPE_MUTEX ( 1U )\r
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( 2U )\r
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( 3U )\r
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( 4U )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ xQueueHandle xQueueCreate(\r
+ unsigned portBASE_TYPE uxQueueLength,\r
+ unsigned portBASE_TYPE uxItemSize\r
+ );\r
+ * </pre>\r
+ *\r
+ * Creates a new queue instance. This allocates the storage required by the\r
+ * new queue and returns a handle for the queue.\r
+ *\r
+ * @param uxQueueLength The maximum number of items that the queue can contain.\r
+ *\r
+ * @param uxItemSize The number of bytes each item in the queue will require.\r
+ * Items are queued by copy, not by reference, so this is the number of bytes\r
+ * that will be copied for each posted item. Each item on the queue must be\r
+ * the same size.\r
+ *\r
+ * @return If the queue is successfully create then a handle to the newly\r
+ * created queue is returned. If the queue cannot be created then 0 is\r
+ * returned.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ };\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+ if( xQueue1 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue2 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueCreate xQueueCreate\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( uxQueueLength, uxItemSize, queueQUEUE_TYPE_BASE )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToToFront(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend().\r
+ *\r
+ * Post an item to the front of a queue. The item is queued by copy, not by\r
+ * reference. This function must not be called from an interrupt service\r
+ * routine. See xQueueSendFromISR () for an alternative which may be used\r
+ * in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToBack(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend().\r
+ *\r
+ * Post an item to the back of a queue. The item is queued by copy, not by\r
+ * reference. This function must not be called from an interrupt service\r
+ * routine. See xQueueSendFromISR () for an alternative which may be used\r
+ * in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the queue\r
+ * is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSend(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend(). It is included for\r
+ * backward compatibility with versions of FreeRTOS.org that did not\r
+ * include the xQueueSendToFront() and xQueueSendToBack() macros. It is\r
+ * equivalent to xQueueSendToBack().\r
+ *\r
+ * Post an item on a queue. The item is queued by copy, not by reference.\r
+ * This function must not be called from an interrupt service routine.\r
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericSend(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ portBASE_TYPE xCopyPosition\r
+ );\r
+ * </pre>\r
+ *\r
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\r
+ * xQueueSendToBack() are used in place of calling this function directly.\r
+ *\r
+ * Post an item on a queue. The item is queued by copy, not by reference.\r
+ * This function must not be called from an interrupt service routine.\r
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r
+ * at the front of the queue (for high priority messages).\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10, queueSEND_TO_BACK ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0, queueSEND_TO_BACK );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueuePeek(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ );</pre>\r
+ *\r
+ * This is a macro that calls the xQueueGenericReceive() function.\r
+ *\r
+ * Receive an item from a queue without removing the item from the queue.\r
+ * The item is received by copy so a buffer of adequate size must be\r
+ * provided. The number of bytes copied into the buffer was defined when\r
+ * the queue was created.\r
+ *\r
+ * Successfully received items remain on the queue so will be returned again\r
+ * by the next call, or a call to xQueueReceive().\r
+ *\r
+ * This macro must not be used in an interrupt service routine.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\r
+ * is empty.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to peek the data from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Peek a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueuePeek( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask, but the item still remains on the queue.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceive(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ );</pre>\r
+ *\r
+ * This is a macro that calls the xQueueGenericReceive() function.\r
+ *\r
+ * Receive an item from a queue. The item is received by copy so a buffer of\r
+ * adequate size must be provided. The number of bytes copied into the buffer\r
+ * was defined when the queue was created.\r
+ *\r
+ * Successfully received items are removed from the queue.\r
+ *\r
+ * This function must not be used in an interrupt service routine. See\r
+ * xQueueReceiveFromISR for an alternative that can.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. xQueueReceive() will return immediately if xTicksToWait\r
+ * is zero and the queue is empty. The time is defined in tick periods so the\r
+ * constant portTICK_RATE_MS should be used to convert to real time if this is\r
+ * required.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to receive from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Receive a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericReceive(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ portBASE_TYPE xJustPeek\r
+ );</pre>\r
+ *\r
+ * It is preferred that the macro xQueueReceive() be used rather than calling\r
+ * this function directly.\r
+ *\r
+ * Receive an item from a queue. The item is received by copy so a buffer of\r
+ * adequate size must be provided. The number of bytes copied into the buffer\r
+ * was defined when the queue was created.\r
+ *\r
+ * This function must not be used in an interrupt service routine. See\r
+ * xQueueReceiveFromISR for an alternative that can.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ * xQueueGenericReceive() will return immediately if the queue is empty and\r
+ * xTicksToWait is 0.\r
+ *\r
+ * @param xJustPeek When set to true, the item received from the queue is not\r
+ * actually removed from the queue - meaning a subsequent call to\r
+ * xQueueReceive() will return the same item. When set to false, the item\r
+ * being received from the queue is also removed from the queue.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to receive from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Receive a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeek );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );</pre>\r
+ *\r
+ * Return the number of messages stored in a queue.\r
+ *\r
+ * @param xQueue A handle to the queue being queried.\r
+ *\r
+ * @return The number of messages available in the queue.\r
+ *\r
+ * \page uxQueueMessagesWaiting uxQueueMessagesWaiting\r
+ * \ingroup QueueManagement\r
+ */\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>void vQueueDelete( xQueueHandle xQueue );</pre>\r
+ *\r
+ * Delete a queue - freeing all the memory allocated for storing of items\r
+ * placed on the queue.\r
+ *\r
+ * @param xQueue A handle to the queue to be deleted.\r
+ *\r
+ * \page vQueueDelete vQueueDelete\r
+ * \ingroup QueueManagement\r
+ */\r
+void vQueueDelete( xQueueHandle pxQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToFrontFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR().\r
+ *\r
+ * Post an item to the front of a queue. It is safe to use this macro from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPrioritTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToFrontFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToBackFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR().\r
+ *\r
+ * Post an item to the back of a queue. It is safe to use this macro from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToBackFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR(). It is included\r
+ * for backward compatibility with versions of FreeRTOS.org that did not\r
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\r
+ * macros.\r
+ *\r
+ * Post an item to the back of a queue. It is safe to use this function from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ // Actual macro used here is port specific.\r
+ taskYIELD_FROM_ISR ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericSendFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken,\r
+ portBASE_TYPE xCopyPosition\r
+ );\r
+ </pre>\r
+ *\r
+ * It is preferred that the macros xQueueSendFromISR(),\r
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\r
+ * of calling this function directly.\r
+ *\r
+ * Post an item on a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r
+ * at the front of the queue (for high priority messages).\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWokenByPost;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWokenByPost = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post each byte.\r
+ xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary. Note that the\r
+ // name of the yield function required is port specific.\r
+ if( xHigherPriorityTaskWokenByPost )\r
+ {\r
+ taskYIELD_YIELD_FROM_ISR();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceiveFromISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portBASE_TYPE *pxTaskWoken\r
+ );\r
+ * </pre>\r
+ *\r
+ * Receive an item from a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param pxTaskWoken A task may be blocked waiting for space to become\r
+ * available on the queue. If xQueueReceiveFromISR causes such a task to\r
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\r
+ * remain unchanged.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Function to create a queue and post some values.\r
+ void vAFunction( void *pvParameters )\r
+ {\r
+ char cValueToPost;\r
+ const portTickType xBlockTime = ( portTickType )0xff;\r
+\r
+ // Create a queue capable of containing 10 characters.\r
+ xQueue = xQueueCreate( 10, sizeof( char ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Post some characters that will be used within an ISR. If the queue\r
+ // is full then this task will block for xBlockTime ticks.\r
+ cValueToPost = 'a';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ cValueToPost = 'b';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+\r
+ // ... keep posting characters ... this task may block when the queue\r
+ // becomes full.\r
+\r
+ cValueToPost = 'c';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ }\r
+\r
+ // ISR that outputs all the characters received on the queue.\r
+ void vISR_Routine( void )\r
+ {\r
+ portBASE_TYPE xTaskWokenByReceive = pdFALSE;\r
+ char cRxedChar;\r
+\r
+ while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\r
+ {\r
+ // A character was received. Output the character now.\r
+ vOutputCharacter( cRxedChar );\r
+\r
+ // If removing the character from the queue woke the task that was\r
+ // posting onto the queue cTaskWokenByReceive will have been set to\r
+ // pdTRUE. No matter how many times this loop iterates only one\r
+ // task will be woken.\r
+ }\r
+\r
+ if( cTaskWokenByPost != ( char ) pdFALSE;\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+\r
+/*\r
+ * Utilities to query queues that are safe to use from an ISR. These utilities\r
+ * should be used only from witin an ISR, or within a critical section.\r
+ */\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue );\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue );\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue );\r
+\r
+\r
+/*\r
+ * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().\r
+ * Likewise xQueueAltGenericReceive() is an alternative version of\r
+ * xQueueGenericReceive().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much\r
+ * simpler because it executes everything from within a critical section.\r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the\r
+ * preferred fully featured API too. The fully featured API has more\r
+ * complex code that takes longer to execute, but makes much less use of\r
+ * critical sections. Therefore the alternative API sacrifices interrupt\r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
+signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
+#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r
+#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r
+#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r
+\r
+/*\r
+ * The functions defined above are for passing data to and from tasks. The\r
+ * functions below are the equivalents for passing data to and from\r
+ * co-routines.\r
+ *\r
+ * These functions are called from the co-routine macro implementation and\r
+ * should not be called directly from application code. Instead use the macro\r
+ * wrappers defined within croutine.h.\r
+ */\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );\r
+\r
+/*\r
+ * For internal use only. Use xSemaphoreCreateMutex(), \r
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling \r
+ * these functions directly.\r
+ */\r
+xQueueHandle xQueueCreateMutex( unsigned char ucQueueType );\r
+xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
+void* xQueueGetMutexHolder( xQueueHandle xSemaphore );\r
+\r
+/*\r
+ * For internal use only. Use xSemaphoreTakeMutexRecursive() or\r
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\r
+ */\r
+portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime );\r
+portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex );\r
+\r
+/*\r
+ * Reset a queue back to its original empty state. pdPASS is returned if the\r
+ * queue is successfully reset. pdFAIL is returned if the queue could not be\r
+ * reset because there are tasks blocked on the queue waiting to either\r
+ * receive from the queue or send to the queue.\r
+ */\r
+#define xQueueReset( pxQueue ) xQueueGenericReset( pxQueue, pdFALSE )\r
+\r
+/*\r
+ * The registry is provided as a means for kernel aware debuggers to\r
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add\r
+ * a queue, semaphore or mutex handle to the registry if you want the handle\r
+ * to be available to a kernel aware debugger. If you are not using a kernel\r
+ * aware debugger then this function can be ignored.\r
+ *\r
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\r
+ * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0\r
+ * within FreeRTOSConfig.h for the registry to be available. Its value\r
+ * does not effect the number of queues, semaphores and mutexes that can be\r
+ * created - just the number that the registry can hold.\r
+ *\r
+ * @param xQueue The handle of the queue being added to the registry. This\r
+ * is the handle returned by a call to xQueueCreate(). Semaphore and mutex\r
+ * handles can also be passed in here.\r
+ *\r
+ * @param pcName The name to be associated with the handle. This is the\r
+ * name that the kernel aware debugger will display.\r
+ */\r
+#if configQUEUE_REGISTRY_SIZE > 0U\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );\r
+#endif\r
+\r
+/*\r
+ * Generic version of the queue creation function, which is in turn called by \r
+ * any queue, semaphore or mutex creation function or macro.\r
+ */\r
+xQueueHandle xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType );\r
+\r
+/* Not public API functions. */\r
+void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait );\r
+portBASE_TYPE xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue );\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* QUEUE_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#ifndef SEMAPHORE_H\r
+#define SEMAPHORE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h" must appear in source files before "include semphr.h"\r
+#endif\r
+\r
+#include "queue.h"\r
+\r
+typedef xQueueHandle xSemaphoreHandle;\r
+\r
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned char ) 1U )\r
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned char ) 0U )\r
+#define semGIVE_BLOCK_TIME ( ( portTickType ) 0U )\r
+\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\r
+ * The queue length is 1 as this is a binary semaphore. The data size is 0\r
+ * as we don't want to actually store any data - we just want to know if the\r
+ * queue is empty or full.\r
+ *\r
+ * This type of semaphore can be used for pure synchronisation between tasks or\r
+ * between an interrupt and a task. The semaphore need not be given back once\r
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while\r
+ * another continuously 'takes' the semaphore. For this reason this type of\r
+ * semaphore does not use a priority inheritance mechanism. For an alternative\r
+ * that does use priority inheritance see xSemaphoreCreateMutex().\r
+ *\r
+ * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\r
+ // This is a macro so pass the variable in directly.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\r
+ * \ingroup Semaphores\r
+ */\r
+#define vSemaphoreCreateBinary( xSemaphore ) \\r
+ { \\r
+ ( xSemaphore ) = xQueueGenericCreate( ( unsigned portBASE_TYPE ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \\r
+ if( ( xSemaphore ) != NULL ) \\r
+ { \\r
+ xSemaphoreGive( ( xSemaphore ) ); \\r
+ } \\r
+ }\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreTake( \r
+ * xSemaphoreHandle xSemaphore, \r
+ * portTickType xBlockTime \r
+ * )</pre>\r
+ *\r
+ * <i>Macro</i> to obtain a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r
+ * xSemaphoreCreateCounting().\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being taken - obtained when\r
+ * the semaphore was created.\r
+ *\r
+ * @param xBlockTime The time in ticks to wait for the semaphore to become\r
+ * available. The macro portTICK_RATE_MS can be used to convert this to a\r
+ * real time. A block time of zero can be used to poll the semaphore. A block\r
+ * time of portMAX_DELAY can be used to block indefinitely (provided\r
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\r
+ *\r
+ * @return pdTRUE if the semaphore was obtained. pdFALSE\r
+ * if xBlockTime expired without the semaphore becoming available.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // A task that creates a semaphore.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ }\r
+\r
+ // A task that uses the semaphore.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // See if we can obtain the semaphore. If the semaphore is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the semaphore and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource. Release the \r
+ // semaphore.\r
+ xSemaphoreGive( xSemaphore );\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the semaphore and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreTake xSemaphoreTake\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r
+\r
+/**\r
+ * semphr. h\r
+ * xSemaphoreTakeRecursive( \r
+ * xSemaphoreHandle xMutex, \r
+ * portTickType xBlockTime \r
+ * )\r
+ *\r
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore. \r
+ * The mutex must have previously been created using a call to \r
+ * xSemaphoreCreateRecursiveMutex();\r
+ * \r
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r
+ * macro to be available.\r
+ * \r
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r
+ *\r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ *\r
+ * @param xMutex A handle to the mutex being obtained. This is the\r
+ * handle returned by xSemaphoreCreateRecursiveMutex();\r
+ *\r
+ * @param xBlockTime The time in ticks to wait for the semaphore to become\r
+ * available. The macro portTICK_RATE_MS can be used to convert this to a\r
+ * real time. A block time of zero can be used to poll the semaphore. If\r
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will\r
+ * return immediately no matter what the value of xBlockTime. \r
+ *\r
+ * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime\r
+ * expired without the semaphore becoming available.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xMutex = NULL;\r
+\r
+ // A task that creates a mutex.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the mutex to guard a shared resource.\r
+ xMutex = xSemaphoreCreateRecursiveMutex();\r
+ }\r
+\r
+ // A task that uses the mutex.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xMutex != NULL )\r
+ {\r
+ // See if we can obtain the mutex. If the mutex is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTakeRecursive( xSemaphore, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the mutex and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+ // For some reason due to the nature of the code further calls to \r
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real\r
+ // code these would not be just sequential calls as this would make\r
+ // no sense. Instead the calls are likely to be buried inside\r
+ // a more complex call structure.\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+\r
+ // The mutex has now been 'taken' three times, so will not be \r
+ // available to another task until it has also been given back\r
+ // three times. Again it is unlikely that real code would have\r
+ // these calls sequentially, but instead buried in a more complex\r
+ // call structure. This is just for illustrative purposes.\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+\r
+ // Now the mutex can be taken by other tasks.\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the mutex and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\r
+\r
+\r
+/* \r
+ * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much \r
+ * simpler because it executes everything from within a critical section. \r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the \r
+ * preferred fully featured API too. The fully featured API has more \r
+ * complex code that takes longer to execute, but makes much less use of \r
+ * critical sections. Therefore the alternative API sacrifices interrupt \r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreGive( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\r
+ *\r
+ * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for\r
+ * an alternative which can be used from an ISR.\r
+ *\r
+ * This macro must also not be used on semaphores created using \r
+ * xSemaphoreCreateRecursiveMutex().\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned when the semaphore was created.\r
+ *\r
+ * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.\r
+ * Semaphores are implemented using queues. An error can occur if there is\r
+ * no space on the queue to post a message - indicating that the \r
+ * semaphore was not first obtained correctly.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would expect this call to fail because we cannot give\r
+ // a semaphore without first "taking" it!\r
+ }\r
+\r
+ // Obtain the semaphore - don't block if the semaphore is not\r
+ // immediately available.\r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )\r
+ {\r
+ // We now have the semaphore and can access the shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource so can free the\r
+ // semaphore.\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would not expect this call to fail because we must have\r
+ // obtained the semaphore to get here.\r
+ }\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGive xSemaphoreGive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreGiveRecursive( xSemaphoreHandle xMutex )</pre>\r
+ *\r
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\r
+ * The mutex must have previously been created using a call to \r
+ * xSemaphoreCreateRecursiveMutex();\r
+ * \r
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r
+ * macro to be available.\r
+ *\r
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r
+ * \r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ *\r
+ * @param xMutex A handle to the mutex being released, or 'given'. This is the\r
+ * handle returned by xSemaphoreCreateMutex();\r
+ *\r
+ * @return pdTRUE if the semaphore was given.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xMutex = NULL;\r
+\r
+ // A task that creates a mutex.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the mutex to guard a shared resource.\r
+ xMutex = xSemaphoreCreateRecursiveMutex();\r
+ }\r
+\r
+ // A task that uses the mutex.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xMutex != NULL )\r
+ {\r
+ // See if we can obtain the mutex. If the mutex is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the mutex and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+ // For some reason due to the nature of the code further calls to \r
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real\r
+ // code these would not be just sequential calls as this would make\r
+ // no sense. Instead the calls are likely to be buried inside\r
+ // a more complex call structure.\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+\r
+ // The mutex has now been 'taken' three times, so will not be \r
+ // available to another task until it has also been given back\r
+ // three times. Again it is unlikely that real code would have\r
+ // these calls sequentially, it would be more likely that the calls\r
+ // to xSemaphoreGiveRecursive() would be called as a call stack\r
+ // unwound. This is just for demonstrative purposes.\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+\r
+ // Now the mutex can be taken by other tasks.\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the mutex and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) )\r
+\r
+/* \r
+ * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much \r
+ * simpler because it executes everything from within a critical section. \r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the \r
+ * preferred fully featured API too. The fully featured API has more \r
+ * complex code that takes longer to execute, but makes much less use of \r
+ * critical sections. Therefore the alternative API sacrifices interrupt \r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>\r
+ xSemaphoreGiveFromISR( \r
+ xSemaphoreHandle xSemaphore, \r
+ signed portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().\r
+ *\r
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\r
+ * must not be used with this macro.\r
+ *\r
+ * This macro can be used from an ISR.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned when the semaphore was created.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ \#define LONG_TIME 0xffff\r
+ \#define TICKS_TO_WAIT 10\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // Repetitive task.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // We want this task to run every 10 ticks of a timer. The semaphore \r
+ // was created before this task was started.\r
+\r
+ // Block waiting for the semaphore to become available.\r
+ if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\r
+ {\r
+ // It is time to execute.\r
+\r
+ // ...\r
+\r
+ // We have finished our task. Return to the top of the loop where\r
+ // we will block on the semaphore until it is time to execute \r
+ // again. Note when using the semaphore for synchronisation with an\r
+ // ISR in this manner there is no need to 'give' the semaphore back.\r
+ }\r
+ }\r
+ }\r
+\r
+ // Timer ISR\r
+ void vTimerISR( void * pvParameters )\r
+ {\r
+ static unsigned char ucLocalTickCount = 0;\r
+ static signed portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // A timer tick has occurred.\r
+\r
+ // ... Do other time functions.\r
+\r
+ // Is it time for vATask () to run?\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+ ucLocalTickCount++;\r
+ if( ucLocalTickCount >= TICKS_TO_WAIT )\r
+ {\r
+ // Unblock the task by releasing the semaphore.\r
+ xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\r
+\r
+ // Reset the count so we release the semaphore again in 10 ticks time.\r
+ ucLocalTickCount = 0;\r
+ }\r
+\r
+ if( xHigherPriorityTaskWoken != pdFALSE )\r
+ {\r
+ // We can force a context switch here. Context switching from an\r
+ // ISR uses port specific syntax. Check the demo task for your port\r
+ // to find the syntax required.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueueHandle ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>\r
+ xSemaphoreTakeFromISR( \r
+ xSemaphoreHandle xSemaphore, \r
+ signed portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ )</pre>\r
+ *\r
+ * <i>Macro</i> to take a semaphore from an ISR. The semaphore must have \r
+ * previously been created with a call to vSemaphoreCreateBinary() or \r
+ * xSemaphoreCreateCounting().\r
+ *\r
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\r
+ * must not be used with this macro.\r
+ *\r
+ * This macro can be used from an ISR, however taking a semaphore from an ISR\r
+ * is not a common operation. It is likely to only be useful when taking a\r
+ * counting semaphore when an interrupt is obtaining an object from a resource\r
+ * pool (when the semaphore count indicates the number of resources available).\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being taken. This is the\r
+ * handle returned when the semaphore was created.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the semaphore was successfully taken, otherwise \r
+ * pdFALSE\r
+ */\r
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( xQueueHandle ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateMutex( void )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a mutex semaphore by using the existing queue \r
+ * mechanism.\r
+ *\r
+ * Mutexes created using this macro can be accessed using the xSemaphoreTake()\r
+ * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and \r
+ * xSemaphoreGiveRecursive() macros should not be used.\r
+ * \r
+ * This type of semaphore uses a priority inheritance mechanism so a task \r
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the \r
+ * semaphore it is no longer required. \r
+ *\r
+ * Mutex type semaphores cannot be used from within interrupt service routines. \r
+ *\r
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be \r
+ * used for pure synchronisation (where one task or interrupt always 'gives' the \r
+ * semaphore and another always 'takes' the semaphore) and from within interrupt \r
+ * service routines.\r
+ *\r
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type \r
+ * xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r
+ // This is a macro so pass the variable in directly.\r
+ xSemaphore = xSemaphoreCreateMutex();\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )\r
+\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateRecursiveMutex( void )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a recursive mutex by using the existing queue \r
+ * mechanism.\r
+ *\r
+ * Mutexes created using this macro can be accessed using the \r
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The \r
+ * xSemaphoreTake() and xSemaphoreGive() macros should not be used.\r
+ *\r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ * \r
+ * This type of semaphore uses a priority inheritance mechanism so a task \r
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the \r
+ * semaphore it is no longer required. \r
+ *\r
+ * Mutex type semaphores cannot be used from within interrupt service routines. \r
+ *\r
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be \r
+ * used for pure synchronisation (where one task or interrupt always 'gives' the \r
+ * semaphore and another always 'takes' the semaphore) and from within interrupt \r
+ * service routines.\r
+ *\r
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type \r
+ * xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r
+ // This is a macro so pass the variable in directly.\r
+ xSemaphore = xSemaphoreCreateRecursiveMutex();\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateCounting( unsigned portBASE_TYPE uxMaxCount, unsigned portBASE_TYPE uxInitialCount )</pre>\r
+ *\r
+ * <i>Macro</i> that creates a counting semaphore by using the existing \r
+ * queue mechanism. \r
+ *\r
+ * Counting semaphores are typically used for two things:\r
+ *\r
+ * 1) Counting events. \r
+ *\r
+ * In this usage scenario an event handler will 'give' a semaphore each time\r
+ * an event occurs (incrementing the semaphore count value), and a handler \r
+ * task will 'take' a semaphore each time it processes an event \r
+ * (decrementing the semaphore count value). The count value is therefore \r
+ * the difference between the number of events that have occurred and the \r
+ * number that have been processed. In this case it is desirable for the \r
+ * initial count value to be zero.\r
+ *\r
+ * 2) Resource management.\r
+ *\r
+ * In this usage scenario the count value indicates the number of resources\r
+ * available. To obtain control of a resource a task must first obtain a \r
+ * semaphore - decrementing the semaphore count value. When the count value\r
+ * reaches zero there are no free resources. When a task finishes with the\r
+ * resource it 'gives' the semaphore back - incrementing the semaphore count\r
+ * value. In this case it is desirable for the initial count value to be\r
+ * equal to the maximum count value, indicating that all resources are free.\r
+ *\r
+ * @param uxMaxCount The maximum count value that can be reached. When the \r
+ * semaphore reaches this value it can no longer be 'given'.\r
+ *\r
+ * @param uxInitialCount The count value assigned to the semaphore when it is\r
+ * created.\r
+ *\r
+ * @return Handle to the created semaphore. Null if the semaphore could not be\r
+ * created.\r
+ * \r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\r
+ // The max value to which the semaphore can count should be 10, and the\r
+ // initial value assigned to the count should be 0.\r
+ xSemaphore = xSemaphoreCreateCounting( 10, 0 );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>void vSemaphoreDelete( xSemaphoreHandle xSemaphore );</pre>\r
+ *\r
+ * Delete a semaphore. This function must be used with care. For example,\r
+ * do not delete a mutex type semaphore if the mutex is held by a task.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore to be deleted.\r
+ *\r
+ * \page vSemaphoreDelete vSemaphoreDelete\r
+ * \ingroup Semaphores\r
+ */\r
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( xQueueHandle ) ( xSemaphore ) )\r
+\r
+/**\r
+ * semphr.h\r
+ * <pre>xTaskHandle xSemaphoreGetMutexHolder( xSemaphoreHandle xMutex );</pre>\r
+ *\r
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\r
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held\r
+ * by a task), return NULL.\r
+ *\r
+ * Note: This Is is a good way of determining if the calling task is the mutex \r
+ * holder, but not a good way of determining the identity of the mutex holder as\r
+ * the holder may change between the function exiting and the returned value\r
+ * being tested.\r
+ */\r
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )\r
+\r
+#endif /* SEMAPHORE_H */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - Selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef TASK_H\r
+#define TASK_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include task.h"\r
+#endif\r
+\r
+#include "portable.h"\r
+#include "list.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * MACROS AND DEFINITIONS\r
+ *----------------------------------------------------------*/\r
+\r
+#define tskKERNEL_VERSION_NUMBER "V7.1.1"\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Type by which tasks are referenced. For example, a call to xTaskCreate\r
+ * returns (via a pointer parameter) an xTaskHandle variable that can then\r
+ * be used as a parameter to vTaskDelete to delete the task.\r
+ *\r
+ * \page xTaskHandle xTaskHandle\r
+ * \ingroup Tasks\r
+ */\r
+typedef void * xTaskHandle;\r
+\r
+/*\r
+ * Used internally only.\r
+ */\r
+typedef struct xTIME_OUT\r
+{\r
+ portBASE_TYPE xOverflowCount;\r
+ portTickType xTimeOnEntering;\r
+} xTimeOutType;\r
+\r
+/*\r
+ * Defines the memory ranges allocated to the task when an MPU is used.\r
+ */\r
+typedef struct xMEMORY_REGION\r
+{\r
+ void *pvBaseAddress;\r
+ unsigned long ulLengthInBytes;\r
+ unsigned long ulParameters;\r
+} xMemoryRegion;\r
+\r
+/*\r
+ * Parameters required to create an MPU protected task.\r
+ */\r
+typedef struct xTASK_PARAMTERS\r
+{\r
+ pdTASK_CODE pvTaskCode;\r
+ const signed char * const pcName;\r
+ unsigned short usStackDepth;\r
+ void *pvParameters;\r
+ unsigned portBASE_TYPE uxPriority;\r
+ portSTACK_TYPE *puxStackBuffer;\r
+ xMemoryRegion xRegions[ portNUM_CONFIGURABLE_REGIONS ];\r
+} xTaskParameters;\r
+\r
+/*\r
+ * Defines the priority used by the idle task. This must not be modified.\r
+ *\r
+ * \ingroup TaskUtils\r
+ */\r
+#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0U )\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro for forcing a context switch.\r
+ *\r
+ * \page taskYIELD taskYIELD\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskYIELD() portYIELD()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the start of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskENTER_CRITICAL taskENTER_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENTER_CRITICAL() portENTER_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the end of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskEXIT_CRITICAL taskEXIT_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to disable all maskable interrupts.\r
+ *\r
+ * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to enable microcontroller interrupts.\r
+ *\r
+ * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()\r
+\r
+/* Definitions returned by xTaskGetSchedulerState(). */\r
+#define taskSCHEDULER_NOT_STARTED 0\r
+#define taskSCHEDULER_RUNNING 1\r
+#define taskSCHEDULER_SUSPENDED 2\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ portBASE_TYPE xTaskCreate(\r
+ pdTASK_CODE pvTaskCode,\r
+ const char * const pcName,\r
+ unsigned short usStackDepth,\r
+ void *pvParameters,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ xTaskHandle *pvCreatedTask\r
+ );</pre>\r
+ *\r
+ * Create a new task and add it to the list of tasks that are ready to run.\r
+ *\r
+ * xTaskCreate() can only be used to create a task that has unrestricted\r
+ * access to the entire microcontroller memory map. Systems that include MPU\r
+ * support can alternatively create an MPU constrained task using\r
+ * xTaskCreateRestricted().\r
+ *\r
+ * @param pvTaskCode Pointer to the task entry function. Tasks\r
+ * must be implemented to never return (i.e. continuous loop).\r
+ *\r
+ * @param pcName A descriptive name for the task. This is mainly used to\r
+ * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default\r
+ * is 16.\r
+ *\r
+ * @param usStackDepth The size of the task stack specified as the number of\r
+ * variables the stack can hold - not the number of bytes. For example, if\r
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\r
+ * will be allocated for stack storage.\r
+ *\r
+ * @param pvParameters Pointer that will be used as the parameter for the task\r
+ * being created.\r
+ *\r
+ * @param uxPriority The priority at which the task should run. Systems that\r
+ * include MPU support can optionally create tasks in a privileged (system)\r
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For\r
+ * example, to create a privileged task at priority 2 the uxPriority parameter\r
+ * should be set to ( 2 | portPRIVILEGE_BIT ).\r
+ *\r
+ * @param pvCreatedTask Used to pass back a handle by which the created task\r
+ * can be referenced.\r
+ *\r
+ * @return pdPASS if the task was successfully created and added to a ready\r
+ * list, otherwise an error code defined in the file errors. h\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Task to be created.\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+ }\r
+ }\r
+\r
+ // Function that creates a task.\r
+ void vOtherFunction( void )\r
+ {\r
+ static unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+\r
+ // Create the task, storing the handle. Note that the passed parameter ucParameterToPass\r
+ // must exist for the lifetime of the task, so in this case is declared static. If it was just an\r
+ // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\r
+ // the new task attempts to access it.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskCreate xTaskCreate\r
+ * \ingroup Tasks\r
+ */\r
+#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) )\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ portBASE_TYPE xTaskCreateRestricted( xTaskParameters *pxTaskDefinition, xTaskHandle *pxCreatedTask );</pre>\r
+ *\r
+ * xTaskCreateRestricted() should only be used in systems that include an MPU\r
+ * implementation.\r
+ *\r
+ * Create a new task and add it to the list of tasks that are ready to run.\r
+ * The function parameters define the memory regions and associated access\r
+ * permissions allocated to the task.\r
+ *\r
+ * @param pxTaskDefinition Pointer to a structure that contains a member\r
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\r
+ * documentation) plus an optional stack buffer and the memory region\r
+ * definitions.\r
+ *\r
+ * @param pxCreatedTask Used to pass back a handle by which the created task\r
+ * can be referenced.\r
+ *\r
+ * @return pdPASS if the task was successfully created and added to a ready\r
+ * list, otherwise an error code defined in the file errors. h\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+// Create an xTaskParameters structure that defines the task to be created.\r
+static const xTaskParameters xCheckTaskParameters =\r
+{\r
+ vATask, // pvTaskCode - the function that implements the task.\r
+ "ATask", // pcName - just a text name for the task to assist debugging.\r
+ 100, // usStackDepth - the stack size DEFINED IN WORDS.\r
+ NULL, // pvParameters - passed into the task function as the function parameters.\r
+ ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\r
+ cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\r
+\r
+ // xRegions - Allocate up to three separate memory regions for access by\r
+ // the task, with appropriate access permissions. Different processors have\r
+ // different memory alignment requirements - refer to the FreeRTOS documentation\r
+ // for full information.\r
+ { \r
+ // Base address Length Parameters\r
+ { cReadWriteArray, 32, portMPU_REGION_READ_WRITE },\r
+ { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY },\r
+ { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE }\r
+ }\r
+};\r
+\r
+int main( void )\r
+{\r
+xTaskHandle xHandle;\r
+\r
+ // Create a task from the const structure defined above. The task handle\r
+ // is requested (the second parameter is not NULL) but in this case just for\r
+ // demonstration purposes as its not actually used.\r
+ xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\r
+\r
+ // Start the scheduler.\r
+ vTaskStartScheduler();\r
+\r
+ // Will only get here if there was insufficient memory to create the idle\r
+ // task.\r
+ for( ;; );\r
+}\r
+ </pre>\r
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted\r
+ * \ingroup Tasks\r
+ */\r
+#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) )\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions );</pre>\r
+ *\r
+ * Memory regions are assigned to a restricted task when the task is created by\r
+ * a call to xTaskCreateRestricted(). These regions can be redefined using\r
+ * vTaskAllocateMPURegions().\r
+ *\r
+ * @param xTask The handle of the task being updated.\r
+ *\r
+ * @param xRegions A pointer to an xMemoryRegion structure that contains the\r
+ * new memory region definitions.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+// Define an array of xMemoryRegion structures that configures an MPU region\r
+// allowing read/write access for 1024 bytes starting at the beginning of the\r
+// ucOneKByte array. The other two of the maximum 3 definable regions are\r
+// unused so set to zero.\r
+static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\r
+{ \r
+ // Base address Length Parameters\r
+ { ucOneKByte, 1024, portMPU_REGION_READ_WRITE },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 }\r
+};\r
+\r
+void vATask( void *pvParameters )\r
+{\r
+ // This task was created such that it has access to certain regions of\r
+ // memory as defined by the MPU configuration. At some point it is\r
+ // desired that these MPU regions are replaced with that defined in the\r
+ // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions()\r
+ // for this purpose. NULL is used as the task handle to indicate that this\r
+ // function should modify the MPU regions of the calling task.\r
+ vTaskAllocateMPURegions( NULL, xAltRegions );\r
+ \r
+ // Now the task can continue its function, but from this point on can only\r
+ // access its stack and the ucOneKByte array (unless any other statically\r
+ // defined or shared regions have been declared elsewhere).\r
+}\r
+ </pre>\r
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted\r
+ * \ingroup Tasks\r
+ */\r
+void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelete( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Remove a task from the RTOS real time kernels management. The task being\r
+ * deleted will be removed from all ready, blocked, suspended and event lists.\r
+ *\r
+ * NOTE: The idle task is responsible for freeing the kernel allocated\r
+ * memory from tasks that have been deleted. It is therefore important that\r
+ * the idle task is not starved of microcontroller processing time if your\r
+ * application makes any calls to vTaskDelete (). Memory allocated by the\r
+ * task code is not automatically freed, and should be freed before the task\r
+ * is deleted.\r
+ *\r
+ * See the demo application file death.c for sample code that utilises\r
+ * vTaskDelete ().\r
+ *\r
+ * @param pxTask The handle of the task to be deleted. Passing NULL will\r
+ * cause the calling task to be deleted.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vOtherFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create the task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelete vTaskDelete\r
+ * \ingroup Tasks\r
+ */\r
+void vTaskDelete( xTaskHandle pxTaskToDelete ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelay( portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a task for a given number of ticks. The actual time that the\r
+ * task remains blocked depends on the tick rate. The constant\r
+ * portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ *\r
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to\r
+ * the time at which vTaskDelay() is called. For example, specifying a block\r
+ * period of 100 ticks will cause the task to unblock 100 ticks after\r
+ * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method\r
+ * of controlling the frequency of a cyclical task as the path taken through the\r
+ * code, as well as other task and interrupt activity, will effect the frequency\r
+ * at which vTaskDelay() gets called and therefore the time at which the task\r
+ * next executes. See vTaskDelayUntil() for an alternative API function designed\r
+ * to facilitate fixed frequency execution. It does this by specifying an\r
+ * absolute time (rather than a relative time) at which the calling task should\r
+ * unblock.\r
+ *\r
+ * @param xTicksToDelay The amount of time, in tick periods, that\r
+ * the calling task should block.\r
+ *\r
+ * Example usage:\r
+\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ // Block for 500ms.\r
+ const portTickType xDelay = 500 / portTICK_RATE_MS;\r
+\r
+ for( ;; )\r
+ {\r
+ // Simply toggle the LED every 500ms, blocking between each toggle.\r
+ vToggleLED();\r
+ vTaskDelay( xDelay );\r
+ }\r
+ }\r
+\r
+ * \defgroup vTaskDelay vTaskDelay\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelay( portTickType xTicksToDelay ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Delay a task until a specified time. This function can be used by cyclical\r
+ * tasks to ensure a constant execution frequency.\r
+ *\r
+ * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will\r
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is\r
+ * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed\r
+ * execution frequency as the time between a task starting to execute and that task\r
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the\r
+ * code between calls, or may get interrupted or preempted a different number of times\r
+ * each time it executes].\r
+ *\r
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\r
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\r
+ * unblock.\r
+ *\r
+ * The constant portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\r
+ * task was last unblocked. The variable must be initialised with the current time\r
+ * prior to its first use (see the example below). Following this the variable is\r
+ * automatically updated within vTaskDelayUntil ().\r
+ *\r
+ * @param xTimeIncrement The cycle time period. The task will be unblocked at\r
+ * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the\r
+ * same xTimeIncrement parameter value will cause the task to execute with\r
+ * a fixed interface period.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Perform an action every 10 ticks.\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ portTickType xLastWakeTime;\r
+ const portTickType xFrequency = 10;\r
+\r
+ // Initialise the xLastWakeTime variable with the current time.\r
+ xLastWakeTime = xTaskGetTickCount ();\r
+ for( ;; )\r
+ {\r
+ // Wait for the next cycle.\r
+ vTaskDelayUntil( &xLastWakeTime, xFrequency );\r
+\r
+ // Perform action here.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelayUntil vTaskDelayUntil\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Obtain the priority of any task.\r
+ *\r
+ * @param pxTask Handle of the task to be queried. Passing a NULL\r
+ * handle results in the priority of the calling task being returned.\r
+ *\r
+ * @return The priority of pxTask.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to obtain the priority of the created task.\r
+ // It was created with tskIDLE_PRIORITY, but may have changed\r
+ // it itself.\r
+ if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\r
+ {\r
+ // The task has changed it's priority.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Is our priority higher than the created task?\r
+ if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\r
+ {\r
+ // Our priority (obtained using NULL handle) is higher.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet\r
+ * \ingroup TaskCtrl\r
+ */\r
+unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );</pre>\r
+ *\r
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Set the priority of any task.\r
+ *\r
+ * A context switch will occur before the function returns if the priority\r
+ * being set is higher than the currently executing task.\r
+ *\r
+ * @param pxTask Handle to the task for which the priority is being set.\r
+ * Passing a NULL handle results in the priority of the calling task being set.\r
+ *\r
+ * @param uxNewPriority The priority to which the task will be set.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to raise the priority of the created task.\r
+ vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\r
+\r
+ // ...\r
+\r
+ // Use a NULL handle to raise our priority to the same value.\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskPrioritySet vTaskPrioritySet\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspend( xTaskHandle pxTaskToSuspend );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Suspend any task. When suspended a task will never get any microcontroller\r
+ * processing time, no matter what its priority.\r
+ *\r
+ * Calls to vTaskSuspend are not accumulative -\r
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one\r
+ * call to vTaskResume () to ready the suspended task.\r
+ *\r
+ * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL\r
+ * handle will cause the calling task to be suspended.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+\r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+\r
+ //...\r
+\r
+\r
+ // Suspend ourselves.\r
+ vTaskSuspend( NULL );\r
+\r
+ // We cannot get here unless another task calls vTaskResume\r
+ // with our handle as the parameter.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspend vTaskSuspend\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskSuspend( xTaskHandle pxTaskToSuspend ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskResume( xTaskHandle pxTaskToResume );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Resumes a suspended task.\r
+ *\r
+ * A task that has been suspended by one of more calls to vTaskSuspend ()\r
+ * will be made available for running again by a single call to\r
+ * vTaskResume ().\r
+ *\r
+ * @param pxTaskToResume Handle to the task being readied.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+\r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+\r
+ //...\r
+\r
+\r
+ // Resume the suspended task ourselves.\r
+ vTaskResume( xHandle );\r
+\r
+ // The created task will once again get microcontroller processing\r
+ // time in accordance with it priority within the system.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskResume vTaskResume\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskResume( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void xTaskResumeFromISR( xTaskHandle pxTaskToResume );</pre>\r
+ *\r
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\r
+ * available. See the configuration section for more information.\r
+ *\r
+ * An implementation of vTaskResume() that can be called from within an ISR.\r
+ *\r
+ * A task that has been suspended by one of more calls to vTaskSuspend ()\r
+ * will be made available for running again by a single call to\r
+ * xTaskResumeFromISR ().\r
+ *\r
+ * @param pxTaskToResume Handle to the task being readied.\r
+ *\r
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR\r
+ * \ingroup TaskCtrl\r
+ */\r
+portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER CONTROL\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskStartScheduler( void );</pre>\r
+ *\r
+ * Starts the real time kernel tick processing. After calling the kernel\r
+ * has control over which tasks are executed and when. This function\r
+ * does not return until an executing task calls vTaskEndScheduler ().\r
+ *\r
+ * At least one task should be created via a call to xTaskCreate ()\r
+ * before calling vTaskStartScheduler (). The idle task is created\r
+ * automatically when the first application task is created.\r
+ *\r
+ * See the demo application file main.c for an example of creating\r
+ * tasks and starting the kernel.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will not get here unless a task calls vTaskEndScheduler ()\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskStartScheduler vTaskStartScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskEndScheduler( void );</pre>\r
+ *\r
+ * Stops the real time kernel tick. All created tasks will be automatically\r
+ * deleted and multitasking (either preemptive or cooperative) will\r
+ * stop. Execution then resumes from the point where vTaskStartScheduler ()\r
+ * was called, as if vTaskStartScheduler () had just returned.\r
+ *\r
+ * See the demo application file main. c in the demo/PC directory for an\r
+ * example that uses vTaskEndScheduler ().\r
+ *\r
+ * vTaskEndScheduler () requires an exit function to be defined within the\r
+ * portable layer (see vPortEndScheduler () in port. c for the PC port). This\r
+ * performs hardware specific operations such as stopping the kernel tick.\r
+ *\r
+ * vTaskEndScheduler () will cause all of the resources allocated by the\r
+ * kernel to be freed - but will not free resources allocated by application\r
+ * tasks.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // At some point we want to end the real time kernel processing\r
+ // so call ...\r
+ vTaskEndScheduler ();\r
+ }\r
+ }\r
+\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will only get here when the vTaskCode () task has called\r
+ // vTaskEndScheduler (). When we get here we are back to single task\r
+ // execution.\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskEndScheduler vTaskEndScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspendAll( void );</pre>\r
+ *\r
+ * Suspends all real time kernel activity while keeping interrupts (including the\r
+ * kernel tick) enabled.\r
+ *\r
+ * After calling vTaskSuspendAll () the calling task will continue to execute\r
+ * without risk of being swapped out until a call to xTaskResumeAll () has been\r
+ * made.\r
+ *\r
+ * API functions that have the potential to cause a context switch (for example,\r
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\r
+ * is suspended.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the kernel\r
+ // tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel.\r
+ xTaskResumeAll ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspendAll vTaskSuspendAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>char xTaskResumeAll( void );</pre>\r
+ *\r
+ * Resumes real time kernel activity following a call to vTaskSuspendAll ().\r
+ * After a call to vTaskSuspendAll () the kernel will take control of which\r
+ * task is executing at any time.\r
+ *\r
+ * @return If resuming the scheduler caused a context switch then pdTRUE is\r
+ * returned, otherwise pdFALSE is returned.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the real\r
+ // time kernel tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel. We want to force\r
+ // a context switch - but there is no point if resuming the scheduler\r
+ // caused a context switch already.\r
+ if( !xTaskResumeAll () )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskResumeAll xTaskResumeAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+signed portBASE_TYPE xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask );</pre>\r
+ *\r
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is\r
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask\r
+ * is in any other state.\r
+ *\r
+ */\r
+signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK UTILITIES\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>portTickType xTaskGetTickCount( void );</PRE>\r
+ *\r
+ * @return The count of ticks since vTaskStartScheduler was called.\r
+ *\r
+ * \page xTaskGetTickCount xTaskGetTickCount\r
+ * \ingroup TaskUtils\r
+ */\r
+portTickType xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>portTickType xTaskGetTickCountFromISR( void );</PRE>\r
+ *\r
+ * @return The count of ticks since vTaskStartScheduler was called.\r
+ *\r
+ * This is a version of xTaskGetTickCount() that is safe to be called from an\r
+ * ISR - provided that portTickType is the natural word size of the\r
+ * microcontroller being used or interrupt nesting is either not supported or\r
+ * not being used.\r
+ *\r
+ * \page xTaskGetTickCount xTaskGetTickCount\r
+ * \ingroup TaskUtils\r
+ */\r
+portTickType xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned short uxTaskGetNumberOfTasks( void );</PRE>\r
+ *\r
+ * @return The number of tasks that the real time kernel is currently managing.\r
+ * This includes all ready, blocked and suspended tasks. A task that\r
+ * has been deleted but not yet freed by the idle task will also be\r
+ * included in the count.\r
+ *\r
+ * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );</PRE>\r
+ *\r
+ * @return The text (human readable) name of the task referenced by the handle\r
+ * xTaskToQueury. A task can query its own name by either passing in its own\r
+ * handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be\r
+ * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.\r
+ *\r
+ * \page pcTaskGetTaskName pcTaskGetTaskName\r
+ * \ingroup TaskUtils\r
+ */\r
+signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>\r
+ *\r
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be\r
+ * available. See the configuration section for more information.\r
+ *\r
+ * NOTE: This function will disable interrupts for its duration. It is\r
+ * not intended for normal application runtime use but as a debug aid.\r
+ *\r
+ * Lists all the current tasks, along with their current state and stack\r
+ * usage high water mark.\r
+ *\r
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\r
+ * suspended ('S').\r
+ *\r
+ * @param pcWriteBuffer A buffer into which the above mentioned details\r
+ * will be written, in ascii form. This buffer is assumed to be large\r
+ * enough to contain the generated report. Approximately 40 bytes per\r
+ * task should be sufficient.\r
+ *\r
+ * \page vTaskList vTaskList\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskList( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>\r
+ *\r
+ * configGENERATE_RUN_TIME_STATS must be defined as 1 for this function\r
+ * to be available. The application must also then provide definitions\r
+ * for portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and\r
+ * portGET_RUN_TIME_COUNTER_VALUE to configure a peripheral timer/counter\r
+ * and return the timers current count value respectively. The counter\r
+ * should be at least 10 times the frequency of the tick count.\r
+ *\r
+ * NOTE: This function will disable interrupts for its duration. It is\r
+ * not intended for normal application runtime use but as a debug aid.\r
+ *\r
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\r
+ * accumulated execution time being stored for each task. The resolution\r
+ * of the accumulated time value depends on the frequency of the timer\r
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\r
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each\r
+ * task into a buffer, both as an absolute count value and as a percentage\r
+ * of the total system execution time.\r
+ *\r
+ * @param pcWriteBuffer A buffer into which the execution times will be\r
+ * written, in ascii form. This buffer is assumed to be large enough to\r
+ * contain the generated report. Approximately 40 bytes per task should\r
+ * be sufficient.\r
+ *\r
+ * \page vTaskGetRunTimeStats vTaskGetRunTimeStats\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskGetRunTimeStats( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskStartTrace( char * pcBuffer, unsigned portBASE_TYPE uxBufferSize );</PRE>\r
+ *\r
+ * Starts a real time kernel activity trace. The trace logs the identity of\r
+ * which task is running when.\r
+ *\r
+ * The trace file is stored in binary format. A separate DOS utility called\r
+ * convtrce.exe is used to convert this into a tab delimited text file which\r
+ * can be viewed and plotted in a spread sheet.\r
+ *\r
+ * @param pcBuffer The buffer into which the trace will be written.\r
+ *\r
+ * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue\r
+ * until either the buffer in full, or ulTaskEndTrace () is called.\r
+ *\r
+ * \page vTaskStartTrace vTaskStartTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned long ulTaskEndTrace( void );</PRE>\r
+ *\r
+ * Stops a kernel activity trace. See vTaskStartTrace ().\r
+ *\r
+ * @return The number of bytes that have been written into the trace buffer.\r
+ *\r
+ * \page usTaskEndTrace usTaskEndTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned long ulTaskEndTrace( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task.h\r
+ * <PRE>unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask );</PRE>\r
+ *\r
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\r
+ * this function to be available.\r
+ *\r
+ * Returns the high water mark of the stack associated with xTask. That is,\r
+ * the minimum free stack space there has been (in words, so on a 32 bit machine\r
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned\r
+ * number the closer the task has come to overflowing its stack.\r
+ *\r
+ * @param xTask Handle of the task associated with the stack to be checked.\r
+ * Set xTask to NULL to check the stack of the calling task.\r
+ *\r
+ * @return The smallest amount of free stack space there has been (in bytes)\r
+ * since the task referenced by xTask was created.\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+\r
+/* When using trace macros it is sometimes necessary to include tasks.h before\r
+FreeRTOS.h. When this is done pdTASK_HOOK_CODE will not yet have been defined,\r
+so the following two prototypes will cause a compilation error. This can be\r
+fixed by simply guarding against the inclusion of these two prototypes unless\r
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\r
+constant. */\r
+#ifdef configUSE_APPLICATION_TASK_TAG\r
+ #if configUSE_APPLICATION_TASK_TAG == 1\r
+ /**\r
+ * task.h\r
+ * <pre>void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre>\r
+ *\r
+ * Sets pxHookFunction to be the task hook function used by the task xTask.\r
+ * Passing xTask as NULL has the effect of setting the calling tasks hook\r
+ * function.\r
+ */\r
+ void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction ) PRIVILEGED_FUNCTION;\r
+\r
+ /**\r
+ * task.h\r
+ * <pre>void xTaskGetApplicationTaskTag( xTaskHandle xTask );</pre>\r
+ *\r
+ * Returns the pxHookFunction value assigned to the task xTask.\r
+ */\r
+ pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+ #endif /* configUSE_APPLICATION_TASK_TAG ==1 */\r
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\r
+\r
+/**\r
+ * task.h\r
+ * <pre>portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre>\r
+ *\r
+ * Calls the hook function associated with xTask. Passing xTask as NULL has\r
+ * the effect of calling the Running tasks (the calling task) hook function.\r
+ *\r
+ * pvParameter is passed to the hook function for the task to interpret as it\r
+ * wants.\r
+ */\r
+portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * xTaskGetIdleTaskHandle() is only available if \r
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\r
+ *\r
+ * Simply returns the handle of the idle task. It is not valid to call\r
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.\r
+ */\r
+xTaskHandle xTaskGetIdleTaskHandle( void );\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Called from the real time kernel tick (either preemptive or cooperative),\r
+ * this increments the tick count and checks if any tasks that are blocked\r
+ * for a finite period required removing from a blocked list and placing on\r
+ * a ready list.\r
+ */\r
+void vTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes the calling task from the ready list and places it both\r
+ * on the list of tasks waiting for a particular event, and the\r
+ * list of delayed tasks. The task will be removed from both lists\r
+ * and replaced on the ready list should either the event occur (and\r
+ * there be no higher priority tasks waiting on the same event) or\r
+ * the delay period expires.\r
+ *\r
+ * @param pxEventList The list containing tasks that are blocked waiting\r
+ * for the event to occur.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time that the task should wait\r
+ * for the event to occur. This is specified in kernel ticks,the constant\r
+ * portTICK_RATE_MS can be used to convert kernel ticks into a real time\r
+ * period.\r
+ */\r
+void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * This function performs nearly the same function as vTaskPlaceOnEventList().\r
+ * The difference being that this function does not permit tasks to block\r
+ * indefinitely, whereas vTaskPlaceOnEventList() does.\r
+ *\r
+ * @return pdTRUE if the task being removed has a higher priority than the task\r
+ * making the call, otherwise pdFALSE.\r
+ */\r
+void vTaskPlaceOnEventListRestricted( const xList * const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes a task from both the specified event list and the list of blocked\r
+ * tasks, and places it on a ready queue.\r
+ *\r
+ * xTaskRemoveFromEventList () will be called if either an event occurs to\r
+ * unblock a task, or the block timeout period expires.\r
+ *\r
+ * @return pdTRUE if the task being removed has a higher priority than the task\r
+ * making the call, otherwise pdFALSE.\r
+ */\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Sets the pointer to the current TCB to the TCB of the highest priority task\r
+ * that is ready to run.\r
+ */\r
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Return the handle of the calling task.\r
+ */\r
+xTaskHandle xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Capture the current time status for future reference.\r
+ */\r
+void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Compare the time status now with that previously captured to see if the\r
+ * timeout has expired.\r
+ */\r
+portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Shortcut used by the queue implementation to prevent unnecessary call to\r
+ * taskYIELD();\r
+ */\r
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,\r
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\r
+ */\r
+portBASE_TYPE xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Raises the priority of the mutex holder to that of the calling task should\r
+ * the mutex holder have a priority less than the calling task.\r
+ */\r
+void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Set the priority of a task back to its proper priority in the case that it\r
+ * inherited a higher priority while it was holding a semaphore.\r
+ */\r
+void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Generic version of the task creation function which is in turn called by the\r
+ * xTaskCreate() and xTaskCreateRestricted() macros.\r
+ */\r
+signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetTaskNumber( xTaskHandle xTask );\r
+\r
+/* \r
+ * Set the uxTCBNumber of the task referenced by the xTask parameter to\r
+ * ucHandle.\r
+ */\r
+void vTaskSetTaskNumber( xTaskHandle xTask, unsigned portBASE_TYPE uxHandle );\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* TASK_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef TIMERS_H\r
+#define TIMERS_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include timers.h"\r
+#endif\r
+\r
+#include "portable.h"\r
+#include "list.h"\r
+#include "task.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* IDs for commands that can be sent/received on the timer queue. These are to\r
+be used solely through the macros that make up the public software timer API,\r
+as defined below. */\r
+#define tmrCOMMAND_START 0\r
+#define tmrCOMMAND_STOP 1\r
+#define tmrCOMMAND_CHANGE_PERIOD 2\r
+#define tmrCOMMAND_DELETE 3\r
+\r
+/*-----------------------------------------------------------\r
+ * MACROS AND DEFINITIONS\r
+ *----------------------------------------------------------*/\r
+\r
+ /**\r
+ * Type by which software timers are referenced. For example, a call to\r
+ * xTimerCreate() returns an xTimerHandle variable that can then be used to\r
+ * reference the subject timer in calls to other software timer API functions\r
+ * (for example, xTimerStart(), xTimerReset(), etc.).\r
+ */\r
+typedef void * xTimerHandle;\r
+\r
+/* Define the prototype to which timer callback functions must conform. */\r
+typedef void (*tmrTIMER_CALLBACK)( xTimerHandle xTimer );\r
+\r
+/**\r
+ * xTimerHandle xTimerCreate( const signed char *pcTimerName,\r
+ * portTickType xTimerPeriodInTicks,\r
+ * unsigned portBASE_TYPE uxAutoReload,\r
+ * void * pvTimerID,\r
+ * tmrTIMER_CALLBACK pxCallbackFunction );\r
+ *\r
+ * Creates a new software timer instance. This allocates the storage required\r
+ * by the new timer, initialises the new timers internal state, and returns a\r
+ * handle by which the new timer can be referenced.\r
+ *\r
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),\r
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\r
+ * active state.\r
+ *\r
+ * @param pcTimerName A text name that is assigned to the timer. This is done\r
+ * purely to assist debugging. The kernel itself only ever references a timer by\r
+ * its handle, and never by its name.\r
+ *\r
+ * @param xTimerPeriodInTicks The timer period. The time is defined in tick periods so\r
+ * the constant portTICK_RATE_MS can be used to convert a time that has been\r
+ * specified in milliseconds. For example, if the timer must expire after 100\r
+ * ticks, then xTimerPeriodInTicks should be set to 100. Alternatively, if the timer\r
+ * must expire after 500ms, then xPeriod can be set to ( 500 / portTICK_RATE_MS )\r
+ * provided configTICK_RATE_HZ is less than or equal to 1000.\r
+ *\r
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\r
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. If\r
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\r
+ * enter the dormant state after it expires.\r
+ *\r
+ * @param pvTimerID An identifier that is assigned to the timer being created.\r
+ * Typically this would be used in the timer callback function to identify which\r
+ * timer expired when the same callback function is assigned to more than one\r
+ * timer.\r
+ *\r
+ * @param pxCallbackFunction The function to call when the timer expires.\r
+ * Callback functions must have the prototype defined by tmrTIMER_CALLBACK,\r
+ * which is "void vCallbackFunction( xTimerHandle xTimer );".\r
+ *\r
+ * @return If the timer is successfully create then a handle to the newly\r
+ * created timer is returned. If the timer cannot be created (because either\r
+ * there is insufficient FreeRTOS heap remaining to allocate the timer\r
+ * structures, or the timer period was set to 0) then 0 is returned.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * #define NUM_TIMERS 5\r
+ *\r
+ * // An array to hold handles to the created timers.\r
+ * xTimerHandle xTimers[ NUM_TIMERS ];\r
+ *\r
+ * // An array to hold a count of the number of times each timer expires.\r
+ * long lExpireCounters[ NUM_TIMERS ] = { 0 };\r
+ *\r
+ * // Define a callback function that will be used by multiple timer instances.\r
+ * // The callback function does nothing but count the number of times the\r
+ * // associated timer expires, and stop the timer once the timer has expired\r
+ * // 10 times.\r
+ * void vTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * long lArrayIndex;\r
+ * const long xMaxExpiryCountBeforeStopping = 10;\r
+ *\r
+ * // Optionally do something if the pxTimer parameter is NULL.\r
+ * configASSERT( pxTimer );\r
+ * \r
+ * // Which timer expired?\r
+ * lArrayIndex = ( long ) pvTimerGetTimerID( pxTimer );\r
+ *\r
+ * // Increment the number of times that pxTimer has expired.\r
+ * lExpireCounters[ lArrayIndex ] += 1;\r
+ *\r
+ * // If the timer has expired 10 times then stop it from running.\r
+ * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\r
+ * {\r
+ * // Do not use a block time if calling a timer API function from a\r
+ * // timer callback function, as doing so could cause a deadlock!\r
+ * xTimerStop( pxTimer, 0 );\r
+ * }\r
+ * }\r
+ *\r
+ * void main( void )\r
+ * {\r
+ * long x;\r
+ *\r
+ * // Create then start some timers. Starting the timers before the scheduler\r
+ * // has been started means the timers will start running immediately that\r
+ * // the scheduler starts.\r
+ * for( x = 0; x < NUM_TIMERS; x++ )\r
+ * {\r
+ * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.\r
+ * ( 100 * x ), // The timer period in ticks.\r
+ * pdTRUE, // The timers will auto-reload themselves when they expire.\r
+ * ( void * ) x, // Assign each timer a unique id equal to its array index.\r
+ * vTimerCallback // Each timer calls the same callback when it expires.\r
+ * );\r
+ *\r
+ * if( xTimers[ x ] == NULL )\r
+ * {\r
+ * // The timer was not created.\r
+ * }\r
+ * else\r
+ * {\r
+ * // Start the timer. No block time is specified, and even if one was\r
+ * // it would be ignored because the scheduler has not yet been\r
+ * // started.\r
+ * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\r
+ * {\r
+ * // The timer could not be set into the Active state.\r
+ * }\r
+ * }\r
+ * }\r
+ *\r
+ * // ...\r
+ * // Create tasks here.\r
+ * // ...\r
+ *\r
+ * // Starting the scheduler will start the timers running as they have already\r
+ * // been set into the active state.\r
+ * xTaskStartScheduler();\r
+ *\r
+ * // Should not reach here.\r
+ * for( ;; );\r
+ * }\r
+ */\r
+xTimerHandle xTimerCreate( const signed char *pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void * pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * void *pvTimerGetTimerID( xTimerHandle xTimer );\r
+ *\r
+ * Returns the ID assigned to the timer.\r
+ *\r
+ * IDs are assigned to timers using the pvTimerID parameter of the call to\r
+ * xTimerCreated() that was used to create the timer.\r
+ *\r
+ * If the same callback function is assigned to multiple timers then the timer\r
+ * ID can be used within the callback function to identify which timer actually\r
+ * expired.\r
+ *\r
+ * @param xTimer The timer being queried.\r
+ *\r
+ * @return The ID assigned to the timer being queried.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ */\r
+void *pvTimerGetTimerID( xTimerHandle xTimer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer );\r
+ *\r
+ * Queries a timer to see if it is active or dormant.\r
+ *\r
+ * A timer will be dormant if:\r
+ * 1) It has been created but not started, or\r
+ * 2) It is an expired on-shot timer that has not been restarted.\r
+ *\r
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),\r
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\r
+ * active state.\r
+ *\r
+ * @param xTimer The timer being queried.\r
+ *\r
+ * @return pdFALSE will be returned if the timer is dormant. A value other than\r
+ * pdFALSE will be returned if the timer is active.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This function assumes xTimer has already been created.\r
+ * void vAFunction( xTimerHandle xTimer )\r
+ * {\r
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"\r
+ * {\r
+ * // xTimer is active, do something.\r
+ * }\r
+ * else\r
+ * {\r
+ * // xTimer is not active, do something else.\r
+ * }\r
+ * }\r
+ */\r
+portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * xTimerGetTimerDaemonTaskHandle() is only available if \r
+ * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.\r
+ *\r
+ * Simply returns the handle of the timer service/daemon task. It it not valid\r
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\r
+ */\r
+xTaskHandle xTimerGetTimerDaemonTaskHandle( void );\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStart( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerStart() starts a timer that was previously created using the\r
+ * xTimerCreate() API function. If the timer had already been started and was\r
+ * already in the active state, then xTimerStart() has equivalent functionality\r
+ * to the xTimerReset() API function.\r
+ *\r
+ * Starting a timer ensures the timer is in the active state. If the timer\r
+ * is not stopped, deleted, or reset in the mean time, the callback function\r
+ * associated with the timer will get called 'n' ticks after xTimerStart() was\r
+ * called, where 'n' is the timers defined period.\r
+ *\r
+ * It is valid to call xTimerStart() before the scheduler has been started, but\r
+ * when this is done the timer will not actually start until the scheduler is\r
+ * started, and the timers expiry time will be relative to when the scheduler is\r
+ * started, not relative to when xTimerStart() was called.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being started/restarted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the start command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerStart() was called. xBlockTime is ignored if xTimerStart() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the start command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system, although the\r
+ * timers expiry time is relative to when xTimerStart() is actually called. The\r
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ *\r
+ */\r
+#define xTimerStart( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStop( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerStop() stops a timer that was previously started using either of the\r
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\r
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\r
+ *\r
+ * Stopping a timer ensures the timer is not in the active state.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being stopped.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the stop command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerStop() was called. xBlockTime is ignored if xTimerStop() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the stop command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system. The timer\r
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ *\r
+ */\r
+#define xTimerStop( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerChangePeriod( xTimerHandle xTimer,\r
+ * portTickType xNewPeriod,\r
+ * portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerChangePeriod() changes the period of a timer that was previously\r
+ * created using the xTimerCreate() API function.\r
+ *\r
+ * xTimerChangePeriod() can be called to change the period of an active or\r
+ * dormant state timer.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for\r
+ * xTimerChangePeriod() to be available.\r
+ *\r
+ * @param xTimer The handle of the timer that is having its period changed.\r
+ *\r
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r
+ * tick periods, so the constant portTICK_RATE_MS can be used to convert a time\r
+ * that has been specified in milliseconds. For example, if the timer must\r
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,\r
+ * if the timer must expire after 500ms, then xNewPeriod can be set to\r
+ * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than\r
+ * or equal to 1000.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the change period command to be\r
+ * successfully sent to the timer command queue, should the queue already be\r
+ * full when xTimerChangePeriod() was called. xBlockTime is ignored if\r
+ * xTimerChangePeriod() is called before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the change period command could not be\r
+ * sent to the timer command queue even after xBlockTime ticks had passed.\r
+ * pdPASS will be returned if the command was successfully sent to the timer\r
+ * command queue. When the command is actually processed will depend on the\r
+ * priority of the timer service/daemon task relative to other tasks in the\r
+ * system. The timer service/daemon task priority is set by the\r
+ * configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This function assumes xTimer has already been created. If the timer\r
+ * // referenced by xTimer is already active when it is called, then the timer\r
+ * // is deleted. If the timer referenced by xTimer is not active when it is\r
+ * // called, then the period of the timer is set to 500ms and the timer is\r
+ * // started.\r
+ * void vAFunction( xTimerHandle xTimer )\r
+ * {\r
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"\r
+ * {\r
+ * // xTimer is already active - delete it.\r
+ * xTimerDelete( xTimer );\r
+ * }\r
+ * else\r
+ * {\r
+ * // xTimer is not active, change its period to 500ms. This will also\r
+ * // cause the timer to start. Block for a maximum of 100 ticks if the\r
+ * // change period command cannot immediately be sent to the timer\r
+ * // command queue.\r
+ * if( xTimerChangePeriod( xTimer, 500 / portTICK_RATE_MS, 100 ) == pdPASS )\r
+ * {\r
+ * // The command was successfully sent.\r
+ * }\r
+ * else\r
+ * {\r
+ * // The command could not be sent, even after waiting for 100 ticks\r
+ * // to pass. Take appropriate action here.\r
+ * }\r
+ * }\r
+ * }\r
+ */\r
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerDelete( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerDelete() deletes a timer that was previously created using the\r
+ * xTimerCreate() API function.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for\r
+ * xTimerDelete() to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being deleted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the delete command to be\r
+ * successfully sent to the timer command queue, should the queue already be\r
+ * full when xTimerDelete() was called. xBlockTime is ignored if xTimerDelete()\r
+ * is called before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the delete command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system. The timer\r
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerChangePeriod() API function example usage scenario.\r
+ */\r
+#define xTimerDelete( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerReset( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerReset() re-starts a timer that was previously created using the\r
+ * xTimerCreate() API function. If the timer had already been started and was\r
+ * already in the active state, then xTimerReset() will cause the timer to\r
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was\r
+ * called. If the timer was in the dormant state then xTimerReset() has\r
+ * equivalent functionality to the xTimerStart() API function.\r
+ *\r
+ * Resetting a timer ensures the timer is in the active state. If the timer\r
+ * is not stopped, deleted, or reset in the mean time, the callback function\r
+ * associated with the timer will get called 'n' ticks after xTimerReset() was\r
+ * called, where 'n' is the timers defined period.\r
+ *\r
+ * It is valid to call xTimerReset() before the scheduler has been started, but\r
+ * when this is done the timer will not actually start until the scheduler is\r
+ * started, and the timers expiry time will be relative to when the scheduler is\r
+ * started, not relative to when xTimerReset() was called.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being reset/started/restarted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the reset command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerReset() was called. xBlockTime is ignored if xTimerReset() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the reset command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system, although the\r
+ * timers expiry time is relative to when xTimerStart() is actually called. The\r
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer.\r
+ *\r
+ * xTimerHandle xBacklightTimer = NULL;\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press event handler.\r
+ * void vKeyPressEventHandler( char cKey )\r
+ * {\r
+ * // Ensure the LCD back-light is on, then reset the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. Wait 10 ticks for the command to be successfully sent\r
+ * // if it cannot be sent immediately.\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\r
+ * {\r
+ * // The reset command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ * }\r
+ *\r
+ * void main( void )\r
+ * {\r
+ * long x;\r
+ *\r
+ * // Create then start the one-shot timer that is responsible for turning\r
+ * // the back-light off if no keys are pressed within a 5 second period.\r
+ * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel.\r
+ * ( 5000 / portTICK_RATE_MS), // The timer period in ticks.\r
+ * pdFALSE, // The timer is a one-shot timer.\r
+ * 0, // The id is not used by the callback so can take any value.\r
+ * vBacklightTimerCallback // The callback function that switches the LCD back-light off.\r
+ * );\r
+ *\r
+ * if( xBacklightTimer == NULL )\r
+ * {\r
+ * // The timer was not created.\r
+ * }\r
+ * else\r
+ * {\r
+ * // Start the timer. No block time is specified, and even if one was\r
+ * // it would be ignored because the scheduler has not yet been\r
+ * // started.\r
+ * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\r
+ * {\r
+ * // The timer could not be set into the Active state.\r
+ * }\r
+ * }\r
+ *\r
+ * // ...\r
+ * // Create tasks here.\r
+ * // ...\r
+ *\r
+ * // Starting the scheduler will start the timer running as it has already\r
+ * // been set into the active state.\r
+ * xTaskStartScheduler();\r
+ *\r
+ * // Should not reach here.\r
+ * for( ;; );\r
+ * }\r
+ */\r
+#define xTimerReset( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStartFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerStart() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer being started/restarted.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerStartFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerStartFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerStartFromISR() function. If\r
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the start command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system, although the timers expiry time is\r
+ * relative to when xTimerStartFromISR() is actually called. The timer service/daemon\r
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xBacklightTimer has already been created. When a\r
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer, and unlike the example given for\r
+ * // the xTimerReset() function, the key press event handler is an interrupt\r
+ * // service routine.\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press interrupt service routine.\r
+ * void vKeyPressEventInterruptHandler( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // Ensure the LCD back-light is on, then restart the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. This is an interrupt service routine so can only\r
+ * // call FreeRTOS API functions that end in "FromISR".\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ *\r
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r
+ * // as both cause the timer to re-calculate its expiry time.\r
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r
+ * // declared (in this function).\r
+ * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The start command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStopFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerStop() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer being stopped.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerStopFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerStopFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerStopFromISR() function. If\r
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the stop command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system. The timer service/daemon task\r
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xTimer has already been created and started. When\r
+ * // an interrupt occurs, the timer should be simply stopped.\r
+ *\r
+ * // The interrupt service routine that stops the timer.\r
+ * void vAnExampleInterruptServiceRoutine( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // The interrupt has occurred - simply stop the timer.\r
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r
+ * // (within this function). As this is an interrupt service routine, only\r
+ * // FreeRTOS API functions that end in "FromISR" can be used.\r
+ * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The stop command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0, ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerChangePeriodFromISR( xTimerHandle xTimer,\r
+ * portTickType xNewPeriod,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerChangePeriod() that can be called from an interrupt\r
+ * service routine.\r
+ *\r
+ * @param xTimer The handle of the timer that is having its period changed.\r
+ *\r
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r
+ * tick periods, so the constant portTICK_RATE_MS can be used to convert a time\r
+ * that has been specified in milliseconds. For example, if the timer must\r
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,\r
+ * if the timer must expire after 500ms, then xNewPeriod can be set to\r
+ * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than\r
+ * or equal to 1000.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerChangePeriodFromISR() writes a message to the\r
+ * timer command queue, so has the potential to transition the timer service/\r
+ * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR()\r
+ * causes the timer service/daemon task to leave the Blocked state, and the\r
+ * timer service/daemon task has a priority equal to or greater than the\r
+ * currently executing task (the task that was interrupted), then\r
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\r
+ * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets\r
+ * this value to pdTRUE then a context switch should be performed before the\r
+ * interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the command to change the timers period\r
+ * could not be sent to the timer command queue. pdPASS will be returned if the\r
+ * command was successfully sent to the timer command queue. When the command\r
+ * is actually processed will depend on the priority of the timer service/daemon\r
+ * task relative to other tasks in the system. The timer service/daemon task\r
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xTimer has already been created and started. When\r
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.\r
+ *\r
+ * // The interrupt service routine that changes the period of xTimer.\r
+ * void vAnExampleInterruptServiceRoutine( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // The interrupt has occurred - change the period of xTimer to 500ms.\r
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r
+ * // (within this function). As this is an interrupt service routine, only\r
+ * // FreeRTOS API functions that end in "FromISR" can be used.\r
+ * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The command to change the timers period was not executed\r
+ * // successfully. Take appropriate action here.\r
+ * }\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerResetFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerReset() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer that is to be started, reset, or\r
+ * restarted.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerResetFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerResetFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerResetFromISR() function. If\r
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the reset command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system, although the timers expiry time is\r
+ * relative to when xTimerResetFromISR() is actually called. The timer service/daemon\r
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xBacklightTimer has already been created. When a\r
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer, and unlike the example given for\r
+ * // the xTimerReset() function, the key press event handler is an interrupt\r
+ * // service routine.\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press interrupt service routine.\r
+ * void vKeyPressEventInterruptHandler( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // Ensure the LCD back-light is on, then reset the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. This is an interrupt service routine so can only\r
+ * // call FreeRTOS API functions that end in "FromISR".\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ *\r
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r
+ * // as both cause the timer to re-calculate its expiry time.\r
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r
+ * // declared (in this function).\r
+ * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The reset command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/*\r
+ * Functions beyond this part are not part of the public API and are intended\r
+ * for use by the kernel only.\r
+ */\r
+portBASE_TYPE xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portTickType xBlockTime ) PRIVILEGED_FUNCTION;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* TIMERS_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "list.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+void vListInitialise( xList *pxList )\r
+{\r
+ /* The list structure contains a list item which is used to mark the\r
+ end of the list. To initialise the list the list end is inserted\r
+ as the only list entry. */\r
+ pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ /* The list end value is the highest possible value in the list to\r
+ ensure it remains at the end of the list. */\r
+ pxList->xListEnd.xItemValue = portMAX_DELAY;\r
+\r
+ /* The list end next and previous pointers point to itself so we know\r
+ when the list is empty. */\r
+ pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd );\r
+ pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ pxList->uxNumberOfItems = ( unsigned portBASE_TYPE ) 0U;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInitialiseItem( xListItem *pxItem )\r
+{\r
+ /* Make sure the list item is not recorded as being on a list. */\r
+ pxItem->pvContainer = NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem * pxIndex;\r
+\r
+ /* Insert a new list item into pxList, but rather than sort the list,\r
+ makes the new list item the last item to be removed by a call to\r
+ pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by\r
+ the pxIndex member. */\r
+ pxIndex = pxList->pxIndex;\r
+\r
+ pxNewListItem->pxNext = pxIndex->pxNext;\r
+ pxNewListItem->pxPrevious = pxList->pxIndex;\r
+ pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+ pxList->pxIndex = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem *pxIterator;\r
+portTickType xValueOfInsertion;\r
+\r
+ /* Insert the new list item into the list, sorted in ulListItem order. */\r
+ xValueOfInsertion = pxNewListItem->xItemValue;\r
+\r
+ /* If the list already contains a list item with the same item value then\r
+ the new list item should be placed after it. This ensures that TCB's which\r
+ are stored in ready lists (all of which have the same ulListItem value)\r
+ get an equal share of the CPU. However, if the xItemValue is the same as\r
+ the back marker the iteration loop below will not end. This means we need\r
+ to guard against this by checking the value first and modifying the\r
+ algorithm slightly if necessary. */\r
+ if( xValueOfInsertion == portMAX_DELAY )\r
+ {\r
+ pxIterator = pxList->xListEnd.pxPrevious;\r
+ }\r
+ else\r
+ {\r
+ /* *** NOTE ***********************************************************\r
+ If you find your application is crashing here then likely causes are:\r
+ 1) Stack overflow -\r
+ see http://www.freertos.org/Stacks-and-stack-overflow-checking.html\r
+ 2) Incorrect interrupt priority assignment, especially on Cortex-M3\r
+ parts where numerically high priority values denote low actual\r
+ interrupt priories, which can seem counter intuitive. See\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html\r
+ 3) Calling an API function from within a critical section or when\r
+ the scheduler is suspended.\r
+ 4) Using a queue or semaphore before it has been initialised or\r
+ before the scheduler has been started (are interrupts firing\r
+ before vTaskStartScheduler() has been called?).\r
+ See http://www.freertos.org/FAQHelp.html for more tips.\r
+ **********************************************************************/\r
+ \r
+ for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )\r
+ {\r
+ /* There is nothing to do here, we are just iterating to the\r
+ wanted insertion position. */\r
+ }\r
+ }\r
+\r
+ pxNewListItem->pxNext = pxIterator->pxNext;\r
+ pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxNewListItem->pxPrevious = pxIterator;\r
+ pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. This allows fast removal of the\r
+ item later. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListRemove( xListItem *pxItemToRemove )\r
+{\r
+xList * pxList;\r
+\r
+ pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r
+ pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r
+ \r
+ /* The list item knows which list it is in. Obtain the list from the list\r
+ item. */\r
+ pxList = ( xList * ) pxItemToRemove->pvContainer;\r
+\r
+ /* Make sure the index is left pointing to a valid item. */\r
+ if( pxList->pxIndex == pxItemToRemove )\r
+ {\r
+ pxList->pxIndex = pxItemToRemove->pxPrevious;\r
+ }\r
+\r
+ pxItemToRemove->pvContainer = NULL;\r
+ ( pxList->uxNumberOfItems )--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
+defined. The value should also ensure backward compatibility.\r
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
+#ifndef configKERNEL_INTERRUPT_PRIORITY\r
+ #define configKERNEL_INTERRUPT_PRIORITY 255\r
+#endif\r
+\r
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0\r
+ #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html\r
+#endif\r
+\r
+/* Constants required to manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )\r
+#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )\r
+#define portNVIC_SYSTICK_CLK 0x00000004\r
+#define portNVIC_SYSTICK_INT 0x00000002\r
+#define portNVIC_SYSTICK_ENABLE 0x00000001\r
+#define portNVIC_PENDSVSET 0x10000000\r
+#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
+#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR ( 0x01000000 )\r
+\r
+/* The priority used by the kernel is assigned to a variable to make access\r
+from inline assembler easier. */\r
+const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/*\r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Exception handlers.\r
+ */\r
+void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
+void xPortSysTickHandler( void );\r
+void vPortSVCHandler( void ) __attribute__ (( naked ));\r
+\r
+/*\r
+ * Start first task is a separate function so it can be tested in isolation.\r
+ */\r
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+ /* Simulate the stack frame as it would be created by a context switch\r
+ interrupt. */\r
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */\r
+ pxTopOfStack--;\r
+ *pxTopOfStack = 0; /* LR */\r
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */\r
+ *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */\r
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+\r
+ return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortSVCHandler( void )\r
+{\r
+ __asm volatile (\r
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */\r
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
+ " msr psp, r0 \n" /* Restore the task stack pointer. */\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " orr r14, #0xd \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPortStartFirstTask( void )\r
+{\r
+ __asm volatile(\r
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */\r
+ " ldr r0, [r0] \n"\r
+ " ldr r0, [r0] \n"\r
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */\r
+ " cpsie i \n" /* Globally enable interrupts. */\r
+ " svc 0 \n" /* System call to start first task. */\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * See header file for description.\r
+ */\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+ /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
+ *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
+ *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+\r
+ /* Start the timer that generates the tick ISR. Interrupts are disabled\r
+ here already. */\r
+ prvSetupTimerInterrupt();\r
+\r
+ /* Initialise the critical nesting count ready for the first task. */\r
+ uxCriticalNesting = 0;\r
+\r
+ /* Start the first task. */\r
+ prvPortStartFirstTask();\r
+\r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+ /* It is unlikely that the CM3 port will require this function as there\r
+ is nothing to return to. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYieldFromISR( void )\r
+{\r
+ /* Set a PendSV to request a context switch. */\r
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+ portDISABLE_INTERRUPTS();\r
+ uxCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+ uxCriticalNesting--;\r
+ if( uxCriticalNesting == 0 )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortPendSVHandler( void )\r
+{\r
+ /* This is a naked function. */\r
+\r
+ __asm volatile\r
+ (\r
+ " mrs r0, psp \n"\r
+ " \n"\r
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */\r
+ " ldr r2, [r3] \n"\r
+ " \n"\r
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */\r
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */\r
+ " \n"\r
+ " stmdb sp!, {r3, r14} \n"\r
+ " mov r0, %0 \n"\r
+ " msr basepri, r0 \n"\r
+ " bl vTaskSwitchContext \n"\r
+ " mov r0, #0 \n"\r
+ " msr basepri, r0 \n"\r
+ " ldmia sp!, {r3, r14} \n"\r
+ " \n" /* Restore the context, including the critical nesting count. */\r
+ " ldr r1, [r3] \n"\r
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */\r
+ " msr psp, r0 \n"\r
+ " bx r14 \n"\r
+ " \n"\r
+ " .align 2 \n"\r
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void xPortSysTickHandler( void )\r
+{\r
+unsigned long ulDummy;\r
+\r
+ /* If using preemption, also force a context switch. */\r
+ #if configUSE_PREEMPTION == 1\r
+ *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
+ #endif\r
+\r
+ ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ vTaskIncrementTick();\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+ /* Configure SysTick to interrupt at the requested rate. */\r
+ *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
+ *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions. \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/ \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH ( -1 )\r
+#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) \r
+#define portBYTE_ALIGNMENT 8\r
+/*-----------------------------------------------------------*/ \r
+\r
+\r
+/* Scheduler utilities. */\r
+extern void vPortYieldFromISR( void );\r
+\r
+#define portYIELD() vPortYieldFromISR()\r
+\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+/* \r
+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other\r
+ * registers. r0 is clobbered.\r
+ */ \r
+#define portSET_INTERRUPT_MASK() \\r
+ __asm volatile \\r
+ ( \\r
+ " mov r0, %0 \n" \\r
+ " msr basepri, r0 \n" \\r
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \\r
+ )\r
+ \r
+/*\r
+ * Set basepri back to 0 without effective other registers.\r
+ * r0 is clobbered.\r
+ */\r
+#define portCLEAR_INTERRUPT_MASK() \\r
+ __asm volatile \\r
+ ( \\r
+ " mov r0, #0 \n" \\r
+ " msr basepri, r0 \n" \\r
+ :::"r0" \\r
+ )\r
+\r
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK()\r
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x\r
+\r
+\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK()\r
+#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define portNOP()\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*\r
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits\r
+ * allocated blocks to be freed, but does not combine adjacent free blocks\r
+ * into a single larger block.\r
+ *\r
+ * See heap_1.c and heap_3.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+#include <stdlib.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Allocate the memory for the heap. The struct is used to force byte\r
+alignment without using any non-portable code. */\r
+static union xRTOS_HEAP\r
+{\r
+ #if portBYTE_ALIGNMENT == 8\r
+ volatile portDOUBLE dDummy;\r
+ #else\r
+ volatile unsigned long ulDummy;\r
+ #endif\r
+ unsigned char ucHeap[ configTOTAL_HEAP_SIZE ];\r
+} xHeap;\r
+\r
+/* Define the linked list structure. This is used to link free blocks in order\r
+of their size. */\r
+typedef struct A_BLOCK_LINK\r
+{\r
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */\r
+ size_t xBlockSize; /*<< The size of the free block. */\r
+} xBlockLink;\r
+\r
+\r
+static const unsigned short heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + portBYTE_ALIGNMENT - ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) );\r
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\r
+\r
+/* Create a couple of list links to mark the start and end of the list. */\r
+static xBlockLink xStart, xEnd;\r
+\r
+/* Keeps track of the number of free bytes remaining, but says nothing about\r
+fragmentation. */\r
+static size_t xFreeBytesRemaining = configTOTAL_HEAP_SIZE;\r
+\r
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\r
+\r
+/*\r
+ * Insert a block into the list of free blocks - which is ordered by size of\r
+ * the block. Small blocks at the start of the list and large blocks at the end\r
+ * of the list.\r
+ */\r
+#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \\r
+{ \\r
+xBlockLink *pxIterator; \\r
+size_t xBlockSize; \\r
+ \\r
+ xBlockSize = pxBlockToInsert->xBlockSize; \\r
+ \\r
+ /* Iterate through the list until a block is found that has a larger size */ \\r
+ /* than the block we are inserting. */ \\r
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \\r
+ { \\r
+ /* There is nothing to do here - just iterate to the correct position. */ \\r
+ } \\r
+ \\r
+ /* Update the list to include the block being inserted in the correct */ \\r
+ /* position. */ \\r
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \\r
+ pxIterator->pxNextFreeBlock = pxBlockToInsert; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#define prvHeapInit() \\r
+{ \\r
+xBlockLink *pxFirstFreeBlock; \\r
+ \\r
+ /* xStart is used to hold a pointer to the first item in the list of free */ \\r
+ /* blocks. The void cast is used to prevent compiler warnings. */ \\r
+ xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \\r
+ xStart.xBlockSize = ( size_t ) 0; \\r
+ \\r
+ /* xEnd is used to mark the end of the list of free blocks. */ \\r
+ xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \\r
+ xEnd.pxNextFreeBlock = NULL; \\r
+ \\r
+ /* To start with there is a single free block that is sized to take up the \\r
+ entire heap space. */ \\r
+ pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \\r
+ pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \\r
+ pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\r
+static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE;\r
+void *pvReturn = NULL;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* If this is the first call to malloc then the heap will require\r
+ initialisation to setup the list of free blocks. */\r
+ if( xHeapHasBeenInitialised == pdFALSE )\r
+ {\r
+ prvHeapInit();\r
+ xHeapHasBeenInitialised = pdTRUE;\r
+ }\r
+\r
+ /* The wanted size is increased so it can contain a xBlockLink\r
+ structure in addition to the requested amount of bytes. */\r
+ if( xWantedSize > 0 )\r
+ {\r
+ xWantedSize += heapSTRUCT_SIZE;\r
+\r
+ /* Ensure that blocks are always aligned to the required number of bytes. */\r
+ if( xWantedSize & portBYTE_ALIGNMENT_MASK )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\r
+ }\r
+ }\r
+\r
+ if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) )\r
+ {\r
+ /* Blocks are stored in byte order - traverse the list from the start\r
+ (smallest) block until one of adequate size is found. */\r
+ pxPreviousBlock = &xStart;\r
+ pxBlock = xStart.pxNextFreeBlock;\r
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) )\r
+ {\r
+ pxPreviousBlock = pxBlock;\r
+ pxBlock = pxBlock->pxNextFreeBlock;\r
+ }\r
+\r
+ /* If we found the end marker then a block of adequate size was not found. */\r
+ if( pxBlock != &xEnd )\r
+ {\r
+ /* Return the memory space - jumping over the xBlockLink structure\r
+ at its start. */\r
+ pvReturn = ( void * ) ( ( ( unsigned char * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\r
+\r
+ /* This block is being returned for use so must be taken our of the\r
+ list of free blocks. */\r
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\r
+\r
+ /* If the block is larger than required it can be split into two. */\r
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\r
+ {\r
+ /* This block is to be split into two. Create a new block\r
+ following the number of bytes requested. The void cast is\r
+ used to prevent byte alignment warnings from the compiler. */\r
+ pxNewBlockLink = ( void * ) ( ( ( unsigned char * ) pxBlock ) + xWantedSize );\r
+\r
+ /* Calculate the sizes of two blocks split from the single\r
+ block. */\r
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\r
+ pxBlock->xBlockSize = xWantedSize;\r
+\r
+ /* Insert the new block into the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\r
+ }\r
+ \r
+ xFreeBytesRemaining -= pxBlock->xBlockSize;\r
+ }\r
+ }\r
+ }\r
+ xTaskResumeAll();\r
+\r
+ #if( configUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+unsigned char *puc = ( unsigned char * ) pv;\r
+xBlockLink *pxLink;\r
+\r
+ if( pv )\r
+ {\r
+ /* The memory being freed will have an xBlockLink structure immediately\r
+ before it. */\r
+ puc -= heapSTRUCT_SIZE;\r
+\r
+ /* This casting is to keep the compiler from issuing warnings. */\r
+ pxLink = ( void * ) puc;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Add this block to the list of free blocks. */\r
+ prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) );\r
+ xFreeBytesRemaining += pxLink->xBlockSize;\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return xFreeBytesRemaining;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* This just exists to keep the linker quiet. */\r
+}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+#if ( configUSE_CO_ROUTINES == 1 )\r
+ #include "croutine.h"\r
+#endif\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants used with the cRxLock and cTxLock structure members. */\r
+#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 )\r
+#define queueLOCKED_UNMODIFIED ( ( signed portBASE_TYPE ) 0 )\r
+\r
+#define queueERRONEOUS_UNBLOCK ( -1 )\r
+\r
+/* For internal use only. */\r
+#define queueSEND_TO_BACK ( 0 )\r
+#define queueSEND_TO_FRONT ( 1 )\r
+\r
+/* Effectively make a union out of the xQUEUE structure. */\r
+#define pxMutexHolder pcTail\r
+#define uxQueueType pcHead\r
+#define uxRecursiveCallCount pcReadFrom\r
+#define queueQUEUE_IS_MUTEX NULL\r
+\r
+/* Semaphores do not actually store or copy data, so have an items size of\r
+zero. */\r
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portBASE_TYPE ) 0 )\r
+#define queueDONT_BLOCK ( ( portTickType ) 0U )\r
+#define queueMUTEX_GIVE_BLOCK_TIME ( ( portTickType ) 0U )\r
+\r
+/* These definitions *must* match those in queue.h. */\r
+#define queueQUEUE_TYPE_BASE ( 0U )\r
+#define queueQUEUE_TYPE_MUTEX ( 1U )\r
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( 2U )\r
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( 3U )\r
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( 4U )\r
+\r
+/*\r
+ * Definition of the queue used by the scheduler.\r
+ * Items are queued by copy, not reference.\r
+ */\r
+typedef struct QueueDefinition\r
+{\r
+ signed char *pcHead; /*< Points to the beginning of the queue storage area. */\r
+ signed char *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\r
+\r
+ signed char *pcWriteTo; /*< Points to the free next place in the storage area. */\r
+ signed char *pcReadFrom; /*< Points to the last place that a queued item was read from. */\r
+\r
+ xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */\r
+ xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */\r
+\r
+ volatile unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */\r
+ unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\r
+ unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */\r
+\r
+ signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+ signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+ \r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ unsigned char ucQueueNumber;\r
+ unsigned char ucQueueType;\r
+ #endif\r
+\r
+} xQUEUE;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Inside this file xQueueHandle is a pointer to a xQUEUE structure.\r
+ * To keep the definition private the API header file defines it as a\r
+ * pointer to void.\r
+ */\r
+typedef xQUEUE * xQueueHandle;\r
+\r
+/*\r
+ * Prototypes for public functions are included here so we don't have to\r
+ * include the API header file (as it defines xQueueHandle differently). These\r
+ * functions are documented in the API header file.\r
+ */\r
+xQueueHandle xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+void vQueueDelete( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\r
+xQueueHandle xQueueCreateMutex( unsigned char ucQueueType ) PRIVILEGED_FUNCTION;\r
+xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+unsigned char ucQueueGetQueueNumber( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+void vQueueSetQueueNumber( xQueueHandle pxQueue, unsigned char ucQueueNumber ) PRIVILEGED_FUNCTION;\r
+unsigned char ucQueueGetQueueType( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue ) PRIVILEGED_FUNCTION;\r
+xTaskHandle xQueueGetMutexHolder( xQueueHandle xSemaphore ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Co-routine queue functions differ from task queue functions. Co-routines are\r
+ * an optional component.\r
+ */\r
+#if configUSE_CO_ROUTINES == 1\r
+ signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+/*\r
+ * The queue registry is just a means for kernel aware debuggers to locate\r
+ * queue structures. It has no other purpose so is an optional component.\r
+ */\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ /* The type stored within the queue registry array. This allows a name\r
+ to be assigned to each queue making kernel aware debugging a little\r
+ more user friendly. */\r
+ typedef struct QUEUE_REGISTRY_ITEM\r
+ {\r
+ signed char *pcQueueName;\r
+ xQueueHandle xHandle;\r
+ } xQueueRegistryItem;\r
+\r
+ /* The queue registry is simply an array of xQueueRegistryItem structures.\r
+ The pcQueueName member of a structure being NULL is indicative of the\r
+ array position being vacant. */\r
+ xQueueRegistryItem xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\r
+\r
+ /* Removes a queue from the registry by simply setting the pcQueueName\r
+ member to NULL. */\r
+ static void vQueueUnregisterQueue( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+/*\r
+ * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not\r
+ * prevent an ISR from adding or removing items to the queue, but does prevent\r
+ * an ISR from removing tasks from the queue event lists. If an ISR finds a\r
+ * queue is locked it will instead increment the appropriate queue lock count\r
+ * to indicate that a task may require unblocking. When the queue in unlocked\r
+ * these lock counts are inspected, and the appropriate action taken.\r
+ */\r
+static void prvUnlockQueue( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any data in a queue.\r
+ *\r
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\r
+ */\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any space in a queue.\r
+ *\r
+ * @return pdTRUE if there is no space, otherwise pdFALSE;\r
+ */\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Copies an item into the queue, either at the front of the queue or the\r
+ * back of the queue.\r
+ */\r
+static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Copies an item out of a queue.\r
+ */\r
+static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro to mark a queue as locked. Locking a queue prevents an ISR from\r
+ * accessing the queue event lists.\r
+ */\r
+#define prvLockQueue( pxQueue ) \\r
+ taskENTER_CRITICAL(); \\r
+ { \\r
+ if( ( pxQueue )->xRxLock == queueUNLOCKED ) \\r
+ { \\r
+ ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \\r
+ } \\r
+ if( ( pxQueue )->xTxLock == queueUNLOCKED ) \\r
+ { \\r
+ ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \\r
+ } \\r
+ } \\r
+ taskEXIT_CRITICAL()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC QUEUE MANAGEMENT API documented in queue.h\r
+ *----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue )\r
+{\r
+ configASSERT( pxQueue );\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );\r
+ pxQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;\r
+ pxQueue->pcWriteTo = pxQueue->pcHead;\r
+ pxQueue->pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( unsigned portBASE_TYPE ) 1U ) * pxQueue->uxItemSize );\r
+ pxQueue->xRxLock = queueUNLOCKED;\r
+ pxQueue->xTxLock = queueUNLOCKED;\r
+\r
+ if( xNewQueue == pdFALSE )\r
+ {\r
+ /* If there are tasks blocked waiting to read from the queue, then \r
+ the tasks will remain blocked as after this function exits the queue \r
+ will still be empty. If there are tasks blocked waiting to write to \r
+ the queue, then one should be unblocked as after this function exits \r
+ it will be possible to write to it. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Ensure the event queues start in the correct state. */\r
+ vListInitialise( &( pxQueue->xTasksWaitingToSend ) );\r
+ vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); \r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* A value is returned for calling semantic consistency with previous\r
+ versions. */\r
+ return pdPASS;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xQueueHandle xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType )\r
+{\r
+xQUEUE *pxNewQueue;\r
+size_t xQueueSizeInBytes;\r
+xQueueHandle xReturn = NULL;\r
+\r
+ /* Remove compiler warnings about unused parameters should\r
+ configUSE_TRACE_FACILITY not be set to 1. */\r
+ ( void ) ucQueueType;\r
+\r
+ /* Allocate the new queue structure. */\r
+ if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );\r
+ if( pxNewQueue != NULL )\r
+ {\r
+ /* Create the list of pointers to queue items. The queue is one byte\r
+ longer than asked for to make wrap checking easier/faster. */\r
+ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1;\r
+\r
+ pxNewQueue->pcHead = ( signed char * ) pvPortMalloc( xQueueSizeInBytes );\r
+ if( pxNewQueue->pcHead != NULL )\r
+ {\r
+ /* Initialise the queue members as described above where the\r
+ queue type is defined. */\r
+ pxNewQueue->uxLength = uxQueueLength;\r
+ pxNewQueue->uxItemSize = uxItemSize;\r
+ xQueueGenericReset( pxNewQueue, pdTRUE );\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ {\r
+ pxNewQueue->ucQueueType = ucQueueType;\r
+ }\r
+ #endif /* configUSE_TRACE_FACILITY */\r
+\r
+ traceQUEUE_CREATE( pxNewQueue );\r
+ xReturn = pxNewQueue;\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_CREATE_FAILED( ucQueueType );\r
+ vPortFree( pxNewQueue );\r
+ }\r
+ }\r
+ }\r
+\r
+ configASSERT( xReturn );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ xQueueHandle xQueueCreateMutex( unsigned char ucQueueType )\r
+ {\r
+ xQUEUE *pxNewQueue;\r
+\r
+ /* Prevent compiler warnings about unused parameters if\r
+ configUSE_TRACE_FACILITY does not equal 1. */\r
+ ( void ) ucQueueType;\r
+\r
+ /* Allocate the new queue structure. */\r
+ pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );\r
+ if( pxNewQueue != NULL )\r
+ {\r
+ /* Information required for priority inheritance. */\r
+ pxNewQueue->pxMutexHolder = NULL;\r
+ pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\r
+\r
+ /* Queues used as a mutex no data is actually copied into or out\r
+ of the queue. */\r
+ pxNewQueue->pcWriteTo = NULL;\r
+ pxNewQueue->pcReadFrom = NULL;\r
+\r
+ /* Each mutex has a length of 1 (like a binary semaphore) and\r
+ an item size of 0 as nothing is actually copied into or out\r
+ of the mutex. */\r
+ pxNewQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;\r
+ pxNewQueue->uxLength = ( unsigned portBASE_TYPE ) 1U;\r
+ pxNewQueue->uxItemSize = ( unsigned portBASE_TYPE ) 0U;\r
+ pxNewQueue->xRxLock = queueUNLOCKED;\r
+ pxNewQueue->xTxLock = queueUNLOCKED;\r
+\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ {\r
+ pxNewQueue->ucQueueType = ucQueueType;\r
+ }\r
+ #endif\r
+\r
+ /* Ensure the event queues start with the correct state. */\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
+\r
+ traceCREATE_MUTEX( pxNewQueue );\r
+\r
+ /* Start with the semaphore in the expected state. */\r
+ xQueueGenericSend( pxNewQueue, NULL, ( portTickType ) 0U, queueSEND_TO_BACK );\r
+ }\r
+ else\r
+ {\r
+ traceCREATE_MUTEX_FAILED();\r
+ }\r
+\r
+ configASSERT( pxNewQueue );\r
+ return pxNewQueue;\r
+ }\r
+\r
+#endif /* configUSE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xQueueGetMutexHolder == 1 ) )\r
+\r
+ void* xQueueGetMutexHolder( xQueueHandle xSemaphore )\r
+ {\r
+ void *pxReturn;\r
+\r
+ /* This function is called by xSemaphoreGetMutexHolder(), and should not\r
+ be called directly. Note: This is is a good way of determining if the\r
+ calling task is the mutex holder, but not a good way of determining the\r
+ identity of the mutex holder, as the holder may change between the \r
+ following critical section exiting and the function returning. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ pxReturn = ( void * ) xSemaphore->pxMutexHolder;\r
+ }\r
+ else\r
+ {\r
+ pxReturn = NULL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ \r
+ return pxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )\r
+\r
+ portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxMutex );\r
+\r
+ /* If this is the task that holds the mutex then pxMutexHolder will not\r
+ change outside of this task. If this task does not hold the mutex then\r
+ pxMutexHolder can never coincidentally equal the tasks handle, and as\r
+ this is the only condition we are interested in it does not matter if\r
+ pxMutexHolder is accessed simultaneously by another task. Therefore no\r
+ mutual exclusion is required to test the pxMutexHolder variable. */\r
+ if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )\r
+ {\r
+ traceGIVE_MUTEX_RECURSIVE( pxMutex );\r
+\r
+ /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to\r
+ the task handle, therefore no underflow check is required. Also,\r
+ uxRecursiveCallCount is only modified by the mutex holder, and as\r
+ there can only be one, no mutual exclusion is required to modify the\r
+ uxRecursiveCallCount member. */\r
+ ( pxMutex->uxRecursiveCallCount )--;\r
+\r
+ /* Have we unwound the call count? */\r
+ if( pxMutex->uxRecursiveCallCount == 0 )\r
+ {\r
+ /* Return the mutex. This will automatically unblock any other\r
+ task that might be waiting to access the mutex. */\r
+ xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* We cannot give the mutex because we are not the holder. */\r
+ xReturn = pdFAIL;\r
+\r
+ traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_RECURSIVE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_RECURSIVE_MUTEXES == 1\r
+\r
+ portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxMutex );\r
+\r
+ /* Comments regarding mutual exclusion as per those within\r
+ xQueueGiveMutexRecursive(). */\r
+\r
+ traceTAKE_MUTEX_RECURSIVE( pxMutex );\r
+\r
+ if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )\r
+ {\r
+ ( pxMutex->uxRecursiveCallCount )++;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueGenericReceive( pxMutex, NULL, xBlockTime, pdFALSE );\r
+\r
+ /* pdPASS will only be returned if we successfully obtained the mutex,\r
+ we may have blocked to reach here. */\r
+ if( xReturn == pdPASS )\r
+ {\r
+ ( pxMutex->uxRecursiveCallCount )++;\r
+ }\r
+ else\r
+ {\r
+ traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_RECURSIVE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_COUNTING_SEMAPHORES == 1\r
+\r
+ xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
+ {\r
+ xQueueHandle pxHandle;\r
+\r
+ pxHandle = xQueueGenericCreate( ( unsigned portBASE_TYPE ) uxCountValue, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\r
+\r
+ if( pxHandle != NULL )\r
+ {\r
+ pxHandle->uxMessagesWaiting = uxInitialCount;\r
+\r
+ traceCREATE_COUNTING_SEMAPHORE();\r
+ }\r
+ else\r
+ {\r
+ traceCREATE_COUNTING_SEMAPHORE_FAILED();\r
+ }\r
+\r
+ configASSERT( pxHandle );\r
+ return pxHandle;\r
+ }\r
+\r
+#endif /* configUSE_COUNTING_SEMAPHORES */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
+{\r
+signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+xTimeOutType xTimeOut;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* This function relaxes the coding standard somewhat to allow return\r
+ statements within the function itself. This is done in the interest\r
+ of execution time efficiency. */\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there room on the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND( pxQueue );\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If there was a task waiting for data to arrive on the\r
+ queue then unblock it now. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+ {\r
+ /* The unblocked task has a priority higher than\r
+ our own so yield immediately. Yes it is ok to do\r
+ this from within the critical section - the kernel\r
+ takes care of that. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Return to the original privilege level before exiting the\r
+ function. */\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ /* The queue was full and no block time is specified (or\r
+ the block time has expired) so leave now. */\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Return to the original privilege level before exiting\r
+ the function. */\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ /* The queue was full and a block time was specified so\r
+ configure the timeout structure. */\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Interrupts and other tasks can send to and receive from the queue\r
+ now the critical section has been exited. */\r
+\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* Update the timeout state to see if it has expired yet. */\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+\r
+ /* Unlocking the queue means queue events can effect the\r
+ event list. It is possible that interrupts occurring now\r
+ remove this task from the event list again - but as the\r
+ scheduler is suspended the task will go onto the pending\r
+ ready last instead of the actual ready list. */\r
+ prvUnlockQueue( pxQueue );\r
+\r
+ /* Resuming the scheduler will move tasks from the pending\r
+ ready list into the ready list - so it is feasible that this\r
+ task is already in a ready list before it yields - in which\r
+ case the yield will not cause a context switch unless there\r
+ is also a higher priority task in the pending ready list. */\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Try again. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The timeout has expired. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+\r
+ /* Return to the original privilege level before exiting the\r
+ function. */\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_ALTERNATIVE_API == 1\r
+\r
+ signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
+ {\r
+ signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+ xTimeOutType xTimeOut;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there room on the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND( pxQueue );\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If there was a task waiting for data to arrive on the\r
+ queue then unblock it now. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+ {\r
+ /* The unblocked task has a priority higher than\r
+ our own so yield immediately. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ return errQUEUE_FULL;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* configUSE_ALTERNATIVE_API */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_ALTERNATIVE_API == 1\r
+\r
+ signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
+ {\r
+ signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+ xTimeOutType xTimeOut;\r
+ signed char *pcOriginalReadPosition;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Remember our read position in case we are just peeking. */\r
+ pcOriginalReadPosition = pxQueue->pcReadFrom;\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+\r
+ if( xJustPeeking == pdFALSE )\r
+ {\r
+ traceQUEUE_RECEIVE( pxQueue );\r
+\r
+ /* We are actually removing data. */\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* Record the information required to implement\r
+ priority inheritance should it become necessary. */\r
+ pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_PEEK( pxQueue );\r
+\r
+ /* We are not removing the data, so reset our read\r
+ pointer. */\r
+ pxQueue->pcReadFrom = pcOriginalReadPosition;\r
+\r
+ /* The data is being left in the queue, so see if there are\r
+ any other tasks waiting for the data. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than this task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ portENTER_CRITICAL();\r
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+\r
+#endif /* configUSE_ALTERNATIVE_API */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* Similar to xQueueGenericSend, except we don't block if there is no room\r
+ in the queue. Also we don't directly wake a task that was blocked on a\r
+ queue read, instead we return a flag to say whether a context switch is\r
+ required or not (i.e. has a task with a higher priority than us been woken\r
+ by this post). */\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND_FROM_ISR( pxQueue );\r
+\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If the queue is locked we do not alter the event list. This will\r
+ be done when the queue is unlocked later. */\r
+ if( pxQueue->xTxLock == queueUNLOCKED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ if( pxHigherPriorityTaskWoken != NULL )\r
+ {\r
+ *pxHigherPriorityTaskWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was posted while it was locked. */\r
+ ++( pxQueue->xTxLock );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
+{\r
+signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+xTimeOutType xTimeOut;\r
+signed char *pcOriginalReadPosition;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* This function relaxes the coding standard somewhat to allow return\r
+ statements within the function itself. This is done in the interest\r
+ of execution time efficiency. */\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there data in the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Remember our read position in case we are just peeking. */\r
+ pcOriginalReadPosition = pxQueue->pcReadFrom;\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+\r
+ if( xJustPeeking == pdFALSE )\r
+ {\r
+ traceQUEUE_RECEIVE( pxQueue );\r
+\r
+ /* We are actually removing data. */\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* Record the information required to implement\r
+ priority inheritance should it become necessary. */\r
+ pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_PEEK( pxQueue );\r
+\r
+ /* We are not removing the data, so reset our read\r
+ pointer. */\r
+ pxQueue->pcReadFrom = pcOriginalReadPosition;\r
+\r
+ /* The data is being left in the queue, so see if there are\r
+ any other tasks waiting for the data. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than this task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ /* The queue was empty and no block time is specified (or\r
+ the block time has expired) so leave now. */\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ /* The queue was empty and a block time was specified so\r
+ configure the timeout structure. */\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Interrupts and other tasks can send to and receive from the queue\r
+ now the critical section has been exited. */\r
+\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* Update the timeout state to see if it has expired yet. */\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ prvUnlockQueue( pxQueue );\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Try again. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxHigherPriorityTaskWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* We cannot block from an ISR, so check there is data available. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ traceQUEUE_RECEIVE_FROM_ISR( pxQueue );\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ /* If the queue is locked we will not modify the event list. Instead\r
+ we update the lock count so the task that unlocks the queue will know\r
+ that an ISR has removed data while the queue was locked. */\r
+ if( pxQueue->xRxLock == queueUNLOCKED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than us so\r
+ force a context switch. */\r
+ if( pxHigherPriorityTaskWoken != NULL )\r
+ {\r
+ *pxHigherPriorityTaskWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was removed while it was locked. */\r
+ ++( pxQueue->xRxLock );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
+{\r
+unsigned portBASE_TYPE uxReturn;\r
+\r
+ configASSERT( pxQueue );\r
+\r
+ taskENTER_CRITICAL();\r
+ uxReturn = pxQueue->uxMessagesWaiting;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue )\r
+{\r
+unsigned portBASE_TYPE uxReturn;\r
+\r
+ configASSERT( pxQueue );\r
+\r
+ uxReturn = pxQueue->uxMessagesWaiting;\r
+\r
+ return uxReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vQueueDelete( xQueueHandle pxQueue )\r
+{\r
+ configASSERT( pxQueue );\r
+\r
+ traceQUEUE_DELETE( pxQueue );\r
+ vQueueUnregisterQueue( pxQueue );\r
+ vPortFree( pxQueue->pcHead );\r
+ vPortFree( pxQueue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ unsigned char ucQueueGetQueueNumber( xQueueHandle pxQueue )\r
+ {\r
+ return pxQueue->ucQueueNumber;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ void vQueueSetQueueNumber( xQueueHandle pxQueue, unsigned char ucQueueNumber )\r
+ {\r
+ pxQueue->ucQueueNumber = ucQueueNumber;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ unsigned char ucQueueGetQueueType( xQueueHandle pxQueue )\r
+ {\r
+ return pxQueue->ucQueueType;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition )\r
+{\r
+ if( pxQueue->uxItemSize == ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* The mutex is no longer being held. */\r
+ vTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );\r
+ pxQueue->pxMutexHolder = NULL;\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ else if( xPosition == queueSEND_TO_BACK )\r
+ {\r
+ memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );\r
+ pxQueue->pcWriteTo += pxQueue->uxItemSize;\r
+ if( pxQueue->pcWriteTo >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcWriteTo = pxQueue->pcHead;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ memcpy( ( void * ) pxQueue->pcReadFrom, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );\r
+ pxQueue->pcReadFrom -= pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom < pxQueue->pcHead )\r
+ {\r
+ pxQueue->pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );\r
+ }\r
+ }\r
+\r
+ ++( pxQueue->uxMessagesWaiting );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer )\r
+{\r
+ if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX )\r
+ {\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUnlockQueue( xQueueHandle pxQueue )\r
+{\r
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r
+\r
+ /* The lock counts contains the number of extra data items placed or\r
+ removed from the queue while the queue was locked. When a queue is\r
+ locked items can be added or removed, but the event lists cannot be\r
+ updated. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* See if data was added to the queue while it was locked. */\r
+ while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )\r
+ {\r
+ /* Data was posted while the queue was locked. Are any tasks\r
+ blocked waiting for data to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ vTaskMissedYield();\r
+ }\r
+\r
+ --( pxQueue->xTxLock );\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ pxQueue->xTxLock = queueUNLOCKED;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Do the same for the Rx lock. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ vTaskMissedYield();\r
+ }\r
+\r
+ --( pxQueue->xRxLock );\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ pxQueue->xRxLock = queueUNLOCKED;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxQueue );\r
+ xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxQueue );\r
+ xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* If the queue is already full we may have to block. A critical section\r
+ is required to prevent an interrupt removing something from the queue\r
+ between the check to see if the queue is full and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ /* The queue is full - do we want to block or just leave without\r
+ posting? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is called from a coroutine we cannot block directly, but\r
+ return indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ /* There is room in the queue, copy the data into the queue. */\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for data to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* In this instance the co-routine could be placed directly\r
+ into the ready list as we are within a critical section.\r
+ Instead the same pending ready list mechanism is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The co-routine waiting has a higher priority so record\r
+ that a yield might be appropriate. */\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* If the queue is already empty we may have to block. A critical section\r
+ is required to prevent an interrupt adding something to the queue\r
+ between the check to see if the queue is empty and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* There are no messages in the queue, do we want to block or just\r
+ leave with nothing? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is a co-routine we cannot block directly, but return\r
+ indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Data is available from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for space to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ /* In this instance the co-routine could be placed directly\r
+ into the ready list as we are within a critical section.\r
+ Instead the same pending ready list mechanism is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken )\r
+{\r
+ /* Cannot block within an ISR so if there is no space on the queue then\r
+ exit without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+\r
+ /* We only want to wake one co-routine per ISR, so check that a\r
+ co-routine has not already been woken. */\r
+ if( xCoRoutinePreviouslyWoken == pdFALSE )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return xCoRoutinePreviouslyWoken;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* We cannot block from an ISR, so check there is data available. If\r
+ not then just leave without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Copy the data from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ if( ( *pxCoRoutineWoken ) == pdFALSE )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ *pxCoRoutineWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName )\r
+ {\r
+ unsigned portBASE_TYPE ux;\r
+\r
+ /* See if there is an empty space in the registry. A NULL name denotes\r
+ a free slot. */\r
+ for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+ {\r
+ if( xQueueRegistry[ ux ].pcQueueName == NULL )\r
+ {\r
+ /* Store the information on this queue. */\r
+ xQueueRegistry[ ux ].pcQueueName = pcQueueName;\r
+ xQueueRegistry[ ux ].xHandle = xQueue;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ static void vQueueUnregisterQueue( xQueueHandle xQueue )\r
+ {\r
+ unsigned portBASE_TYPE ux;\r
+\r
+ /* See if the handle of the queue being unregistered in actually in the\r
+ registry. */\r
+ for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+ {\r
+ if( xQueueRegistry[ ux ].xHandle == xQueue )\r
+ {\r
+ /* Set the name to NULL to show that this slot if free again. */\r
+ xQueueRegistry[ ux ].pcQueueName = NULL;\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TIMERS == 1\r
+\r
+ void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait )\r
+ {\r
+ /* This function should not be called by application code hence the\r
+ 'Restricted' in its name. It is not part of the public API. It is\r
+ designed for use by kernel code, and has special calling requirements.\r
+ It can result in vListInsert() being called on a list that can only\r
+ possibly ever have one item in it, so the list will be fast, but even\r
+ so it should be called with the scheduler locked and not from a critical\r
+ section. */\r
+\r
+ /* Only do anything if there are no messages in the queue. This function\r
+ will not actually cause the task to block, just place it on a blocked\r
+ list. It will not block until the scheduler is unlocked - at which\r
+ time a yield will be performed. If an item is added to the queue while\r
+ the queue is locked, and the calling task blocks on the queue, then the\r
+ calling task will be immediately unblocked when the queue is unlocked. */\r
+ prvLockQueue( pxQueue );\r
+ if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ /* There is nothing in the queue, block for the specified period. */\r
+ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ }\r
+ prvUnlockQueue( pxQueue );\r
+ }\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "StackMacros.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/*\r
+ * Macro to define the amount of stack available to the idle task.\r
+ */\r
+#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+/*\r
+ * Task control block. A task control block (TCB) is allocated to each task,\r
+ * and stores the context of the task.\r
+ */\r
+typedef struct tskTaskControlBlock\r
+{\r
+ volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */\r
+\r
+ #if ( portUSING_MPU_WRAPPERS == 1 )\r
+ xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE STRUCT. */\r
+ #endif \r
+ \r
+ xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the TCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */\r
+ portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */\r
+ signed char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */\r
+\r
+ #if ( portSTACK_GROWTH > 0 )\r
+ portSTACK_TYPE *pxEndOfStack; /*< Used for stack overflow checking on architectures where the stack grows up from low memory. */\r
+ #endif\r
+\r
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+ unsigned portBASE_TYPE uxCriticalNesting;\r
+ #endif\r
+\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ unsigned portBASE_TYPE uxTCBNumber; /*< This stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */\r
+ unsigned portBASE_TYPE uxTaskNumber; /*< This stores a number specifically for use by third party trace code. */\r
+ #endif\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ unsigned portBASE_TYPE uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */\r
+ #endif\r
+\r
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+ pdTASK_HOOK_CODE pxTaskTag;\r
+ #endif\r
+\r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ unsigned long ulRunTimeCounter; /*< Used for calculating how much CPU time each task is utilising. */\r
+ #endif\r
+\r
+} tskTCB;\r
+\r
+\r
+/*\r
+ * Some kernel aware debuggers require data to be viewed to be global, rather\r
+ * than file scope.\r
+ */\r
+#ifdef portREMOVE_STATIC_QUALIFIER\r
+ #define static\r
+#endif\r
+\r
+/*lint -e956 */\r
+PRIVILEGED_DATA tskTCB * volatile pxCurrentTCB = NULL;\r
+\r
+/* Lists for ready and blocked tasks. --------------------*/\r
+\r
+PRIVILEGED_DATA static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */\r
+PRIVILEGED_DATA static xList xDelayedTaskList1; /*< Delayed tasks. */\r
+PRIVILEGED_DATA static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\r
+PRIVILEGED_DATA static xList * volatile pxDelayedTaskList ; /*< Points to the delayed task list currently being used. */\r
+PRIVILEGED_DATA static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\r
+PRIVILEGED_DATA static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ PRIVILEGED_DATA static xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */\r
+ PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0U;\r
+\r
+#endif\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ PRIVILEGED_DATA static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */\r
+\r
+#endif\r
+\r
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+ \r
+ PRIVILEGED_DATA static xTaskHandle xIdleTaskHandle = NULL;\r
+ \r
+#endif\r
+\r
+/* File private variables. --------------------------------*/\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static volatile portTickType xTickCount = ( portTickType ) 0U;\r
+PRIVILEGED_DATA static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY;\r
+PRIVILEGED_DATA static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE;\r
+PRIVILEGED_DATA static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0;\r
+PRIVILEGED_DATA static unsigned portBASE_TYPE uxTaskNumber = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static portTickType xNextTaskUnblockTime = ( portTickType ) portMAX_DELAY;\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ PRIVILEGED_DATA static char pcStatsString[ 50 ] ;\r
+ PRIVILEGED_DATA static unsigned long ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */\r
+ static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/* Debugging and trace facilities private variables and macros. ------------*/\r
+\r
+/*\r
+ * The value used to fill the stack of a task when the task is created. This\r
+ * is used purely for checking the high water mark for tasks.\r
+ */\r
+#define tskSTACK_FILL_BYTE ( 0xa5U )\r
+\r
+/*\r
+ * Macros used by vListTask to indicate which state a task is in.\r
+ */\r
+#define tskBLOCKED_CHAR ( ( signed char ) 'B' )\r
+#define tskREADY_CHAR ( ( signed char ) 'R' )\r
+#define tskDELETED_CHAR ( ( signed char ) 'D' )\r
+#define tskSUSPENDED_CHAR ( ( signed char ) 'S' )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Place the task represented by pxTCB into the appropriate ready queue for\r
+ * the task. It is inserted at the end of the list. One quirk of this is\r
+ * that if the task being inserted is at the same priority as the currently\r
+ * executing task, then it will only be rescheduled after the currently\r
+ * executing task has been rescheduled.\r
+ */\r
+#define prvAddTaskToReadyQueue( pxTCB ) \\r
+ traceMOVED_TASK_TO_READY_STATE( pxTCB ) \\r
+ if( ( pxTCB )->uxPriority > uxTopReadyPriority ) \\r
+ { \\r
+ uxTopReadyPriority = ( pxTCB )->uxPriority; \\r
+ } \\r
+ vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro that looks at the list of tasks that are currently delayed to see if\r
+ * any require waking.\r
+ *\r
+ * Tasks are stored in the queue in the order of their wake time - meaning\r
+ * once one tasks has been found whose timer has not expired we need not look\r
+ * any further down the list.\r
+ */\r
+#define prvCheckDelayedTasks() \\r
+{ \\r
+portTickType xItemValue; \\r
+ \\r
+ /* Is the tick count greater than or equal to the wake time of the first \\r
+ task referenced from the delayed tasks list? */ \\r
+ if( xTickCount >= xNextTaskUnblockTime ) \\r
+ { \\r
+ for( ;; ) \\r
+ { \\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) \\r
+ { \\r
+ /* The delayed list is empty. Set xNextTaskUnblockTime to the \\r
+ maximum possible value so it is extremely unlikely that the \\r
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass next \\r
+ time through. */ \\r
+ xNextTaskUnblockTime = portMAX_DELAY; \\r
+ break; \\r
+ } \\r
+ else \\r
+ { \\r
+ /* The delayed list is not empty, get the value of the item at \\r
+ the head of the delayed list. This is the time at which the \\r
+ task at the head of the delayed list should be removed from \\r
+ the Blocked state. */ \\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); \\r
+ xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ); \\r
+ \\r
+ if( xTickCount < xItemValue ) \\r
+ { \\r
+ /* It is not time to unblock this item yet, but the item \\r
+ value is the time at which the task at the head of the \\r
+ blocked list should be removed from the Blocked state - \\r
+ so record the item value in xNextTaskUnblockTime. */ \\r
+ xNextTaskUnblockTime = xItemValue; \\r
+ break; \\r
+ } \\r
+ \\r
+ /* It is time to remove the item from the Blocked state. */ \\r
+ vListRemove( &( pxTCB->xGenericListItem ) ); \\r
+ \\r
+ /* Is the task waiting on an event also? */ \\r
+ if( pxTCB->xEventListItem.pvContainer != NULL ) \\r
+ { \\r
+ vListRemove( &( pxTCB->xEventListItem ) ); \\r
+ } \\r
+ prvAddTaskToReadyQueue( pxTCB ); \\r
+ } \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Several functions take an xTaskHandle parameter that can optionally be NULL,\r
+ * where NULL is used to indicate that the handle of the currently executing\r
+ * task should be used in place of the parameter. This macro simply checks to\r
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.\r
+ */\r
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) ( pxHandle ) )\r
+\r
+/* Callback function prototypes. --------------------------*/\r
+extern void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName );\r
+extern void vApplicationTickHook( void );\r
+ \r
+/* File private functions. --------------------------------*/\r
+\r
+/*\r
+ * Utility to ready a TCB for a given task. Mainly just copies the parameters\r
+ * into the TCB structure.\r
+ */\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Utility to ready all the lists used by the scheduler. This is called\r
+ * automatically upon the creation of the first task.\r
+ */\r
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The idle task, which as all tasks is implemented as a never ending loop.\r
+ * The idle task is automatically created and added to the ready lists upon\r
+ * creation of the first user task.\r
+ *\r
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\r
+\r
+/*\r
+ * Utility to free all memory allocated by the scheduler to hold a TCB,\r
+ * including the stack pointed to by the TCB.\r
+ *\r
+ * This does not free memory allocated by the task itself (i.e. memory\r
+ * allocated by calls to pvPortMalloc from within the tasks application code).\r
+ */\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ static void prvDeleteTCB( tskTCB *pxTCB ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/*\r
+ * Used only by the idle task. This checks to see if anything has been placed\r
+ * in the list of tasks waiting to be deleted. If so the task is cleaned up\r
+ * and its TCB deleted.\r
+ */\r
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The currently executing task is entering the Blocked state. Add the task to\r
+ * either the current or the overflow delayed task list.\r
+ */\r
+static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Allocates memory from the heap for a TCB and associated stack. Checks the\r
+ * allocation was successful.\r
+ */\r
+static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Called from vTaskList. vListTasks details all the tasks currently under\r
+ * control of the scheduler. The tasks may be in one of a number of lists.\r
+ * prvListTaskWithinSingleList accepts a list and details the tasks from\r
+ * within just that list.\r
+ *\r
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\r
+ * NORMAL APPLICATION CODE.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/*\r
+ * When a task is created, the stack of the task is filled with a known value.\r
+ * This function determines the 'high water mark' of the task stack by\r
+ * determining how much of the stack remains at the original preset value.\r
+ */\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+\r
+ static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+\r
+/*lint +e956 */\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+tskTCB * pxNewTCB;\r
+\r
+ configASSERT( pxTaskCode );\r
+ configASSERT( ( uxPriority < configMAX_PRIORITIES ) );\r
+\r
+ /* Allocate the memory required by the TCB and stack for the new task,\r
+ checking that the allocation was successful. */\r
+ pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );\r
+\r
+ if( pxNewTCB != NULL )\r
+ {\r
+ portSTACK_TYPE *pxTopOfStack;\r
+\r
+ #if( portUSING_MPU_WRAPPERS == 1 )\r
+ /* Should the task be created in privileged mode? */\r
+ portBASE_TYPE xRunPrivileged;\r
+ if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\r
+ {\r
+ xRunPrivileged = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xRunPrivileged = pdFALSE;\r
+ }\r
+ uxPriority &= ~portPRIVILEGE_BIT;\r
+ #endif /* portUSING_MPU_WRAPPERS == 1 */\r
+\r
+ /* Calculate the top of stack address. This depends on whether the\r
+ stack grows from high memory to low (as per the 80x86) or visa versa.\r
+ portSTACK_GROWTH is used to make the result positive or negative as\r
+ required by the port. */\r
+ #if( portSTACK_GROWTH < 0 )\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( unsigned short ) 1 );\r
+ pxTopOfStack = ( portSTACK_TYPE * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );\r
+\r
+ /* Check the alignment of the calculated top of stack is correct. */\r
+ configASSERT( ( ( ( unsigned long ) pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+ }\r
+ #else\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack;\r
+ \r
+ /* Check the alignment of the stack buffer is correct. */\r
+ configASSERT( ( ( ( unsigned long ) pxNewTCB->pxStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+\r
+ /* If we want to use stack checking on architectures that use\r
+ a positive stack growth direction then we also need to store the\r
+ other extreme of the stack space. */\r
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );\r
+ }\r
+ #endif\r
+\r
+ /* Setup the newly allocated TCB with the initial state of the task. */\r
+ prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );\r
+\r
+ /* Initialize the TCB stack to look as if the task was already running,\r
+ but had been interrupted by the scheduler. The return address is set\r
+ to the start of the task function. Once the stack has been initialised\r
+ the top of stack variable is updated. */\r
+ #if( portUSING_MPU_WRAPPERS == 1 )\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
+ }\r
+ #endif\r
+\r
+ /* Check the alignment of the initialised stack. */\r
+ portALIGNMENT_ASSERT_pxCurrentTCB( ( ( ( unsigned long ) pxNewTCB->pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+\r
+ if( ( void * ) pxCreatedTask != NULL )\r
+ {\r
+ /* Pass the TCB out - in an anonymous way. The calling function/\r
+ task can use this as a handle to delete the task later if\r
+ required.*/\r
+ *pxCreatedTask = ( xTaskHandle ) pxNewTCB;\r
+ }\r
+ \r
+ /* We are going to manipulate the task queues to add this task to a\r
+ ready list, so must make sure no interrupts occur. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ uxCurrentNumberOfTasks++;\r
+ if( pxCurrentTCB == NULL )\r
+ {\r
+ /* There are no other tasks, or all the other tasks are in\r
+ the suspended state - make this the current task. */\r
+ pxCurrentTCB = pxNewTCB;\r
+\r
+ if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ /* This is the first task to be created so do the preliminary\r
+ initialisation required. We will not recover if this call\r
+ fails, but we will report the failure. */\r
+ prvInitialiseTaskLists();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If the scheduler is not already running, make this task the\r
+ current task if it is the highest priority task to be created\r
+ so far. */\r
+ if( xSchedulerRunning == pdFALSE )\r
+ {\r
+ if( pxCurrentTCB->uxPriority <= uxPriority )\r
+ {\r
+ pxCurrentTCB = pxNewTCB;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Remember the top priority to make context switching faster. Use\r
+ the priority in pxNewTCB as this has been capped to a valid value. */\r
+ if( pxNewTCB->uxPriority > uxTopUsedPriority )\r
+ {\r
+ uxTopUsedPriority = pxNewTCB->uxPriority;\r
+ }\r
+\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ {\r
+ /* Add a counter into the TCB for tracing only. */\r
+ pxNewTCB->uxTCBNumber = uxTaskNumber;\r
+ }\r
+ #endif\r
+ uxTaskNumber++;\r
+\r
+ prvAddTaskToReadyQueue( pxNewTCB );\r
+\r
+ xReturn = pdPASS;\r
+ portSETUP_TCB( pxNewTCB );\r
+ traceTASK_CREATE( pxNewTCB );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+ traceTASK_CREATE_FAILED();\r
+ }\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ /* If the created task is of a higher priority than the current task\r
+ then it should run now. */\r
+ if( pxCurrentTCB->uxPriority < uxPriority )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ void vTaskDelete( xTaskHandle pxTaskToDelete )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Ensure a yield is performed if the current task is being\r
+ deleted. */\r
+ if( pxTaskToDelete == pxCurrentTCB )\r
+ {\r
+ pxTaskToDelete = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are deleting ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToDelete );\r
+\r
+ /* Remove task from the ready list and place in the termination list.\r
+ This will stop the task from be scheduled. The idle task will check\r
+ the termination list and free up any memory allocated by the\r
+ scheduler for the TCB and stack. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */\r
+ if( pxTCB->xEventListItem.pvContainer != NULL )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Increment the ucTasksDeleted variable so the idle task knows\r
+ there is a task that has been deleted and that it should therefore\r
+ check the xTasksWaitingTermination list. */\r
+ ++uxTasksDeleted;\r
+\r
+ /* Increment the uxTaskNumberVariable also so kernel aware debuggers\r
+ can detect that the task lists need re-generating. */\r
+ uxTaskNumber++;\r
+\r
+ traceTASK_DELETE( pxTCB );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Force a reschedule if we have just deleted the current task. */\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( ( void * ) pxTaskToDelete == NULL )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelayUntil == 1 )\r
+\r
+ void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
+ {\r
+ portTickType xTimeToWake;\r
+ portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE;\r
+\r
+ configASSERT( pxPreviousWakeTime );\r
+ configASSERT( ( xTimeIncrement > 0U ) );\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Generate the tick time at which the task wants to wake. */\r
+ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r
+\r
+ if( xTickCount < *pxPreviousWakeTime )\r
+ {\r
+ /* The tick count has overflowed since this function was\r
+ lasted called. In this case the only time we should ever\r
+ actually delay is if the wake time has also overflowed,\r
+ and the wake time is greater than the tick time. When this\r
+ is the case it is as if neither time had overflowed. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The tick time has not overflowed. In this case we will\r
+ delay if either the wake time has overflowed, and/or the\r
+ tick time is less than the wake time. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Update the wake time ready for the next call. */\r
+ *pxPreviousWakeTime = xTimeToWake;\r
+\r
+ if( xShouldDelay != pdFALSE )\r
+ {\r
+ traceTASK_DELAY_UNTIL();\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+\r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( xAlreadyYielded == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelay == 1 )\r
+\r
+ void vTaskDelay( portTickType xTicksToDelay )\r
+ {\r
+ portTickType xTimeToWake;\r
+ signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* A delay time of zero just forces a reschedule. */\r
+ if( xTicksToDelay > ( portTickType ) 0U )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ traceTASK_DELAY();\r
+\r
+ /* A task that is removed from the event list while the\r
+ scheduler is suspended will not get placed in the ready\r
+ list or removed from the blocked list until the scheduler\r
+ is resumed.\r
+\r
+ This task cannot be in an event list as it is the currently\r
+ executing task. */\r
+\r
+ /* Calculate the time to wake - this may overflow but this is\r
+ not a problem. */\r
+ xTimeToWake = xTickCount + xTicksToDelay;\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+ }\r
+\r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( xAlreadyYielded == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_uxTaskPriorityGet == 1 )\r
+\r
+ unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+ uxReturn = pxTCB->uxPriority;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskPrioritySet == 1 )\r
+\r
+ void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxCurrentPriority;\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+\r
+ configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\r
+\r
+ /* Ensure the new priority is valid. */\r
+ if( uxNewPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxNewPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;\r
+ }\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxTask == pxCurrentTCB )\r
+ {\r
+ pxTask = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+\r
+ traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ uxCurrentPriority = pxTCB->uxBasePriority;\r
+ }\r
+ #else\r
+ {\r
+ uxCurrentPriority = pxTCB->uxPriority;\r
+ }\r
+ #endif\r
+\r
+ if( uxCurrentPriority != uxNewPriority )\r
+ {\r
+ /* The priority change may have readied a task of higher\r
+ priority than the calling task. */\r
+ if( uxNewPriority > uxCurrentPriority )\r
+ {\r
+ if( pxTask != NULL )\r
+ {\r
+ /* The priority of another task is being raised. If we\r
+ were raising the priority of the currently running task\r
+ there would be no need to switch as it must have already\r
+ been the highest priority task. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ }\r
+ else if( pxTask == NULL )\r
+ {\r
+ /* Setting our own priority down means there may now be another\r
+ task of higher priority that is ready to execute. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+\r
+\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ /* Only change the priority being used if the task is not\r
+ currently using an inherited priority. */\r
+ if( pxTCB->uxBasePriority == pxTCB->uxPriority )\r
+ {\r
+ pxTCB->uxPriority = uxNewPriority;\r
+ }\r
+\r
+ /* The base priority gets set whatever. */\r
+ pxTCB->uxBasePriority = uxNewPriority;\r
+ }\r
+ #else\r
+ {\r
+ pxTCB->uxPriority = uxNewPriority;\r
+ }\r
+ #endif\r
+\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( configMAX_PRIORITIES - ( portTickType ) uxNewPriority ) );\r
+\r
+ /* If the task is in the blocked or suspended list we need do\r
+ nothing more than change it's priority variable. However, if\r
+ the task is in a ready list it needs to be removed and placed\r
+ in the queue appropriate to its new priority. */\r
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) )\r
+ {\r
+ /* The task is currently in its ready list - remove before adding\r
+ it to it's new ready list. As we are in a critical section we\r
+ can do this even if the scheduler is suspended. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+\r
+ if( xYieldRequired == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Ensure a yield is performed if the current task is being\r
+ suspended. */\r
+ if( pxTaskToSuspend == pxCurrentTCB )\r
+ {\r
+ pxTaskToSuspend = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are suspending ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToSuspend );\r
+\r
+ traceTASK_SUSPEND( pxTCB );\r
+\r
+ /* Remove task from the ready/delayed list and place in the suspended list. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */\r
+ if( pxTCB->xEventListItem.pvContainer != NULL )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ if( ( void * ) pxTaskToSuspend == NULL )\r
+ {\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ /* We have just suspended the current task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ else\r
+ {\r
+ /* The scheduler is not running, but the task that was pointed\r
+ to by pxCurrentTCB has just been suspended and pxCurrentTCB\r
+ must be adjusted to point to a different task. */\r
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )\r
+ {\r
+ /* No other tasks are ready, so set pxCurrentTCB back to\r
+ NULL so when the next task is created pxCurrentTCB will\r
+ be set to point to it no matter what its relative priority\r
+ is. */\r
+ pxCurrentTCB = NULL;\r
+ }\r
+ else\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask )\r
+ {\r
+ portBASE_TYPE xReturn = pdFALSE;\r
+ const tskTCB * const pxTCB = ( tskTCB * ) xTask;\r
+\r
+ /* It does not make sense to check if the calling task is suspended. */\r
+ configASSERT( xTask );\r
+\r
+ /* Is the task we are attempting to resume actually in the\r
+ suspended list? */\r
+ if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+ {\r
+ /* Has the task already been resumed from within an ISR? */\r
+ if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE )\r
+ {\r
+ /* Is it in the suspended list because it is in the\r
+ Suspended state? It is possible to be in the suspended\r
+ list because it is blocked on a task with no timeout\r
+ specified. */\r
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE )\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskResume( xTaskHandle pxTaskToResume )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ /* It does not make sense to resume the calling task. */\r
+ configASSERT( pxTaskToResume );\r
+\r
+ /* Remove the task from whichever list it is currently in, and place\r
+ it in the ready list. */\r
+ pxTCB = ( tskTCB * ) pxTaskToResume;\r
+\r
+ /* The parameter cannot be NULL as it is impossible to resume the\r
+ currently executing task. */\r
+ if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+ {\r
+ traceTASK_RESUME( pxTCB );\r
+\r
+ /* As we are in a critical section we can access the ready\r
+ lists even if the scheduler is suspended. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+\r
+ /* We may have just resumed a higher priority task. */\r
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ /* This yield may not cause the task just resumed to run, but\r
+ will leave the lists in the correct state for the next yield. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r
+\r
+ portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume )\r
+ {\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ configASSERT( pxTaskToResume );\r
+\r
+ pxTCB = ( tskTCB * ) pxTaskToResume;\r
+\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+ {\r
+ traceTASK_RESUME_FROM_ISR( pxTCB );\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed, at which point a\r
+ yield will be performed if necessary. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+ }\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xYieldRequired;\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC SCHEDULER CONTROL documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+void vTaskStartScheduler( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Add the idle task at the lowest priority. */\r
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+ {\r
+ /* Create the idle task, storing its handle in xIdleTaskHandle so it can\r
+ be returned by the xTaskGetIdleTaskHandle() function. */\r
+ xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle );\r
+ }\r
+ #else\r
+ {\r
+ /* Create the idle task without storing its handle. */\r
+ xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL );\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_TIMERS == 1 )\r
+ {\r
+ if( xReturn == pdPASS )\r
+ {\r
+ xReturn = xTimerCreateTimerTask();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ /* Interrupts are turned off here, to ensure a tick does not occur\r
+ before or during the call to xPortStartScheduler(). The stacks of\r
+ the created tasks contain a status word with interrupts switched on\r
+ so interrupts will automatically get re-enabled when the first task\r
+ starts to run.\r
+\r
+ STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE\r
+ DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ xSchedulerRunning = pdTRUE;\r
+ xTickCount = ( portTickType ) 0U;\r
+\r
+ /* If configGENERATE_RUN_TIME_STATS is defined then the following\r
+ macro must be defined to configure the timer/counter used to generate\r
+ the run time counter time base. */\r
+ portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\r
+ \r
+ /* Setting up the timer tick is hardware specific and thus in the\r
+ portable interface. */\r
+ if( xPortStartScheduler() != pdFALSE )\r
+ {\r
+ /* Should not reach here as if the scheduler is running the\r
+ function will not return. */\r
+ }\r
+ else\r
+ {\r
+ /* Should only reach here if a task calls xTaskEndScheduler(). */\r
+ }\r
+ }\r
+\r
+ /* This line will only be reached if the kernel could not be started. */\r
+ configASSERT( xReturn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskEndScheduler( void )\r
+{\r
+ /* Stop the scheduler interrupts and call the portable scheduler end\r
+ routine so the original ISRs can be restored if necessary. The port\r
+ layer must ensure interrupts enable bit is left in the correct state. */\r
+ portDISABLE_INTERRUPTS();\r
+ xSchedulerRunning = pdFALSE;\r
+ vPortEndScheduler();\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+void vTaskSuspendAll( void )\r
+{\r
+ /* A critical section is not required as the variable is of type\r
+ portBASE_TYPE. */\r
+ ++uxSchedulerSuspended;\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskResumeAll( void )\r
+{\r
+register tskTCB *pxTCB;\r
+signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* If uxSchedulerSuspended is zero then this function does not match a\r
+ previous call to vTaskSuspendAll(). */\r
+ configASSERT( uxSchedulerSuspended );\r
+\r
+ /* It is possible that an ISR caused a task to be removed from an event\r
+ list while the scheduler was suspended. If this was the case then the\r
+ removed task will have been added to the xPendingReadyList. Once the\r
+ scheduler has been resumed it is safe to move all the pending ready\r
+ tasks from this list into their appropriate ready list. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ --uxSchedulerSuspended;\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+\r
+ /* Move any readied tasks from the pending list into the\r
+ appropriate ready list. */\r
+ while( listLIST_IS_EMPTY( ( xList * ) &xPendingReadyList ) == pdFALSE )\r
+ {\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) );\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+\r
+ /* If we have moved a task that has a priority higher than\r
+ the current task then we should yield. */\r
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* If any ticks occurred while the scheduler was suspended then\r
+ they should be processed now. This ensures the tick count does not\r
+ slip, and that any delayed tasks are resumed at the correct time. */\r
+ if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vTaskIncrementTick();\r
+ --uxMissedTicks;\r
+ }\r
+\r
+ /* As we have processed some ticks it is appropriate to yield\r
+ to ensure the highest priority task that is ready to run is\r
+ the task actually running. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ #endif\r
+ }\r
+\r
+ if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) )\r
+ {\r
+ xAlreadyYielded = pdTRUE;\r
+ xMissedYield = pdFALSE;\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xAlreadyYielded;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC TASK UTILITIES documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+portTickType xTaskGetTickCount( void )\r
+{\r
+portTickType xTicks;\r
+\r
+ /* Critical section required if running on a 16 bit processor. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ xTicks = xTickCount;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xTicks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portTickType xTaskGetTickCountFromISR( void )\r
+{\r
+portTickType xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ xReturn = xTickCount;\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )\r
+{\r
+ /* A critical section is not required because the variables are of type\r
+ portBASE_TYPE. */\r
+ return uxCurrentNumberOfTasks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_pcTaskGetTaskName == 1 )\r
+\r
+ signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ /* If null is passed in here then the name of the calling task is being queried. */\r
+ pxTCB = prvGetTCBFromHandle( xTaskToQuery );\r
+ configASSERT( pxTCB );\r
+ return &( pxTCB->pcTaskName[ 0 ] );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ void vTaskList( signed char *pcWriteBuffer )\r
+ {\r
+ unsigned portBASE_TYPE uxQueue;\r
+\r
+ /* This is a VERY costly function that should be used for debug only.\r
+ It leaves interrupts disabled for a LONG time. */\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Run through all the lists that could potentially contain a TCB and\r
+ report the task name, state and stack high water mark. */\r
+\r
+ *pcWriteBuffer = ( signed char ) 0x00;\r
+ strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );\r
+\r
+ uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;\r
+\r
+ do\r
+ {\r
+ uxQueue--;\r
+\r
+ if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR );\r
+ }\r
+ }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );\r
+\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ #if( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, &xTasksWaitingTermination, tskDELETED_CHAR );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, &xSuspendedTaskList, tskSUSPENDED_CHAR );\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ void vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
+ {\r
+ unsigned portBASE_TYPE uxQueue;\r
+ unsigned long ulTotalRunTime;\r
+\r
+ /* This is a VERY costly function that should be used for debug only.\r
+ It leaves interrupts disabled for a LONG time. */\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\r
+ #else\r
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r
+ #endif\r
+\r
+ /* Divide ulTotalRunTime by 100 to make the percentage caluclations\r
+ simpler in the prvGenerateRunTimeStatsForTasksInList() function. */\r
+ ulTotalRunTime /= 100UL;\r
+ \r
+ /* Run through all the lists that could potentially contain a TCB,\r
+ generating a table of run timer percentages in the provided\r
+ buffer. */\r
+\r
+ *pcWriteBuffer = ( signed char ) 0x00;\r
+ strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );\r
+\r
+ uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;\r
+\r
+ do\r
+ {\r
+ uxQueue--;\r
+\r
+ if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), ulTotalRunTime );\r
+ }\r
+ }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );\r
+\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, ulTotalRunTime );\r
+ }\r
+\r
+ if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, ulTotalRunTime );\r
+ }\r
+\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xTasksWaitingTermination, ulTotalRunTime );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xSuspendedTaskList, ulTotalRunTime );\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+\r
+ xTaskHandle xTaskGetIdleTaskHandle( void )\r
+ {\r
+ /* If xTaskGetIdleTaskHandle() is called before the scheduler has been\r
+ started, then xIdleTaskHandle will be NULL. */\r
+ configASSERT( ( xIdleTaskHandle != NULL ) );\r
+ return xIdleTaskHandle;\r
+ }\r
+ \r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ * documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+void vTaskIncrementTick( void )\r
+{\r
+tskTCB * pxTCB;\r
+\r
+ /* Called by the portable layer each time a tick interrupt occurs.\r
+ Increments the tick then checks to see if the new tick value will cause any\r
+ tasks to be unblocked. */\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ ++xTickCount;\r
+ if( xTickCount == ( portTickType ) 0U )\r
+ {\r
+ xList *pxTemp;\r
+\r
+ /* Tick count has overflowed so we need to swap the delay lists.\r
+ If there are any items in pxDelayedTaskList here then there is\r
+ an error! */\r
+ configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );\r
+ \r
+ pxTemp = pxDelayedTaskList;\r
+ pxDelayedTaskList = pxOverflowDelayedTaskList;\r
+ pxOverflowDelayedTaskList = pxTemp;\r
+ xNumOfOverflows++;\r
+ \r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
+ {\r
+ /* The new current delayed list is empty. Set\r
+ xNextTaskUnblockTime to the maximum possible value so it is\r
+ extremely unlikely that the \r
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass until\r
+ there is an item in the delayed list. */\r
+ xNextTaskUnblockTime = portMAX_DELAY;\r
+ }\r
+ else\r
+ {\r
+ /* The new current delayed list is not empty, get the value of\r
+ the item at the head of the delayed list. This is the time at\r
+ which the task at the head of the delayed list should be removed\r
+ from the Blocked state. */\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
+ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );\r
+ }\r
+ }\r
+\r
+ /* See if this tick has made a timeout expire. */\r
+ prvCheckDelayedTasks();\r
+ }\r
+ else\r
+ {\r
+ ++uxMissedTicks;\r
+\r
+ /* The tick hook gets called at regular intervals, even if the\r
+ scheduler is locked. */\r
+ #if ( configUSE_TICK_HOOK == 1 )\r
+ {\r
+ vApplicationTickHook();\r
+ }\r
+ #endif\r
+ }\r
+\r
+ #if ( configUSE_TICK_HOOK == 1 )\r
+ {\r
+ /* Guard against the tick hook being called when the missed tick\r
+ count is being unwound (when the scheduler is being unlocked. */\r
+ if( uxMissedTicks == ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vApplicationTickHook();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ traceTASK_INCREMENT_TICK( xTickCount );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction )\r
+ {\r
+ tskTCB *xTCB;\r
+\r
+ /* If xTask is NULL then we are setting our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ /* Save the hook function in the TCB. A critical section is required as\r
+ the value can be accessed from an interrupt. */\r
+ taskENTER_CRITICAL();\r
+ xTCB->pxTaskTag = pxHookFunction;\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
+ {\r
+ tskTCB *xTCB;\r
+ pdTASK_HOOK_CODE xReturn;\r
+\r
+ /* If xTask is NULL then we are setting our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ /* Save the hook function in the TCB. A critical section is required as\r
+ the value can be accessed from an interrupt. */\r
+ taskENTER_CRITICAL();\r
+ xReturn = xTCB->pxTaskTag;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
+ {\r
+ tskTCB *xTCB;\r
+ portBASE_TYPE xReturn;\r
+\r
+ /* If xTask is NULL then we are calling our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ if( xTCB->pxTaskTag != NULL )\r
+ {\r
+ xReturn = xTCB->pxTaskTag( pvParameter );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskSwitchContext( void )\r
+{\r
+ if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ /* The scheduler is currently suspended - do not allow a context\r
+ switch. */\r
+ xMissedYield = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ traceTASK_SWITCHED_OUT();\r
+ \r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ {\r
+ unsigned long ulTempCounter;\r
+ \r
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTempCounter );\r
+ #else\r
+ ulTempCounter = portGET_RUN_TIME_COUNTER_VALUE();\r
+ #endif\r
+ \r
+ /* Add the amount of time the task has been running to the accumulated\r
+ time so far. The time the task started running was stored in\r
+ ulTaskSwitchedInTime. Note that there is no overflow protection here\r
+ so count values are only valid until the timer overflows. Generally\r
+ this will be about 1 hour assuming a 1uS timer increment. */\r
+ pxCurrentTCB->ulRunTimeCounter += ( ulTempCounter - ulTaskSwitchedInTime );\r
+ ulTaskSwitchedInTime = ulTempCounter;\r
+ }\r
+ #endif\r
+ \r
+ taskFIRST_CHECK_FOR_STACK_OVERFLOW();\r
+ taskSECOND_CHECK_FOR_STACK_OVERFLOW();\r
+ \r
+ /* Find the highest priority queue that contains ready tasks. */\r
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )\r
+ {\r
+ configASSERT( uxTopReadyPriority );\r
+ --uxTopReadyPriority;\r
+ }\r
+ \r
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the\r
+ same priority get an equal share of the processor time. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );\r
+ \r
+ traceTASK_SWITCHED_IN();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait )\r
+{\r
+portTickType xTimeToWake;\r
+\r
+ configASSERT( pxEventList );\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. */\r
+\r
+ /* Place the event list item of the TCB in the appropriate event list.\r
+ This is placed in the list in priority order so the highest priority task\r
+ is the first to be woken by the event. */\r
+ vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );\r
+\r
+ /* We must remove ourselves from the ready list before adding ourselves\r
+ to the blocked list as the same list item is used for both lists. We have\r
+ exclusive access to the ready lists as the scheduler is locked. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( xTicksToWait == portMAX_DELAY )\r
+ {\r
+ /* Add ourselves to the suspended task list instead of a delayed task\r
+ list to ensure we are not woken by a timing event. We will block\r
+ indefinitely. */\r
+ vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ }\r
+ #else\r
+ {\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TIMERS == 1\r
+\r
+ void vTaskPlaceOnEventListRestricted( const xList * const pxEventList, portTickType xTicksToWait )\r
+ {\r
+ portTickType xTimeToWake;\r
+\r
+ configASSERT( pxEventList );\r
+\r
+ /* This function should not be called by application code hence the\r
+ 'Restricted' in its name. It is not part of the public API. It is\r
+ designed for use by kernel code, and has special calling requirements -\r
+ it should be called from a critical section. */\r
+\r
+ \r
+ /* Place the event list item of the TCB in the appropriate event list.\r
+ In this case it is assume that this is the only task that is going to\r
+ be waiting on this event list, so the faster vListInsertEnd() function\r
+ can be used in place of vListInsert. */\r
+ vListInsertEnd( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );\r
+\r
+ /* We must remove this task from the ready list before adding it to the\r
+ blocked list as the same list item is used for both lists. This\r
+ function is called form a critical section. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ \r
+#endif /* configUSE_TIMERS */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList )\r
+{\r
+tskTCB *pxUnblockedTCB;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. It can also be called from within an ISR. */\r
+\r
+ /* The event list is sorted in priority order, so we can remove the\r
+ first in the list, remove the TCB from the delayed list, and add\r
+ it to the ready list.\r
+\r
+ If an event is for a queue that is locked then this function will never\r
+ get called - the lock count on the queue will get modified instead. This\r
+ means we can always expect exclusive access to the event list here.\r
+ \r
+ This function assumes that a check has already been made to ensure that\r
+ pxEventList is not empty. */\r
+ pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+ configASSERT( pxUnblockedTCB );\r
+ vListRemove( &( pxUnblockedTCB->xEventListItem ) );\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ vListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxUnblockedTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r
+ }\r
+\r
+ if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ /* Return true if the task removed from the event list has\r
+ a higher priority than the calling task. This allows\r
+ the calling task to know if it should force a context\r
+ switch now. */\r
+ xReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut )\r
+{\r
+ configASSERT( pxTimeOut );\r
+ pxTimeOut->xOverflowCount = xNumOfOverflows;\r
+ pxTimeOut->xTimeOnEntering = xTickCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxTimeOut );\r
+ configASSERT( pxTicksToWait );\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is\r
+ the maximum block time then the task should block indefinitely, and\r
+ therefore never time out. */\r
+ if( *pxTicksToWait == portMAX_DELAY )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else /* We are not blocking indefinitely, perform the checks below. */\r
+ #endif\r
+\r
+ if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( ( portTickType ) xTickCount >= ( portTickType ) pxTimeOut->xTimeOnEntering ) )\r
+ {\r
+ /* The tick count is greater than the time at which vTaskSetTimeout()\r
+ was called, but has also overflowed since vTaskSetTimeOut() was called.\r
+ It must have wrapped all the way around and gone past us again. This\r
+ passed since vTaskSetTimeout() was called. */\r
+ xReturn = pdTRUE;\r
+ }\r
+ else if( ( ( portTickType ) ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering ) ) < ( portTickType ) *pxTicksToWait )\r
+ {\r
+ /* Not a genuine timeout. Adjust parameters for time remaining. */\r
+ *pxTicksToWait -= ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering );\r
+ vTaskSetTimeOutState( pxTimeOut );\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskMissedYield( void )\r
+{\r
+ xMissedYield = pdTRUE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+ unsigned portBASE_TYPE uxTaskGetTaskNumber( xTaskHandle xTask )\r
+ {\r
+ unsigned portBASE_TYPE uxReturn;\r
+ tskTCB *pxTCB;\r
+ \r
+ if( xTask != NULL )\r
+ {\r
+ pxTCB = ( tskTCB * ) xTask;\r
+ uxReturn = pxTCB->uxTaskNumber;\r
+ }\r
+ else\r
+ {\r
+ uxReturn = 0U;\r
+ }\r
+ \r
+ return uxReturn;\r
+ }\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+ void vTaskSetTaskNumber( xTaskHandle xTask, unsigned portBASE_TYPE uxHandle )\r
+ {\r
+ tskTCB *pxTCB;\r
+ \r
+ if( xTask != NULL )\r
+ {\r
+ pxTCB = ( tskTCB * ) xTask;\r
+ pxTCB->uxTaskNumber = uxHandle;\r
+ }\r
+ }\r
+#endif\r
+\r
+\r
+/*\r
+ * -----------------------------------------------------------\r
+ * The Idle task.\r
+ * ----------------------------------------------------------\r
+ *\r
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION( prvIdleTask, pvParameters )\r
+{\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* See if any tasks have been deleted. */\r
+ prvCheckTasksWaitingTermination();\r
+\r
+ #if ( configUSE_PREEMPTION == 0 )\r
+ {\r
+ /* If we are not using preemption we keep forcing a task switch to\r
+ see if any other task has become available. If we are using\r
+ preemption we don't need to do this as any task becoming available\r
+ will automatically get the processor anyway. */\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\r
+ {\r
+ /* When using preemption tasks of equal priority will be\r
+ timesliced. If a task that is sharing the idle priority is ready\r
+ to run then the idle task should yield before the end of the\r
+ timeslice.\r
+\r
+ A critical region is not required here as we are just reading from\r
+ the list, and an occasional incorrect value will not matter. If\r
+ the ready list at the idle priority contains more than one task\r
+ then a task other than the idle task is ready to execute. */\r
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_IDLE_HOOK == 1 )\r
+ {\r
+ extern void vApplicationIdleHook( void );\r
+\r
+ /* Call the user defined function from within the idle task. This\r
+ allows the application designer to add background functionality\r
+ without the overhead of a separate task.\r
+ NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\r
+ CALL A FUNCTION THAT MIGHT BLOCK. */\r
+ vApplicationIdleHook();\r
+ }\r
+ #endif\r
+ }\r
+} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * File private functions documented at the top of the file.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth )\r
+{\r
+ /* Store the function name in the TCB. */\r
+ #if configMAX_TASK_NAME_LEN > 1\r
+ {\r
+ /* Don't bring strncpy into the build unnecessarily. */\r
+ strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned short ) configMAX_TASK_NAME_LEN );\r
+ }\r
+ #endif\r
+ pxTCB->pcTaskName[ ( unsigned short ) configMAX_TASK_NAME_LEN - ( unsigned short ) 1 ] = ( signed char ) '\0';\r
+\r
+ /* This is used as an array index so must ensure it's not too large. First\r
+ remove the privilege bit if one is present. */\r
+ if( uxPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;\r
+ }\r
+\r
+ pxTCB->uxPriority = uxPriority;\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ pxTCB->uxBasePriority = uxPriority;\r
+ }\r
+ #endif\r
+\r
+ vListInitialiseItem( &( pxTCB->xGenericListItem ) );\r
+ vListInitialiseItem( &( pxTCB->xEventListItem ) );\r
+\r
+ /* Set the pxTCB as a link back from the xListItem. This is so we can get\r
+ back to the containing TCB from a generic item in a list. */\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r
+\r
+ /* Event lists are always in priority order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r
+\r
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+ {\r
+ pxTCB->uxCriticalNesting = ( unsigned portBASE_TYPE ) 0U;\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+ {\r
+ pxTCB->pxTaskTag = NULL;\r
+ }\r
+ #endif\r
+\r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ {\r
+ pxTCB->ulRunTimeCounter = 0UL;\r
+ }\r
+ #endif\r
+\r
+ #if ( portUSING_MPU_WRAPPERS == 1 )\r
+ {\r
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );\r
+ }\r
+ #else\r
+ {\r
+ ( void ) xRegions;\r
+ ( void ) usStackDepth;\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portUSING_MPU_WRAPPERS == 1 )\r
+\r
+ void vTaskAllocateMPURegions( xTaskHandle xTaskToModify, const xMemoryRegion * const xRegions )\r
+ {\r
+ tskTCB *pxTCB;\r
+ \r
+ if( xTaskToModify == pxCurrentTCB )\r
+ {\r
+ xTaskToModify = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are deleting ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( xTaskToModify );\r
+\r
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+#endif\r
+\r
+static void prvInitialiseTaskLists( void )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ for( uxPriority = ( unsigned portBASE_TYPE ) 0U; uxPriority < configMAX_PRIORITIES; uxPriority++ )\r
+ {\r
+ vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) );\r
+ }\r
+\r
+ vListInitialise( ( xList * ) &xDelayedTaskList1 );\r
+ vListInitialise( ( xList * ) &xDelayedTaskList2 );\r
+ vListInitialise( ( xList * ) &xPendingReadyList );\r
+\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xTasksWaitingTermination );\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xSuspendedTaskList );\r
+ }\r
+ #endif\r
+\r
+ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r
+ using list2. */\r
+ pxDelayedTaskList = &xDelayedTaskList1;\r
+ pxOverflowDelayedTaskList = &xDelayedTaskList2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTasksWaitingTermination( void )\r
+{\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ portBASE_TYPE xListIsEmpty;\r
+\r
+ /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r
+ too often in the idle task. */\r
+ if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vTaskSuspendAll();\r
+ xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );\r
+ xTaskResumeAll();\r
+\r
+ if( xListIsEmpty == pdFALSE )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ --uxCurrentNumberOfTasks;\r
+ --uxTasksDeleted;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ prvDeleteTCB( pxTCB );\r
+ }\r
+ }\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake )\r
+{\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the current block list. */\r
+ vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* If the task entering the blocked state was placed at the head of the\r
+ list of blocked tasks then xNextTaskUnblockTime needs to be updated\r
+ too. */\r
+ if( xTimeToWake < xNextTaskUnblockTime )\r
+ {\r
+ xNextTaskUnblockTime = xTimeToWake;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer )\r
+{\r
+tskTCB *pxNewTCB;\r
+\r
+ /* Allocate space for the TCB. Where the memory comes from depends on\r
+ the implementation of the port malloc function. */\r
+ pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) );\r
+\r
+ if( pxNewTCB != NULL )\r
+ {\r
+ /* Allocate space for the stack used by the task being created.\r
+ The base of the stack memory stored in the TCB so the task can\r
+ be deleted later if required. */\r
+ pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMallocAligned( ( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ), puxStackBuffer );\r
+\r
+ if( pxNewTCB->pxStack == NULL )\r
+ {\r
+ /* Could not allocate the stack. Delete the allocated TCB. */\r
+ vPortFree( pxNewTCB );\r
+ pxNewTCB = NULL;\r
+ }\r
+ else\r
+ {\r
+ /* Just to help debugging. */\r
+ memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( portSTACK_TYPE ) );\r
+ }\r
+ }\r
+\r
+ return pxNewTCB;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus )\r
+ {\r
+ volatile tskTCB *pxNextTCB, *pxFirstTCB;\r
+ unsigned short usStackRemaining;\r
+ PRIVILEGED_DATA static char pcStatusString[ configMAX_TASK_NAME_LEN + 30 ];\r
+\r
+ /* Write the details of all the TCB's in pxList into the buffer. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+ do\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+ #if ( portSTACK_GROWTH > 0 )\r
+ {\r
+ usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxEndOfStack );\r
+ }\r
+ #else\r
+ {\r
+ usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxStack );\r
+ }\r
+ #endif \r
+ \r
+ sprintf( pcStatusString, ( char * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber );\r
+ strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatusString );\r
+\r
+ } while( pxNextTCB != pxFirstTCB );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime )\r
+ {\r
+ volatile tskTCB *pxNextTCB, *pxFirstTCB;\r
+ unsigned long ulStatsAsPercentage;\r
+\r
+ /* Write the run time stats of all the TCB's in pxList into the buffer. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+ do\r
+ {\r
+ /* Get next TCB in from the list. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+\r
+ /* Divide by zero check. */\r
+ if( ulTotalRunTime > 0UL )\r
+ {\r
+ /* Has the task run at all? */\r
+ if( pxNextTCB->ulRunTimeCounter == 0UL )\r
+ {\r
+ /* The task has used no CPU time at all. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t0\t\t0%%\r\n", pxNextTCB->pcTaskName );\r
+ }\r
+ else\r
+ {\r
+ /* What percentage of the total run time has the task used?\r
+ This will always be rounded down to the nearest integer.\r
+ ulTotalRunTime has already been divided by 100. */\r
+ ulStatsAsPercentage = pxNextTCB->ulRunTimeCounter / ulTotalRunTime;\r
+\r
+ if( ulStatsAsPercentage > 0UL )\r
+ {\r
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+ {\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t%lu%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter, ulStatsAsPercentage ); \r
+ }\r
+ #else\r
+ {\r
+ /* sizeof( int ) == sizeof( long ) so a smaller\r
+ printf() library can be used. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t%u%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );\r
+ }\r
+ #endif\r
+ }\r
+ else\r
+ {\r
+ /* If the percentage is zero here then the task has\r
+ consumed less than 1% of the total run time. */\r
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+ {\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t<1%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter ); \r
+ }\r
+ #else\r
+ {\r
+ /* sizeof( int ) == sizeof( long ) so a smaller\r
+ printf() library can be used. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t<1%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter );\r
+ }\r
+ #endif\r
+ }\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatsString );\r
+ }\r
+\r
+ } while( pxNextTCB != pxFirstTCB );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+\r
+ static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte )\r
+ {\r
+ register unsigned short usCount = 0U;\r
+\r
+ while( *pucStackByte == tskSTACK_FILL_BYTE )\r
+ {\r
+ pucStackByte -= portSTACK_GROWTH;\r
+ usCount++;\r
+ }\r
+\r
+ usCount /= sizeof( portSTACK_TYPE );\r
+\r
+ return usCount;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
+\r
+ unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned char *pcEndOfStack;\r
+ unsigned portBASE_TYPE uxReturn;\r
+\r
+ pxTCB = prvGetTCBFromHandle( xTask );\r
+\r
+ #if portSTACK_GROWTH < 0\r
+ {\r
+ pcEndOfStack = ( unsigned char * ) pxTCB->pxStack;\r
+ }\r
+ #else\r
+ {\r
+ pcEndOfStack = ( unsigned char * ) pxTCB->pxEndOfStack;\r
+ }\r
+ #endif\r
+\r
+ uxReturn = ( unsigned portBASE_TYPE ) usTaskCheckFreeStackSpace( pcEndOfStack );\r
+\r
+ return uxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ static void prvDeleteTCB( tskTCB *pxTCB )\r
+ {\r
+ /* This call is required specifically for the TriCore port. It must be\r
+ above the vPortFree() calls. The call is also used by ports/demos that\r
+ want to allocate and clean RAM statically. */\r
+ portCLEAN_UP_TCB( pxTCB );\r
+\r
+ /* Free up the memory allocated by the scheduler for the task. It is up to\r
+ the task to free any memory allocated at the application level. */\r
+ vPortFreeAligned( pxTCB->pxStack );\r
+ vPortFree( pxTCB );\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r
+\r
+ xTaskHandle xTaskGetCurrentTaskHandle( void )\r
+ {\r
+ xTaskHandle xReturn;\r
+\r
+ /* A critical section is not required as this is not called from\r
+ an interrupt and the current TCB will always be the same for any\r
+ individual execution thread. */\r
+ xReturn = pxCurrentTCB;\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+\r
+ portBASE_TYPE xTaskGetSchedulerState( void )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ if( xSchedulerRunning == pdFALSE )\r
+ {\r
+ xReturn = taskSCHEDULER_NOT_STARTED;\r
+ }\r
+ else\r
+ {\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xReturn = taskSCHEDULER_RUNNING;\r
+ }\r
+ else\r
+ {\r
+ xReturn = taskSCHEDULER_SUSPENDED;\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder )\r
+ {\r
+ tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;\r
+\r
+ configASSERT( pxMutexHolder );\r
+\r
+ if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )\r
+ {\r
+ /* Adjust the mutex holder state to account for its new priority. */\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxCurrentTCB->uxPriority );\r
+\r
+ /* If the task being modified is in the ready state it will need to\r
+ be moved in to a new list. */\r
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+ {\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Inherit the priority before being moved into the new list. */\r
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* Just inherit the priority. */\r
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+ }\r
+\r
+ traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder )\r
+ {\r
+ tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;\r
+\r
+ if( pxMutexHolder != NULL )\r
+ {\r
+ if( pxTCB->uxPriority != pxTCB->uxBasePriority )\r
+ {\r
+ /* We must be the running task to be able to give the mutex back.\r
+ Remove ourselves from the ready list we currently appear in. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Disinherit the priority before adding the task into the new\r
+ ready list. */\r
+ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\r
+ pxTCB->uxPriority = pxTCB->uxBasePriority;\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxTCB->uxPriority );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+\r
+ void vTaskEnterCritical( void )\r
+ {\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ ( pxCurrentTCB->uxCriticalNesting )++;\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+\r
+void vTaskExitCritical( void )\r
+{\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( pxCurrentTCB->uxCriticalNesting > 0U )\r
+ {\r
+ ( pxCurrentTCB->uxCriticalNesting )--;\r
+\r
+ if( pxCurrentTCB->uxCriticalNesting == 0U )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* This entire source file will be skipped if the application is not configured\r
+to include software timer functionality. This #if is closed at the very bottom\r
+of this file. If you want to include software timer functionality then ensure\r
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+#if ( configUSE_TIMERS == 1 )\r
+\r
+/* Misc definitions. */\r
+#define tmrNO_DELAY ( portTickType ) 0U\r
+\r
+/* The definition of the timers themselves. */\r
+typedef struct tmrTimerControl\r
+{\r
+ const signed char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */\r
+ xListItem xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */\r
+ portTickType xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\r
+ unsigned portBASE_TYPE uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one shot timer. */\r
+ void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */\r
+ tmrTIMER_CALLBACK pxCallbackFunction; /*<< The function that will be called when the timer expires. */\r
+} xTIMER;\r
+\r
+/* The definition of messages that can be sent and received on the timer\r
+queue. */\r
+typedef struct tmrTimerQueueMessage\r
+{\r
+ portBASE_TYPE xMessageID; /*<< The command being sent to the timer service task. */\r
+ portTickType xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\r
+ xTIMER * pxTimer; /*<< The timer to which the command will be applied. */\r
+} xTIMER_MESSAGE;\r
+\r
+\r
+/* The list in which active timers are stored. Timers are referenced in expire\r
+time order, with the nearest expiry time at the front of the list. Only the\r
+timer service task is allowed to access xActiveTimerList. */\r
+PRIVILEGED_DATA static xList xActiveTimerList1;\r
+PRIVILEGED_DATA static xList xActiveTimerList2;\r
+PRIVILEGED_DATA static xList *pxCurrentTimerList;\r
+PRIVILEGED_DATA static xList *pxOverflowTimerList;\r
+\r
+/* A queue that is used to send commands to the timer service task. */\r
+PRIVILEGED_DATA static xQueueHandle xTimerQueue = NULL;\r
+\r
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+ \r
+ PRIVILEGED_DATA static xTaskHandle xTimerTaskHandle = NULL;\r
+ \r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the infrastructure used by the timer service task if it has not\r
+ * been initialised already.\r
+ */\r
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The timer service task (daemon). Timer functionality is controlled by this\r
+ * task. Other tasks communicate with the timer service task using the\r
+ * xTimerQueue queue.\r
+ */\r
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Called by the timer service task to interpret and process a command it\r
+ * received on the timer queue.\r
+ */\r
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\r
+ * depending on if the expire time causes a timer counter overflow.\r
+ */\r
+static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * An active timer has reached its expire time. Reload the timer if it is an\r
+ * auto reload timer, then call its callback.\r
+ */\r
+static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The tick count has overflowed. Switch the timer lists after ensuring the\r
+ * current timer list does not still reference some timers.\r
+ */\r
+static void prvSwitchTimerLists( portTickType xLastTime ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\r
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.\r
+ */\r
+static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * If the timer list contains any active timers then return the expire time of\r
+ * the timer that will expire first and set *pxListWasEmpty to false. If the\r
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty\r
+ * to pdTRUE.\r
+ */\r
+static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * If a timer has expired, process it. Otherwise, block the timer service task\r
+ * until either a timer does expire or a command is received.\r
+ */\r
+static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerCreateTimerTask( void )\r
+{\r
+portBASE_TYPE xReturn = pdFAIL;\r
+\r
+ /* This function is called when the scheduler is started if\r
+ configUSE_TIMERS is set to 1. Check that the infrastructure used by the\r
+ timer service task has been created/initialised. If timers have already\r
+ been created then the initialisation will already have been performed. */\r
+ prvCheckForValidListAndQueue();\r
+\r
+ if( xTimerQueue != NULL )\r
+ {\r
+ #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+ {\r
+ /* Create the timer task, storing its handle in xTimerTaskHandle so\r
+ it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */\r
+ xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, &xTimerTaskHandle ); \r
+ }\r
+ #else\r
+ {\r
+ /* Create the timer task without storing its handle. */\r
+ xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, NULL);\r
+ }\r
+ #endif\r
+ }\r
+\r
+ configASSERT( xReturn );\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xTimerHandle xTimerCreate( const signed char *pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void *pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction )\r
+{\r
+xTIMER *pxNewTimer;\r
+\r
+ /* Allocate the timer structure. */\r
+ if( xTimerPeriodInTicks == ( portTickType ) 0U )\r
+ {\r
+ pxNewTimer = NULL;\r
+ configASSERT( ( xTimerPeriodInTicks > 0 ) );\r
+ }\r
+ else\r
+ {\r
+ pxNewTimer = ( xTIMER * ) pvPortMalloc( sizeof( xTIMER ) );\r
+ if( pxNewTimer != NULL )\r
+ {\r
+ /* Ensure the infrastructure used by the timer service task has been\r
+ created/initialised. */\r
+ prvCheckForValidListAndQueue();\r
+ \r
+ /* Initialise the timer structure members using the function parameters. */\r
+ pxNewTimer->pcTimerName = pcTimerName;\r
+ pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\r
+ pxNewTimer->uxAutoReload = uxAutoReload;\r
+ pxNewTimer->pvTimerID = pvTimerID;\r
+ pxNewTimer->pxCallbackFunction = pxCallbackFunction;\r
+ vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\r
+ \r
+ traceTIMER_CREATE( pxNewTimer );\r
+ }\r
+ else\r
+ {\r
+ traceTIMER_CREATE_FAILED();\r
+ }\r
+ }\r
+ \r
+ return ( xTimerHandle ) pxNewTimer;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portTickType xBlockTime )\r
+{\r
+portBASE_TYPE xReturn = pdFAIL;\r
+xTIMER_MESSAGE xMessage;\r
+\r
+ /* Send a message to the timer service task to perform a particular action\r
+ on a particular timer definition. */\r
+ if( xTimerQueue != NULL )\r
+ {\r
+ /* Send a command to the timer service task to start the xTimer timer. */\r
+ xMessage.xMessageID = xCommandID;\r
+ xMessage.xMessageValue = xOptionalValue;\r
+ xMessage.pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ if( pxHigherPriorityTaskWoken == NULL )\r
+ {\r
+ if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\r
+ {\r
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xBlockTime );\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
+ }\r
+ \r
+ traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\r
+ }\r
+ \r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+\r
+ xTaskHandle xTimerGetTimerDaemonTaskHandle( void )\r
+ {\r
+ /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\r
+ started, then xTimerTaskHandle will be NULL. */\r
+ configASSERT( ( xTimerTaskHandle != NULL ) );\r
+ return xTimerTaskHandle;\r
+ }\r
+ \r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow )\r
+{\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xResult;\r
+\r
+ /* Remove the timer from the list of active timers. A check has already\r
+ been performed to ensure the list is not empty. */\r
+ pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+ traceTIMER_EXPIRED( pxTimer );\r
+\r
+ /* If the timer is an auto reload timer then calculate the next\r
+ expiry time and re-insert the timer in the list of active timers. */\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ /* This is the only time a timer is inserted into a list using\r
+ a time relative to anything other than the current time. It\r
+ will therefore be inserted into the correct list relative to\r
+ the time this task thinks it is now, even if a command to\r
+ switch lists due to a tick count overflow is already waiting in\r
+ the timer queue. */\r
+ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )\r
+ {\r
+ /* The timer expired before it was added to the active timer\r
+ list. Reload it now. */\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+\r
+ /* Call the timer callback. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTimerTask( void *pvParameters )\r
+{\r
+portTickType xNextExpireTime;\r
+portBASE_TYPE xListWasEmpty;\r
+\r
+ /* Just to avoid compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Query the timers list to see if it contains any timers, and if so,\r
+ obtain the time at which the next timer will expire. */\r
+ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\r
+\r
+ /* If a timer has expired, process it. Otherwise, block this task\r
+ until either a timer does expire, or a command is received. */\r
+ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\r
+ \r
+ /* Empty the command queue. */\r
+ prvProcessReceivedCommands(); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty )\r
+{\r
+portTickType xTimeNow;\r
+portBASE_TYPE xTimerListsWereSwitched;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Obtain the time now to make an assessment as to whether the timer\r
+ has expired or not. If obtaining the time causes the lists to switch\r
+ then don't process this timer as any timers that remained in the list\r
+ when the lists were switched will have been processed within the\r
+ prvSampelTimeNow() function. */\r
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+ if( xTimerListsWereSwitched == pdFALSE )\r
+ {\r
+ /* The tick count has not overflowed, has the timer expired? */\r
+ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\r
+ {\r
+ xTaskResumeAll();\r
+ prvProcessExpiredTimer( xNextExpireTime, xTimeNow );\r
+ }\r
+ else\r
+ {\r
+ /* The tick count has not overflowed, and the next expire\r
+ time has not been reached yet. This task should therefore\r
+ block to wait for the next expire time or a command to be\r
+ received - whichever comes first. The following line cannot\r
+ be reached unless xNextExpireTime > xTimeNow, except in the\r
+ case when the current timer list is empty. */\r
+ vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );\r
+\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ /* Yield to wait for either a command to arrive, or the block time\r
+ to expire. If a command arrived between the critical section being\r
+ exited and this yield then the yield will not cause the task\r
+ to block. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xTaskResumeAll();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty )\r
+{\r
+portTickType xNextExpireTime;\r
+\r
+ /* Timers are listed in expiry time order, with the head of the list\r
+ referencing the task that will expire first. Obtain the time at which\r
+ the timer with the nearest expiry time will expire. If there are no\r
+ active timers then just set the next expire time to 0. That will cause\r
+ this task to unblock when the tick count overflows, at which point the\r
+ timer lists will be switched and the next expiry time can be\r
+ re-assessed. */\r
+ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\r
+ if( *pxListWasEmpty == pdFALSE )\r
+ {\r
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ }\r
+ else\r
+ {\r
+ /* Ensure the task unblocks when the tick count rolls over. */\r
+ xNextExpireTime = ( portTickType ) 0U;\r
+ }\r
+\r
+ return xNextExpireTime;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched )\r
+{\r
+portTickType xTimeNow;\r
+static portTickType xLastTime = ( portTickType ) 0U;\r
+\r
+ xTimeNow = xTaskGetTickCount();\r
+ \r
+ if( xTimeNow < xLastTime )\r
+ {\r
+ prvSwitchTimerLists( xLastTime );\r
+ *pxTimerListsWereSwitched = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ *pxTimerListsWereSwitched = pdFALSE;\r
+ }\r
+ \r
+ xLastTime = xTimeNow;\r
+ \r
+ return xTimeNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime )\r
+{\r
+portBASE_TYPE xProcessTimerNow = pdFALSE;\r
+\r
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\r
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+ \r
+ if( xNextExpiryTime <= xTimeNow )\r
+ {\r
+ /* Has the expiry time elapsed between the command to start/reset a\r
+ timer was issued, and the time the command was processed? */\r
+ if( ( ( portTickType ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )\r
+ {\r
+ /* The time between a command being issued and the command being\r
+ processed actually exceeds the timers period. */\r
+ xProcessTimerNow = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\r
+ {\r
+ /* If, since the command was issued, the tick count has overflowed\r
+ but the expiry time has not, then the timer must have already passed\r
+ its expiry time and should be processed immediately. */\r
+ xProcessTimerNow = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+\r
+ return xProcessTimerNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessReceivedCommands( void )\r
+{\r
+xTIMER_MESSAGE xMessage;\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xTimerListsWereSwitched, xResult;\r
+portTickType xTimeNow;\r
+\r
+ /* In this case the xTimerListsWereSwitched parameter is not used, but it\r
+ must be present in the function call. */\r
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+\r
+ while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )\r
+ {\r
+ pxTimer = xMessage.pxTimer;\r
+\r
+ /* Is the timer already in a list of active timers? When the command\r
+ is trmCOMMAND_PROCESS_TIMER_OVERFLOW, the timer will be NULL as the\r
+ command is to the task rather than to an individual timer. */\r
+ if( pxTimer != NULL )\r
+ {\r
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )\r
+ {\r
+ /* The timer is in a list, remove it. */\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+\r
+ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.xMessageValue );\r
+ \r
+ switch( xMessage.xMessageID )\r
+ {\r
+ case tmrCOMMAND_START : \r
+ /* Start or restart a timer. */\r
+ if( prvInsertTimerInActiveList( pxTimer, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.xMessageValue ) == pdTRUE )\r
+ {\r
+ /* The timer expired before it was added to the active timer\r
+ list. Process it now. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case tmrCOMMAND_STOP : \r
+ /* The timer has already been removed from the active list.\r
+ There is nothing to do here. */\r
+ break;\r
+\r
+ case tmrCOMMAND_CHANGE_PERIOD :\r
+ pxTimer->xTimerPeriodInTicks = xMessage.xMessageValue;\r
+ configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\r
+ prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\r
+ break;\r
+\r
+ case tmrCOMMAND_DELETE :\r
+ /* The timer has already been removed from the active list,\r
+ just free up the memory. */\r
+ vPortFree( pxTimer );\r
+ break;\r
+\r
+ default : \r
+ /* Don't expect to get here. */\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSwitchTimerLists( portTickType xLastTime )\r
+{\r
+portTickType xNextExpireTime, xReloadTime;\r
+xList *pxTemp;\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xResult;\r
+\r
+ /* Remove compiler warnings if configASSERT() is not defined. */\r
+ ( void ) xLastTime;\r
+ \r
+ /* The tick count has overflowed. The timer lists must be switched.\r
+ If there are any timers still referenced from the current timer list\r
+ then they must have expired and should be processed before the lists\r
+ are switched. */\r
+ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\r
+ {\r
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+\r
+ /* Remove the timer from the list. */\r
+ pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+\r
+ /* Execute its callback, then send a command to restart the timer if\r
+ it is an auto-reload timer. It cannot be restarted here as the lists\r
+ have not yet been switched. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ /* Calculate the reload value, and if the reload value results in\r
+ the timer going into the same timer list then it has already expired\r
+ and the timer should be re-inserted into the current list so it is\r
+ processed again within this loop. Otherwise a command should be sent\r
+ to restart the timer to ensure it is only inserted into a list after\r
+ the lists have been swapped. */\r
+ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\r
+ if( xReloadTime > xNextExpireTime )\r
+ {\r
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\r
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ else\r
+ {\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+ }\r
+\r
+ pxTemp = pxCurrentTimerList;\r
+ pxCurrentTimerList = pxOverflowTimerList;\r
+ pxOverflowTimerList = pxTemp;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckForValidListAndQueue( void )\r
+{\r
+ /* Check that the list from which active timers are referenced, and the\r
+ queue used to communicate with the timer service, have been\r
+ initialised. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTimerQueue == NULL )\r
+ {\r
+ vListInitialise( &xActiveTimerList1 );\r
+ vListInitialise( &xActiveTimerList2 );\r
+ pxCurrentTimerList = &xActiveTimerList1;\r
+ pxOverflowTimerList = &xActiveTimerList2;\r
+ xTimerQueue = xQueueCreate( ( unsigned portBASE_TYPE ) configTIMER_QUEUE_LENGTH, sizeof( xTIMER_MESSAGE ) );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer )\r
+{\r
+portBASE_TYPE xTimerIsInActiveList;\r
+xTIMER *pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ /* Is the timer in the list of active timers? */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Checking to see if it is in the NULL list in effect checks to see if\r
+ it is referenced from either the current or the overflow timer lists in\r
+ one go, but the logic has to be reversed, hence the '!'. */\r
+ xTimerIsInActiveList = !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xTimerIsInActiveList;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvTimerGetTimerID( xTimerHandle xTimer )\r
+{\r
+xTIMER *pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ return pxTimer->pvTimerID;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This entire source file will be skipped if the application is not configured\r
+to include software timer functionality. If you want to include software timer\r
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+#endif /* configUSE_TIMERS == 1 */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/* \r
+ * The following #error directive is to remind users that a batch file must be\r
+ * executed prior to this project being built. Once it has been executed \r
+ * remove the #error line below.\r
+ */\r
+#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#include <stdint.h>\r
+extern uint32_t SystemCoreClock;\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )\r
+#define configMAX_TASK_NAME_LEN ( 10 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Cortex-M specific definitions. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 4 /* 15 priority levels */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x0f\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL\r
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\r
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 10\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\r
+ \r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } \r
+ \r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple IO routines to control the LEDs.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo includes. */\r
+#include "partest.h"\r
+\r
+/* Library includes. */\r
+#include <board.h>\r
+#include <gpio.h>\r
+\r
+/* The number of LEDs available to the user on the evaluation kit. */\r
+#define partestNUM_LEDS ( 3UL )\r
+\r
+/* Definitions not included in sam3s_ek.h. */\r
+#define LED2_GPIO ( PIO_PC20_IDX )\r
+\r
+/* One of the LEDs is wired in the inverse to the others as it is also used as\r
+the power LED. */\r
+#define partstsINVERTED_LED ( 0UL )\r
+\r
+/* The index of the pins to which the LEDs are connected. The ordering of the\r
+LEDs in this array is intentional and matches the order they appear on the \r
+hardware. */\r
+static const uint32_t ulLED[] = { LED2_GPIO, LED0_GPIO, LED1_GPIO };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+long l;\r
+\r
+ for( l = 0; l < partestNUM_LEDS; l++ )\r
+ {\r
+ /* Configure the LED, before ensuring it starts in the off state. */\r
+ gpio_configure_pin( ulLED[ l ], ( PIO_OUTPUT_1 | PIO_DEFAULT ) );\r
+ vParTestSetLED( l, pdFALSE );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{ \r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ if( uxLED == partstsINVERTED_LED )\r
+ {\r
+ xValue = !xValue; \r
+ }\r
+ \r
+ if( xValue != pdFALSE )\r
+ {\r
+ /* Turn the LED on. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_low( ulLED[ uxLED ]);\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */\r
+ portENTER_CRITICAL();\r
+ {\r
+ gpio_set_pin_high( ulLED[ uxLED ]);\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+ if( uxLED < partestNUM_LEDS )\r
+ {\r
+ gpio_toggle_pin( ulLED[ uxLED ] );\r
+ }\r
+}\r
+ \r
+\r
+\r
--- /dev/null
+/**
+ * \file
+ *
+ * \brief Autogenerated API include file for the Atmel Software Framework (ASF)
+ *
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ASF_H
+#define ASF_H
+
+/*
+ * This file includes all API header files for the selected drivers from ASF.
+ * Note: There might be duplicate includes required by more than one driver.
+ *
+ * The file is automatically generated and will be re-written when
+ * running the ASF driver selector tool. Any changes will be discarded.
+ */
+\r
+// From module: Common SAM compiler driver\r
+#include <compiler.h>\r
+#include <status_codes.h>\r
+\r
+// From module: GPIO - General purpose Input/Output\r
+#include <gpio.h>\r
+\r
+// From module: Generic board support\r
+#include <board.h>\r
+\r
+// From module: Interrupt management - SAM3 implementation\r
+#include <interrupt.h>\r
+\r
+// From module: PIO - Parallel Input/Output Controller\r
+#include <pio.h>\r
+#include <pio_handler.h>\r
+\r
+// From module: SAM4S startup code\r
+#include <exceptions.h>\r
+
+#endif // ASF_H
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Standard board header file.\r
+ *\r
+ * This file includes the appropriate board header file according to the\r
+ * defined board (parameter BOARD).\r
+ *\r
+ * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice, this\r
+ * list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an Atmel\r
+ * microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+/**\r
+ * \defgroup group_common_boards Generic board support\r
+ *\r
+ * The generic board support module includes board-specific definitions\r
+ * and function prototypes, such as the board initialization function.\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
+#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+#define UC3C_EK 3 //!< AT32UC3C UC3C_EK board.\r
+#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.\r
+#define EVK1105 5 //!< AT32UC3A EVK1105 board.\r
+#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.\r
+#define UC3L_EK 7 //!< AT32UC3L-EK board.\r
+#define XPLAIN 8 //!< ATxmega128A1 Xplain board.\r
+#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.\r
+#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.\r
+#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.\r
+#define UC3_C2_XPLAINED 14 //!< ATUC3A3 UC3-C2 Xplained board.\r
+#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.\r
+#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.\r
+#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.\r
+#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.\r
+#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.\r
+#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board\r
+#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board\r
+#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board\r
+#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.\r
+#define STK600_RCUC3B 25 //!< STK600 RCUC3B board.\r
+#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.\r
+#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.\r
+#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.\r
+#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.\r
+#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards\r
+#define RZ600 31 //!< AT32UC3A RZ600 MCU board\r
+#define SAM3S_EK 32 //!< SAM3S-EK board.\r
+#define SAM3U_EK 33 //!< SAM3U-EK board.\r
+#define SAM3X_EK 34 //!< SAM3X-EK board.\r
+#define SAM3N_EK 35 //!< SAM3N-EK board.\r
+#define SAM3S_EK2 36 //!< SAM3S-EK2 board.\r
+#define SAM4S_EK 37 //!< SAM4S-EK board.\r
+#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.\r
+#define SAM4S_XPLAINED 39 //!< SAM4S Xplained board. \r
+#define ATXMEGA128A1_QT600 40 //!< QT600 ATXMEGA128A1 MCU board.\r
+#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices\r
+#define AVR_SIMULATOR_UC3 98 //!< AVR SIMULATOR for AVR UC3 device family.\r
+#define USER_BOARD 99 //!< User-reserved board (if any).\r
+#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board\r
+#define MC300 2 //!< AT32UC3 MC300 board\r
+#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1\r
+#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2\r
+#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board\r
+#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board\r
+#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"\r
+#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF230B 9 //!< AT86RF231 RF board in RZ600\r
+#define RZ600_AT86RF212 10 //!< AT86RF231 RF board in RZ600\r
+#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard\r
+\r
+#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+ #include "evk1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+ #include "evk1101/evk1101.h"\r
+#elif BOARD == UC3C_EK\r
+ #include "uc3c_ek/uc3c_ek.h"\r
+#elif BOARD == EVK1104\r
+ #include "evk1104/evk1104.h"\r
+#elif BOARD == EVK1105\r
+ #include "evk1105/evk1105.h"\r
+#elif BOARD == STK600_RCUC3L0\r
+ #include "stk600/rcuc3l0/stk600_rcuc3l0.h"\r
+#elif BOARD == UC3L_EK\r
+ #include "uc3l_ek/uc3l_ek.h"\r
+#elif BOARD == STK600_RCUC3L4\r
+ #include "stk600/rcuc3l4/stk600_rcuc3l4.h"\r
+#elif BOARD == XPLAIN\r
+ #include "xplain/xplain.h"\r
+#elif BOARD == STK600_RC044X\r
+ #include "stk600/rc044x/stk600_rc044x.h"\r
+#elif BOARD == STK600_RC064X\r
+ #include "stk600/rc064x/stk600_rc064x.h"\r
+#elif BOARD == STK600_RC100X\r
+ #include "stk600/rc100x/stk600_rc100x.h"\r
+#elif BOARD == UC3_A3_XPLAINED\r
+ #include "uc3_a3_xplained/uc3_a3_xplained.h"\r
+#elif BOARD == UC3_C2_XPLAINED\r
+ #include "uc3_c2_xplained/uc3_c2_xplained.h"\r
+ #elif BOARD == UC3_L0_XPLAINED\r
+ #include "uc3_l0_xplained/uc3_l0_xplained.h"\r
+#elif BOARD == STK600_RCUC3B\r
+ #include "stk600/rcuc3b/stk600_rcuc3b.h"\r
+#elif BOARD == STK600_RCUC3D\r
+ #include "stk600/rcuc3d/stk600_rcuc3d.h"\r
+#elif BOARD == STK600_RCUC3C0\r
+ #include "stk600/rcuc3c0/stk600_rcuc3c0.h"\r
+#elif BOARD == XMEGA_B1_XPLAINED\r
+ #include "xmega_b1_xplained/xmega_b1_xplained.h"\r
+#elif BOARD == STK600_RC064X_LCDX\r
+ #include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"\r
+#elif BOARD == STK600_RC100X_LCDX\r
+ #include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"\r
+#elif BOARD == XMEGA_A1_XPLAINED\r
+ #include "xmega_a1_xplained/xmega_a1_xplained.h"\r
+#elif BOARD == UC3_L0_XPLAINED_BC\r
+ #include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"\r
+#elif BOARD == SAM3S_EK\r
+ #include "sam3s_ek/sam3s_ek.h"\r
+ #include "system_sam3s.h"\r
+#elif BOARD == SAM3S_EK2\r
+ #include "sam3s_ek2/sam3s_ek2.h"\r
+ #include "system_sam3sd8.h"\r
+#elif BOARD == SAM3U_EK\r
+ #include "sam3u_ek/sam3u_ek.h"\r
+ #include "system_sam3u.h"\r
+#elif BOARD == SAM3X_EK\r
+ #include "sam3x_ek/sam3x_ek.h"\r
+ #include "system_sam3x.h"\r
+#elif BOARD == SAM3N_EK\r
+ #include "sam3n_ek/sam3n_ek.h"\r
+ #include "system_sam3n.h" \r
+#elif BOARD == SAM4S_EK\r
+ #include "sam4s_ek/sam4s_ek.h"\r
+ #include "system_sam4s.h"\r
+#elif BOARD == SAM4S_XPLAINED\r
+ #include "sam4s_xplained/sam4s_xplained.h"\r
+ #include "system_sam4s.h" \r
+#elif BOARD == MEGA1284P_XPLAINED_BC\r
+ #include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"\r
+#elif BOARD == UC3_L0_QT600\r
+ #include "uc3_l0_qt600/uc3_l0_qt600.h"\r
+#elif BOARD == XMEGA_A3BU_XPLAINED\r
+ #include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"\r
+#elif BOARD == UC3B_BOARD_CONTROLLER\r
+ #include "uc3b_board_controller/uc3b_board_controller.h"\r
+#elif BOARD == RZ600\r
+ #include "rz600/rz600.h"\r
+#elif BOARD == STK600_RCUC3A0\r
+ #include "stk600/rcuc3a0/stk600_rcuc3a0.h"\r
+#elif BOARD == ATXMEGA128A1_QT600\r
+ #include "atxmega128a1_qt600/atxmega128a1_qt600.h"\r
+#elif BOARD == SIMULATOR_XMEGA_A1\r
+ #include "simulator/xmega_a1/simulator_xmega_a1.h"\r
+#elif BOARD == AVR_SIMULATOR_UC3\r
+ #include "avr_simulator_uc3/avr_simulator_uc3.h"\r
+#elif BOARD == USER_BOARD\r
+ // User-reserved area: #include the header file of your board here (if any).\r
+ #include "user_board.h"\r
+#elif BOARD == DUMMY_BOARD\r
+ #include "dummy/dummy_board.h"\r
+#else\r
+ #error No known AVR board defined\r
+#endif\r
+\r
+#if (defined EXT_BOARD)\r
+ #if EXT_BOARD == MC300\r
+ #include "mc300/mc300.h"\r
+ #elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \\r
+ (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)\r
+ #include "sensors_xplained/sensors_xplained.h"\r
+ #elif EXT_BOARD == RZ600_AT86RF231\r
+ #include "at86rf231/at86rf231.h"\r
+ #elif EXT_BOARD == RZ600_AT86RF230B\r
+ #include "at86rf230b/at86rf230b.h"\r
+ #elif EXT_BOARD == RZ600_AT86RF212\r
+ #include "at86rf212/at86rf212.h"\r
+ #elif EXT_BOARD == USER_EXT_BOARD\r
+ // User-reserved area: #include the header file of your extension board here\r
+ // (if any).\r
+ #endif\r
+#endif\r
+\r
+\r
+#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+\r
+#endif // #ifdef __AVR32_ABI_COMPILER__\r
+#else\r
+/*! \brief This function initializes the board target resources\r
+ *\r
+ * This function should be called to ensure proper initialization of the target\r
+ * board hardware connected to the part.\r
+ */\r
+extern void board_init(void);\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _BOARD_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Common GPIO API.\r
+ *\r
+ * Copyright (c) 2010 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef _GPIO_H_\r
+#define _GPIO_H_\r
+\r
+#include <parts.h>\r
+\r
+#if ( SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S )\r
+# include "sam_ioport/sam_gpio.h"\r
+#elif XMEGA\r
+# include "xmega_ioport/xmega_gpio.h"\r
+#else\r
+# error Unsupported chip type\r
+#endif\r
+\r
+\r
+/**\r
+ * \defgroup gpio_group General Purpose Input/Output\r
+ *\r
+ * This is the common API for GPIO. Additional features are available\r
+ * in the documentation of the specific modules.\r
+ *\r
+ * \section io_group_platform Platform Dependencies\r
+ *\r
+ * The following functions are available on all platforms, but there may\r
+ * be variations in the function signature (i.e. parameters) and\r
+ * behaviour. These functions are typically called by platform-specific\r
+ * parts of drivers, and applications that aren't intended to be\r
+ * portable:\r
+ * - gpio_pin_is_low()\r
+ * - gpio_pin_is_high()\r
+ * - gpio_set_pin_high()\r
+ * - gpio_set_pin_group_high()\r
+ * - gpio_set_pin_low()\r
+ * - gpio_set_pin_group_low()\r
+ * - gpio_toggle_pin()\r
+ * - gpio_toggle_pin_group()\r
+ * - gpio_configure_pin()\r
+ * - gpio_configure_group()\r
+ */\r
+\r
+#endif // _GPIO_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief GPIO service for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SAM_GPIO_H_INCLUDED\r
+#define SAM_GPIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+#include "pio.h"\r
+\r
+#define gpio_pin_is_low(io_id) \\r
+ (pio_get_pin_value(io_id) ? 0 : 1)\r
+\r
+#define gpio_pin_is_high(io_id) \\r
+ (pio_get_pin_value(io_id) ? 1 : 0)\r
+\r
+#define gpio_set_pin_high(io_id) \\r
+ pio_set_pin_high(io_id)\r
+\r
+#define gpio_set_pin_low(io_id) \\r
+ pio_set_pin_low(io_id)\r
+\r
+#define gpio_toggle_pin(io_id) \\r
+ pio_toggle_pin(io_id)\r
+\r
+#define gpio_configure_pin(io_id,io_flags) \\r
+ pio_configure_pin(io_id,io_flags)\r
+\r
+#define gpio_configure_group(port_id,port_mask,io_flags) \\r
+ pio_configure_pin_group(port_id,port_mask,io_flags)\r
+\r
+#define gpio_set_pin_group_high(port_id,mask) \\r
+ pio_set_pin_group_high(port_id,mask)\r
+\r
+#define gpio_set_pin_group_low(port_id,mask) \\r
+ pio_set_pin_group_low(port_id,mask)\r
+\r
+#define gpio_toggle_pin_group(port_id,mask) \\r
+ pio_toggle_pin_group(port_id,mask)\r
+\r
+#endif /* SAM_GPIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for 8- and 32-bit AVR\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+#ifndef UTILS_INTERRUPT_H\r
+#define UTILS_INTERRUPT_H\r
+\r
+#include <parts.h>\r
+\r
+#if XMEGA || MEGA\r
+# include "interrupt/interrupt_avr8.h"\r
+#elif UC3\r
+# include "interrupt/interrupt_avr32.h"\r
+#elif SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S\r
+# include "interrupt/interrupt_sam_nvic.h"\r
+#else\r
+# error Unsupported device.\r
+#endif\r
+\r
+/**\r
+ * \defgroup interrupt_group Global interrupt management\r
+ *\r
+ * This is a driver for global enabling and disabling of interrupts.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#if defined(__DOXYGEN__)\r
+/**\r
+ * \def CONFIG_INTERRUPT_FORCE_INTC\r
+ * \brief Force usage of the ASF INTC driver\r
+ *\r
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.\r
+ * This is useful to ensure compatibilty accross compilers and shall be used only when required\r
+ * by the application needs.\r
+ */\r
+# define CONFIG_INTERRUPT_FORCE_INTC\r
+#endif\r
+\r
+//! \name Global interrupt flags\r
+//@{\r
+/**\r
+ * \typedef irqflags_t\r
+ * \brief Type used for holding state of interrupt flag\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_enable\r
+ * \brief Enable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_disable\r
+ * \brief Disable interrupts globally\r
+ */\r
+\r
+/**\r
+ * \fn irqflags_t cpu_irq_save(void)\r
+ * \brief Get and clear the global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_restore.\r
+ *\r
+ * \return Current state of interrupt flags.\r
+ *\r
+ * \note This function leaves interrupts disabled.\r
+ */\r
+\r
+/**\r
+ * \fn void cpu_irq_restore(irqflags_t flags)\r
+ * \brief Restore global interrupt flags\r
+ *\r
+ * Use in conjunction with \ref cpu_irq_save.\r
+ *\r
+ * \param flags State to set interrupt flag to.\r
+ */\r
+\r
+/**\r
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+ * \brief Check if interrupts are globally enabled in supplied flags\r
+ *\r
+ * \param flags Currents state of interrupt flags.\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+\r
+/**\r
+ * \def cpu_irq_is_enabled\r
+ * \brief Check if interrupts are globally enabled\r
+ *\r
+ * \return True if interrupts are enabled.\r
+ */\r
+//@}\r
+\r
+//! @}\r
+\r
+/**\r
+ * \ingroup interrupt_group\r
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions\r
+ */\r
+\r
+#endif /* UTILS_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "interrupt_sam_nvic.h"\r
+\r
+//! Global NVIC interrupt enable status (by default it's enabled)\r
+bool g_interrupt_enabled = true;\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Global interrupt management for SAM3 and SAM4 (NVIC based)\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_INTERRUPT_INTERRUPT_H\r
+#define UTILS_INTERRUPT_INTERRUPT_H\r
+\r
+#include <compiler.h>\r
+#include <parts.h>\r
+\r
+/**\r
+ * \weakgroup interrupt_group\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Interrupt Service Routine definition\r
+ *\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \brief Define service routine\r
+ *\r
+ * \note For NVIC devices the interrupt service routines are predefined to\r
+ * add to vector table in binary generation, so there is no service\r
+ * register at run time. The routine collections are in exceptions.h.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * ISR(foo_irq_handler)\r
+ * {\r
+ * // Function definition\r
+ * ...\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \param func Name for the function.\r
+ */\r
+# define ISR(func) \\r
+ void func (void)\r
+\r
+/**\r
+ * \brief Initialize interrupt vectors\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to initialize them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * This must be called prior to \ref irq_register_handler.\r
+ */\r
+# define irq_initialize_vectors() \\r
+ do { \\r
+ } while(0)\r
+\r
+/**\r
+ * \brief Register handler for interrupt\r
+ *\r
+ * For NVIC the interrupt vectors are put in vector table. So nothing\r
+ * to do to register them, except defined the vector function with\r
+ * right name.\r
+ *\r
+ * Usage:\r
+ * \code\r
+ * irq_initialize_vectors();\r
+ * irq_register_handler(foo_irq_handler);\r
+ * \endcode\r
+ *\r
+ * \note The function \a func must be defined with the \ref ISR macro.\r
+ * \note The functions prototypes can be found in the device exception header\r
+ * files (exceptions.h).\r
+ */\r
+# define irq_register_handler(...) \\r
+ do { \\r
+ } while(0)\r
+\r
+//@}\r
+\r
+# define cpu_irq_enable() \\r
+ do { \\r
+ g_interrupt_enabled = true; \\r
+ __DMB(); \\r
+ __enable_irq(); \\r
+ } while (0)\r
+# define cpu_irq_disable() \\r
+ do { \\r
+ __disable_irq(); \\r
+ __DMB(); \\r
+ g_interrupt_enabled = false; \\r
+ } while (0)\r
+\r
+typedef uint32_t irqflags_t;\r
+extern bool g_interrupt_enabled;\r
+\r
+static inline irqflags_t cpu_irq_save(void)\r
+{\r
+ irqflags_t flags = g_interrupt_enabled;\r
+ cpu_irq_disable();\r
+ return flags;\r
+}\r
+\r
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)\r
+{\r
+ return (flags);\r
+}\r
+\r
+static inline void cpu_irq_restore(irqflags_t flags)\r
+{\r
+ if (cpu_irq_is_enabled_flags(flags))\r
+ cpu_irq_enable();\r
+}\r
+\r
+#define cpu_irq_is_enabled() g_interrupt_enabled\r
+\r
+/**\r
+ * \weakgroup interrupt_deprecated_group\r
+ * @{\r
+ */\r
+\r
+#define Enable_global_interrupt() cpu_irq_enable()\r
+#define Disable_global_interrupt() cpu_irq_disable()\r
+#define Is_global_interrupt_enabled() cpu_irq_is_enabled()\r
+\r
+//@}\r
+\r
+//@}\r
+\r
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4S-EK board init.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "compiler.h"\r
+#include "board.h"\r
+#include "conf_board.h"\r
+#include "gpio.h"\r
+\r
+void board_init(void)\r
+{\r
+#ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT \r
+ /* Disable the watchdog */\r
+ WDT->WDT_MR = WDT_MR_WDDIS;\r
+#endif\r
+\r
+ /* Configure LED pins */\r
+ gpio_configure_pin(LED0_GPIO, LED0_FLAGS);\r
+ gpio_configure_pin(LED1_GPIO, LED1_FLAGS);\r
+ \r
+ /* Configure Push Button pins */\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS);\r
+ gpio_configure_pin(GPIO_PUSH_BUTTON_2, GPIO_PUSH_BUTTON_2_FLAGS);\r
+ \r
+#ifdef CONF_BOARD_UART_CONSOLE\r
+ /* Configure UART pins */\r
+ gpio_configure_group(PINS_UART_PIO, PINS_UART, PINS_UART_FLAGS);\r
+#endif\r
+\r
+ /* Configure ADC example pins */\r
+#ifdef CONF_BOARD_ADC\r
+ /* TC TIOA configuration */\r
+ gpio_configure_pin(PIN_TC0_TIOA0,PIN_TC0_TIOA0_FLAGS);\r
+\r
+ /* ADC Trigger configuration */\r
+ gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG);\r
+\r
+ /* PWMH0 configuration */\r
+ gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED0\r
+ /* Configure PWM LED0 pin */\r
+ gpio_configure_pin(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED1\r
+ /* Configure PWM LED1 pin */\r
+ gpio_configure_pin(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_PWM_LED2\r
+ /* Configure PWM LED2 pin */\r
+ gpio_configure_pin(PIN_PWM_LED2_GPIO, PIN_PWM_LED2_FLAGS);\r
+#endif\r
+\r
+ /* Configure SPI pins */\r
+#ifdef CONF_BOARD_SPI\r
+ gpio_configure_pin(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ gpio_configure_pin(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+ \r
+ /**\r
+ * For NPCS 1, 2, and 3, different PINs can be used to access the same NPCS line.\r
+ * Depending on the application requirements, the default PIN may not be available. \r
+ * Hence a different PIN should be selected using the CONF_BOARD_SPI_NPCS_GPIO and \r
+ * CONF_BOARD_SPI_NPCS_FLAGS macros.\r
+ */\r
+ \r
+ #ifdef CONF_BOARD_SPI_NPCS0\r
+ gpio_configure_pin(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS1\r
+ #if defined(CONF_BOARD_SPI_NPCS1_GPIO) && defined(CONF_BOARD_SPI_NPCS1_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS1_GPIO, CONF_BOARD_SPI_NPCS1_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS1_PA31_GPIO, SPI_NPCS1_PA31_FLAGS);\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS2\r
+ #if defined(CONF_BOARD_SPI_NPCS2_GPIO) && defined(CONF_BOARD_SPI_NPCS2_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS2_GPIO, CONF_BOARD_SPI_NPCS2_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS2_PA30_GPIO, SPI_NPCS2_PA30_FLAGS);\r
+ #endif\r
+ #endif\r
+\r
+ #ifdef CONF_BOARD_SPI_NPCS3\r
+ #if defined(CONF_BOARD_SPI_NPCS3_GPIO) && defined(CONF_BOARD_SPI_NPCS3_FLAGS)\r
+ gpio_configure_pin(CONF_BOARD_SPI_NPCS3_GPIO, CONF_BOARD_SPI_NPCS3_FLAGS);\r
+ #else\r
+ gpio_configure_pin(SPI_NPCS3_PA22_GPIO, SPI_NPCS3_PA22_FLAGS);\r
+ #endif\r
+ #endif\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RXD\r
+ /* Configure USART RXD pin */\r
+ gpio_configure_pin(PIN_USART1_RXD_IDX, PIN_USART1_RXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_TXD\r
+ /* Configure USART TXD pin */\r
+ gpio_configure_pin(PIN_USART1_TXD_IDX, PIN_USART1_TXD_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_CTS\r
+ /* Configure USART CTS pin */\r
+ gpio_configure_pin(PIN_USART1_CTS_IDX, PIN_USART1_CTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_RTS\r
+ /* Configure USART RTS pin */\r
+ gpio_configure_pin(PIN_USART1_RTS_IDX, PIN_USART1_RTS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_USART_SCK\r
+ /* Configure USART synchronous communication SCK pin */\r
+ gpio_configure_pin(PIN_USART1_SCK_IDX, PIN_USART1_SCK_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3312_EN\r
+ /* Configure ADM33312 enable pin */\r
+ gpio_configure_pin(PIN_USART1_EN_IDX, PIN_USART1_EN_FLAGS);\r
+ gpio_set_pin_low(PIN_USART1_EN_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_TFDU4300_SD\r
+ /* Configure IrDA transceiver shutdown pin */\r
+ gpio_configure_pin(PIN_IRDA_SD_IDX, PIN_IRDA_SD_FLAGS);\r
+ gpio_set_pin_low(PIN_IRDA_SD_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADM3485_RE\r
+ /* Configure RS485 transceiver RE pin */\r
+ gpio_configure_pin(PIN_RE_IDX, PIN_RE_FLAGS);\r
+ gpio_set_pin_low(PIN_RE_IDX);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ILI9325\r
+ /* Configure LCD EBI pins */\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D0, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D1, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D2, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D3, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D4, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D5, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D6, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_DATA_BUS_D7, PIN_EBI_DATA_BUS_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NRD, PIN_EBI_NRD_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NWE, PIN_EBI_NWE_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_NCS1, PIN_EBI_NCS1_FLAGS);\r
+ gpio_configure_pin(PIN_EBI_LCD_RS, PIN_EBI_LCD_RS_FLAGS);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_AAT3155\r
+ /* Configure Backlight control pin */\r
+ gpio_configure_pin(BOARD_BACKLIGHT, BOARD_BACKLIGHT_FLAG);\r
+#endif\r
+\r
+#ifdef CONF_BOARD_ADS7843\r
+ /* Configure Touchscreen SPI pins */\r
+ gpio_configure_pin(PIN_TSC_IRQ_IDX,PIN_TSC_IRQ_FLAG);\r
+ gpio_configure_pin(SPI_MISO_GPIO, SPI_MISO_FLAGS);\r
+ gpio_configure_pin(SPI_MOSI_GPIO, SPI_MOSI_FLAGS);\r
+ gpio_configure_pin(SPI_SPCK_GPIO, SPI_SPCK_FLAGS);\r
+ gpio_configure_pin(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);\r
+ gpio_configure_pin(PIN_TSC_BUSY_IDX, PIN_TSC_BUSY_FLAG);\r
+#endif\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief SAM4S-EK Board Definition.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_EK_H_\r
+#define _SAM4S_EK_H_\r
+\r
+#include "compiler.h"\r
+#include "system_sam4s.h"\r
+#include "exceptions.h"\r
+\r
+/*\r
+#define BOARD_REV_A\r
+*/\r
+#define BOARD_REV_B\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_opfreq "SAM4S-EK - Operating frequencies"\r
+ * This page lists several definition related to the board operating frequency\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_FREQ_*\r
+ * - \ref BOARD_MCK\r
+ */\r
+\r
+/** Board oscillator settings */\r
+#define BOARD_FREQ_SLCK_XTAL (32768U)\r
+#define BOARD_FREQ_SLCK_BYPASS (32768U)\r
+#define BOARD_FREQ_MAINCK_XTAL (12000000U)\r
+#define BOARD_FREQ_MAINCK_BYPASS (12000000U)\r
+\r
+/** Master clock frequency */\r
+#define BOARD_MCK CHIP_FREQ_CPU_MAX\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_board_info "SAM4S-EK - Board informations"\r
+ * This page lists several definition related to the board description.\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_NAME\r
+ */\r
+\r
+/** Name of the board */\r
+#define BOARD_NAME "SAM4S-EK"\r
+/** Board definition */\r
+#define sam4sek\r
+/** Family definition (already defined) */\r
+#define sam4s\r
+/** Core definition */\r
+#define cortexm3\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_piodef "SAM4S-EK - PIO definitions"\r
+ * This pages lists all the pio definitions. The constants\r
+ * are named using the following convention: PIN_* for a constant which defines\r
+ * a single Pin instance (but may include several PIOs sharing the same\r
+ * controller), and PINS_* for a list of Pin instances.\r
+ *\r
+ * ADC\r
+ * - \ref PIN_ADC0_AD0\r
+ * - \ref PIN_ADC0_AD1\r
+ * - \ref PIN_ADC0_AD2\r
+ * - \ref PIN_ADC0_AD3\r
+ * - \ref PIN_ADC0_AD4\r
+ * - \ref PIN_ADC0_AD5\r
+ * - \ref PIN_ADC0_AD6\r
+ * - \ref PIN_ADC0_AD7\r
+ * - \ref PINS_ADC\r
+ *\r
+ * UART\r
+ * - \ref PINS_UART\r
+ *\r
+ * EBI\r
+ * - \ref PIN_EBI_DATA_BUS\r
+ * - \ref PIN_EBI_NRD\r
+ * - \ref PIN_EBI_NWE\r
+ * - \ref PIN_EBI_NCS0\r
+ * - \ref PIN_EBI_PSRAM_ADDR_BUS\r
+ * - \ref PIN_EBI_PSRAM_NBS\r
+ * - \ref PIN_EBI_A1\r
+ * - \ref PIN_EBI_NCS1\r
+ * - \ref PIN_EBI_LCD_RS\r
+ *\r
+ * LEDs\r
+ * - \ref PIN_LED_0\r
+ * - \ref PIN_LED_1\r
+ * - \ref PIN_LED_2\r
+ * - \ref PINS_LEDS\r
+ *\r
+ * MCI\r
+ * - \ref PINS_MCI\r
+ *\r
+ * Push buttons\r
+ * - \ref PIN_PUSHBUTTON_1\r
+ * - \ref PIN_PUSHBUTTON_2\r
+ * - \ref PINS_PUSHBUTTONS\r
+ * - \ref PUSHBUTTON_BP1\r
+ * - \ref PUSHBUTTON_BP2\r
+ *\r
+ * PWMC\r
+ * - \ref PIN_PWMC_PWMH0\r
+ * - \ref PIN_PWMC_PWML0\r
+ * - \ref PIN_PWMC_PWMH1\r
+ * - \ref PIN_PWMC_PWML1\r
+ * - \ref PIN_PWMC_PWMH2\r
+ * - \ref PIN_PWMC_PWML2\r
+ * - \ref PIN_PWMC_PWMH3\r
+ * - \ref PIN_PWMC_PWML3\r
+ * - \ref PIN_PWM_LED0\r
+ * - \ref PIN_PWM_LED1\r
+ * - \ref PIN_PWM_LED2\r
+ * - \ref CHANNEL_PWM_LED0\r
+ * - \ref CHANNEL_PWM_LED1\r
+ * - \ref CHANNEL_PWM_LED2\r
+ *\r
+ * SPI\r
+ * - \ref PIN_SPI_MISO\r
+ * - \ref PIN_SPI_MOSI\r
+ * - \ref PIN_SPI_SPCK\r
+ * - \ref PINS_SPI\r
+ * - \ref PIN_SPI_NPCS0_PA11\r
+ *\r
+ * SSC\r
+ * - \ref PIN_SSC_TD\r
+ * - \ref PIN_SSC_TK\r
+ * - \ref PIN_SSC_TF\r
+ * - \ref PINS_SSC_CODEC\r
+ *\r
+ * PCK0\r
+ * - \ref PIN_PCK0\r
+ *\r
+ * PIO PARALLEL CAPTURE\r
+ * - \ref PIN_PIODCEN1\r
+ * - \ref PIN_PIODCEN2\r
+ *\r
+ * TWI\r
+ * - \ref TWI_V3XX\r
+ * - \ref PIN_TWI_TWD0\r
+ * - \ref PIN_TWI_TWCK0\r
+ * - \ref PINS_TWI0\r
+ * - \ref PIN_TWI_TWD1\r
+ * - \ref PIN_TWI_TWCK1\r
+ * - \ref PINS_TWI1\r
+ *\r
+ * USART0\r
+ * - \ref PIN_USART0_RXD\r
+ * - \ref PIN_USART0_TXD\r
+ * - \ref PIN_USART0_CTS\r
+ * - \ref PIN_USART0_RTS\r
+ * - \ref PIN_USART0_SCK\r
+ *\r
+ * USB\r
+ * - \ref PIN_USB_VBUS\r
+ *\r
+ * NandFlash\r
+ * - \ref PIN_EBI_NANDOE\r
+ * - \ref PIN_EBI_NANDWE\r
+ * - \ref PIN_EBI_NANDCLE\r
+ * - \ref PIN_EBI_NANDALE\r
+ * - \ref PIN_EBI_NANDIO\r
+ * - \ref BOARD_NF_CE_PIN\r
+ * - \ref BOARD_NF_RB_PIN\r
+ * - \ref PINS_NANDFLASH\r
+ *\r
+ * QTouch\r
+ * PIO definitions for Slider\r
+ * \ref SLIDER_IOMASK_SNS\r
+ * \ref SLIDER_IOMASK_SNSK\r
+ * \ref PINS_SLIDER_SNS\r
+ * \ref PINS_SLIDER_SNSK\r
+ *\r
+ * PIO definitions for keys\r
+ * \ref KEY_IOMASK_SNS\r
+ * \ref KEY_IOMASK_SNSK\r
+ * \ref PINS_KEY_SNS\r
+ * \ref PINS_KEY_SNSK\r
+ *\r
+ * PIOS for QTouch\r
+ * \ref PINS_QTOUCH\r
+ */\r
+\r
+/** ADC_AD0 pin definition. */\r
+#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD1 pin definition. */\r
+#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD2 pin definition. */\r
+#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD3 pin definition. */\r
+#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD4 pin definition. */\r
+#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD5 pin definition. */\r
+#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD6 pin definition. */\r
+#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+/** ADC_AD7 pin definition. */\r
+#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/** Pins ADC */\r
+#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7\r
+#define PINS_ADC_TRIG PIO_PA8_IDX\r
+#define PINS_ADC_TRIG_FLAG (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** Startup time max, return from Idle mode (in µs) */\r
+#define ADC_STARTUP_TIME_MAX 15\r
+/** Track and hold Acquisition Time min (in ns) */\r
+#define ADC_TRACK_HOLD_TIME_MIN 1200\r
+/** ADC clock frequence */\r
+#define BOARD_ADC_FREQ (6000000)\r
+\r
+/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */\r
+#define PINS_UART (PIO_PA9A_URXD0 | PIO_PA10A_UTXD0)\r
+#define PINS_UART_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+#define PINS_UART_MASK PIO_PA9A_URXD0|PIO_PA10A_UTXD0\r
+#define PINS_UART_PIO PIOA\r
+#define PINS_UART_ID ID_PIOA\r
+#define PINS_UART_TYPE PIO_PERIPH_A\r
+#define PINS_UART_ATTR PIO_DEFAULT\r
+\r
+/** EBI Data Bus pins */\r
+#define PIN_EBI_DATA_BUS_D0 PIO_PC0_IDX\r
+#define PIN_EBI_DATA_BUS_D1 PIO_PC1_IDX\r
+#define PIN_EBI_DATA_BUS_D2 PIO_PC2_IDX\r
+#define PIN_EBI_DATA_BUS_D3 PIO_PC3_IDX\r
+#define PIN_EBI_DATA_BUS_D4 PIO_PC4_IDX\r
+#define PIN_EBI_DATA_BUS_D5 PIO_PC5_IDX\r
+#define PIN_EBI_DATA_BUS_D6 PIO_PC6_IDX\r
+#define PIN_EBI_DATA_BUS_D7 PIO_PC7_IDX\r
+#define PIN_EBI_DATA_BUS_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_DATA_BUS_MASK 0xFF\r
+#define PIN_EBI_DATA_BUS_PIO PIOC\r
+#define PIN_EBI_DATA_BUS_ID ID_PIOC\r
+#define PIN_EBI_DATA_BUS_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_DATA_BUS_ATTR PIO_PULLUP\r
+/** EBI NRD pin */\r
+#define PIN_EBI_NRD PIO_PC11_IDX\r
+#define PIN_EBI_NRD_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NRD_MASK 1 << 11\r
+#define PIN_EBI_NRD_PIO PIOC\r
+#define PIN_EBI_NRD_ID ID_PIOC\r
+#define PIN_EBI_NRD_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NRD_ATTR PIO_PULLUP\r
+/** EBI NWE pin */\r
+#define PIN_EBI_NWE PIO_PC8_IDX\r
+#define PIN_EBI_NWE_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NWE_MASK 1 << 8\r
+#define PIN_EBI_NWE_PIO PIOC\r
+#define PIN_EBI_NWE_ID ID_PIOC\r
+#define PIN_EBI_NWE_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NWE_ATTR PIO_PULLUP\r
+/** EBI NCS0 pin */\r
+#define PIN_EBI_NCS0 PIO_PC14_IDX\r
+#define PIN_EBI_NCS0_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NCS0_MASK 1 << 14\r
+#define PIN_EBI_NCS0_PIO PIOC\r
+#define PIN_EBI_NCS0_ID ID_PIOC\r
+#define PIN_EBI_NCS0_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NCS0_ATTR PIO_PULLUP\r
+/** EBI address bus pins */\r
+#define PIN_EBI_ADDR_BUS_A0 PIO_PC18_IDX\r
+#define PIN_EBI_ADDR_BUS_A1 PIO_PC19_IDX\r
+#define PIN_EBI_ADDR_BUS_A2 PIO_PC20_IDX\r
+#define PIN_EBI_ADDR_BUS_A3 PIO_PC21_IDX\r
+#define PIN_EBI_ADDR_BUS_A4 PIO_PC22_IDX\r
+#define PIN_EBI_ADDR_BUS_A5 PIO_PC23_IDX\r
+#define PIN_EBI_ADDR_BUS_A6 PIO_PC24_IDX\r
+#define PIN_EBI_ADDR_BUS_A7 PIO_PC25_IDX\r
+#define PIN_EBI_ADDR_BUS_A8 PIO_PC26_IDX\r
+#define PIN_EBI_ADDR_BUS_A9 PIO_PC27_IDX\r
+#define PIN_EBI_ADDR_BUS_A10 PIO_PC28_IDX\r
+#define PIN_EBI_ADDR_BUS_A11 PIO_PC29_IDX\r
+#define PIN_EBI_ADDR_BUS_A12 PIO_PC30_IDX\r
+#define PIN_EBI_ADDR_BUS_A13 PIO_PC31_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG1 PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_ADDR_BUS_A14 PIO_PA18_IDX\r
+#define PIN_EBI_ADDR_BUS_A15 PIO_PA19_IDX\r
+#define PIN_EBI_ADDR_BUS_A16 PIO_PA20_IDX\r
+#define PIN_EBI_ADDR_BUS_A17 PIO_PA0_IDX\r
+#define PIN_EBI_ADDR_BUS_A18 PIO_PA1_IDX\r
+#define PIN_EBI_ADDR_BUS_A19 PIO_PA23_IDX\r
+#define PIN_EBI_ADDR_BUS_A20 PIO_PA24_IDX\r
+#define PIN_EBI_ADDR_BUS_FLAG2 PIO_PERIPH_C | PIO_PULLUP\r
+/** EBI pin for LCD CS */\r
+#define PIN_EBI_NCS1 PIO_PC15_IDX\r
+#define PIN_EBI_NCS1_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_NCS1_MASK 1 << 15\r
+#define PIN_EBI_NCS1_PIO PIOC\r
+#define PIN_EBI_NCS1_ID ID_PIOC\r
+#define PIN_EBI_NCS1_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_NCS1_ATTR PIO_PULLUP\r
+/** EBI pin for LCD RS */\r
+#define PIN_EBI_LCD_RS PIO_PC19_IDX\r
+#define PIN_EBI_LCD_RS_FLAGS PIO_PERIPH_A | PIO_PULLUP\r
+#define PIN_EBI_LCD_RS_MASK 1 << 19\r
+#define PIN_EBI_LCD_RS_PIO PIOC\r
+#define PIN_EBI_LCD_RS_ID ID_PIOC\r
+#define PIN_EBI_LCD_RS_TYPE PIO_PERIPH_A\r
+#define PIN_EBI_LCD_RS_ATTR PIO_PULLUP\r
+\r
+#define LED_BLUE 0\r
+#define LED_GREEN 1\r
+#define LED_RED 2\r
+\r
+#ifdef BOARD_REV_A\r
+/** LED #0 pin definition (BLUE). */\r
+#define PIN_LED_0 {PIO_PC20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK PIO_PC20\r
+#define PIN_LED_0_PIO PIOC\r
+#define PIN_LED_0_ID ID_PIOC\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+#define LED0_GPIO (PIO_PC20_IDX)\r
+#define LED0_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/** LED #1 pin definition (GREEN). */\r
+#define PIN_LED_1 {PIO_PC21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+\r
+#define LED1_GPIO (PIO_PC21_IDX)\r
+#define LED1_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/** LED #2 pin definition (RED). */\r
+#define PIN_LED_2 {PIO_PC22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+/** LED #0 pin definition (BLUE). */\r
+#define PIN_LED_0 {PIO_PA19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_0_MASK PIO_PA19\r
+#define PIN_LED_0_PIO PIOA\r
+#define PIN_LED_0_ID ID_PIOA\r
+#define PIN_LED_0_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_0_ATTR PIO_DEFAULT\r
+\r
+#define LED0_GPIO (PIO_PA19_IDX)\r
+#define LED0_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/** LED #1 pin definition (GREEN). */\r
+#define PIN_LED_1 {PIO_PA20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}\r
+#define PIN_LED_1_MASK PIO_PA20\r
+#define PIN_LED_1_PIO PIOA\r
+#define PIN_LED_1_ID ID_PIOA\r
+#define PIN_LED_1_TYPE PIO_OUTPUT_1\r
+#define PIN_LED_1_ATTR PIO_DEFAULT\r
+\r
+#define LED1_GPIO (PIO_PA20_IDX)\r
+#define LED1_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/** LED #2 pin definition (RED). */\r
+#define PIN_LED_2 {PIO_PC20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+\r
+#endif\r
+\r
+/** List of all LEDs definitions. */\r
+#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2\r
+\r
+/** MCI pins definition. */\r
+#define PINS_MCI {0x3fUL << 26, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_PULLUP}\r
+/** MCI pin Card Detect. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_MCI_CD {PIO_PA15, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_MCI_CD {PIO_PA6, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */\r
+#define GPIO_PUSH_BUTTON_1 (PIO_PB3_IDX)\r
+#define GPIO_PUSH_BUTTON_1_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_1 {PIO_PB3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE}\r
+#define PIN_PUSHBUTTON_1_MASK PIO_PB3\r
+#define PIN_PUSHBUTTON_1_PIO PIOB\r
+#define PIN_PUSHBUTTON_1_ID ID_PIOB\r
+#define PIN_PUSHBUTTON_1_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_1_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_RISE_EDGE\r
+\r
+/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */\r
+#define GPIO_PUSH_BUTTON_2 (PIO_PC12_IDX)\r
+#define GPIO_PUSH_BUTTON_2_FLAGS (PIO_INPUT | PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE)\r
+\r
+#define PIN_PUSHBUTTON_2 {PIO_PC12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE}\r
+#define PIN_PUSHBUTTON_2_MASK PIO_PC12\r
+#define PIN_PUSHBUTTON_2_PIO PIOC\r
+#define PIN_PUSHBUTTON_2_ID ID_PIOC\r
+#define PIN_PUSHBUTTON_2_TYPE PIO_INPUT\r
+#define PIN_PUSHBUTTON_2_ATTR PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE\r
+\r
+/** List of all push button definitions. */\r
+#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2\r
+\r
+/** Push button #1 index. */\r
+#define PUSHBUTTON_BP1 0\r
+/** Push button #2 index. */\r
+#define PUSHBUTTON_BP2 1\r
+\r
+#define PIN_TC0_TIOA0 (PIO_PA0_IDX)\r
+#define PIN_TC0_TIOA0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1 (PIO_PA15_IDX)\r
+#define PIN_TC0_TIOA1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA1_PIO PIOA\r
+#define PIN_TC0_TIOA1_MASK PIO_PA15\r
+#define PIN_TC0_TIOA1_ID ID_PIOA\r
+#define PIN_TC0_TIOA1_TYPE PIO_PERIPH_B\r
+#define PIN_TC0_TIOA1_ATTR PIO_DEFAULT\r
+\r
+#define PIN_TC0_TIOA2 (PIO_PA26_IDX)\r
+#define PIN_TC0_TIOA2_FLAGS (PIO_INPUT | PIO_DEFAULT)\r
+\r
+#define PIN_TC0_TIOA2_PIO PIOA\r
+#define PIN_TC0_TIOA2_MASK PIO_PA26\r
+#define PIN_TC0_TIOA2_ID ID_PIOA\r
+#define PIN_TC0_TIOA2_TYPE PIO_INPUT\r
+#define PIN_TC0_TIOA2_ATTR PIO_DEFAULT\r
+\r
+/** PWMC PWM0 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH0 {PIO_PC18B_PWMH0, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_PWMC_PWMH0_TRIG PIO_PC18_IDX\r
+#define PIN_PWMC_PWMH0_TRIG_FLAG PIO_PERIPH_B | PIO_DEFAULT\r
+/** PWMC PWM0 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML0 {PIO_PA19B_PWML0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM1 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH1 {PIO_PC19B_PWMH1, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM1 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML1 {PIO_PA20B_PWML1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM2 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH2 {PIO_PC20B_PWMH2, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM2 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML2 {PIO_PA16C_PWML2, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** PWMC PWM3 pin definition: Output High. */\r
+#define PIN_PWMC_PWMH3 {PIO_PC21B_PWMH3, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}\r
+/** PWMC PWM3 pin definition: Output Low. */\r
+#define PIN_PWMC_PWML3 {PIO_PA15C_PWML3, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT}\r
+/** PWM pins definition for LED0 */\r
+#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0\r
+/** PWM pins definition for LED1 */\r
+#define PIN_PWM_LED1 PIN_PWMC_PWMH1, PIN_PWMC_PWML1\r
+/** PWM pins definition for LED2 */\r
+#define PIN_PWM_LED2 PIN_PWMC_PWMH2, PIN_PWMC_PWML2\r
+/** PWM channel for LED0 */\r
+#define CHANNEL_PWM_LED0 0\r
+/** PWM channel for LED1 */\r
+#define CHANNEL_PWM_LED1 1\r
+/** PWM channel for LED2 */\r
+#define CHANNEL_PWM_LED2 2\r
+\r
+/** PWM LED0 pin definitions. */\r
+#define PIN_PWM_LED0_GPIO PIO_PA19_IDX\r
+#define PIN_PWM_LED0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** PWM LED1 pin definitions. */\r
+#define PIN_PWM_LED1_GPIO PIO_PA20_IDX\r
+#define PIN_PWM_LED1_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** PWM LED2 pin definitions. */\r
+#define PIN_PWM_LED2_GPIO PIO_PC20_IDX\r
+#define PIN_PWM_LED2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** SPI MISO pin definition. */\r
+#define PIN_SPI_MISO {PIO_PA12A_MISO, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI MOSI pin definition. */\r
+#define PIN_SPI_MOSI {PIO_PA13A_MOSI, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI SPCK pin definition. */\r
+#define PIN_SPI_SPCK {PIO_PA14A_SPCK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SPI chip select pin definition. */\r
+#define PIN_SPI_NPCS0_PA11 {PIO_PA11A_NPCS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** List of SPI pin definitions (MISO, MOSI & SPCK). */\r
+#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK\r
+/** SPI MISO pin definition. */\r
+#define SPI_MISO_GPIO (PIO_PA12_IDX)\r
+#define SPI_MISO_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI MOSI pin definition. */\r
+#define SPI_MOSI_GPIO (PIO_PA13_IDX)\r
+#define SPI_MOSI_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI SPCK pin definition. */\r
+#define SPI_SPCK_GPIO (PIO_PA14_IDX)\r
+#define SPI_SPCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** SPI chip select 0 pin definition. (Only one configuration is possible) */\r
+#define SPI_NPCS0_GPIO (PIO_PA11_IDX)\r
+#define SPI_NPCS0_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** SPI chip select 1 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS1_PA9_GPIO (PIO_PA9_IDX)\r
+#define SPI_NPCS1_PA9_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS1_PA31_GPIO (PIO_PA31_IDX)\r
+#define SPI_NPCS1_PA31_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI_NPCS1_PB14_GPIO (PIO_PB14_IDX)\r
+#define SPI_NPCS1_PB14_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define SPI_NPCS1_PC4_GPIO (PIO_PC4_IDX)\r
+#define SPI_NPCS1_PC4_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** SPI chip select 2 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS2_PA10_GPIO (PIO_PA10_IDX)\r
+#define SPI_NPCS2_PA10_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS2_PA30_GPIO (PIO_PA30_IDX)\r
+#define SPI_NPCS2_PA30_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS2_PB2_GPIO (PIO_PB2_IDX)\r
+#define SPI_NPCS2_PB2_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+/** SPI chip select 3 pin definition. (multiple configurations are possible) */\r
+#define SPI_NPCS3_PA3_GPIO (PIO_PA3_IDX)\r
+#define SPI_NPCS3_PA3_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS3_PA5_GPIO (PIO_PA5_IDX)\r
+#define SPI_NPCS3_PA5_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+#define SPI_NPCS3_PA22_GPIO (PIO_PA22_IDX)\r
+#define SPI_NPCS3_PA22_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+/** SSC pin Transmitter Data (TD) */\r
+#define PIN_SSC_TD {PIO_PA17A_TD, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pin Transmitter Clock (TK) */\r
+#define PIN_SSC_TK {PIO_PA16A_TK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pin Transmitter FrameSync (TF) */\r
+#define PIN_SSC_TF {PIO_PA15A_TF, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** SSC pins definition for codec. */\r
+#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF\r
+\r
+/** PCK0 */\r
+#define PIN_PCK0 (PIO_PA6_IDX)\r
+#define PIN_PCK0_FLAGS (PIO_PERIPH_B | PIO_DEFAULT)\r
+\r
+#define PIN_PCK_0_MASK PIO_PA6\r
+#define PIN_PCK_0_PIO PIOA\r
+#define PIN_PCK_0_ID ID_PIOA\r
+#define PIN_PCK_0_TYPE PIO_PERIPH_B\r
+#define PIN_PCK_0_ATTR PIO_DEFAULT\r
+#define PIN_PCK1 {PIO_PA17B_PCK1,PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}\r
+#define PIN_PCK_1_MASK PIO_PA17\r
+#define PIN_PCK_1_PIO PIOA\r
+#define PIN_PCK_1_ID ID_PIOA\r
+#define PIN_PCK_1_TYPE PIO_PERIPH_B\r
+#define PIN_PCK_1_ATTR PIO_DEFAULT\r
+\r
+/** PIO PARALLEL CAPTURE */\r
+/** Parallel Capture Mode Data Enable1 */\r
+#define PIN_PIODCEN1 PIO_PA15\r
+/** Parallel Capture Mode Data Enable2 */\r
+#define PIN_PIODCEN2 PIO_PA16\r
+\r
+/** TWI ver 3.xx */\r
+#define TWI_V3XX\r
+/** TWI0 data pin */\r
+#define PIN_TWI_TWD0 {PIO_PA3A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 clock pin */\r
+#define PIN_TWI_TWCK0 {PIO_PA4A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI0 pins */\r
+#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0\r
+/** TWI1 data pin */\r
+#define PIN_TWI_TWD1 {PIO_PB4A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI1 clock pin */\r
+#define PIN_TWI_TWCK1 {PIO_PB5A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}\r
+/** TWI1 pins */\r
+#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1\r
+\r
+/** USART0 pin RX */\r
+#define PIN_USART0_RXD {PIO_PA5A_RXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RXD_IDX (PIO_PA5_IDX)\r
+#define PIN_USART0_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin TX */\r
+#define PIN_USART0_TXD {PIO_PA6A_TXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_TXD_IDX (PIO_PA6_IDX)\r
+#define PIN_USART0_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin CTS */\r
+#define PIN_USART0_CTS {PIO_PA8A_CTS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_CTS_IDX (PIO_PA8_IDX)\r
+#define PIN_USART0_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin RTS */\r
+#define PIN_USART0_RTS {PIO_PA7A_RTS0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_RTS_IDX (PIO_PA7_IDX)\r
+#define PIN_USART0_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART0 pin SCK */\r
+#define PIN_USART0_SCK {PIO_PA2B_SCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART0_SCK_IDX (PIO_PA2_IDX)\r
+#define PIN_USART0_SCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** USART1 pin RX */\r
+#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RXD_IDX (PIO_PA21_IDX)\r
+#define PIN_USART1_RXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin TX */\r
+#define PIN_USART1_TXD {PIO_PA22A_TXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_TXD_IDX (PIO_PA22_IDX)\r
+#define PIN_USART1_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin CTS */\r
+#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_CTS_IDX (PIO_PA25_IDX)\r
+#define PIN_USART1_CTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin RTS */\r
+#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_RTS_IDX (PIO_PA24_IDX)\r
+#define PIN_USART1_RTS_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+/** USART1 pin ENABLE */\r
+#define PIN_USART1_EN {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_USART1_EN_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_EN_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+/** USART1 pin SCK */\r
+#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}\r
+#define PIN_USART1_SCK_IDX (PIO_PA23_IDX)\r
+#define PIN_USART1_SCK_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+\r
+/** USB VBus monitoring pin definition. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_USB_VBUS {PIO_PC23, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_USB_VBUS {PIO_PC21, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+#endif\r
+\r
+/** NandFlash pins definition: OE. */\r
+#define PIN_EBI_NANDOE {PIO_PC9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: WE. */\r
+#define PIN_EBI_NANDWE {PIO_PC10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: CLE. */\r
+#define PIN_EBI_NANDCLE {PIO_PC17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: ALE. */\r
+#define PIN_EBI_NANDALE {PIO_PC16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+/** NandFlash pins definition: DATA. */\r
+#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP}\r
+\r
+/** Nandflash chip enable pin definition. */\r
+#define BOARD_NF_CE_PIN {PIO_PC14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}\r
+/** Nandflash ready/busy pin definition. */\r
+#define BOARD_NF_RB_PIN {PIO_PC18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP}\r
+\r
+/** Nandflash controller peripheral pins definition. */\r
+#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \\r
+ PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE\r
+\r
+/* PIO definitions for Slider */\r
+#define SLIDER_IOMASK_SNS (uint32_t)(PIO_PA0 | PIO_PA2 | PIO_PA4)\r
+#define SLIDER_IOMASK_SNSK (uint32_t)(PIO_PA1 | PIO_PA3 | PIO_PA5)\r
+#define PINS_SLIDER_SNS {SLIDER_IOMASK_SNS, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_SLIDER_SNSK {SLIDER_IOMASK_SNSK, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/* PIO definitions for keys */\r
+#define KEY_IOMASK_SNS (uint32_t)(PIO_PC22 | PIO_PC24 | PIO_PC26 | PIO_PC28 | PIO_PC30)\r
+#define KEY_IOMASK_SNSK (uint32_t)(PIO_PC23 | PIO_PC25 | PIO_PC27 | PIO_PC29 | PIO_PC31)\r
+#define PINS_KEY_SNS {KEY_IOMASK_SNS, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+#define PINS_KEY_SNSK {KEY_IOMASK_SNSK, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/* PIOS for QTouch */\r
+#define PINS_QTOUCH PINS_SLIDER_SNS, PINS_SLIDER_SNSK, PINS_KEY_SNS, PINS_KEY_SNSK\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_usb "SAM4S-EK - USB device"\r
+ *\r
+ * \section Definitions\r
+ * - \ref BOARD_USB_BMATTRIBUTES\r
+ * - \ref CHIP_USB_UDP\r
+ * - \ref CHIP_USB_PULLUP_INTERNAL\r
+ * - \ref CHIP_USB_NUMENDPOINTS\r
+ * - \ref CHIP_USB_ENDPOINTS_MAXPACKETSIZE\r
+ * - \ref CHIP_USB_ENDPOINTS_BANKS\r
+ */\r
+\r
+/** USB attributes configuration descriptor (bus or self powered, remote wakeup) */\r
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP\r
+\r
+/** Indicates chip has an UDP Full Speed. */\r
+#define CHIP_USB_UDP\r
+\r
+/** Indicates chip has an internal pull-up. */\r
+#define CHIP_USB_PULLUP_INTERNAL\r
+\r
+/** Number of USB endpoints */\r
+#define CHIP_USB_NUMENDPOINTS 8\r
+\r
+/** Endpoints max paxcket size */\r
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \\r
+ ((i == 0) ? 64 : \\r
+ ((i == 1) ? 64 : \\r
+ ((i == 2) ? 64 : \\r
+ ((i == 3) ? 64 : \\r
+ ((i == 4) ? 512 : \\r
+ ((i == 5) ? 512 : \\r
+ ((i == 6) ? 64 : \\r
+ ((i == 7) ? 64 : 0 ))))))))\r
+\r
+/** Endpoints Number of Bank */\r
+#define CHIP_USB_ENDPOINTS_BANKS(i) \\r
+ ((i == 0) ? 1 : \\r
+ ((i == 1) ? 2 : \\r
+ ((i == 2) ? 2 : \\r
+ ((i == 3) ? 1 : \\r
+ ((i == 4) ? 2 : \\r
+ ((i == 5) ? 2 : \\r
+ ((i == 6) ? 2 : \\r
+ ((i == 7) ? 2 : 0 ))))))))\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_extcomp "SAM4S-EK - External components"\r
+ * This page lists the definitions related to external on-board components\r
+ * located in the board.h file for the SAM4S-EK.\r
+ *\r
+ * SD Card\r
+ * - \ref BOARD_SD_PINS\r
+ * - \ref BOARD_SD_PIN_CD\r
+ *\r
+ * LCD\r
+ * - \ref BOARD_LCD_ILI9325\r
+ * - \ref BOARD_LCD_PINS\r
+ * - \ref BOARD_BACKLIGHT_PIN\r
+ * - \ref BOARD_LCD_BASE\r
+ * - \ref BOARD_LCD_RS\r
+ * - \ref BOARD_LCD_WIDTH\r
+ * - \ref BOARD_LCD_HEIGHT\r
+ *\r
+ * TouchScreen\r
+ * - \ref BOARD_TSC_ADS7843\r
+ * - \ref PIN_TCS_IRQ\r
+ * - \ref PIN_TCS_BUSY\r
+ * - \ref BOARD_TSC_SPI_BASE\r
+ * - \ref BOARD_TSC_SPI_ID\r
+ * - \ref BOARD_TSC_SPI_PINS\r
+ * - \ref BOARD_TSC_NPCS\r
+ * - \ref BOARD_TSC_NPCS_PIN\r
+ *\r
+ * SmartCard\r
+ * - \ref SMARTCARD_CONNECT_PIN\r
+ * - \ref PIN_ISO7816_RSTMC\r
+ * - \ref PINS_ISO7816\r
+ */\r
+\r
+/** MCI pins that shall be configured to access the SD card. */\r
+#define BOARD_SD_PINS PINS_MCI\r
+/** MCI Card Detect pin. */\r
+#define BOARD_SD_PIN_CD PIN_MCI_CD\r
+\r
+/** Indicates board has an ILI9325 external component to manage LCD. */\r
+#define BOARD_LCD_ILI9325\r
+\r
+/** Backlight pin definition. */\r
+#define BOARD_BACKLIGHT PIO_PC13_IDX\r
+#define BOARD_BACKLIGHT_FLAG PIO_OUTPUT_0 | PIO_DEFAULT\r
+#define BOARD_BACKLIGHT_PIN {PIO_PC13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT}\r
+#define PIN_BOARD_BACKLIGHT_MASK PIO_PC13\r
+#define PIN_BOARD_BACKLIGHT_PIO PIOC\r
+#define PIN_BOARD_BACKLIGHT_ID ID_PIOC\r
+#define PIN_BOARD_BACKLIGHT_TYPE PIO_OUTPUT_0\r
+#define PIN_BOARD_BACKLIGHT_ATTR PIO_PULLUP\r
+/** Define ILI9325 base address. */\r
+#define BOARD_LCD_BASE 0x61000000\r
+/** Define ILI9325 register select signal. */\r
+#define BOARD_LCD_RS (1 << 1)\r
+/** Display width in pixels. */\r
+#define BOARD_LCD_WIDTH 240\r
+/** Display height in pixels. */\r
+#define BOARD_LCD_HEIGHT 320\r
+\r
+/** Indicates board has an ADS7843 external component to manage Touch Screen */\r
+#define BOARD_TSC_ADS7843\r
+\r
+/** Touchscreen controller IRQ pin definition. */\r
+#ifdef BOARD_REV_A\r
+#define PIN_TSC_IRQ_IDX PIO_PA4_IDX\r
+#define PIN_TSC_IRQ_FLAG PIO_INPUT | PIO_PULLUP \r
+#define PIN_TSC_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_IRQ_MASK PIO_PA4\r
+#define PIN_TSC_IRQ_PIO PIOA\r
+#define PIN_TSC_IRQ_ID ID_PIOA\r
+#define PIN_TSC_IRQ_TYPE PIO_INPUT\r
+#define PIN_TSC_IRQ_ATTR PIO_PULLUP\r
+#define PIN_TSC_IRQ_WUP_ID (1 << 3)\r
+/** Touchscreen controller Busy pin definition. */\r
+#define PIN_TSC_BUSY_IDX PIO_PA5_IDX\r
+#define PIN_TSC_BUSY_FLAG PIO_INPUT | PIO_PULLUP \r
+#define PIN_TSC_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_BUSY_MASK PIO_PA5\r
+#define PIN_TSC_BUSY_PIO PIOA\r
+#define PIN_TSC_BUSY_ID ID_PIOA\r
+#define PIN_TSC_BUSY_TYPE PIO_INPUT\r
+#define PIN_TSC_BUSY_ATTR PIO_PULLUP\r
+#endif\r
+\r
+#ifdef BOARD_REV_B\r
+#define PIN_TSC_IRQ_IDX PIO_PA16_IDX\r
+#define PIN_TSC_IRQ_FLAG PIO_INPUT | PIO_PULLUP \r
+#define PIN_TSC_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_IRQ_MASK PIO_PA16\r
+#define PIN_TSC_IRQ_PIO PIOA\r
+#define PIN_TSC_IRQ_ID ID_PIOA\r
+#define PIN_TSC_IRQ_TYPE PIO_INPUT\r
+#define PIN_TSC_IRQ_ATTR PIO_PULLUP\r
+#define PIN_TSC_IRQ_WUP_ID (1 << 15)\r
+/** Touchscreen controller Busy pin definition. */\r
+#define PIN_TSC_BUSY_IDX PIO_PA17_IDX\r
+#define PIN_TSC_BUSY_FLAG PIO_INPUT | PIO_PULLUP\r
+#define PIN_TSC_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP}\r
+#define PIN_TSC_BUSY_MASK PIO_PA17\r
+#define PIN_TSC_BUSY_PIO PIOA\r
+#define PIN_TSC_BUSY_ID ID_PIOA\r
+#define PIN_TSC_BUSY_TYPE PIO_INPUT\r
+#define PIN_TSC_BUSY_ATTR PIO_PULLUP\r
+#endif\r
+\r
+/** Base address of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_BASE SPI\r
+/** Identifier of SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_ID ID_SPI\r
+/** Pins of the SPI peripheral connected to the touchscreen controller. */\r
+#define BOARD_TSC_SPI_PINS PINS_SPI\r
+/** Chip select connected to the touchscreen controller. */\r
+#define BOARD_TSC_NPCS 0\r
+/** Chip select pin connected to the touchscreen controller. */\r
+#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11\r
+\r
+/// Smartcard detection pin\r
+//#define SMARTCARD_CONNECT_PIN {1 << 13, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT}\r
+\r
+/// PIN used for reset the smartcard\r
+#define PIN_ISO7816_RSTMC {1 << 11, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}\r
+/// Pins used for connect the smartcard\r
+#define PINS_ISO7816 PIN_USART1_TXD, PIN_USART1_SCK, PIN_ISO7816_RSTMC\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_mem "SAM4S-EK - Memories"\r
+ * This page lists definitions related to internal & external on-board memories.\r
+ *\r
+ * \section NandFlash\r
+ * - \ref BOARD_NF_COMMAND_ADDR\r
+ * - \ref BOARD_NF_ADDRESS_ADDR\r
+ * - \ref BOARD_NF_DATA_ADDR\r
+ *\r
+ * \section NorFlash\r
+ * - \ref BOARD_NORFLASH_ADDR\r
+ * - \ref BOARD_NORFLASH_DFT_BUS_SIZE\r
+ */\r
+\r
+/** Address for transferring command bytes to the nandflash. */\r
+#define BOARD_NF_COMMAND_ADDR 0x60400000\r
+/** Address for transferring address bytes to the nandflash. */\r
+#define BOARD_NF_ADDRESS_ADDR 0x60200000\r
+/** Address for transferring data bytes to the nandflash. */\r
+#define BOARD_NF_DATA_ADDR 0x60000000\r
+\r
+/** Address for transferring command bytes to the norflash. */\r
+#define BOARD_NORFLASH_ADDR 0x63000000\r
+/** Default NOR bus size after power up reset */\r
+#define BOARD_NORFLASH_DFT_BUS_SIZE 8\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/**\r
+ * \page sam4s_ek_chipdef "SAM4S-EK - Individual chip definition"\r
+ * This page lists the definitions related to different chip's definition\r
+ * located in the board.h file for the SAM4S-EK.\r
+ *\r
+ * \section USART\r
+ * - \ref BOARD_PIN_USART_RXD\r
+ * - \ref BOARD_PIN_USART_TXD\r
+ * - \ref BOARD_PIN_USART_CTS\r
+ * - \ref BOARD_PIN_USART_RTS\r
+ * - \ref BOARD_PIN_USART_EN\r
+ * - \ref BOARD_USART_BASE\r
+ * - \ref BOARD_ID_USART\r
+ */\r
+\r
+/** Rtc */\r
+#define BOARD_RTC_ID ID_RTC\r
+\r
+/** TWI ID for EEPROM application to use */\r
+#define BOARD_ID_TWI_EEPROM ID_TWI1\r
+/** TWI ID for SLAVE application to use */\r
+#define BOARD_ID_TWI_SLAVE ID_TWI1\r
+/** TWI Base for TWI EEPROM application to use */\r
+#define BOARD_BASE_TWI_EEPROM TWI1\r
+/** TWI Base for TWI SLAVE application to use */\r
+#define BOARD_BASE_TWI_SLAVE TWI1\r
+/** TWI pins for EEPROM application to use */\r
+#define BOARD_PINS_TWI_EEPROM PINS_TWI1\r
+/** TWI pins for TWI SLAVE application to use */\r
+#define BOARD_PINS_TWI_SLAVE PINS_TWI1\r
+\r
+/** USART RX pin for application */\r
+#define BOARD_PIN_USART_RXD PIN_USART1_RXD\r
+/** USART TX pin for application */\r
+#define BOARD_PIN_USART_TXD PIN_USART1_TXD\r
+/** USART CTS pin for application */\r
+#define BOARD_PIN_USART_CTS PIN_USART1_CTS\r
+/** USART RTS pin for application */\r
+#define BOARD_PIN_USART_RTS PIN_USART1_RTS\r
+/** USART ENABLE pin for application */\r
+#define BOARD_PIN_USART_EN PIN_USART1_EN\r
+/** USART Base for application */\r
+#define BOARD_USART_BASE USART1\r
+/** USART ID for application */\r
+#define BOARD_ID_USART ID_USART1\r
+\r
+#define CONSOLE_UART UART0\r
+#define CONSOLE_UART_ID ID_UART0\r
+\r
+/* RE pin. */\r
+#define PIN_RE_IDX PIN_USART1_CTS_IDX\r
+#define PIN_RE_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT)\r
+\r
+/* IRDA SD pin. */\r
+#define PIN_IRDA_SD_IDX PIN_USART1_CTS_IDX\r
+#define PIN_IRDA_SD_FLAGS (PIO_OUTPUT_1 | PIO_DEFAULT)\r
+\r
+/* TXD pin configuration. */\r
+#define PIN_USART_TXD_IDX PIN_USART1_TXD_IDX\r
+#define PIN_USART_TXD_FLAGS (PIO_PERIPH_A | PIO_DEFAULT)\r
+#define PIN_USART_TXD_IO_FLAGS (PIO_OUTPUT_0 | PIO_DEFAULT) \r
+\r
+#endif // _SAM4S_EK_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "pio.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/**\r
+ * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * The Parallel Input/Output Controller (PIO) manages up to 32 fully\r
+ * programmable input/output lines. Each I/O line may be dedicated as a\r
+ * general-purpose I/O or be assigned to a function of an embedded peripheral.\r
+ * This assures effective optimization of the pins of a product.\r
+ *\r
+ * @{\r
+ */\r
+\r
+#ifndef FREQ_SLOW_CLOCK_EXT\r
+/* External slow clock frequency (hz) */\r
+#define FREQ_SLOW_CLOCK_EXT 32768\r
+#endif\r
+\r
+/**\r
+ * \brief Configure PIO internal pull-up.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be\r
+ * configured.\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ /* Enable the pull-up(s) if necessary */\r
+ if (ul_pull_up_enable) {\r
+ p_pio->PIO_PUER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PUDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure Glitch or Debouncing filter for the specified input(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_cut_off Cuts off frequency for debouncing filter.\r
+ */\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off)\r
+{\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+#elif (SAM3XA || SAM3U)\r
+ /* Set Debouncing, 0 bit field no effect */\r
+ p_pio->PIO_DIFSR = ul_mask;\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* The debouncing filter can filter a pulse of less than 1/2 Period of a\r
+ programmable Divided Slow Clock:\r
+ Tdiv_slclk = ((DIV+1)*2).Tslow_clock */\r
+ p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT /\r
+ (2 * (ul_cut_off))) - 1);\r
+}\r
+\r
+/**\r
+ * \brief Set a high output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Set a low output level on all the PIOs defined in ul_mask.\r
+ * This has no immediate effects on PIOs that are not output, but the PIO\r
+ * controller will save the value if they are changed to outputs.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin instance currently have\r
+ * a high level; otherwise returns 0. This method returns the actual value that\r
+ * is being read on the pin. To return the supposed output value of a pin, use\r
+ * pio_get_output_data_status() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ *\r
+ * \retval 1 at least one PIO currently has a high level.\r
+ * \retval 0 all PIOs have a low level.\r
+ */\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_reg;\r
+\r
+ if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) {\r
+ ul_reg = p_pio->PIO_ODSR;\r
+ } else {\r
+ ul_reg = p_pio->PIO_PDSR;\r
+ }\r
+\r
+ if ((ul_reg & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure IO of a PIO controller as being controlled by a specific\r
+ * peripheral.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask)\r
+{\r
+ uint32_t ul_sr;\r
+\r
+ /* Disable interrupts on the pin(s) */\r
+ p_pio->PIO_IDR = ul_mask;\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_C:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_D:\r
+ ul_sr = p_pio->PIO_ABCDSR[0];\r
+ p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr);\r
+\r
+ ul_sr = p_pio->PIO_ABCDSR[1];\r
+ p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR &= (~ul_mask & ul_sr);\r
+ break;\r
+\r
+ case PIO_PERIPH_B:\r
+ ul_sr = p_pio->PIO_ABSR;\r
+ p_pio->PIO_ABSR = (ul_mask | ul_sr);\r
+ break;\r
+\r
+ // other types are invalid in this function\r
+ case PIO_INPUT:\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ case PIO_NOT_A_PIN:\r
+ return;\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ // Remove the pins from under the control of PIO\r
+ p_pio->PIO_PDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) or a PIO controller as inputs.\r
+ * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can\r
+ * be enabled.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure as input(s).\r
+ * \param ul_attribute PIO attribute(s).\r
+ */\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP);\r
+\r
+ /* Enable Input Filter if necessary */\r
+ if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) {\r
+ p_pio->PIO_IFER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_IFDR = ul_mask;\r
+ }\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_IFSCDR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_IFSCER = ul_mask;\r
+ }\r
+ }\r
+#elif (SAM3XA|| SAM3U)\r
+ /* Enable de-glitch or de-bounce if necessary */\r
+ if (ul_attribute & PIO_DEGLITCH) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ } else {\r
+ if (ul_attribute & PIO_DEBOUNCE) {\r
+ p_pio->PIO_SCIFSR = ul_mask;\r
+ }\r
+ }\r
+#else\r
+#error "Unsupported device"\r
+#endif\r
+\r
+ /* Configure pin as input */\r
+ p_pio->PIO_ODR = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Configure one or more pin(s) of a PIO controller as outputs, with\r
+ * the given default value. Optionally, the multi-drive feature can be enabled\r
+ * on the pin(s).\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask indicating which pin(s) to configure.\r
+ * \param ul_default_level Default level on the pin(s).\r
+ * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as\r
+ * open-drain.\r
+ * \param ul_pull_up_enable Indicates if the pin shall have its pull-up\r
+ * activated.\r
+ */\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable)\r
+{\r
+ pio_disable_interrupt(p_pio, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, ul_pull_up_enable);\r
+\r
+ /* Enable multi-drive if necessary */\r
+ if (ul_multidrive_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+\r
+ /* Set default value */\r
+ if (ul_default_level) {\r
+ p_pio->PIO_SODR = ul_mask;\r
+ } else {\r
+ p_pio->PIO_CODR = ul_mask;\r
+ }\r
+\r
+ /* Configure pin(s) as output(s) */\r
+ p_pio->PIO_OER = ul_mask;\r
+ p_pio->PIO_PER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_type PIO type.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_attribute Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_type) {\r
+ case PIO_PERIPH_A:\r
+ case PIO_PERIPH_B:\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_PERIPH_C:\r
+ case PIO_PERIPH_D:\r
+# endif\r
+ pio_set_peripheral(p_pio, ul_type, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP));\r
+ break;\r
+\r
+ case PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_attribute);\r
+ break;\r
+\r
+ case PIO_OUTPUT_0:\r
+ case PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1),\r
+ (ul_attribute & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_attribute & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Return 1 if one or more PIOs of the given Pin are configured to\r
+ * output a high level (even if they are not output).\r
+ * To get the actual value of the pin, use PIO_Get() instead.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s).\r
+ *\r
+ * \retval 1 At least one PIO is configured to output a high level.\r
+ * \retval 0 All PIOs are configued to output a low level.\r
+ */\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask)\r
+{\r
+ if ((p_pio->PIO_ODSR & ul_mask) == 0) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Configure PIO pin multi-driver.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be\r
+ * configured.\r
+ */\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable)\r
+{\r
+ /* Enable the multi-driver if necessary */\r
+ if (ul_multi_driver_enable) {\r
+ p_pio->PIO_MDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_MDDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Get multi-driver status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The multi-driver mask value.\r
+ */\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_MDSR;\r
+}\r
+\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin internal pull-down.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall\r
+ * be configured.\r
+ */\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable)\r
+{\r
+ /* Enable the pull-down if necessary */\r
+ if (ul_pull_down_enable) {\r
+ p_pio->PIO_PPDER = ul_mask;\r
+ } else {\r
+ p_pio->PIO_PPDDR = ul_mask;\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Enable PIO output write for synchronous data output.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO output write.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_OWDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO output write status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The output write mask value.\r
+ */\r
+uint32_t pio_get_output_write_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_OWSR;\r
+}\r
+\r
+/**\r
+ * \brief Synchronously write on output pins.\r
+ * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are\r
+ * written.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ODSR = ul_mask;\r
+}\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+/**\r
+ * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is\r
+ * active.\r
+ * Disabling the Schmitt Trigger is requested when using the QTouch Library.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_SCHMITT = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Get PIO pin schmitt trigger status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The schmitt trigger mask value.\r
+ */\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_SCHMITT;\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Configure the given interrupt source.\r
+ * Interrupt can be configured to trigger on rising edge, falling edge,\r
+ * high level, low level or simply on level change.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt source bit map.\r
+ * \param ul_attr Interrupt source attributes.\r
+ */\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attr)\r
+{\r
+ /* Configure additional interrupt mode registers. */\r
+ if (ul_attr & PIO_IT_AIME) {\r
+ /* Enable additional interrupt mode. */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ Rising Edge/High level detection event. */\r
+ if (ul_attr & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* If bit field of the selected pin is 1, set as\r
+ edge detection source. */\r
+ if (ul_attr & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode. */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source.\r
+ * The PIO must be configured as an NVIC interrupt source as well.\r
+ * The status register of the corresponding PIO controller is cleared\r
+ * prior to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_ISR;\r
+ p_pio->PIO_IER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source, with no added side effects.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_IDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_ISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_IMR;\r
+}\r
+\r
+/**\r
+ * \brief Set additional interrupt mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ * \param ul_attribute Pin(s) attributes.\r
+ */\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute)\r
+{\r
+ /* Enables additional interrupt mode if needed */\r
+ if (ul_attribute & PIO_IT_AIME) {\r
+ /* Enables additional interrupt mode */\r
+ p_pio->PIO_AIMER = ul_mask;\r
+\r
+ /* Configures the Polarity of the event detection */\r
+ /* (Rising/Falling Edge or High/Low Level) */\r
+ if (ul_attribute & PIO_IT_RE_OR_HL) {\r
+ /* Rising Edge or High Level */\r
+ p_pio->PIO_REHLSR = ul_mask;\r
+ } else {\r
+ /* Falling Edge or Low Level */\r
+ p_pio->PIO_FELLSR = ul_mask;\r
+ }\r
+\r
+ /* Configures the type of event detection (Edge or Level) */\r
+ if (ul_attribute & PIO_IT_EDGE) {\r
+ /* Edge select */\r
+ p_pio->PIO_ESR = ul_mask;\r
+ } else {\r
+ /* Level select */\r
+ p_pio->PIO_LSR = ul_mask;\r
+ }\r
+ } else {\r
+ /* Disable additional interrupt mode */\r
+ p_pio->PIO_AIMDR = ul_mask;\r
+ }\r
+}\r
+\r
+#define PIO_WPMR_WPKEY_VALUE PIO_WPMR_WPKEY(0x50494Fu)\r
+\r
+/**\r
+ * \brief Enable or disable write protect of PIO registers.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_enable 1 to enable, 0 to disable.\r
+ */\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable)\r
+{\r
+ p_pio->PIO_WPMR = PIO_WPMR_WPKEY_VALUE | ul_enable;\r
+}\r
+\r
+/**\r
+ * \brief Read write protect status.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return Return write protect status.\r
+ */\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_WPSR;\r
+}\r
+\r
+#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA)\r
+\r
+/**\r
+ * \brief Return the value of a pin.\r
+ *\r
+ * \param ul_pin The pin number.\r
+ *\r
+ * \return The pin value.\r
+ *\r
+ * \note If pin is output: a pull-up or pull-down could hide the actual value.\r
+ * The function \ref pio_get can be called to get the actual pin output\r
+ * level.\r
+ * \note If pin is input: PIOx must be clocked to sample the signal.\r
+ * See PMC driver.\r
+ */\r
+uint32_t pio_get_pin_value(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 1.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called beforehand.\r
+ */\r
+void pio_set_pin_high(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO pin to 0.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_set_pin_low(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref pio_configure_pin must be called before.\r
+ */\r
+void pio_toggle_pin(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = 1 << (ul_pin & 0x1F);\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = 1 << (ul_pin & 0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param ul_pin Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pins attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F)));\r
+ pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, (1 << (ul_pin & 0x1F)),\r
+ (ul_flags & PIO_TYPE_PIO_OUTPUT_1),\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 1.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Drive a GPIO port to 0.\r
+ *\r
+ * \param p_pio Base address of the PIO port.\r
+ * \param ul_mask Bitmask of one or more pin(s) to toggle.\r
+ */\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Toggle a GPIO group.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ */\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask)\r
+{\r
+ if (p_pio->PIO_ODSR & ul_mask) {\r
+ // Value to be driven on the I/O line: 0.\r
+ p_pio->PIO_CODR = ul_mask;\r
+ } else {\r
+ // Value to be driven on the I/O line: 1.\r
+ p_pio->PIO_SODR = ul_mask;\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Perform complete pin(s) configuration; general attributes and PIO init\r
+ * if necessary.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Bitmask of one or more pin(s) to configure.\r
+ * \param ul_flags Pin(s) attributes.\r
+ *\r
+ * \return Whether the pin(s) have been configured properly.\r
+ */\r
+uint32_t pio_configure_pin_group(Pio *p_pio,\r
+ uint32_t ul_mask, const uint32_t ul_flags)\r
+{\r
+ /* Configure pins */\r
+ switch (ul_flags & PIO_TYPE_Msk) {\r
+ case PIO_TYPE_PIO_PERIPH_A:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_B:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# if (SAM3S || SAM3N || SAM4S)\r
+ case PIO_TYPE_PIO_PERIPH_C:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+ case PIO_TYPE_PIO_PERIPH_D:\r
+ pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask);\r
+ pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP));\r
+ break;\r
+# endif\r
+\r
+ case PIO_TYPE_PIO_INPUT:\r
+ pio_set_input(p_pio, ul_mask, ul_flags);\r
+ break;\r
+\r
+ case PIO_TYPE_PIO_OUTPUT_0:\r
+ case PIO_TYPE_PIO_OUTPUT_1:\r
+ pio_set_output(p_pio, ul_mask,\r
+ (ul_flags & PIO_TYPE_PIO_OUTPUT_1),\r
+ (ul_flags & PIO_OPENDRAIN) ? 1 : 0,\r
+ (ul_flags & PIO_PULLUP) ? 1 : 0);\r
+ break;\r
+\r
+ default:\r
+ return 0;\r
+ }\r
+\r
+ return 1;\r
+}\r
+\r
+/**\r
+ * \brief Enable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_enable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IER = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Disable interrupt for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \note The function \ref gpio_configure_pin must be called before.\r
+ */\r
+void pio_disable_pin_interrupt(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ p_pio->PIO_IDR = 1 << (ul_pin & 0x1F);\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return Pointer to \ref Pio struct for GPIO port.\r
+ */\r
+Pio *pio_get_pin_group(uint32_t ul_pin)\r
+{\r
+ Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5)));\r
+ return p_pio;\r
+}\r
+\r
+/**\r
+ * \brief Return GPIO port peripheral ID for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port peripheral ID.\r
+ */\r
+uint32_t pio_get_pin_group_id(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_id = ID_PIOA + (ul_pin >> 5);\r
+ return ul_id;\r
+}\r
+\r
+\r
+/**\r
+ * \brief Return GPIO port pin mask for a GPIO pin.\r
+ *\r
+ * \param ul_pin The pin index.\r
+ *\r
+ * \return GPIO port pin mask.\r
+ */\r
+uint32_t pio_get_pin_group_mask(uint32_t ul_pin)\r
+{\r
+ uint32_t ul_mask = 1 << (ul_pin & 0x1F);\r
+ return ul_mask;\r
+}\r
+\r
+\r
+\r
+#if (SAM3S || SAM4S)\r
+/**\r
+ * \brief Configure PIO capture mode.\r
+ * \note PIO capture mode will be disabled automatically.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mode Bitmask of one or more modes.\r
+ */\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode)\r
+{\r
+ ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */\r
+ p_pio->PIO_PCMR = ul_mode;\r
+}\r
+\r
+/**\r
+ * \brief Enable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_enable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR |= PIO_PCMR_PCEN;\r
+}\r
+\r
+/**\r
+ * \brief Disable PIO capture mode.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ */\r
+void pio_capture_disable(Pio *p_pio)\r
+{\r
+ p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN);\r
+}\r
+\r
+/**\r
+ * \brief Read from Capture Reception Holding Register.\r
+ * Data presence should be tested before any read attempt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param pul_data Pointer to store the data.\r
+ *\r
+ * \retval 0 Success.\r
+ * \retval 1 I/O Failure, Capture data is not ready.\r
+ */\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data)\r
+{\r
+ /* Check if the data is ready */\r
+ if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) {\r
+ return 1;\r
+ }\r
+\r
+ /* Read data */\r
+ *pul_data = p_pio->PIO_PCRHR;\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Enable the given interrupt source of PIO capture. The status\r
+ * register of the corresponding PIO capture controller is cleared prior\r
+ * to enabling the interrupt.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCISR;\r
+ p_pio->PIO_PCIER = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Disable a given interrupt source of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ * \param ul_mask Interrupt sources bit map.\r
+ */\r
+void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask)\r
+{\r
+ p_pio->PIO_PCIDR = ul_mask;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt status of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt status mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCISR;\r
+}\r
+\r
+/**\r
+ * \brief Read PIO interrupt mask of PIO capture.\r
+ *\r
+ * \param p_pio Pointer to a PIO instance.\r
+ *\r
+ * \return The interrupt mask value.\r
+ */\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio)\r
+{\r
+ return p_pio->PIO_PCIMR;\r
+}\r
+\r
+/**\r
+ * \brief Get PDC registers base address.\r
+ *\r
+ * \param p_pio Pointer to an PIO peripheral.\r
+ *\r
+ * \return PIOA PDC register base address.\r
+ */\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio)\r
+{\r
+ p_pio = p_pio; /* Stop warning */\r
+ return PDC_PIOA;\r
+}\r
+#endif\r
+\r
+//@}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) Controller driver for SAM.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_H_INCLUDED\r
+#define PIO_H_INCLUDED\r
+\r
+#include "compiler.h"\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+/* GPIO Support */\r
+#define PIO_TYPE_Pos 27\r
+/* PIO Type Mask */\r
+#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos)\r
+/* The pin is not a function pin. */\r
+#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral A. */\r
+#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral B. */\r
+#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral C. */\r
+#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos)\r
+/* The pin is controlled by the peripheral D. */\r
+#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos)\r
+/* The pin is an input. */\r
+#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 0. */\r
+#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos)\r
+/* The pin is an output and has a default level of 1. */\r
+#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos)\r
+\r
+typedef enum _pio_type {\r
+ PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN,\r
+ PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A,\r
+ PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B,\r
+#if (SAM3S || SAM3N || SAM4S)\r
+ PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C,\r
+ PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D,\r
+#endif\r
+ PIO_INPUT = PIO_TYPE_PIO_INPUT,\r
+ PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0,\r
+ PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1\r
+} pio_type_t;\r
+\r
+/* Default pin configuration (no attribute). */\r
+#define PIO_DEFAULT (0u << 0)\r
+/* The internal pin pull-up is active. */\r
+#define PIO_PULLUP (1u << 0)\r
+/* The internal glitch filter is active. */\r
+#define PIO_DEGLITCH (1u << 1)\r
+/* The pin is open-drain. */\r
+#define PIO_OPENDRAIN (1u << 2)\r
+\r
+/* The internal debouncing filter is active. */\r
+#define PIO_DEBOUNCE (1u << 3)\r
+\r
+/* Enable additional interrupt modes. */\r
+#define PIO_IT_AIME (1u << 4)\r
+\r
+/* Interrupt High Level/Rising Edge detection is active. */\r
+#define PIO_IT_RE_OR_HL (1u << 5)\r
+/* Interrupt Edge detection is active. */\r
+#define PIO_IT_EDGE (1u << 6)\r
+\r
+/* Low level interrupt is active */\r
+#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME)\r
+/* High level interrupt is active */\r
+#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)\r
+/* Falling edge interrupt is active */\r
+#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME)\r
+/* Rising edge interrupt is active */\r
+#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)\r
+\r
+/*\r
+ * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT,\r
+ * or combine (using bitwise OR '|') any number of the following constants:\r
+ * - PIO_PULLUP\r
+ * - PIO_DEGLITCH\r
+ * - PIO_DEBOUNCE\r
+ * - PIO_OPENDRAIN\r
+ * - PIO_IT_LOW_LEVEL\r
+ * - PIO_IT_HIGH_LEVEL\r
+ * - PIO_IT_FALL_EDGE\r
+ * - PIO_IT_RISE_EDGE\r
+ */\r
+void pio_pull_up(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_up_enable);\r
+void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_cut_off);\r
+void pio_set(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_clear(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask);\r
+void pio_set_input(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_attribute);\r
+void pio_set_output(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_default_level,\r
+ const uint32_t ul_multidrive_enable,\r
+ const uint32_t ul_pull_up_enable);\r
+uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+uint32_t pio_get_output_data_status(const Pio *p_pio,\r
+ const uint32_t ul_mask);\r
+void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_multi_driver_enable);\r
+uint32_t pio_get_multi_driver_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_pull_down(Pio *p_pio, const uint32_t ul_mask,\r
+ const uint32_t ul_pull_down_enable);\r
+#endif\r
+\r
+void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_output_write_status(const Pio *p_pio);\r
+void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask);\r
+\r
+#if (SAM3S || SAM3N || SAM4S)\r
+void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_schmitt_trigger(const Pio *p_pio);\r
+#endif\r
+\r
+void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, const uint32_t ul_attr);\r
+void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+uint32_t pio_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_get_interrupt_mask(const Pio *p_pio);\r
+void pio_set_additional_interrupt_mode(Pio *p_pio,\r
+ const uint32_t ul_mask, const uint32_t ul_attribute);\r
+void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable);\r
+uint32_t pio_get_writeprotect_status(const Pio *p_pio);\r
+\r
+#if (SAM3S || SAM4S)\r
+void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode);\r
+void pio_capture_enable(Pio *p_pio);\r
+void pio_capture_disable(Pio *p_pio);\r
+uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data);\r
+void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask);\r
+void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask);\r
+uint32_t pio_capture_get_interrupt_status(const Pio *p_pio);\r
+uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio);\r
+Pdc *pio_capture_get_pdc_base(const Pio *p_pio);\r
+#endif\r
+\r
+/* GPIO Support */\r
+uint32_t pio_get_pin_value(uint32_t pin);\r
+void pio_set_pin_high(uint32_t pin);\r
+void pio_set_pin_low(uint32_t pin);\r
+void pio_toggle_pin(uint32_t pin);\r
+void pio_enable_pin_interrupt(uint32_t pin);\r
+void pio_disable_pin_interrupt(uint32_t pin);\r
+Pio *pio_get_pin_group(uint32_t pin);\r
+uint32_t pio_get_pin_group_id(uint32_t pin);\r
+uint32_t pio_get_pin_group_mask(uint32_t pin);\r
+uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags);\r
+void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask);\r
+void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask);\r
+void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask);\r
+uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, const uint32_t ul_flags);\r
+\r
+/**\r
+ * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver\r
+ *\r
+ * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver",\r
+ * with step-by-step instructions on how to configure and use the driver for\r
+ * specific use cases.\r
+ *\r
+ * The section described below can be compiled into e.g. the main application\r
+ * loop or any other function that will need to interface with the IO port.\r
+ *\r
+ * \section sam_pio_usecases PIO use cases\r
+ * - \ref sam_pio_quickstart_basic\r
+ * - \ref sam_pio_quickstart_use_case_2\r
+ *\r
+ * \section sam_pio_quickstart_basic Basic usage of the PIO driver\r
+ * This section will present a basic use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_code Example code\r
+ * Set the state of output pin 23 to match input pin 16:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/**\r
+ * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection\r
+ *\r
+ * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1\r
+ * This section will present a more advanced use case for the PIO driver. This use case\r
+ * will configure pin 23 on port A as output and pin 16 as an input with pullup,\r
+ * and then toggle the output pin's value to match that of the input pin using the interrupt\r
+ * controller within the device.\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites\r
+ * - \ref group_pmc "Power Management Controller driver"\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code\r
+ * Add to the application initialization code:\r
+ * \code\r
+ * pmc_enable_periph_clk(ID_PIOA);\r
+ *\r
+ * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE);\r
+ * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP);\r
+ *\r
+ * pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler);\r
+ * pio_enable_interrupt(PIOA, PIO_PA16);\r
+ *\r
+ * NVIC_EnableIRQ(PIOA_IRQn);\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow\r
+ * -# Enable the module clock to the PIOA peripheral:\r
+ * \code pmc_enable_periph_clk(ID_PIOA); \endcode\r
+ * -# Set pin 23 direction on PIOA as output, default low level:\r
+ * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode\r
+ * -# Set pin 16 direction on PIOA as input, with pullup:\r
+ * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode\r
+ * -# Configure the input pin 16 interrupt mode and handler:\r
+ * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode\r
+ * -# Enable the interrupt for the configured input pin:\r
+ * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode\r
+ * -# Enable interrupt handling from the PIOA module:\r
+ * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_code Example code\r
+ * Add the following function to your application:\r
+ * \code\r
+ * void pin_edge_handler(void)\r
+ * {\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * }\r
+ * \endcode\r
+ *\r
+ * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow\r
+ * -# We check the value of the pin:\r
+ * \code\r
+ * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16))\r
+ * \endcode\r
+ * -# Then we set the new output value based on the read pin value:\r
+ * \code\r
+ * pio_clear(PIOA, PIO_PA23);\r
+ * else\r
+ * pio_set(PIOA, PIO_PA23);\r
+ * \endcode\r
+ */\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "pio.h"\r
+#include "pio_handler.h"\r
+\r
+/** \r
+ * Maximum number of interrupt sources that can be defined. This\r
+ * constant can be increased, but the current value is the smallest possible one\r
+ * that will be compatible with all existing projects.\r
+ */\r
+#define MAX_INTERRUPT_SOURCES 7\r
+\r
+/**\r
+ * Describes a PIO interrupt source, including the PIO instance triggering the\r
+ * interrupt and the associated interrupt handler.\r
+ */\r
+struct s_interrupt_source {\r
+ uint32_t id;\r
+ uint32_t mask;\r
+ uint32_t attr;\r
+\r
+ /* Interrupt handler. */\r
+ void (*handler) (const uint32_t, const uint32_t);\r
+};\r
+\r
+\r
+/* List of interrupt sources. */\r
+static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES];\r
+\r
+/* Number of currently defined interrupt sources. */\r
+static uint32_t gs_ul_nb_sources = 0;\r
+\r
+/**\r
+ * \brief Process an interrupt request on the given PIO controller.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO controller ID.\r
+ */\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id)\r
+{\r
+ uint32_t status;\r
+ uint32_t i;\r
+\r
+ /* Read PIO controller status */\r
+ status = pio_get_interrupt_status(p_pio);\r
+ status &= pio_get_interrupt_mask(p_pio);\r
+\r
+ /* Check pending events */\r
+ if (status != 0) {\r
+ /* Find triggering source */\r
+ i = 0;\r
+ while (status != 0) {\r
+ /* Source is configured on the same controller */\r
+ if (gs_interrupt_sources[i].id == ul_id) {\r
+ /* Source has PIOs whose statuses have changed */\r
+ if ((status & gs_interrupt_sources[i].mask) != 0) {\r
+ gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id,\r
+ gs_interrupt_sources[i].mask);\r
+ status &= ~(gs_interrupt_sources[i].mask);\r
+ }\r
+ }\r
+ i++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief Set an interrupt handler for the provided pins.\r
+ * The provided handler will be called with the triggering pin as its parameter \r
+ * as soon as an interrupt is detected. \r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_id PIO ID.\r
+ * \param ul_mask Pins (bit mask) to configure.\r
+ * \param ul_attr Pins attribute to configure.\r
+ * \param p_handler Interrupt handler function pointer.\r
+ *\r
+ * \return 0 if successful, 1 if the maximum number of sources has been defined.\r
+ */\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t))\r
+{\r
+ struct s_interrupt_source *pSource;\r
+\r
+ if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES)\r
+ return 1;\r
+\r
+ /* Define new source */\r
+ pSource = &(gs_interrupt_sources[gs_ul_nb_sources]);\r
+ pSource->id = ul_id;\r
+ pSource->mask = ul_mask;\r
+ pSource->attr = ul_attr;\r
+ pSource->handler = p_handler;\r
+ gs_ul_nb_sources++;\r
+\r
+ /* Configure interrupt mode */\r
+ pio_configure_interrupt(p_pio, ul_mask, ul_attr);\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller A interrupt handler.\r
+ * Redefined PIOA interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOA_Handler(void)\r
+{\r
+ pio_handler_process(PIOA, ID_PIOA);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller B interrupt handler\r
+ * Redefined PIOB interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOB_Handler(void)\r
+{\r
+ pio_handler_process(PIOB, ID_PIOB);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller C interrupt handler.\r
+ * Redefined PIOC interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOC_Handler(void)\r
+{\r
+ pio_handler_process(PIOC, ID_PIOC);\r
+}\r
+\r
+#if SAM3XA\r
+/**\r
+ * \brief Parallel IO Controller D interrupt handler.\r
+ * Redefined PIOD interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOD_Handler(void)\r
+{\r
+ pio_handler_process(PIOD, ID_PIOD);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller E interrupt handler.\r
+ * Redefined PIOE interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOE_Handler(void)\r
+{\r
+ pio_handler_process(PIOE, ID_PIOE);\r
+}\r
+\r
+/**\r
+ * \brief Parallel IO Controller F interrupt handler.\r
+ * Redefined PIOF interrupt handler for NVIC interrupt table.\r
+ */\r
+void PIOF_Handler(void)\r
+{\r
+ pio_handler_process(PIOF, ID_PIOF);\r
+}\r
+#endif\r
+\r
+/**\r
+ * \brief Initialize PIO interrupt management logic.\r
+ *\r
+ * \note The desired priority of PIO must be provided.\r
+ * Calling this function multiple times result in the reset of currently\r
+ * configured interrupt on the provided PIO.\r
+ *\r
+ * \param p_pio PIO controller base address.\r
+ * \param ul_irqn NVIC line number.\r
+ * \param ul_priority PIO controller interrupts priority.\r
+ */\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority)\r
+{\r
+ /* Configure PIO interrupt sources */\r
+ pio_get_interrupt_status(p_pio);\r
+ pio_disable_interrupt(p_pio, 0xFFFFFFFF);\r
+ NVIC_DisableIRQ(ul_irqn);\r
+ NVIC_ClearPendingIRQ(ul_irqn);\r
+ NVIC_SetPriority(ul_irqn, ul_priority);\r
+ NVIC_EnableIRQ(ul_irqn);\r
+}\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Parallel Input/Output (PIO) interrupt handler for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef PIO_HANDLER_H_INCLUDED\r
+#define PIO_HANDLER_H_INCLUDED\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+void pio_handler_process(Pio *p_pio, uint32_t ul_id);\r
+void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority);\r
+uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask,\r
+ uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t));\r
+\r
+/// @cond 0\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/// @endcond\r
+\r
+#endif /* PIO_HANDLER_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_ACC_COMPONENT_\r
+#define _SAM4S_ACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_ACC Analog Comparator Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Acc hardware registers */\r
+typedef struct {\r
+ WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */\r
+ RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[7];\r
+ WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[24];\r
+ RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved3[19];\r
+ RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */\r
+} Acc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */\r
+#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */\r
+/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */\r
+#define ACC_MR_SELMINUS_Pos 0\r
+#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */\r
+#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */\r
+#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */\r
+#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */\r
+#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */\r
+#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_Pos 4\r
+#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */\r
+#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */\r
+#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */\r
+#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */\r
+#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */\r
+#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */\r
+#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */\r
+#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */\r
+#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */\r
+#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */\r
+#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */\r
+#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */\r
+#define ACC_MR_EDGETYP_Pos 9\r
+#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */\r
+#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */\r
+#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */\r
+#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */\r
+#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */\r
+#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */\r
+#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */\r
+#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */\r
+#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */\r
+#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */\r
+#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */\r
+#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */\r
+#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */\r
+/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */\r
+/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */\r
+/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */\r
+/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */\r
+#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */\r
+#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */\r
+/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */\r
+#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */\r
+#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */\r
+#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */\r
+#define ACC_ACR_HYST_Pos 1\r
+#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */\r
+#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))\r
+/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */\r
+#define ACC_WPMR_WPKEY_Pos 8\r
+#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */\r
+#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))\r
+/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_ACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_ADC_COMPONENT_\r
+#define _SAM4S_ADC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_ADC Analog-to-digital Converter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Adc hardware registers */\r
+typedef struct {\r
+ WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */\r
+ RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */\r
+ RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */\r
+ RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */\r
+ WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */\r
+ WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */\r
+ RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved1[1];\r
+ RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */\r
+ WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved2[2];\r
+ RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */\r
+ RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */\r
+ RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */\r
+ RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */\r
+ RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */\r
+ RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */\r
+ RoReg Reserved3[1];\r
+ RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */\r
+ RoReg Reserved4[19];\r
+ RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved5[5];\r
+ RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */\r
+ RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */\r
+ RoReg Reserved7[2];\r
+ WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */\r
+ RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */\r
+} Adc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */\r
+#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */\r
+#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */\r
+#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */\r
+/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */\r
+#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */\r
+#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */\r
+#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */\r
+#define ADC_MR_TRGSEL_Pos 1\r
+#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */\r
+#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */\r
+#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */\r
+#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */\r
+#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */\r
+#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */\r
+#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */\r
+#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */\r
+#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */\r
+#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */\r
+#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */\r
+#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */\r
+#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */\r
+#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */\r
+#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */\r
+#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */\r
+#define ADC_MR_PRESCAL_Pos 8\r
+#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */\r
+#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))\r
+#define ADC_MR_STARTUP_Pos 16\r
+#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */\r
+#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */\r
+#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */\r
+#define ADC_MR_SETTLING_Pos 20\r
+#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */\r
+#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */\r
+#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */\r
+#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */\r
+#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */\r
+#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */\r
+#define ADC_MR_TRACKTIM_Pos 24\r
+#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */\r
+#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))\r
+#define ADC_MR_TRANSFER_Pos 28\r
+#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */\r
+#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos)))\r
+#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */\r
+#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */\r
+#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */\r
+/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */\r
+#define ADC_SEQR1_USCH1_Pos 0\r
+#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */\r
+#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))\r
+#define ADC_SEQR1_USCH2_Pos 4\r
+#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */\r
+#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))\r
+#define ADC_SEQR1_USCH3_Pos 8\r
+#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */\r
+#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))\r
+#define ADC_SEQR1_USCH4_Pos 12\r
+#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */\r
+#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))\r
+#define ADC_SEQR1_USCH5_Pos 16\r
+#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */\r
+#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))\r
+#define ADC_SEQR1_USCH6_Pos 20\r
+#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */\r
+#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))\r
+#define ADC_SEQR1_USCH7_Pos 24\r
+#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */\r
+#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))\r
+#define ADC_SEQR1_USCH8_Pos 28\r
+#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */\r
+#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))\r
+/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */\r
+#define ADC_SEQR2_USCH9_Pos 0\r
+#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */\r
+#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))\r
+#define ADC_SEQR2_USCH10_Pos 4\r
+#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */\r
+#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))\r
+#define ADC_SEQR2_USCH11_Pos 8\r
+#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */\r
+#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))\r
+#define ADC_SEQR2_USCH12_Pos 12\r
+#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */\r
+#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))\r
+#define ADC_SEQR2_USCH13_Pos 16\r
+#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */\r
+#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))\r
+#define ADC_SEQR2_USCH14_Pos 20\r
+#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */\r
+#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))\r
+#define ADC_SEQR2_USCH15_Pos 24\r
+#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */\r
+#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))\r
+#define ADC_SEQR2_USCH16_Pos 28\r
+#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */\r
+#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))\r
+/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */\r
+#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */\r
+#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */\r
+#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */\r
+#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */\r
+#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */\r
+#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */\r
+#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */\r
+#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */\r
+#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */\r
+#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */\r
+#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */\r
+#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */\r
+#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */\r
+#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */\r
+#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */\r
+#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */\r
+/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */\r
+#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */\r
+#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */\r
+#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */\r
+#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */\r
+#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */\r
+#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */\r
+#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */\r
+#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */\r
+#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */\r
+#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */\r
+#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */\r
+#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */\r
+#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */\r
+#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */\r
+#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */\r
+#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */\r
+/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */\r
+#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */\r
+#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */\r
+#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */\r
+#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */\r
+#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */\r
+#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */\r
+#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */\r
+#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */\r
+#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */\r
+#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */\r
+#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */\r
+#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */\r
+#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */\r
+#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */\r
+#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */\r
+#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */\r
+/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */\r
+#define ADC_LCDR_LDATA_Pos 0\r
+#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */\r
+#define ADC_LCDR_CHNB_Pos 12\r
+#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */\r
+/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */\r
+#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */\r
+#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */\r
+#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */\r
+#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */\r
+#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */\r
+#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */\r
+#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */\r
+#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */\r
+#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */\r
+#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */\r
+#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */\r
+#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */\r
+#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */\r
+#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */\r
+#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */\r
+#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */\r
+#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */\r
+#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */\r
+#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */\r
+#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */\r
+/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */\r
+#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */\r
+#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */\r
+#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */\r
+#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */\r
+#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */\r
+#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */\r
+#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */\r
+#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */\r
+#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */\r
+#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */\r
+#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */\r
+#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */\r
+#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */\r
+#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */\r
+#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */\r
+#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */\r
+#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */\r
+#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */\r
+#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */\r
+#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */\r
+/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */\r
+#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */\r
+#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */\r
+#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */\r
+#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */\r
+#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */\r
+#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */\r
+#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */\r
+#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */\r
+#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */\r
+#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */\r
+#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */\r
+#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */\r
+#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */\r
+#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */\r
+#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */\r
+#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */\r
+#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */\r
+#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */\r
+#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */\r
+#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */\r
+/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */\r
+#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */\r
+#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */\r
+#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */\r
+#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */\r
+#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */\r
+#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */\r
+#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */\r
+#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */\r
+#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */\r
+#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */\r
+#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */\r
+#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */\r
+#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */\r
+#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */\r
+#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */\r
+#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */\r
+#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */\r
+#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */\r
+#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */\r
+#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */\r
+#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */\r
+#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */\r
+/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */\r
+#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */\r
+#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */\r
+#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */\r
+#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */\r
+#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */\r
+#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */\r
+#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */\r
+#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */\r
+#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */\r
+#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */\r
+#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */\r
+#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */\r
+#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */\r
+#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */\r
+#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */\r
+#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */\r
+/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */\r
+#define ADC_EMR_CMPMODE_Pos 0\r
+#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */\r
+#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */\r
+#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */\r
+#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */\r
+#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */\r
+#define ADC_EMR_CMPSEL_Pos 4\r
+#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */\r
+#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))\r
+#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */\r
+#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */\r
+/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */\r
+#define ADC_CWR_LOWTHRES_Pos 0\r
+#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */\r
+#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))\r
+#define ADC_CWR_HIGHTHRES_Pos 16\r
+#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */\r
+#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))\r
+/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */\r
+#define ADC_CGR_GAIN0_Pos 0\r
+#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */\r
+#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos)))\r
+#define ADC_CGR_GAIN1_Pos 2\r
+#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */\r
+#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos)))\r
+#define ADC_CGR_GAIN2_Pos 4\r
+#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */\r
+#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos)))\r
+#define ADC_CGR_GAIN3_Pos 6\r
+#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */\r
+#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos)))\r
+#define ADC_CGR_GAIN4_Pos 8\r
+#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */\r
+#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos)))\r
+#define ADC_CGR_GAIN5_Pos 10\r
+#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */\r
+#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos)))\r
+#define ADC_CGR_GAIN6_Pos 12\r
+#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */\r
+#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos)))\r
+#define ADC_CGR_GAIN7_Pos 14\r
+#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */\r
+#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos)))\r
+#define ADC_CGR_GAIN8_Pos 16\r
+#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */\r
+#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos)))\r
+#define ADC_CGR_GAIN9_Pos 18\r
+#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */\r
+#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos)))\r
+#define ADC_CGR_GAIN10_Pos 20\r
+#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */\r
+#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos)))\r
+#define ADC_CGR_GAIN11_Pos 22\r
+#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */\r
+#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos)))\r
+#define ADC_CGR_GAIN12_Pos 24\r
+#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */\r
+#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos)))\r
+#define ADC_CGR_GAIN13_Pos 26\r
+#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */\r
+#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos)))\r
+#define ADC_CGR_GAIN14_Pos 28\r
+#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */\r
+#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos)))\r
+#define ADC_CGR_GAIN15_Pos 30\r
+#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */\r
+#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos)))\r
+/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */\r
+#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */\r
+#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */\r
+#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */\r
+#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */\r
+#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */\r
+#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */\r
+#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */\r
+#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */\r
+#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */\r
+#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */\r
+#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */\r
+#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */\r
+#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */\r
+#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */\r
+#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */\r
+#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */\r
+#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */\r
+#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */\r
+#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */\r
+#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */\r
+#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */\r
+#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */\r
+#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */\r
+#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */\r
+#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */\r
+#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */\r
+#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */\r
+#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */\r
+#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */\r
+#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */\r
+#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */\r
+#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */\r
+/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */\r
+#define ADC_CDR_DATA_Pos 0\r
+#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */\r
+/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */\r
+#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */\r
+#define ADC_ACR_IBCTL_Pos 8\r
+#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */\r
+#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos)))\r
+/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */\r
+#define ADC_WPMR_WPKEY_Pos 8\r
+#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */\r
+#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))\r
+/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */\r
+#define ADC_WPSR_WPVSRC_Pos 8\r
+#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */\r
+/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */\r
+#define ADC_RPR_RXPTR_Pos 0\r
+#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */\r
+#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))\r
+/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */\r
+#define ADC_RCR_RXCTR_Pos 0\r
+#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */\r
+#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))\r
+/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define ADC_RNPR_RXNPTR_Pos 0\r
+#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */\r
+#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))\r
+/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define ADC_RNCR_RXNCTR_Pos 0\r
+#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */\r
+#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))\r
+/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */\r
+#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */\r
+#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */\r
+#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */\r
+#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */\r
+/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */\r
+#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */\r
+#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_ADC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_CHIPID_COMPONENT_\r
+#define _SAM4S_CHIPID_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Chip Identifier */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_CHIPID Chip Identifier */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Chipid hardware registers */\r
+typedef struct {\r
+ RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */\r
+ RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */\r
+} Chipid;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */\r
+#define CHIPID_CIDR_VERSION_Pos 0\r
+#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */\r
+#define CHIPID_CIDR_EPROC_Pos 5\r
+#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */\r
+#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */\r
+#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */\r
+#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */\r
+#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */\r
+#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */\r
+#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */\r
+#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */\r
+#define CHIPID_CIDR_NVPSIZ_Pos 8\r
+#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */\r
+#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_Pos 12\r
+#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) */\r
+#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */\r
+#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */\r
+#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_Pos 16\r
+#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */\r
+#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */\r
+#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */\r
+#define CHIPID_CIDR_ARCH_Pos 20\r
+#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */\r
+#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */\r
+#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */\r
+#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */\r
+#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */\r
+#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */\r
+#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3ASAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC or SAM4AxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XSAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxCor SAM4XxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XSAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxEor SAM4XxE Series (144-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3XSAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxGor or SAM4XxG Series (208/217-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SSAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxA or SAM4SxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SSAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxBor SAM4SxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SSAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxCor SAM4SxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */\r
+#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */\r
+#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */\r
+#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */\r
+#define CHIPID_CIDR_NVPTYP_Pos 28\r
+#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */\r
+#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */\r
+#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */\r
+#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */\r
+#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */\r
+#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */\r
+#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */\r
+/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */\r
+#define CHIPID_EXID_EXID_Pos 0\r
+#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_CHIPID_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_CRCCU_COMPONENT_\r
+#define _SAM4S_CRCCU_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_CRCCU Cyclic Redundancy Check Calculation Unit */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Crccu hardware registers */\r
+typedef struct {\r
+ RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */\r
+ RoReg Reserved1[1];\r
+ WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */\r
+ WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */\r
+ RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */\r
+ WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */\r
+ WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */\r
+ RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */\r
+ RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */\r
+ RoReg Reserved2[4];\r
+ WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */\r
+ RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */\r
+ RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */\r
+ WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */\r
+ WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */\r
+ RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */\r
+ RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */\r
+} Crccu;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */\r
+#define CRCCU_DSCR_DSCR_Pos 9\r
+#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */\r
+#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos)))\r
+/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */\r
+#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */\r
+/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */\r
+#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */\r
+/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */\r
+#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */\r
+/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */\r
+#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */\r
+/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */\r
+#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */\r
+/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */\r
+#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */\r
+/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */\r
+#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */\r
+/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */\r
+#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */\r
+/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */\r
+#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */\r
+#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */\r
+#define CRCCU_MR_PTYPE_Pos 2\r
+#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */\r
+#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */\r
+#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */\r
+#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */\r
+#define CRCCU_MR_DIVIDER_Pos 4\r
+#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */\r
+#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))\r
+/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */\r
+#define CRCCU_SR_CRC_Pos 0\r
+#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */\r
+/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */\r
+#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */\r
+/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */\r
+#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */\r
+/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */\r
+#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */\r
+/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */\r
+#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_CRCCU_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_DACC_COMPONENT_\r
+#define _SAM4S_DACC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_DACC Digital-to-Analog Converter Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Dacc hardware registers */\r
+typedef struct {\r
+ WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */\r
+ RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */\r
+ RoReg Reserved1[2];\r
+ WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */\r
+ WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */\r
+ RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */\r
+ WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */\r
+ WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */\r
+ RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */\r
+ RoReg Reserved3[24];\r
+ RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */\r
+ RoReg Reserved4[19];\r
+ RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */\r
+ RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */\r
+ RoReg Reserved5[7];\r
+ RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */\r
+ RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */\r
+} Dacc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */\r
+#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */\r
+/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */\r
+#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */\r
+#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */\r
+#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */\r
+#define DACC_MR_TRGSEL_Pos 1\r
+#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */\r
+#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos)))\r
+#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */\r
+#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */\r
+#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */\r
+#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */\r
+#define DACC_MR_REFRESH_Pos 8\r
+#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */\r
+#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))\r
+#define DACC_MR_USER_SEL_Pos 16\r
+#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */\r
+#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */\r
+#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */\r
+#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */\r
+#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */\r
+#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */\r
+#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */\r
+#define DACC_MR_STARTUP_Pos 24\r
+#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */\r
+#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */\r
+#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */\r
+#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */\r
+#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */\r
+#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */\r
+#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */\r
+#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */\r
+#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */\r
+#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */\r
+#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */\r
+#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */\r
+#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */\r
+#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */\r
+#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */\r
+#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */\r
+#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */\r
+#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */\r
+#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */\r
+#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */\r
+#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */\r
+#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */\r
+#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */\r
+#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */\r
+#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */\r
+#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */\r
+#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */\r
+#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */\r
+#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */\r
+#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */\r
+#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */\r
+#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */\r
+#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */\r
+/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */\r
+#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */\r
+#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */\r
+/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */\r
+#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */\r
+#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */\r
+/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */\r
+#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */\r
+#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */\r
+/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */\r
+#define DACC_CDR_DATA_Pos 0\r
+#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */\r
+#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))\r
+/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */\r
+#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */\r
+#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */\r
+#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */\r
+#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */\r
+#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */\r
+#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */\r
+#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */\r
+#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */\r
+#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */\r
+#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */\r
+#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */\r
+#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */\r
+#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */\r
+/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */\r
+#define DACC_ACR_IBCTLCH0_Pos 0\r
+#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))\r
+#define DACC_ACR_IBCTLCH1_Pos 2\r
+#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */\r
+#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))\r
+#define DACC_ACR_IBCTLDACCORE_Pos 8\r
+#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */\r
+#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos)))\r
+/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */\r
+#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */\r
+#define DACC_WPMR_WPKEY_Pos 8\r
+#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */\r
+#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))\r
+/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */\r
+#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */\r
+#define DACC_WPSR_WPROTADDR_Pos 8\r
+#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */\r
+/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define DACC_TPR_TXPTR_Pos 0\r
+#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */\r
+#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))\r
+/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define DACC_TCR_TXCTR_Pos 0\r
+#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */\r
+#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))\r
+/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define DACC_TNPR_TXNPTR_Pos 0\r
+#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */\r
+#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))\r
+/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define DACC_TNCR_TXNCTR_Pos 0\r
+#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */\r
+#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))\r
+/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */\r
+#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */\r
+#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */\r
+#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */\r
+#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */\r
+/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */\r
+#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */\r
+#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_DACC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_EFC_COMPONENT_\r
+#define _SAM4S_EFC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_EFC Embedded Flash Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Efc hardware registers */\r
+typedef struct {\r
+ RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */\r
+ WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */\r
+ RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */\r
+ RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */\r
+} Efc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */\r
+#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */\r
+#define EEFC_FMR_FWS_Pos 8\r
+#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */\r
+#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))\r
+#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */\r
+#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */\r
+#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loops Optimization Enable */\r
+/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */\r
+#define EEFC_FCR_FCMD_Pos 0\r
+#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */\r
+#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))\r
+#define EEFC_FCR_FARG_Pos 8\r
+#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */\r
+#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))\r
+#define EEFC_FCR_FKEY_Pos 24\r
+#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */\r
+#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))\r
+/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */\r
+#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */\r
+#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */\r
+#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */\r
+#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status */\r
+/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */\r
+#define EEFC_FRR_FVALUE_Pos 0\r
+#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_EFC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_GPBR_COMPONENT_\r
+#define _SAM4S_GPBR_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_GPBR General Purpose Backup Register */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Gpbr hardware registers */\r
+typedef struct {\r
+ RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */\r
+} Gpbr;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */\r
+#define SYS_GPBR_GPBR_VALUE_Pos 0\r
+#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */\r
+#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_GPBR_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_HSMCI_COMPONENT_\r
+#define _SAM4S_HSMCI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_HSMCI High Speed MultiMedia Card Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Hsmci hardware registers */\r
+typedef struct {\r
+ WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */\r
+ RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */\r
+ RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */\r
+ RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */\r
+ RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */\r
+ WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */\r
+ RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */\r
+ RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */\r
+ RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */\r
+ RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */\r
+ WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */\r
+ RoReg Reserved1[2];\r
+ RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */\r
+ WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */\r
+ WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */\r
+ RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved2[1];\r
+ RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */\r
+ RoReg Reserved3[35];\r
+ RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */\r
+ RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */\r
+ RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */\r
+ RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */\r
+ RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */\r
+ RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */\r
+ RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */\r
+ RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved5[54];\r
+ RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */\r
+} Hsmci;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */\r
+#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */\r
+#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */\r
+#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */\r
+#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */\r
+#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */\r
+/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */\r
+#define HSMCI_MR_CLKDIV_Pos 0\r
+#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */\r
+#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))\r
+#define HSMCI_MR_PWSDIV_Pos 8\r
+#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */\r
+#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))\r
+#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */\r
+#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */\r
+#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */\r
+#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */\r
+#define HSMCI_MR_BLKLEN_Pos 16\r
+#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */\r
+#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos)))\r
+/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */\r
+#define HSMCI_DTOR_DTOCYC_Pos 0\r
+#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */\r
+#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))\r
+#define HSMCI_DTOR_DTOMUL_Pos 4\r
+#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */\r
+#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */\r
+#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */\r
+#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */\r
+#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */\r
+#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */\r
+#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */\r
+#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */\r
+#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */\r
+/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */\r
+#define HSMCI_SDCR_SDCSEL_Pos 0\r
+#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */\r
+#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */\r
+#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */\r
+#define HSMCI_SDCR_SDCBUS_Pos 6\r
+#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */\r
+#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */\r
+#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */\r
+#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */\r
+/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */\r
+#define HSMCI_ARGR_ARG_Pos 0\r
+#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */\r
+#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))\r
+/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */\r
+#define HSMCI_CMDR_CMDNB_Pos 0\r
+#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */\r
+#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))\r
+#define HSMCI_CMDR_RSPTYP_Pos 6\r
+#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */\r
+#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */\r
+#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */\r
+#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */\r
+#define HSMCI_CMDR_SPCMD_Pos 8\r
+#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */\r
+#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */\r
+#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */\r
+#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */\r
+#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */\r
+#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */\r
+#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */\r
+#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */\r
+#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */\r
+#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */\r
+#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */\r
+#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */\r
+#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */\r
+#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */\r
+#define HSMCI_CMDR_TRCMD_Pos 16\r
+#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */\r
+#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */\r
+#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */\r
+#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */\r
+#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */\r
+#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */\r
+#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */\r
+#define HSMCI_CMDR_TRTYP_Pos 19\r
+#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */\r
+#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */\r
+#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */\r
+#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */\r
+#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */\r
+#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */\r
+#define HSMCI_CMDR_IOSPCMD_Pos 24\r
+#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */\r
+#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */\r
+#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */\r
+#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */\r
+#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */\r
+#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */\r
+#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */\r
+/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */\r
+#define HSMCI_BLKR_BCNT_Pos 0\r
+#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */\r
+#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */\r
+#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */\r
+#define HSMCI_BLKR_BLKLEN_Pos 16\r
+#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */\r
+#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))\r
+/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */\r
+#define HSMCI_CSTOR_CSTOCYC_Pos 0\r
+#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */\r
+#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))\r
+#define HSMCI_CSTOR_CSTOMUL_Pos 4\r
+#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */\r
+#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */\r
+#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */\r
+#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */\r
+#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */\r
+#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */\r
+#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */\r
+#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */\r
+#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */\r
+/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */\r
+#define HSMCI_RSPR_RSP_Pos 0\r
+#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */\r
+/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */\r
+#define HSMCI_RDR_DATA_Pos 0\r
+#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */\r
+/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */\r
+#define HSMCI_TDR_DATA_Pos 0\r
+#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */\r
+#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))\r
+/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */\r
+#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */\r
+#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */\r
+#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */\r
+#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */\r
+#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */\r
+#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */\r
+#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */\r
+#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */\r
+#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */\r
+#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */\r
+#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */\r
+#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */\r
+#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */\r
+#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */\r
+#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */\r
+#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */\r
+#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */\r
+#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */\r
+#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */\r
+#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */\r
+#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */\r
+#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */\r
+#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */\r
+#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */\r
+#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */\r
+#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */\r
+#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */\r
+/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */\r
+#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */\r
+#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */\r
+#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */\r
+#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */\r
+#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */\r
+#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */\r
+#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */\r
+#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */\r
+#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */\r
+#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */\r
+#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */\r
+#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */\r
+#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */\r
+#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */\r
+#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */\r
+#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */\r
+#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */\r
+#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */\r
+#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */\r
+#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */\r
+#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */\r
+#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */\r
+#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */\r
+#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */\r
+/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */\r
+#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */\r
+#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */\r
+#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */\r
+#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */\r
+#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */\r
+#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */\r
+#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */\r
+#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */\r
+#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */\r
+#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */\r
+#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */\r
+#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */\r
+#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */\r
+#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */\r
+#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */\r
+#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */\r
+#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */\r
+#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */\r
+#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */\r
+#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */\r
+/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */\r
+#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */\r
+#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */\r
+#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */\r
+#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */\r
+#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */\r
+#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */\r
+#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */\r
+#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */\r
+#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */\r
+#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */\r
+#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */\r
+#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */\r
+#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */\r
+#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */\r
+#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */\r
+#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */\r
+#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */\r
+#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */\r
+/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */\r
+#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */\r
+#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */\r
+#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */\r
+#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */\r
+/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */\r
+#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */\r
+#define HSMCI_WPMR_WP_KEY_Pos 8\r
+#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */\r
+#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))\r
+/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define HSMCI_WPSR_WP_VS_Pos 0\r
+#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */\r
+#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */\r
+#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */\r
+#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */\r
+#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */\r
+#define HSMCI_WPSR_WP_VSRC_Pos 8\r
+#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */\r
+/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */\r
+#define HSMCI_RPR_RXPTR_Pos 0\r
+#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */\r
+#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos)))\r
+/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */\r
+#define HSMCI_RCR_RXCTR_Pos 0\r
+#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */\r
+#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos)))\r
+/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define HSMCI_TPR_TXPTR_Pos 0\r
+#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */\r
+#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos)))\r
+/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define HSMCI_TCR_TXCTR_Pos 0\r
+#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */\r
+#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos)))\r
+/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define HSMCI_RNPR_RXNPTR_Pos 0\r
+#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */\r
+#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos)))\r
+/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define HSMCI_RNCR_RXNCTR_Pos 0\r
+#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */\r
+#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos)))\r
+/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define HSMCI_TNPR_TXNPTR_Pos 0\r
+#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */\r
+#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos)))\r
+/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define HSMCI_TNCR_TXNCTR_Pos 0\r
+#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */\r
+#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos)))\r
+/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */\r
+#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */\r
+#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */\r
+#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */\r
+#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */\r
+/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */\r
+#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */\r
+#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */\r
+/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */\r
+#define HSMCI_FIFO_DATA_Pos 0\r
+#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */\r
+#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_HSMCI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_MATRIX_COMPONENT_\r
+#define _SAM4S_MATRIX_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_MATRIX AHB Bus Matrix */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Matrix hardware registers */\r
+typedef struct {\r
+ RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */\r
+ RoReg Reserved1[12];\r
+ RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */\r
+ RoReg Reserved2[11];\r
+ RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */\r
+ RoReg Reserved3[1];\r
+ RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */\r
+ RoReg Reserved4[1];\r
+ RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */\r
+ RoReg Reserved5[1];\r
+ RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */\r
+ RoReg Reserved6[1];\r
+ RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */\r
+ RoReg Reserved7[1];\r
+ RoReg Reserved8[27];\r
+ RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */\r
+ RoReg Reserved9[1];\r
+ RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */\r
+ RoReg Reserved10[49];\r
+ RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */\r
+ RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */\r
+} Matrix;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */\r
+#define MATRIX_MCFG_ULBT_Pos 0\r
+#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */\r
+#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))\r
+/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */\r
+#define MATRIX_SCFG_SLOT_CYCLE_Pos 0\r
+#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */\r
+#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16\r
+#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */\r
+#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18\r
+#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */\r
+#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))\r
+#define MATRIX_SCFG_ARBT_Pos 24\r
+#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */\r
+#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))\r
+/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */\r
+#define MATRIX_PRAS0_M0PR_Pos 0\r
+#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */\r
+#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))\r
+#define MATRIX_PRAS0_M1PR_Pos 4\r
+#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */\r
+#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))\r
+#define MATRIX_PRAS0_M2PR_Pos 8\r
+#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */\r
+#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))\r
+#define MATRIX_PRAS0_M3PR_Pos 12\r
+#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */\r
+#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))\r
+#define MATRIX_PRAS0_M4PR_Pos 16\r
+#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */\r
+#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */\r
+#define MATRIX_PRAS1_M0PR_Pos 0\r
+#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */\r
+#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))\r
+#define MATRIX_PRAS1_M1PR_Pos 4\r
+#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */\r
+#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))\r
+#define MATRIX_PRAS1_M2PR_Pos 8\r
+#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */\r
+#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))\r
+#define MATRIX_PRAS1_M3PR_Pos 12\r
+#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */\r
+#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))\r
+#define MATRIX_PRAS1_M4PR_Pos 16\r
+#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */\r
+#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */\r
+#define MATRIX_PRAS2_M0PR_Pos 0\r
+#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */\r
+#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))\r
+#define MATRIX_PRAS2_M1PR_Pos 4\r
+#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */\r
+#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))\r
+#define MATRIX_PRAS2_M2PR_Pos 8\r
+#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */\r
+#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))\r
+#define MATRIX_PRAS2_M3PR_Pos 12\r
+#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */\r
+#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))\r
+#define MATRIX_PRAS2_M4PR_Pos 16\r
+#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */\r
+#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */\r
+#define MATRIX_PRAS3_M0PR_Pos 0\r
+#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */\r
+#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))\r
+#define MATRIX_PRAS3_M1PR_Pos 4\r
+#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */\r
+#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))\r
+#define MATRIX_PRAS3_M2PR_Pos 8\r
+#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */\r
+#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))\r
+#define MATRIX_PRAS3_M3PR_Pos 12\r
+#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */\r
+#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))\r
+#define MATRIX_PRAS3_M4PR_Pos 16\r
+#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */\r
+#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))\r
+/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */\r
+#define MATRIX_PRAS4_M0PR_Pos 0\r
+#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */\r
+#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))\r
+#define MATRIX_PRAS4_M1PR_Pos 4\r
+#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */\r
+#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))\r
+#define MATRIX_PRAS4_M2PR_Pos 8\r
+#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */\r
+#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))\r
+#define MATRIX_PRAS4_M3PR_Pos 12\r
+#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */\r
+#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))\r
+#define MATRIX_PRAS4_M4PR_Pos 16\r
+#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */\r
+#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))\r
+/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */\r
+#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */\r
+#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */\r
+#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */\r
+#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */\r
+#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */\r
+#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */\r
+#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */\r
+/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */\r
+#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */\r
+#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */\r
+/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */\r
+#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */\r
+#define MATRIX_WPMR_WPKEY_Pos 8\r
+#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */\r
+#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))\r
+/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */\r
+#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */\r
+#define MATRIX_WPSR_WPVSRC_Pos 8\r
+#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_MATRIX_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PDC_COMPONENT_\r
+#define _SAM4S_PDC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_PDC Peripheral DMA Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pdc hardware registers */\r
+typedef struct {\r
+ RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */\r
+ RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */\r
+ RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */\r
+ RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */\r
+ RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */\r
+ RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */\r
+ RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */\r
+ RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */\r
+ WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */\r
+ RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */\r
+} Pdc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */\r
+#define PERIPH_RPR_RXPTR_Pos 0\r
+#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */\r
+#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))\r
+/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */\r
+#define PERIPH_RCR_RXCTR_Pos 0\r
+#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */\r
+#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))\r
+/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */\r
+#define PERIPH_TPR_TXPTR_Pos 0\r
+#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */\r
+#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))\r
+/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */\r
+#define PERIPH_TCR_TXCTR_Pos 0\r
+#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */\r
+#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))\r
+/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */\r
+#define PERIPH_RNPR_RXNPTR_Pos 0\r
+#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */\r
+#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))\r
+/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */\r
+#define PERIPH_RNCR_RXNCTR_Pos 0\r
+#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */\r
+#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))\r
+/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */\r
+#define PERIPH_TNPR_TXNPTR_Pos 0\r
+#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */\r
+#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))\r
+/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */\r
+#define PERIPH_TNCR_TXNCTR_Pos 0\r
+#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */\r
+#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))\r
+/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */\r
+#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */\r
+#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */\r
+#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */\r
+#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */\r
+/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */\r
+#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */\r
+#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_PDC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PIO_COMPONENT_\r
+#define _SAM4S_PIO_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_PIO Parallel Input/Output Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pio hardware registers */\r
+typedef struct {\r
+ WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */\r
+ WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */\r
+ RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */\r
+ WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */\r
+ RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */\r
+ RoReg Reserved2[1];\r
+ WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */\r
+ WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */\r
+ RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */\r
+ RoReg Reserved3[1];\r
+ WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */\r
+ WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */\r
+ RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */\r
+ RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */\r
+ WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */\r
+ WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */\r
+ RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */\r
+ RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */\r
+ WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */\r
+ WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */\r
+ RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */\r
+ RoReg Reserved4[1];\r
+ WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */\r
+ WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */\r
+ RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */\r
+ RoReg Reserved5[1];\r
+ RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */\r
+ RoReg Reserved6[2];\r
+ WoReg PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */\r
+ WoReg PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */\r
+ RoReg PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */\r
+ RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */\r
+ WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */\r
+ WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */\r
+ RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */\r
+ RoReg Reserved7[1];\r
+ WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */\r
+ WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */\r
+ RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */\r
+ RoReg Reserved8[1];\r
+ WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */\r
+ WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */\r
+ RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */\r
+ RoReg Reserved9[1];\r
+ WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */\r
+ WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */\r
+ RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */\r
+ RoReg Reserved10[1];\r
+ WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */\r
+ WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */\r
+ RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */\r
+ RoReg Reserved11[1];\r
+ RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */\r
+ RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved12[5];\r
+ RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */\r
+ RoReg Reserved13[19];\r
+ RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */\r
+ WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */\r
+ WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */\r
+ RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */\r
+ RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */\r
+ RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */\r
+ RwReg PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */\r
+ RwReg PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */\r
+ RoReg Reserved14[2];\r
+ RwReg PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */\r
+ RwReg PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */\r
+ RoReg Reserved15[2];\r
+ WoReg PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */\r
+ RoReg PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */\r
+} Pio;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */\r
+#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */\r
+#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */\r
+/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */\r
+#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */\r
+#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */\r
+/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */\r
+#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */\r
+#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */\r
+/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */\r
+#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */\r
+#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */\r
+/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */\r
+#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */\r
+#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */\r
+/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */\r
+#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */\r
+#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */\r
+/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */\r
+#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */\r
+#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */\r
+/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */\r
+#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */\r
+/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */\r
+#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */\r
+#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */\r
+/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */\r
+#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */\r
+#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */\r
+/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */\r
+#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */\r
+#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */\r
+/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */\r
+#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */\r
+#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */\r
+/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */\r
+#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */\r
+#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */\r
+/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */\r
+#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */\r
+/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */\r
+#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */\r
+/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */\r
+#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */\r
+/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */\r
+#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */\r
+/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */\r
+#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */\r
+/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */\r
+#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */\r
+/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */\r
+#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */\r
+/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */\r
+#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */\r
+/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */\r
+#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */\r
+/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */\r
+#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */\r
+/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */\r
+#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */\r
+/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */\r
+#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */\r
+/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */\r
+#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */\r
+/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */\r
+#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */\r
+/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */\r
+#define PIO_SCDR_DIV_Pos 0\r
+#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */\r
+#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))\r
+/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */\r
+#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */\r
+/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */\r
+#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */\r
+/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */\r
+#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */\r
+/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */\r
+#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */\r
+#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */\r
+/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */\r
+#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */\r
+/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */\r
+#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */\r
+#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */\r
+/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */\r
+#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */\r
+/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */\r
+#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */\r
+/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */\r
+#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */\r
+/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */\r
+#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */\r
+/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */\r
+#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */\r
+/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */\r
+#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */\r
+/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */\r
+#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */\r
+/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */\r
+#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */\r
+/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */\r
+#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */\r
+/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */\r
+#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */\r
+/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */\r
+#define PIO_WPMR_WPKEY_Pos 8\r
+#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */\r
+#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))\r
+/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */\r
+#define PIO_WPSR_WPVSRC_Pos 8\r
+#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */\r
+/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */\r
+#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */\r
+#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */\r
+/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */\r
+#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */\r
+#define PIO_PCMR_DSIZE_Pos 4\r
+#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */\r
+#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))\r
+#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */\r
+#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */\r
+#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */\r
+/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */\r
+#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */\r
+#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */\r
+#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */\r
+#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */\r
+/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */\r
+#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */\r
+#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */\r
+#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */\r
+#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */\r
+/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */\r
+#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */\r
+#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */\r
+#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */\r
+#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */\r
+/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */\r
+#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */\r
+#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */\r
+#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */\r
+#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */\r
+/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */\r
+#define PIO_PCRHR_RDATA_Pos 0\r
+#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */\r
+/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */\r
+#define PIO_RPR_RXPTR_Pos 0\r
+#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */\r
+#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos)))\r
+/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */\r
+#define PIO_RCR_RXCTR_Pos 0\r
+#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */\r
+#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos)))\r
+/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */\r
+#define PIO_RNPR_RXNPTR_Pos 0\r
+#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */\r
+#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos)))\r
+/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */\r
+#define PIO_RNCR_RXNCTR_Pos 0\r
+#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */\r
+#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos)))\r
+/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */\r
+#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */\r
+#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */\r
+#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */\r
+#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */\r
+/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */\r
+#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */\r
+#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_PIO_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PMC_COMPONENT_\r
+#define _SAM4S_PMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Power Management Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_PMC Power Management Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Pmc hardware registers */\r
+typedef struct {\r
+ WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */\r
+ WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */\r
+ RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */\r
+ RoReg Reserved1[1];\r
+ WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */\r
+ WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */\r
+ RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */\r
+ RoReg Reserved2[1];\r
+ RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */\r
+ RwReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */\r
+ RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */\r
+ RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */\r
+ RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */\r
+ RoReg Reserved3[1];\r
+ RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */\r
+ RoReg Reserved4[1];\r
+ RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */\r
+ RoReg Reserved5[5];\r
+ WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */\r
+ WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */\r
+ RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */\r
+ RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */\r
+ RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */\r
+ RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */\r
+ WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */\r
+ RoReg Reserved6[26];\r
+ RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */\r
+ RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */\r
+ RoReg Reserved7[5];\r
+ WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */\r
+ WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */\r
+ RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */\r
+ RoReg Reserved8[1];\r
+ RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */\r
+} Pmc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */\r
+#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */\r
+#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */\r
+#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */\r
+#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */\r
+/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */\r
+#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */\r
+#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */\r
+#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */\r
+#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */\r
+/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */\r
+#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */\r
+#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */\r
+#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */\r
+#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */\r
+/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */\r
+#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */\r
+#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */\r
+#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */\r
+#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */\r
+#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */\r
+#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */\r
+#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */\r
+#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */\r
+#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */\r
+#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */\r
+#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */\r
+#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */\r
+#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */\r
+#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */\r
+#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */\r
+#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */\r
+#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */\r
+#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */\r
+#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */\r
+#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */\r
+#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */\r
+#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */\r
+#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */\r
+#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */\r
+#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */\r
+#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */\r
+#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */\r
+#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */\r
+#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */\r
+#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */\r
+/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */\r
+#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */\r
+#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */\r
+#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */\r
+#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */\r
+#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */\r
+#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */\r
+#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */\r
+#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */\r
+#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */\r
+#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */\r
+#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */\r
+#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */\r
+#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */\r
+#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */\r
+#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */\r
+#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */\r
+#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */\r
+#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */\r
+#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */\r
+#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */\r
+#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */\r
+#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */\r
+#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */\r
+#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */\r
+#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */\r
+#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */\r
+#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */\r
+#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */\r
+#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */\r
+#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */\r
+/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */\r
+#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */\r
+#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */\r
+#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */\r
+#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */\r
+#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */\r
+#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */\r
+#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */\r
+#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */\r
+#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */\r
+#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */\r
+#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */\r
+#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */\r
+#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */\r
+#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */\r
+#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */\r
+#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */\r
+#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */\r
+#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */\r
+#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */\r
+#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */\r
+#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */\r
+#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */\r
+#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */\r
+#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */\r
+#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */\r
+#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */\r
+#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */\r
+#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */\r
+#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */\r
+#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */\r
+/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */\r
+#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */\r
+#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */\r
+#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */\r
+#define CKGR_MOR_MOSCRCF_Pos 4\r
+#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */\r
+#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */\r
+#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */\r
+#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */\r
+#define CKGR_MOR_MOSCXTST_Pos 8\r
+#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */\r
+#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))\r
+#define CKGR_MOR_KEY_Pos 16\r
+#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */\r
+#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))\r
+#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */\r
+#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */\r
+/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */\r
+#define CKGR_MCFR_MAINF_Pos 0\r
+#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */\r
+#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))\r
+#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */\r
+#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */\r
+/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */\r
+#define CKGR_PLLAR_DIVA_Pos 0\r
+#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */\r
+#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))\r
+#define CKGR_PLLAR_PLLACOUNT_Pos 8\r
+#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */\r
+#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))\r
+#define CKGR_PLLAR_MULA_Pos 16\r
+#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */\r
+#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))\r
+#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */\r
+/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */\r
+#define CKGR_PLLBR_DIVB_Pos 0\r
+#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */\r
+#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos)))\r
+#define CKGR_PLLBR_PLLBCOUNT_Pos 8\r
+#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */\r
+#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos)))\r
+#define CKGR_PLLBR_MULB_Pos 16\r
+#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */\r
+#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos)))\r
+/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */\r
+#define PMC_MCKR_CSS_Pos 0\r
+#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */\r
+#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */\r
+#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */\r
+#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */\r
+#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */\r
+#define PMC_MCKR_PRES_Pos 4\r
+#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */\r
+#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */\r
+#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */\r
+#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */\r
+#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */\r
+#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */\r
+#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */\r
+#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */\r
+#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */\r
+#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */\r
+#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */\r
+/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */\r
+#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */\r
+#define PMC_USB_USBDIV_Pos 8\r
+#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */\r
+#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))\r
+/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */\r
+#define PMC_PCK_CSS_Pos 0\r
+#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */\r
+#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */\r
+#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */\r
+#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */\r
+#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */\r
+#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */\r
+#define PMC_PCK_PRES_Pos 4\r
+#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */\r
+#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */\r
+#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */\r
+#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */\r
+#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */\r
+#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */\r
+#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */\r
+#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */\r
+/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */\r
+#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */\r
+#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */\r
+#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */\r
+#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */\r
+#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */\r
+#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */\r
+#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */\r
+#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */\r
+#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */\r
+#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */\r
+/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */\r
+#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */\r
+#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */\r
+#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */\r
+#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */\r
+#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */\r
+#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */\r
+#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */\r
+#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */\r
+#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */\r
+/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */\r
+#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */\r
+#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */\r
+#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */\r
+#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */\r
+#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */\r
+#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */\r
+#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */\r
+#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */\r
+#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */\r
+#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */\r
+#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */\r
+/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */\r
+#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */\r
+#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */\r
+#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */\r
+#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */\r
+#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */\r
+#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */\r
+#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */\r
+#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */\r
+#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */\r
+/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */\r
+#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */\r
+#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */\r
+#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */\r
+#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */\r
+#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */\r
+#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */\r
+#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */\r
+#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */\r
+#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */\r
+#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */\r
+#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */\r
+#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */\r
+#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */\r
+#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */\r
+#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */\r
+#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */\r
+#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */\r
+#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */\r
+#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */\r
+#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */\r
+#define PMC_FSMR_FLPM_Pos 21\r
+#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low Power Mode */\r
+#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby mode when system enters wait mode */\r
+#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in deep power down mode when system enters wait mode */\r
+#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) idle mode */\r
+/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */\r
+#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */\r
+/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */\r
+#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */\r
+/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */\r
+#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */\r
+#define PMC_WPMR_WPKEY_Pos 8\r
+#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */\r
+#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))\r
+/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */\r
+#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */\r
+#define PMC_WPSR_WPVSRC_Pos 8\r
+#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */\r
+/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */\r
+#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */\r
+#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */\r
+#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */\r
+/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */\r
+#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */\r
+#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */\r
+#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */\r
+/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */\r
+#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */\r
+#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */\r
+#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */\r
+/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */\r
+#define PMC_OCR_CAL4_Pos 0\r
+#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */\r
+#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))\r
+#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */\r
+#define PMC_OCR_CAL8_Pos 8\r
+#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */\r
+#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))\r
+#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */\r
+#define PMC_OCR_CAL12_Pos 16\r
+#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */\r
+#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))\r
+#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_PMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PWM_COMPONENT_\r
+#define _SAM4S_PWM_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_PWM Pulse Width Modulation Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief PwmCh_num hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */\r
+ RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */\r
+ RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */\r
+ RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */\r
+ RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */\r
+ RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */\r
+ RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */\r
+ RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */\r
+} PwmCh_num;\r
+/** \brief PwmCmp hardware registers */\r
+typedef struct {\r
+ RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */\r
+ RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */\r
+ RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */\r
+ RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */\r
+} PwmCmp;\r
+/** \brief Pwm hardware registers */\r
+#define PWMCMP_NUMBER 8\r
+#define PWMCH_NUM_NUMBER 4\r
+typedef struct {\r
+ RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */\r
+ WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */\r
+ WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */\r
+ RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */\r
+ WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */\r
+ WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */\r
+ RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */\r
+ RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */\r
+ RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */\r
+ RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */\r
+ WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */\r
+ WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */\r
+ WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */\r
+ RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */\r
+ RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */\r
+ RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */\r
+ RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */\r
+ WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */\r
+ WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */\r
+ WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */\r
+ WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */\r
+ RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */\r
+ RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */\r
+ WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */\r
+ RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */\r
+ RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */\r
+ RoReg Reserved2[3];\r
+ RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */\r
+ RoReg Reserved3[11];\r
+ RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */\r
+ RoReg Reserved4[12];\r
+ WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */\r
+ RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */\r
+ RoReg Reserved5[7];\r
+ RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */\r
+ RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */\r
+ RoReg Reserved6[2];\r
+ RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */\r
+ RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */\r
+ RoReg Reserved7[2];\r
+ PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */\r
+ RoReg Reserved8[20];\r
+ PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */\r
+} Pwm;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */\r
+#define PWM_CLK_DIVA_Pos 0\r
+#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))\r
+#define PWM_CLK_PREA_Pos 8\r
+#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))\r
+#define PWM_CLK_DIVB_Pos 16\r
+#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */\r
+#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))\r
+#define PWM_CLK_PREB_Pos 24\r
+#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */\r
+#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))\r
+/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */\r
+#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */\r
+#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */\r
+/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */\r
+#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */\r
+#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */\r
+/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */\r
+#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */\r
+#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */\r
+/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */\r
+#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */\r
+#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */\r
+#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */\r
+#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */\r
+#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */\r
+/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */\r
+#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */\r
+#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */\r
+#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */\r
+#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */\r
+#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */\r
+/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */\r
+#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */\r
+#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */\r
+#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */\r
+#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */\r
+#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */\r
+/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */\r
+#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */\r
+#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */\r
+#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */\r
+#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */\r
+#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */\r
+#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */\r
+#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */\r
+#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */\r
+/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */\r
+#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */\r
+#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */\r
+#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */\r
+#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */\r
+#define PWM_SCM_UPDM_Pos 16\r
+#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */\r
+#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */\r
+#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */\r
+#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */\r
+#define PWM_SCM_PTRCS_Pos 21\r
+#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */\r
+#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))\r
+/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */\r
+#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */\r
+/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */\r
+#define PWM_SCUP_UPR_Pos 0\r
+#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */\r
+#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))\r
+#define PWM_SCUP_UPRCNT_Pos 4\r
+#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */\r
+#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))\r
+/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */\r
+#define PWM_SCUPUPD_UPRUPD_Pos 0\r
+#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */\r
+#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))\r
+/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */\r
+#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */\r
+#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */\r
+#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */\r
+#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */\r
+#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */\r
+#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */\r
+#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */\r
+#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */\r
+/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */\r
+#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */\r
+#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */\r
+#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */\r
+#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */\r
+#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */\r
+#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */\r
+#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */\r
+/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */\r
+#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */\r
+#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */\r
+#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */\r
+#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */\r
+#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */\r
+#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */\r
+#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */\r
+/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */\r
+#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */\r
+#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */\r
+#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */\r
+#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */\r
+#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */\r
+#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */\r
+#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */\r
+#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */\r
+#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */\r
+#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */\r
+#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */\r
+#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */\r
+#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */\r
+#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */\r
+#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */\r
+#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */\r
+#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */\r
+#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */\r
+#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */\r
+#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */\r
+/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */\r
+#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */\r
+#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */\r
+#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */\r
+#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */\r
+#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */\r
+#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */\r
+#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */\r
+#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */\r
+/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */\r
+#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */\r
+#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */\r
+#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */\r
+#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */\r
+#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */\r
+#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */\r
+#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */\r
+#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */\r
+/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */\r
+#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */\r
+#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */\r
+#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */\r
+#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */\r
+#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */\r
+#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */\r
+#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */\r
+/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */\r
+#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */\r
+#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */\r
+#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */\r
+#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */\r
+#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */\r
+/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */\r
+#define PWM_FMR_FPOL_Pos 0\r
+#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))\r
+#define PWM_FMR_FMOD_Pos 8\r
+#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))\r
+#define PWM_FMR_FFIL_Pos 16\r
+#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */\r
+#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))\r
+/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */\r
+#define PWM_FSR_FIV_Pos 0\r
+#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */\r
+#define PWM_FSR_FS_Pos 8\r
+#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */\r
+/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */\r
+#define PWM_FCR_FCLR_Pos 0\r
+#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */\r
+#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))\r
+/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */\r
+#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */\r
+#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */\r
+#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */\r
+#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */\r
+#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */\r
+#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */\r
+#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */\r
+#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */\r
+/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */\r
+#define PWM_FPE_FPE0_Pos 0\r
+#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))\r
+#define PWM_FPE_FPE1_Pos 8\r
+#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))\r
+#define PWM_FPE_FPE2_Pos 16\r
+#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))\r
+#define PWM_FPE_FPE3_Pos 24\r
+#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */\r
+#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))\r
+/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */\r
+#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */\r
+#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */\r
+#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */\r
+#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */\r
+#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */\r
+#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */\r
+#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */\r
+#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */\r
+/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */\r
+#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */\r
+#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */\r
+#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */\r
+/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */\r
+#define PWM_WPCR_WPCMD_Pos 0\r
+#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */\r
+#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))\r
+#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */\r
+#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */\r
+#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */\r
+#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */\r
+#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */\r
+#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */\r
+#define PWM_WPCR_WPKEY_Pos 8\r
+#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */\r
+#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))\r
+/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */\r
+#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */\r
+#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */\r
+#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */\r
+#define PWM_WPSR_WPVSRC_Pos 16\r
+#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */\r
+/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */\r
+#define PWM_TPR_TXPTR_Pos 0\r
+#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */\r
+#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))\r
+/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */\r
+#define PWM_TCR_TXCTR_Pos 0\r
+#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */\r
+#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))\r
+/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define PWM_TNPR_TXNPTR_Pos 0\r
+#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */\r
+#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))\r
+/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define PWM_TNCR_TXNCTR_Pos 0\r
+#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */\r
+#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))\r
+/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */\r
+#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */\r
+#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */\r
+#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */\r
+#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */\r
+/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */\r
+#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */\r
+#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */\r
+/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */\r
+#define PWM_CMPV_CV_Pos 0\r
+#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */\r
+#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))\r
+#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */\r
+/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */\r
+#define PWM_CMPVUPD_CVUPD_Pos 0\r
+#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */\r
+#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))\r
+#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */\r
+/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */\r
+#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */\r
+#define PWM_CMPM_CTR_Pos 4\r
+#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */\r
+#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))\r
+#define PWM_CMPM_CPR_Pos 8\r
+#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */\r
+#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))\r
+#define PWM_CMPM_CPRCNT_Pos 12\r
+#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */\r
+#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))\r
+#define PWM_CMPM_CUPR_Pos 16\r
+#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */\r
+#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))\r
+#define PWM_CMPM_CUPRCNT_Pos 20\r
+#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */\r
+#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))\r
+/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */\r
+#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */\r
+#define PWM_CMPMUPD_CTRUPD_Pos 4\r
+#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */\r
+#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))\r
+#define PWM_CMPMUPD_CPRUPD_Pos 8\r
+#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */\r
+#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))\r
+#define PWM_CMPMUPD_CUPRUPD_Pos 16\r
+#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */\r
+#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))\r
+/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */\r
+#define PWM_CMR_CPRE_Pos 0\r
+#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */\r
+#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */\r
+#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */\r
+#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */\r
+#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */\r
+#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */\r
+#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */\r
+#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */\r
+#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */\r
+#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */\r
+#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */\r
+#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */\r
+#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */\r
+#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */\r
+#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */\r
+#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */\r
+#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */\r
+#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */\r
+#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */\r
+#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */\r
+/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */\r
+#define PWM_CDTY_CDTY_Pos 0\r
+#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */\r
+#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))\r
+/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */\r
+#define PWM_CDTYUPD_CDTYUPD_Pos 0\r
+#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */\r
+#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))\r
+/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */\r
+#define PWM_CPRD_CPRD_Pos 0\r
+#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */\r
+#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))\r
+/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */\r
+#define PWM_CPRDUPD_CPRDUPD_Pos 0\r
+#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */\r
+#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))\r
+/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */\r
+#define PWM_CCNT_CNT_Pos 0\r
+#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */\r
+/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */\r
+#define PWM_DT_DTH_Pos 0\r
+#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */\r
+#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))\r
+#define PWM_DT_DTL_Pos 16\r
+#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */\r
+#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))\r
+/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */\r
+#define PWM_DTUPD_DTHUPD_Pos 0\r
+#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */\r
+#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))\r
+#define PWM_DTUPD_DTLUPD_Pos 16\r
+#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */\r
+#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_PWM_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RSTC_COMPONENT_\r
+#define _SAM4S_RSTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Reset Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_RSTC Reset Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rstc hardware registers */\r
+typedef struct {\r
+ WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */\r
+ RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */\r
+ RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */\r
+} Rstc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */\r
+#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */\r
+#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */\r
+#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */\r
+#define RSTC_CR_KEY_Pos 24\r
+#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */\r
+#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))\r
+/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */\r
+#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */\r
+#define RSTC_SR_RSTTYP_Pos 8\r
+#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */\r
+#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */\r
+#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */\r
+/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */\r
+#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */\r
+#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */\r
+#define RSTC_MR_ERSTL_Pos 8\r
+#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */\r
+#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))\r
+#define RSTC_MR_KEY_Pos 24\r
+#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */\r
+#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_RSTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RTC_COMPONENT_\r
+#define _SAM4S_RTC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Clock */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_RTC Real-time Clock */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtc hardware registers */\r
+typedef struct {\r
+ RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */\r
+ RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */\r
+ RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */\r
+ RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */\r
+ RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */\r
+ RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */\r
+ RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */\r
+ WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */\r
+ WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */\r
+ WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */\r
+ RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */\r
+ RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */\r
+} Rtc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */\r
+#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */\r
+#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */\r
+#define RTC_CR_TIMEVSEL_Pos 8\r
+#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */\r
+#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */\r
+#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */\r
+#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */\r
+#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */\r
+#define RTC_CR_CALEVSEL_Pos 16\r
+#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */\r
+#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */\r
+#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */\r
+/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */\r
+#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */\r
+#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */\r
+#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */\r
+#define RTC_MR_CORRECTION_Pos 8\r
+#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) */\r
+#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))\r
+#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */\r
+#define RTC_MR_OUT0_Pos 16\r
+#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */\r
+#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_OUT1_Pos 20\r
+#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */\r
+#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */\r
+#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */\r
+#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */\r
+#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */\r
+#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */\r
+#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */\r
+#define RTC_MR_THIGH_Pos 24\r
+#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */\r
+#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */\r
+#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */\r
+#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */\r
+#define RTC_MR_THIGH_H_967US (0x3u << 24) /**< \brief (RTC_MR) 967 \xb5 s */\r
+#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 \xb5 s */\r
+#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 \xb5 s */\r
+#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 \xb5 s */\r
+#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 \xb5 s */\r
+#define RTC_MR_TPERIOD_Pos 28\r
+#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */\r
+#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */\r
+#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */\r
+#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */\r
+#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */\r
+/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */\r
+#define RTC_TIMR_SEC_Pos 0\r
+#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */\r
+#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))\r
+#define RTC_TIMR_MIN_Pos 8\r
+#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */\r
+#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))\r
+#define RTC_TIMR_HOUR_Pos 16\r
+#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */\r
+#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))\r
+#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */\r
+/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */\r
+#define RTC_CALR_CENT_Pos 0\r
+#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */\r
+#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))\r
+#define RTC_CALR_YEAR_Pos 8\r
+#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */\r
+#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))\r
+#define RTC_CALR_MONTH_Pos 16\r
+#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */\r
+#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))\r
+#define RTC_CALR_DAY_Pos 21\r
+#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */\r
+#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))\r
+#define RTC_CALR_DATE_Pos 24\r
+#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */\r
+#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))\r
+/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */\r
+#define RTC_TIMALR_SEC_Pos 0\r
+#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */\r
+#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))\r
+#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */\r
+#define RTC_TIMALR_MIN_Pos 8\r
+#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */\r
+#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))\r
+#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */\r
+#define RTC_TIMALR_HOUR_Pos 16\r
+#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */\r
+#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))\r
+#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */\r
+#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */\r
+/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */\r
+#define RTC_CALALR_MONTH_Pos 16\r
+#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */\r
+#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))\r
+#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */\r
+#define RTC_CALALR_DATE_Pos 24\r
+#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */\r
+#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))\r
+#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */\r
+/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */\r
+#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */\r
+#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */\r
+#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */\r
+#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */\r
+#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */\r
+/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */\r
+#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */\r
+#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */\r
+#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */\r
+#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */\r
+#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */\r
+/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */\r
+#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */\r
+#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */\r
+#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */\r
+#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */\r
+#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */\r
+/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */\r
+#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */\r
+#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */\r
+#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */\r
+#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */\r
+#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */\r
+/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */\r
+#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */\r
+#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */\r
+#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */\r
+#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */\r
+#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */\r
+/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */\r
+#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */\r
+#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */\r
+#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */\r
+#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_RTC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RTT_COMPONENT_\r
+#define _SAM4S_RTT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Real-time Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_RTT Real-time Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Rtt hardware registers */\r
+typedef struct {\r
+ RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */\r
+ RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */\r
+ RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */\r
+ RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */\r
+} Rtt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */\r
+#define RTT_MR_RTPRES_Pos 0\r
+#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */\r
+#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))\r
+#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */\r
+#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */\r
+#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */\r
+/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */\r
+#define RTT_AR_ALMV_Pos 0\r
+#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */\r
+#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))\r
+/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */\r
+#define RTT_VR_CRTV_Pos 0\r
+#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */\r
+/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */\r
+#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */\r
+#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_RTT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SMC_COMPONENT_\r
+#define _SAM4S_SMC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Static Memory Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_SMC Static Memory Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief SmcCs_number hardware registers */\r
+typedef struct {\r
+ RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */\r
+ RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */\r
+ RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */\r
+ RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */\r
+} SmcCs_number;\r
+/** \brief Smc hardware registers */\r
+#define SMCCS_NUMBER_NUMBER 5\r
+typedef struct {\r
+ SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */\r
+ RoReg Reserved1[12];\r
+ RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */\r
+ WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */\r
+ WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */\r
+ RoReg Reserved2[22];\r
+ RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */\r
+ RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */\r
+} Smc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */\r
+#define SMC_SETUP_NWE_SETUP_Pos 0\r
+#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */\r
+#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_WR_SETUP_Pos 8\r
+#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */\r
+#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))\r
+#define SMC_SETUP_NRD_SETUP_Pos 16\r
+#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */\r
+#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))\r
+#define SMC_SETUP_NCS_RD_SETUP_Pos 24\r
+#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */\r
+#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))\r
+/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */\r
+#define SMC_PULSE_NWE_PULSE_Pos 0\r
+#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */\r
+#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_WR_PULSE_Pos 8\r
+#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */\r
+#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))\r
+#define SMC_PULSE_NRD_PULSE_Pos 16\r
+#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */\r
+#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))\r
+#define SMC_PULSE_NCS_RD_PULSE_Pos 24\r
+#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */\r
+#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))\r
+/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */\r
+#define SMC_CYCLE_NWE_CYCLE_Pos 0\r
+#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */\r
+#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))\r
+#define SMC_CYCLE_NRD_CYCLE_Pos 16\r
+#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */\r
+#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))\r
+/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */\r
+#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */\r
+#define SMC_MODE_EXNW_MODE_Pos 4\r
+#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */\r
+#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */\r
+#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */\r
+#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */\r
+#define SMC_MODE_DBW_Pos 12\r
+#define SMC_MODE_DBW_Msk (0x3u << SMC_MODE_DBW_Pos) /**< \brief (SMC_MODE) Data Bus Width */\r
+#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */\r
+#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */\r
+#define SMC_MODE_DBW_32_BIT (0x2u << 12) /**< \brief (SMC_MODE) 32-bit bus */\r
+#define SMC_MODE_TDF_CYCLES_Pos 16\r
+#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */\r
+#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))\r
+#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */\r
+#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */\r
+#define SMC_MODE_PS_Pos 28\r
+#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */\r
+#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */\r
+#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */\r
+#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */\r
+#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */\r
+/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */\r
+#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */\r
+#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */\r
+/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */\r
+#define SMC_KEY1_KEY1_Pos 0\r
+#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */\r
+#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))\r
+/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */\r
+#define SMC_KEY2_KEY2_Pos 0\r
+#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */\r
+#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))\r
+/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */\r
+#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */\r
+#define SMC_WPMR_WPKEY_Pos 8\r
+#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */\r
+#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))\r
+/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */\r
+#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */\r
+#define SMC_WPSR_WPVSRC_Pos 8\r
+#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_SMC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SPI_COMPONENT_\r
+#define _SAM4S_SPI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_SPI Serial Peripheral Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Spi hardware registers */\r
+typedef struct {\r
+ WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */\r
+ RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */\r
+ RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */\r
+ WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */\r
+ RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */\r
+ WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */\r
+ WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */\r
+ RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */\r
+ RoReg Reserved1[4];\r
+ RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */\r
+ RoReg Reserved2[41];\r
+ RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */\r
+ RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */\r
+ RoReg Reserved3[5];\r
+ RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */\r
+ RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */\r
+ RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */\r
+ RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */\r
+} Spi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */\r
+#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */\r
+#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */\r
+#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */\r
+#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */\r
+/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */\r
+#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */\r
+#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */\r
+#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */\r
+#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */\r
+#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */\r
+#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */\r
+#define SPI_MR_PCS_Pos 16\r
+#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */\r
+#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))\r
+#define SPI_MR_DLYBCS_Pos 24\r
+#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */\r
+#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))\r
+/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */\r
+#define SPI_RDR_RD_Pos 0\r
+#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */\r
+#define SPI_RDR_PCS_Pos 16\r
+#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */\r
+/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */\r
+#define SPI_TDR_TD_Pos 0\r
+#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */\r
+#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))\r
+#define SPI_TDR_PCS_Pos 16\r
+#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */\r
+#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))\r
+#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */\r
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */\r
+#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */\r
+#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */\r
+#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */\r
+#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */\r
+#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */\r
+#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */\r
+#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */\r
+#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */\r
+#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */\r
+#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */\r
+#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */\r
+#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */\r
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */\r
+#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */\r
+#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */\r
+#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */\r
+#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */\r
+#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */\r
+#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */\r
+#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */\r
+#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */\r
+#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */\r
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */\r
+#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */\r
+#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */\r
+#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */\r
+#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */\r
+#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */\r
+#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */\r
+#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */\r
+/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */\r
+#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */\r
+#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */\r
+#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */\r
+#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */\r
+#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */\r
+#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */\r
+#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */\r
+/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */\r
+#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */\r
+#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */\r
+#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */\r
+#define SPI_CSR_BITS_Pos 4\r
+#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */\r
+#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */\r
+#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */\r
+#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */\r
+#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */\r
+#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */\r
+#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */\r
+#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */\r
+#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */\r
+#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */\r
+#define SPI_CSR_SCBR_Pos 8\r
+#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */\r
+#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))\r
+#define SPI_CSR_DLYBS_Pos 16\r
+#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */\r
+#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))\r
+#define SPI_CSR_DLYBCT_Pos 24\r
+#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */\r
+#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))\r
+/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */\r
+#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */\r
+#define SPI_WPMR_WPKEY_Pos 8\r
+#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */\r
+#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))\r
+/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */\r
+#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVS_Pos 0\r
+#define SPI_WPSR_WPVS_Msk (0x1u << SPI_WPSR_WPVS_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Status */\r
+#define SPI_WPSR_WPVSRC_Pos 8\r
+#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */\r
+/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */\r
+#define SPI_RPR_RXPTR_Pos 0\r
+#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */\r
+#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))\r
+/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */\r
+#define SPI_RCR_RXCTR_Pos 0\r
+#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */\r
+#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))\r
+/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define SPI_TPR_TXPTR_Pos 0\r
+#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */\r
+#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))\r
+/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define SPI_TCR_TXCTR_Pos 0\r
+#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */\r
+#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))\r
+/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define SPI_RNPR_RXNPTR_Pos 0\r
+#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */\r
+#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))\r
+/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define SPI_RNCR_RXNCTR_Pos 0\r
+#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */\r
+#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))\r
+/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define SPI_TNPR_TXNPTR_Pos 0\r
+#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */\r
+#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))\r
+/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define SPI_TNCR_TXNCTR_Pos 0\r
+#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */\r
+#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))\r
+/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */\r
+#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */\r
+#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */\r
+#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */\r
+#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */\r
+/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */\r
+#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */\r
+#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_SPI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SSC_COMPONENT_\r
+#define _SAM4S_SSC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_SSC Synchronous Serial Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Ssc hardware registers */\r
+typedef struct {\r
+ WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */\r
+ RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */\r
+ RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */\r
+ RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */\r
+ RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */\r
+ RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */\r
+ WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */\r
+ RoReg Reserved2[2];\r
+ RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */\r
+ RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */\r
+ RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */\r
+ RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */\r
+ RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */\r
+ WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */\r
+ WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */\r
+ RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */\r
+ RoReg Reserved3[37];\r
+ RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[5];\r
+ RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */\r
+ RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */\r
+ RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */\r
+ RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */\r
+ RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */\r
+ RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */\r
+ RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */\r
+} Ssc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */\r
+#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */\r
+#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */\r
+#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */\r
+#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */\r
+#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */\r
+/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */\r
+#define SSC_CMR_DIV_Pos 0\r
+#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */\r
+#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))\r
+/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */\r
+#define SSC_RCMR_CKS_Pos 0\r
+#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */\r
+#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */\r
+#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */\r
+#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */\r
+#define SSC_RCMR_CKO_Pos 2\r
+#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */\r
+#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */\r
+#define SSC_RCMR_CKG_Pos 6\r
+#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */\r
+#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */\r
+#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */\r
+#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */\r
+#define SSC_RCMR_START_Pos 8\r
+#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */\r
+#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */\r
+#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */\r
+#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */\r
+#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */\r
+#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */\r
+#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */\r
+#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */\r
+#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */\r
+#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */\r
+#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */\r
+#define SSC_RCMR_STTDLY_Pos 16\r
+#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */\r
+#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))\r
+#define SSC_RCMR_PERIOD_Pos 24\r
+#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */\r
+#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))\r
+/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */\r
+#define SSC_RFMR_DATLEN_Pos 0\r
+#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */\r
+#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))\r
+#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */\r
+#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */\r
+#define SSC_RFMR_DATNB_Pos 8\r
+#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */\r
+#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))\r
+#define SSC_RFMR_FSLEN_Pos 16\r
+#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */\r
+#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))\r
+#define SSC_RFMR_FSOS_Pos 20\r
+#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */\r
+#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */\r
+#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */\r
+#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */\r
+#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */\r
+#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */\r
+#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */\r
+#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */\r
+#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */\r
+#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */\r
+#define SSC_RFMR_FSLEN_EXT_Pos 28\r
+#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */\r
+#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */\r
+#define SSC_TCMR_CKS_Pos 0\r
+#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */\r
+#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */\r
+#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */\r
+#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */\r
+#define SSC_TCMR_CKO_Pos 2\r
+#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */\r
+#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */\r
+#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */\r
+#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */\r
+#define SSC_TCMR_CKG_Pos 6\r
+#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */\r
+#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */\r
+#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */\r
+#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */\r
+#define SSC_TCMR_START_Pos 8\r
+#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */\r
+#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */\r
+#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */\r
+#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */\r
+#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */\r
+#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */\r
+#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */\r
+#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */\r
+#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */\r
+#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */\r
+#define SSC_TCMR_STTDLY_Pos 16\r
+#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */\r
+#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))\r
+#define SSC_TCMR_PERIOD_Pos 24\r
+#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */\r
+#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))\r
+/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */\r
+#define SSC_TFMR_DATLEN_Pos 0\r
+#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */\r
+#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))\r
+#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */\r
+#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */\r
+#define SSC_TFMR_DATNB_Pos 8\r
+#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */\r
+#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))\r
+#define SSC_TFMR_FSLEN_Pos 16\r
+#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */\r
+#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))\r
+#define SSC_TFMR_FSOS_Pos 20\r
+#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */\r
+#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */\r
+#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */\r
+#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */\r
+#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */\r
+#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */\r
+#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */\r
+#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */\r
+#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */\r
+#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */\r
+#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */\r
+#define SSC_TFMR_FSLEN_EXT_Pos 28\r
+#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */\r
+#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))\r
+/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */\r
+#define SSC_RHR_RDAT_Pos 0\r
+#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */\r
+/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */\r
+#define SSC_THR_TDAT_Pos 0\r
+#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */\r
+#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))\r
+/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */\r
+#define SSC_RSHR_RSDAT_Pos 0\r
+#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */\r
+/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */\r
+#define SSC_TSHR_TSDAT_Pos 0\r
+#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */\r
+#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))\r
+/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */\r
+#define SSC_RC0R_CP0_Pos 0\r
+#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */\r
+#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))\r
+/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */\r
+#define SSC_RC1R_CP1_Pos 0\r
+#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */\r
+#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))\r
+/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */\r
+#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */\r
+#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */\r
+#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */\r
+#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */\r
+#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */\r
+#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */\r
+#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */\r
+#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */\r
+#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */\r
+#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */\r
+#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */\r
+#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */\r
+#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */\r
+#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */\r
+/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */\r
+#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */\r
+#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */\r
+#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */\r
+#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */\r
+#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */\r
+#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */\r
+#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */\r
+#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */\r
+#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */\r
+#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */\r
+#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */\r
+#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */\r
+#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */\r
+#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */\r
+#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */\r
+#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */\r
+#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */\r
+#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */\r
+#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */\r
+#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */\r
+#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */\r
+#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */\r
+#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */\r
+#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */\r
+/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */\r
+#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */\r
+#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */\r
+#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */\r
+#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */\r
+#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */\r
+#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */\r
+#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */\r
+#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */\r
+#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */\r
+#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */\r
+#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */\r
+#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */\r
+/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */\r
+#define SSC_WPMR_WPKEY_Pos 8\r
+#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */\r
+#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))\r
+/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */\r
+#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */\r
+#define SSC_WPSR_WPVSRC_Pos 8\r
+#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */\r
+/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */\r
+#define SSC_RPR_RXPTR_Pos 0\r
+#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */\r
+#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos)))\r
+/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */\r
+#define SSC_RCR_RXCTR_Pos 0\r
+#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */\r
+#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos)))\r
+/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */\r
+#define SSC_TPR_TXPTR_Pos 0\r
+#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */\r
+#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos)))\r
+/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */\r
+#define SSC_TCR_TXCTR_Pos 0\r
+#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */\r
+#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos)))\r
+/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define SSC_RNPR_RXNPTR_Pos 0\r
+#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */\r
+#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos)))\r
+/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */\r
+#define SSC_RNCR_RXNCTR_Pos 0\r
+#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */\r
+#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos)))\r
+/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define SSC_TNPR_TXNPTR_Pos 0\r
+#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */\r
+#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos)))\r
+/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define SSC_TNCR_TXNCTR_Pos 0\r
+#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */\r
+#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos)))\r
+/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */\r
+#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */\r
+#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */\r
+#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */\r
+#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */\r
+/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */\r
+#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */\r
+#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_SSC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SUPC_COMPONENT_\r
+#define _SAM4S_SUPC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Supply Controller */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_SUPC Supply Controller */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Supc hardware registers */\r
+typedef struct {\r
+ WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */\r
+ RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */\r
+ RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */\r
+ RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */\r
+ RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */\r
+ RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */\r
+} Supc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */\r
+#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */\r
+#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */\r
+#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */\r
+#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */\r
+#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */\r
+#define SUPC_CR_KEY_Pos 24\r
+#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */\r
+#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))\r
+/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */\r
+#define SUPC_SMMR_SMTH_Pos 0\r
+#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */\r
+#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */\r
+#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */\r
+#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */\r
+#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */\r
+#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */\r
+#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */\r
+#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */\r
+#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */\r
+#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */\r
+#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */\r
+#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */\r
+#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */\r
+#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */\r
+#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */\r
+#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */\r
+#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */\r
+#define SUPC_SMMR_SMSMPL_Pos 8\r
+#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */\r
+#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */\r
+#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */\r
+#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */\r
+#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */\r
+#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */\r
+#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */\r
+#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */\r
+#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */\r
+/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */\r
+#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */\r
+#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */\r
+#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */\r
+#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */\r
+#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */\r
+#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */\r
+#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */\r
+#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */\r
+#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */\r
+#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */\r
+#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */\r
+#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */\r
+#define SUPC_MR_KEY_Pos 24\r
+#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */\r
+#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))\r
+/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */\r
+#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */\r
+#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */\r
+#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */\r
+#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */\r
+#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */\r
+#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */\r
+#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */\r
+#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force the a core wake up. */\r
+#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */\r
+#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */\r
+#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force the a core wake up. */\r
+#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */\r
+#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on half GPBR registers. */\r
+#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on half GPBR registers. */\r
+#define SUPC_WUMR_WKUPDBC_Pos 12\r
+#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */\r
+#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */\r
+#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */\r
+#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */\r
+#define SUPC_WUMR_LPDBC_Pos 16\r
+#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */\r
+#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */\r
+#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */\r
+#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */\r
+/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */\r
+#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */\r
+#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */\r
+#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */\r
+#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */\r
+#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */\r
+#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */\r
+#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */\r
+#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */\r
+#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */\r
+#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */\r
+#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */\r
+#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */\r
+#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */\r
+#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */\r
+#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */\r
+#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */\r
+#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */\r
+#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */\r
+#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */\r
+#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */\r
+#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */\r
+#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */\r
+#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */\r
+#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */\r
+#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */\r
+#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */\r
+#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */\r
+#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */\r
+#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */\r
+#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */\r
+#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */\r
+#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */\r
+#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */\r
+#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */\r
+/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */\r
+#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */\r
+#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */\r
+#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */\r
+#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */\r
+#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */\r
+#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */\r
+#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */\r
+#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */\r
+#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */\r
+#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */\r
+#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */\r
+#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */\r
+#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */\r
+#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */\r
+#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */\r
+#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */\r
+#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */\r
+#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */\r
+#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */\r
+#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */\r
+#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */\r
+#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */\r
+#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */\r
+#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */\r
+#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */\r
+#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */\r
+#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */\r
+#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */\r
+#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */\r
+#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */\r
+#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */\r
+#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */\r
+#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */\r
+#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_SUPC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TC_COMPONENT_\r
+#define _SAM4S_TC_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Timer Counter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_TC Timer Counter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief TcChannel hardware registers */\r
+typedef struct {\r
+ RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */\r
+ RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */\r
+ RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */\r
+ RoReg Reserved1[1];\r
+ RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */\r
+ RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */\r
+ RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */\r
+ RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */\r
+ RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */\r
+ RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */\r
+ RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */\r
+ RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg Reserved2[4];\r
+} TcChannel;\r
+/** \brief Tc hardware registers */\r
+#define TCCHANNEL_NUMBER 3\r
+typedef struct {\r
+ TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */\r
+ WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */\r
+ RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */\r
+ WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */\r
+ WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */\r
+ RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */\r
+ RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */\r
+ RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */\r
+ RoReg Reserved1[2];\r
+ RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */\r
+} Tc;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */\r
+#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */\r
+#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */\r
+#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */\r
+/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */\r
+#define TC_CMR_TCCLKS_Pos 0\r
+#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */\r
+#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */\r
+#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */\r
+#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */\r
+#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */\r
+#define TC_CMR_BURST_Pos 4\r
+#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */\r
+#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */\r
+#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */\r
+#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */\r
+#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */\r
+#define TC_CMR_ETRGEDG_Pos 8\r
+#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */\r
+#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */\r
+#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */\r
+#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */\r
+#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) */\r
+#define TC_CMR_LDRA_Pos 16\r
+#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Selection */\r
+#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_LDRB_Pos 18\r
+#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Selection */\r
+#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */\r
+#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */\r
+#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */\r
+#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */\r
+#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */\r
+#define TC_CMR_EEVTEDG_Pos 8\r
+#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */\r
+#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */\r
+#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */\r
+#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */\r
+#define TC_CMR_EEVT_Pos 10\r
+#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */\r
+#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */\r
+#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */\r
+#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */\r
+#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */\r
+#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */\r
+#define TC_CMR_WAVSEL_Pos 13\r
+#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */\r
+#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */\r
+#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */\r
+#define TC_CMR_ACPA_Pos 16\r
+#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */\r
+#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ACPC_Pos 18\r
+#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */\r
+#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_AEEVT_Pos 20\r
+#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */\r
+#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_ASWTRG_Pos 22\r
+#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */\r
+#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPB_Pos 24\r
+#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */\r
+#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BCPC_Pos 26\r
+#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */\r
+#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BEEVT_Pos 28\r
+#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */\r
+#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */\r
+#define TC_CMR_BSWTRG_Pos 30\r
+#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */\r
+#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */\r
+#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */\r
+#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */\r
+#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */\r
+/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */\r
+#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */\r
+#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */\r
+/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */\r
+#define TC_CV_CV_Pos 0\r
+#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */\r
+/* -------- TC_RA : (TC Offset: N/A) Register A -------- */\r
+#define TC_RA_RA_Pos 0\r
+#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */\r
+#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))\r
+/* -------- TC_RB : (TC Offset: N/A) Register B -------- */\r
+#define TC_RB_RB_Pos 0\r
+#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */\r
+#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))\r
+/* -------- TC_RC : (TC Offset: N/A) Register C -------- */\r
+#define TC_RC_RC_Pos 0\r
+#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */\r
+#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))\r
+/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */\r
+#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */\r
+#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */\r
+#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */\r
+#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */\r
+#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */\r
+#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */\r
+#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */\r
+#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */\r
+#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */\r
+#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */\r
+#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */\r
+/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */\r
+#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */\r
+#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */\r
+#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */\r
+#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */\r
+#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */\r
+#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */\r
+#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */\r
+#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */\r
+/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */\r
+#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */\r
+#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */\r
+#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */\r
+#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */\r
+#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */\r
+#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */\r
+#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */\r
+#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */\r
+/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */\r
+#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */\r
+#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */\r
+#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */\r
+#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */\r
+#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */\r
+#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */\r
+#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */\r
+#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */\r
+/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */\r
+#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */\r
+/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */\r
+#define TC_BMR_TC0XC0S_Pos 0\r
+#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */\r
+#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */\r
+#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */\r
+#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */\r
+#define TC_BMR_TC1XC1S_Pos 2\r
+#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */\r
+#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */\r
+#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */\r
+#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */\r
+#define TC_BMR_TC2XC2S_Pos 4\r
+#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */\r
+#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */\r
+#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */\r
+#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */\r
+#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */\r
+#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */\r
+#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */\r
+#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */\r
+#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */\r
+#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */\r
+#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */\r
+#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */\r
+#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */\r
+#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */\r
+#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */\r
+#define TC_BMR_MAXFILT_Pos 20\r
+#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */\r
+#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))\r
+/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */\r
+#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */\r
+#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */\r
+#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */\r
+/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */\r
+#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */\r
+#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */\r
+#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */\r
+/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */\r
+#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */\r
+#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */\r
+#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */\r
+/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */\r
+#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */\r
+#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */\r
+#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */\r
+#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */\r
+/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */\r
+#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */\r
+#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */\r
+/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */\r
+#define TC_WPMR_WPKEY_Pos 8\r
+#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */\r
+#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_TC_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TWI_COMPONENT_\r
+#define _SAM4S_TWI_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Two-wire Interface */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_TWI Two-wire Interface */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Twi hardware registers */\r
+typedef struct {\r
+ WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */\r
+ RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */\r
+ RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */\r
+ RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */\r
+ RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */\r
+ RoReg Reserved1[3];\r
+ RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */\r
+ WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */\r
+ WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */\r
+ RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */\r
+ RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */\r
+ WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */\r
+ RoReg Reserved2[50];\r
+ RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */\r
+ RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */\r
+ RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */\r
+ RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */\r
+ RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */\r
+ RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */\r
+ RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */\r
+} Twi;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */\r
+#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */\r
+#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */\r
+#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */\r
+#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */\r
+#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */\r
+#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */\r
+#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */\r
+#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */\r
+/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */\r
+#define TWI_MMR_IADRSZ_Pos 8\r
+#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */\r
+#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */\r
+#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */\r
+#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */\r
+#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */\r
+#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */\r
+#define TWI_MMR_DADR_Pos 16\r
+#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */\r
+#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))\r
+/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */\r
+#define TWI_SMR_SADR_Pos 16\r
+#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */\r
+#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))\r
+/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */\r
+#define TWI_IADR_IADR_Pos 0\r
+#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */\r
+#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))\r
+/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */\r
+#define TWI_CWGR_CLDIV_Pos 0\r
+#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */\r
+#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))\r
+#define TWI_CWGR_CHDIV_Pos 8\r
+#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */\r
+#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))\r
+#define TWI_CWGR_CKDIV_Pos 16\r
+#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */\r
+#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))\r
+/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */\r
+#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */\r
+#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */\r
+#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */\r
+#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */\r
+#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */\r
+#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */\r
+#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */\r
+#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */\r
+#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */\r
+#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */\r
+#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */\r
+#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */\r
+#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */\r
+#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */\r
+/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */\r
+#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */\r
+#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */\r
+#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */\r
+#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */\r
+#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */\r
+#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */\r
+#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */\r
+#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */\r
+#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */\r
+#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */\r
+#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */\r
+#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */\r
+#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */\r
+/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */\r
+#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */\r
+#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */\r
+#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */\r
+#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */\r
+#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */\r
+#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */\r
+#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */\r
+#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */\r
+#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */\r
+#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */\r
+#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */\r
+#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */\r
+#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */\r
+/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */\r
+#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */\r
+#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */\r
+#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */\r
+#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */\r
+#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */\r
+#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */\r
+#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */\r
+#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */\r
+#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */\r
+#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */\r
+#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */\r
+#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */\r
+#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */\r
+/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */\r
+#define TWI_RHR_RXDATA_Pos 0\r
+#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */\r
+/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */\r
+#define TWI_THR_TXDATA_Pos 0\r
+#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */\r
+#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))\r
+/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */\r
+#define TWI_RPR_RXPTR_Pos 0\r
+#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */\r
+#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))\r
+/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */\r
+#define TWI_RCR_RXCTR_Pos 0\r
+#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */\r
+#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))\r
+/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */\r
+#define TWI_TPR_TXPTR_Pos 0\r
+#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */\r
+#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))\r
+/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */\r
+#define TWI_TCR_TXCTR_Pos 0\r
+#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */\r
+#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))\r
+/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define TWI_RNPR_RXNPTR_Pos 0\r
+#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */\r
+#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))\r
+/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */\r
+#define TWI_RNCR_RXNCTR_Pos 0\r
+#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */\r
+#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))\r
+/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define TWI_TNPR_TXNPTR_Pos 0\r
+#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */\r
+#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))\r
+/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define TWI_TNCR_TXNCTR_Pos 0\r
+#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */\r
+#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))\r
+/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */\r
+#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */\r
+#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */\r
+#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */\r
+#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */\r
+/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */\r
+#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */\r
+#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_TWI_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_UART_COMPONENT_\r
+#define _SAM4S_UART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_UART Universal Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Uart hardware registers */\r
+typedef struct {\r
+ WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */\r
+ RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */\r
+ WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */\r
+ RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */\r
+ WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */\r
+ RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */\r
+ RoReg Reserved1[55];\r
+ RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */\r
+ RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */\r
+ RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */\r
+ RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */\r
+} Uart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */\r
+#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */\r
+#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */\r
+#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */\r
+#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */\r
+#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */\r
+#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */\r
+#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */\r
+/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */\r
+#define UART_MR_PAR_Pos 9\r
+#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */\r
+#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */\r
+#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */\r
+#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */\r
+#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */\r
+#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */\r
+#define UART_MR_CHMODE_Pos 14\r
+#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */\r
+#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */\r
+#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */\r
+#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */\r
+#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */\r
+/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */\r
+#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */\r
+#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */\r
+#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */\r
+#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */\r
+#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */\r
+#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */\r
+#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */\r
+#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */\r
+#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */\r
+/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */\r
+#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */\r
+#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */\r
+#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */\r
+#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */\r
+#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */\r
+#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */\r
+#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */\r
+#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */\r
+#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */\r
+/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */\r
+#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */\r
+#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */\r
+#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */\r
+#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */\r
+#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */\r
+#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */\r
+#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */\r
+#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */\r
+#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */\r
+/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */\r
+#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */\r
+#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */\r
+#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */\r
+#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */\r
+#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */\r
+#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */\r
+#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */\r
+#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */\r
+#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */\r
+#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */\r
+/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */\r
+#define UART_RHR_RXCHR_Pos 0\r
+#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */\r
+/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */\r
+#define UART_THR_TXCHR_Pos 0\r
+#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */\r
+#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))\r
+/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define UART_BRGR_CD_Pos 0\r
+#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */\r
+#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))\r
+/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */\r
+#define UART_RPR_RXPTR_Pos 0\r
+#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */\r
+#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))\r
+/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */\r
+#define UART_RCR_RXCTR_Pos 0\r
+#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */\r
+#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))\r
+/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define UART_TPR_TXPTR_Pos 0\r
+#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */\r
+#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))\r
+/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define UART_TCR_TXCTR_Pos 0\r
+#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */\r
+#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))\r
+/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define UART_RNPR_RXNPTR_Pos 0\r
+#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */\r
+#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))\r
+/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define UART_RNCR_RXNCTR_Pos 0\r
+#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */\r
+#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))\r
+/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define UART_TNPR_TXNPTR_Pos 0\r
+#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */\r
+#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))\r
+/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define UART_TNCR_TXNCTR_Pos 0\r
+#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */\r
+#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))\r
+/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */\r
+#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */\r
+#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */\r
+#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */\r
+#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */\r
+/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */\r
+#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */\r
+#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_UART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_UDP_COMPONENT_\r
+#define _SAM4S_UDP_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR USB Device Port */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_UDP USB Device Port */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Udp hardware registers */\r
+typedef struct {\r
+ RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */\r
+ RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */\r
+ RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */\r
+ RoReg Reserved1[1];\r
+ WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */\r
+ WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */\r
+ RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */\r
+ RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */\r
+ WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */\r
+ RoReg Reserved2[1];\r
+ RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */\r
+ RoReg Reserved3[1];\r
+ RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */\r
+ RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */\r
+ RoReg Reserved4[1];\r
+ RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */\r
+} Udp;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */\r
+#define UDP_FRM_NUM_FRM_NUM_Pos 0\r
+#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */\r
+#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */\r
+#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */\r
+/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */\r
+#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */\r
+#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */\r
+#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */\r
+#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */\r
+#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */\r
+/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */\r
+#define UDP_FADDR_FADD_Pos 0\r
+#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */\r
+#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos)))\r
+#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */\r
+/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */\r
+#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */\r
+#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */\r
+#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */\r
+#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */\r
+#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */\r
+#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */\r
+#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */\r
+#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */\r
+#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */\r
+#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */\r
+#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */\r
+#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */\r
+#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */\r
+/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */\r
+#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */\r
+#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */\r
+#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */\r
+#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */\r
+#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */\r
+#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */\r
+#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */\r
+#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */\r
+#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */\r
+#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */\r
+#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */\r
+#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */\r
+#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */\r
+/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */\r
+#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */\r
+#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */\r
+#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */\r
+#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */\r
+#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */\r
+#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */\r
+#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */\r
+#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */\r
+#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */\r
+#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */\r
+#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */\r
+#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */\r
+#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */\r
+#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */\r
+/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */\r
+#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */\r
+#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */\r
+#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */\r
+#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */\r
+#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */\r
+#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */\r
+#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */\r
+#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */\r
+#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */\r
+#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */\r
+#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */\r
+#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */\r
+#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */\r
+/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */\r
+#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */\r
+#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */\r
+#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */\r
+#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */\r
+#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */\r
+#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */\r
+/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */\r
+#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */\r
+#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */\r
+#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */\r
+#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */\r
+#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */\r
+#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */\r
+#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */\r
+#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */\r
+/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */\r
+#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */\r
+#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */\r
+#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */\r
+#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */\r
+#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) */\r
+#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */\r
+#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */\r
+#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */\r
+#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */\r
+#define UDP_CSR_EPTYPE_Pos 8\r
+#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */\r
+#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */\r
+#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */\r
+#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */\r
+#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */\r
+#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */\r
+#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */\r
+#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */\r
+#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */\r
+#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */\r
+#define UDP_CSR_RXBYTECNT_Pos 16\r
+#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */\r
+#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos)))\r
+/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */\r
+#define UDP_FDR_FIFO_DATA_Pos 0\r
+#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */\r
+#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos)))\r
+/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */\r
+#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */\r
+#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pullup On */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_UDP_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_USART_COMPONENT_\r
+#define _SAM4S_USART_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_USART Universal Synchronous Asynchronous Receiver Transmitter */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Usart hardware registers */\r
+typedef struct {\r
+ WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */\r
+ RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */\r
+ WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */\r
+ WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */\r
+ RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */\r
+ RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */\r
+ RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */\r
+ WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */\r
+ RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */\r
+ RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */\r
+ RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */\r
+ RoReg Reserved1[5];\r
+ RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */\r
+ RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */\r
+ RoReg Reserved2[1];\r
+ RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */\r
+ RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */\r
+ RoReg Reserved3[36];\r
+ RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */\r
+ RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */\r
+ RoReg Reserved4[4];\r
+ RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */\r
+ RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */\r
+ RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */\r
+ RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */\r
+ RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */\r
+ RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */\r
+ RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */\r
+ RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */\r
+ RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */\r
+ WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */\r
+ RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */\r
+} Usart;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */\r
+#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */\r
+#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */\r
+#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */\r
+#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */\r
+#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */\r
+#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */\r
+#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */\r
+#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */\r
+#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */\r
+#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */\r
+#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */\r
+#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */\r
+#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */\r
+#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */\r
+#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */\r
+#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */\r
+#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */\r
+#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */\r
+#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */\r
+#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */\r
+/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */\r
+#define US_MR_USART_MODE_Pos 0\r
+#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */\r
+#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */\r
+#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */\r
+#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */\r
+#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */\r
+#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */\r
+#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */\r
+#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */\r
+#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */\r
+#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */\r
+#define US_MR_USCLKS_Pos 4\r
+#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */\r
+#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */\r
+#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */\r
+#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */\r
+#define US_MR_CHRL_Pos 6\r
+#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */\r
+#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */\r
+#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */\r
+#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */\r
+#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */\r
+#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */\r
+#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */\r
+#define US_MR_PAR_Pos 9\r
+#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */\r
+#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */\r
+#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */\r
+#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */\r
+#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */\r
+#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */\r
+#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */\r
+#define US_MR_NBSTOP_Pos 12\r
+#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */\r
+#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */\r
+#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */\r
+#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */\r
+#define US_MR_CHMODE_Pos 14\r
+#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */\r
+#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */\r
+#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */\r
+#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */\r
+#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */\r
+#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */\r
+#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */\r
+#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */\r
+#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */\r
+#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */\r
+#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */\r
+#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */\r
+#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */\r
+#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */\r
+#define US_MR_MAX_ITERATION_Pos 24\r
+#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */\r
+#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))\r
+#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */\r
+#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */\r
+#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */\r
+#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */\r
+/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */\r
+#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */\r
+#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */\r
+#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */\r
+#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */\r
+#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */\r
+#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */\r
+#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */\r
+#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */\r
+#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */\r
+#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */\r
+#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */\r
+#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */\r
+#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */\r
+#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */\r
+#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */\r
+#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */\r
+#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */\r
+#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */\r
+#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */\r
+#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */\r
+/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */\r
+#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */\r
+#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */\r
+#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */\r
+#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */\r
+#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */\r
+#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */\r
+#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */\r
+#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */\r
+#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */\r
+#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */\r
+#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */\r
+#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */\r
+#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */\r
+#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */\r
+#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */\r
+#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */\r
+#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */\r
+#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */\r
+#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */\r
+#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */\r
+/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */\r
+#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */\r
+#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */\r
+#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */\r
+#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */\r
+#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */\r
+#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */\r
+#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */\r
+#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */\r
+#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */\r
+#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */\r
+#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */\r
+#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */\r
+#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */\r
+#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */\r
+#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */\r
+#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */\r
+#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */\r
+#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */\r
+#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */\r
+#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */\r
+/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */\r
+#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */\r
+#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */\r
+#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */\r
+#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */\r
+#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */\r
+#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */\r
+#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */\r
+#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */\r
+#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */\r
+#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */\r
+#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */\r
+#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */\r
+#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */\r
+#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */\r
+#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */\r
+#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */\r
+#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */\r
+#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */\r
+#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */\r
+#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */\r
+#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */\r
+#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */\r
+#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */\r
+#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */\r
+/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */\r
+#define US_RHR_RXCHR_Pos 0\r
+#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */\r
+#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */\r
+/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */\r
+#define US_THR_TXCHR_Pos 0\r
+#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */\r
+#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))\r
+#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */\r
+/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */\r
+#define US_BRGR_CD_Pos 0\r
+#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */\r
+#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))\r
+#define US_BRGR_FP_Pos 16\r
+#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */\r
+#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))\r
+/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */\r
+#define US_RTOR_TO_Pos 0\r
+#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */\r
+#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))\r
+/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */\r
+#define US_TTGR_TG_Pos 0\r
+#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */\r
+#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))\r
+/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */\r
+#define US_FIDI_FI_DI_RATIO_Pos 0\r
+#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */\r
+#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))\r
+/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */\r
+#define US_NER_NB_ERRORS_Pos 0\r
+#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */\r
+/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */\r
+#define US_IF_IRDA_FILTER_Pos 0\r
+#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */\r
+#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))\r
+/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */\r
+#define US_MAN_TX_PL_Pos 0\r
+#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */\r
+#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))\r
+#define US_MAN_TX_PP_Pos 8\r
+#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */\r
+#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */\r
+#define US_MAN_RX_PL_Pos 16\r
+#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */\r
+#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))\r
+#define US_MAN_RX_PP_Pos 24\r
+#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */\r
+#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */\r
+#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */\r
+#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */\r
+#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */\r
+#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */\r
+#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */\r
+#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */\r
+/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */\r
+#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */\r
+#define US_WPMR_WPKEY_Pos 8\r
+#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */\r
+#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))\r
+/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */\r
+#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */\r
+#define US_WPSR_WPVSRC_Pos 8\r
+#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */\r
+/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */\r
+#define US_VERSION_VERSION_Pos 0\r
+#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) */\r
+#define US_VERSION_MFN_Pos 16\r
+#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) */\r
+/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */\r
+#define US_RPR_RXPTR_Pos 0\r
+#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */\r
+#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))\r
+/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */\r
+#define US_RCR_RXCTR_Pos 0\r
+#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */\r
+#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))\r
+/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */\r
+#define US_TPR_TXPTR_Pos 0\r
+#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */\r
+#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))\r
+/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */\r
+#define US_TCR_TXCTR_Pos 0\r
+#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */\r
+#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))\r
+/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */\r
+#define US_RNPR_RXNPTR_Pos 0\r
+#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */\r
+#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))\r
+/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */\r
+#define US_RNCR_RXNCTR_Pos 0\r
+#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */\r
+#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))\r
+/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */\r
+#define US_TNPR_TXNPTR_Pos 0\r
+#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */\r
+#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))\r
+/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */\r
+#define US_TNCR_TXNCTR_Pos 0\r
+#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */\r
+#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))\r
+/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */\r
+#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */\r
+#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */\r
+#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */\r
+#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */\r
+/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */\r
+#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */\r
+#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_USART_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_WDT_COMPONENT_\r
+#define _SAM4S_WDT_COMPONENT_\r
+\r
+/* ============================================================================= */\r
+/** SOFTWARE API DEFINITION FOR Watchdog Timer */\r
+/* ============================================================================= */\r
+/** \addtogroup SAM4S_WDT Watchdog Timer */\r
+/*@{*/\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+/** \brief Wdt hardware registers */\r
+typedef struct {\r
+ WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */\r
+ RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */\r
+ RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */\r
+} Wdt;\r
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */\r
+#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */\r
+#define WDT_CR_KEY_Pos 24\r
+#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */\r
+#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))\r
+/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */\r
+#define WDT_MR_WDV_Pos 0\r
+#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */\r
+#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))\r
+#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */\r
+#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */\r
+#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */\r
+#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */\r
+#define WDT_MR_WDD_Pos 16\r
+#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */\r
+#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))\r
+#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */\r
+#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */\r
+/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */\r
+#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */\r
+#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */\r
+\r
+/*@}*/\r
+\r
+\r
+#endif /* _SAM4S_WDT_COMPONENT_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_ACC_INSTANCE_\r
+#define _SAM4S_ACC_INSTANCE_\r
+\r
+/* ========== Register definition for ACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ACC_CR (0x40040000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (0x40040004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (0x40040030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (0x40040094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#else\r
+#define REG_ACC_CR (*(WoReg*)0x40040000U) /**< \brief (ACC) Control Register */\r
+#define REG_ACC_MR (*(RwReg*)0x40040004U) /**< \brief (ACC) Mode Register */\r
+#define REG_ACC_IER (*(WoReg*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */\r
+#define REG_ACC_IDR (*(WoReg*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */\r
+#define REG_ACC_IMR (*(RoReg*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */\r
+#define REG_ACC_ISR (*(RoReg*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */\r
+#define REG_ACC_ACR (*(RwReg*)0x40040094U) /**< \brief (ACC) Analog Control Register */\r
+#define REG_ACC_WPMR (*(RwReg*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */\r
+#define REG_ACC_WPSR (*(RoReg*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_ACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_ADC_INSTANCE_\r
+#define _SAM4S_ADC_INSTANCE_\r
+\r
+/* ========== Register definition for ADC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (0x40038048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (0x40038094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */\r
+#else\r
+#define REG_ADC_CR (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */\r
+#define REG_ADC_MR (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */\r
+#define REG_ADC_SEQR1 (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */\r
+#define REG_ADC_SEQR2 (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */\r
+#define REG_ADC_CHER (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */\r
+#define REG_ADC_CHDR (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */\r
+#define REG_ADC_CHSR (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */\r
+#define REG_ADC_LCDR (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */\r
+#define REG_ADC_IER (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */\r
+#define REG_ADC_IDR (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */\r
+#define REG_ADC_IMR (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */\r
+#define REG_ADC_ISR (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */\r
+#define REG_ADC_OVER (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */\r
+#define REG_ADC_EMR (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */\r
+#define REG_ADC_CWR (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */\r
+#define REG_ADC_CGR (*(RwReg*)0x40038048U) /**< \brief (ADC) Channel Gain Register */\r
+#define REG_ADC_COR (*(RwReg*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */\r
+#define REG_ADC_CDR (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */\r
+#define REG_ADC_ACR (*(RwReg*)0x40038094U) /**< \brief (ADC) Analog Control Register */\r
+#define REG_ADC_WPMR (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */\r
+#define REG_ADC_WPSR (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */\r
+#define REG_ADC_RPR (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */\r
+#define REG_ADC_RCR (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */\r
+#define REG_ADC_RNPR (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */\r
+#define REG_ADC_RNCR (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */\r
+#define REG_ADC_PTCR (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */\r
+#define REG_ADC_PTSR (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_ADC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_CHIPID_INSTANCE_\r
+#define _SAM4S_CHIPID_INSTANCE_\r
+\r
+/* ========== Register definition for CHIPID peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#else\r
+#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */\r
+#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_CHIPID_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_CRCCU_INSTANCE_\r
+#define _SAM4S_CRCCU_INSTANCE_\r
+\r
+/* ========== Register definition for CRCCU peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#else\r
+#define REG_CRCCU_DSCR (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */\r
+#define REG_CRCCU_DMA_EN (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */\r
+#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */\r
+#define REG_CRCCU_DMA_SR (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */\r
+#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */\r
+#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */\r
+#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */\r
+#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */\r
+#define REG_CRCCU_CR (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */\r
+#define REG_CRCCU_MR (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */\r
+#define REG_CRCCU_SR (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */\r
+#define REG_CRCCU_IER (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */\r
+#define REG_CRCCU_IDR (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */\r
+#define REG_CRCCU_IMR (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */\r
+#define REG_CRCCU_ISR (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_CRCCU_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_DACC_INSTANCE_\r
+#define _SAM4S_DACC_INSTANCE_\r
+\r
+/* ========== Register definition for DACC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (0x4003C010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (0x4003C014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (0x4003C018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (0x4003C020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (0x4003C094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */\r
+#else\r
+#define REG_DACC_CR (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */\r
+#define REG_DACC_MR (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */\r
+#define REG_DACC_CHER (*(WoReg*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */\r
+#define REG_DACC_CHDR (*(WoReg*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */\r
+#define REG_DACC_CHSR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Channel Status Register */\r
+#define REG_DACC_CDR (*(WoReg*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */\r
+#define REG_DACC_IER (*(WoReg*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */\r
+#define REG_DACC_IDR (*(WoReg*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */\r
+#define REG_DACC_IMR (*(RoReg*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */\r
+#define REG_DACC_ISR (*(RoReg*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */\r
+#define REG_DACC_ACR (*(RwReg*)0x4003C094U) /**< \brief (DACC) Analog Current Register */\r
+#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */\r
+#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */\r
+#define REG_DACC_TPR (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */\r
+#define REG_DACC_TCR (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */\r
+#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */\r
+#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */\r
+#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */\r
+#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_DACC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_EFC_INSTANCE_\r
+#define _SAM4S_EFC_INSTANCE_\r
+\r
+/* ========== Register definition for EFC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#else\r
+#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */\r
+#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */\r
+#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */\r
+#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_EFC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_GPBR_INSTANCE_\r
+#define _SAM4S_GPBR_INSTANCE_\r
+\r
+/* ========== Register definition for GPBR peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#else\r
+#define REG_GPBR_GPBR (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_GPBR_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_HSMCI_INSTANCE_\r
+#define _SAM4S_HSMCI_INSTANCE_\r
+\r
+/* ========== Register definition for HSMCI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#else\r
+#define REG_HSMCI_CR (*(WoReg*)0x40000000U) /**< \brief (HSMCI) Control Register */\r
+#define REG_HSMCI_MR (*(RwReg*)0x40000004U) /**< \brief (HSMCI) Mode Register */\r
+#define REG_HSMCI_DTOR (*(RwReg*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */\r
+#define REG_HSMCI_SDCR (*(RwReg*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */\r
+#define REG_HSMCI_ARGR (*(RwReg*)0x40000010U) /**< \brief (HSMCI) Argument Register */\r
+#define REG_HSMCI_CMDR (*(WoReg*)0x40000014U) /**< \brief (HSMCI) Command Register */\r
+#define REG_HSMCI_BLKR (*(RwReg*)0x40000018U) /**< \brief (HSMCI) Block Register */\r
+#define REG_HSMCI_CSTOR (*(RwReg*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */\r
+#define REG_HSMCI_RSPR (*(RoReg*)0x40000020U) /**< \brief (HSMCI) Response Register */\r
+#define REG_HSMCI_RDR (*(RoReg*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */\r
+#define REG_HSMCI_TDR (*(WoReg*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */\r
+#define REG_HSMCI_SR (*(RoReg*)0x40000040U) /**< \brief (HSMCI) Status Register */\r
+#define REG_HSMCI_IER (*(WoReg*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */\r
+#define REG_HSMCI_IDR (*(WoReg*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */\r
+#define REG_HSMCI_IMR (*(RoReg*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */\r
+#define REG_HSMCI_CFG (*(RwReg*)0x40000054U) /**< \brief (HSMCI) Configuration Register */\r
+#define REG_HSMCI_WPMR (*(RwReg*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */\r
+#define REG_HSMCI_WPSR (*(RoReg*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */\r
+#define REG_HSMCI_RPR (*(RwReg*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */\r
+#define REG_HSMCI_RCR (*(RwReg*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */\r
+#define REG_HSMCI_TPR (*(RwReg*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */\r
+#define REG_HSMCI_TCR (*(RwReg*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */\r
+#define REG_HSMCI_RNPR (*(RwReg*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */\r
+#define REG_HSMCI_RNCR (*(RwReg*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */\r
+#define REG_HSMCI_TNPR (*(RwReg*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */\r
+#define REG_HSMCI_TNCR (*(RwReg*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */\r
+#define REG_HSMCI_PTCR (*(WoReg*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */\r
+#define REG_HSMCI_PTSR (*(RoReg*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */\r
+#define REG_HSMCI_FIFO (*(RwReg*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_HSMCI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_MATRIX_INSTANCE_\r
+#define _SAM4S_MATRIX_INSTANCE_\r
+\r
+/* ========== Register definition for MATRIX peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_CCFG_SMCNFCS (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */\r
+#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#else\r
+#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */\r
+#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */\r
+#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */\r
+#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */\r
+#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */\r
+#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */\r
+#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */\r
+#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */\r
+#define REG_CCFG_SMCNFCS (*(RwReg*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */\r
+#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */\r
+#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_MATRIX_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PIOA_INSTANCE_\r
+#define _SAM4S_PIOA_INSTANCE_\r
+\r
+/* ========== Register definition for PIOA peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#else\r
+#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */\r
+#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */\r
+#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */\r
+#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */\r
+#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */\r
+#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */\r
+#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */\r
+#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */\r
+#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */\r
+#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */\r
+#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */\r
+#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */\r
+#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */\r
+#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */\r
+#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */\r
+#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */\r
+#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */\r
+#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */\r
+#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */\r
+#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */\r
+#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */\r
+#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */\r
+#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */\r
+#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */\r
+#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */\r
+#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */\r
+#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */\r
+#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */\r
+#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */\r
+#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */\r
+#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */\r
+#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */\r
+#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */\r
+#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */\r
+#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */\r
+#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */\r
+#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */\r
+#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */\r
+#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */\r
+#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */\r
+#define REG_PIOA_PCMR (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */\r
+#define REG_PIOA_PCIER (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOA_PCIDR (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOA_PCIMR (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOA_PCISR (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOA_PCRHR (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */\r
+#define REG_PIOA_RPR (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */\r
+#define REG_PIOA_RCR (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */\r
+#define REG_PIOA_RNPR (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */\r
+#define REG_PIOA_RNCR (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */\r
+#define REG_PIOA_PTCR (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */\r
+#define REG_PIOA_PTSR (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_PIOA_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PIOB_INSTANCE_\r
+#define _SAM4S_PIOB_INSTANCE_\r
+\r
+/* ========== Register definition for PIOB peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */\r
+#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */\r
+#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */\r
+#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */\r
+#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */\r
+#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */\r
+#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */\r
+#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */\r
+#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */\r
+#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */\r
+#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */\r
+#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */\r
+#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */\r
+#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */\r
+#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */\r
+#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */\r
+#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */\r
+#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */\r
+#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */\r
+#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */\r
+#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */\r
+#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */\r
+#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */\r
+#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */\r
+#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */\r
+#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */\r
+#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */\r
+#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */\r
+#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */\r
+#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */\r
+#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */\r
+#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */\r
+#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */\r
+#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */\r
+#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */\r
+#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */\r
+#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */\r
+#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */\r
+#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */\r
+#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */\r
+#define REG_PIOB_PCMR (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */\r
+#define REG_PIOB_PCIER (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOB_PCIDR (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOB_PCIMR (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOB_PCISR (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOB_PCRHR (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_PIOB_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PIOC_INSTANCE_\r
+#define _SAM4S_PIOC_INSTANCE_\r
+\r
+/* ========== Register definition for PIOC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#else\r
+#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */\r
+#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */\r
+#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */\r
+#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */\r
+#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */\r
+#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */\r
+#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */\r
+#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */\r
+#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */\r
+#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */\r
+#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */\r
+#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */\r
+#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */\r
+#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */\r
+#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */\r
+#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */\r
+#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */\r
+#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */\r
+#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */\r
+#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */\r
+#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */\r
+#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */\r
+#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */\r
+#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */\r
+#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */\r
+#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */\r
+#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */\r
+#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */\r
+#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */\r
+#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */\r
+#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */\r
+#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */\r
+#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */\r
+#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */\r
+#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */\r
+#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */\r
+#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */\r
+#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */\r
+#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */\r
+#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */\r
+#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */\r
+#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */\r
+#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */\r
+#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */\r
+#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */\r
+#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */\r
+#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */\r
+#define REG_PIOC_PCMR (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */\r
+#define REG_PIOC_PCIER (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */\r
+#define REG_PIOC_PCIDR (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */\r
+#define REG_PIOC_PCIMR (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */\r
+#define REG_PIOC_PCISR (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */\r
+#define REG_PIOC_PCRHR (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_PIOC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PMC_INSTANCE_\r
+#define _SAM4S_PMC_INSTANCE_\r
+\r
+/* ========== Register definition for PMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */\r
+#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#else\r
+#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */\r
+#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */\r
+#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */\r
+#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */\r
+#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */\r
+#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */\r
+#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */\r
+#define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */\r
+#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */\r
+#define REG_CKGR_PLLBR (*(RwReg*)0x400E042CU) /**< \brief (PMC) PLLB Register */\r
+#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */\r
+#define REG_PMC_USB (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */\r
+#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */\r
+#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */\r
+#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */\r
+#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */\r
+#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */\r
+#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */\r
+#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */\r
+#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */\r
+#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */\r
+#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */\r
+#define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */\r
+#define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */\r
+#define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */\r
+#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_PMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_PWM_INSTANCE_\r
+#define _SAM4S_PWM_INSTANCE_\r
+\r
+/* ========== Register definition for PWM peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_PWM_CLK (0x40020000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (0x40020120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (0x40020124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#else\r
+#define REG_PWM_CLK (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Clock Register */\r
+#define REG_PWM_ENA (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */\r
+#define REG_PWM_DIS (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */\r
+#define REG_PWM_SR (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */\r
+#define REG_PWM_IER1 (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */\r
+#define REG_PWM_IDR1 (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */\r
+#define REG_PWM_IMR1 (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */\r
+#define REG_PWM_ISR1 (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */\r
+#define REG_PWM_SCM (*(RwReg*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */\r
+#define REG_PWM_SCUC (*(RwReg*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */\r
+#define REG_PWM_SCUP (*(RwReg*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */\r
+#define REG_PWM_SCUPUPD (*(WoReg*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */\r
+#define REG_PWM_IER2 (*(WoReg*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */\r
+#define REG_PWM_IDR2 (*(WoReg*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */\r
+#define REG_PWM_IMR2 (*(RoReg*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */\r
+#define REG_PWM_ISR2 (*(RoReg*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */\r
+#define REG_PWM_OOV (*(RwReg*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */\r
+#define REG_PWM_OS (*(RwReg*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */\r
+#define REG_PWM_OSS (*(WoReg*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */\r
+#define REG_PWM_OSC (*(WoReg*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */\r
+#define REG_PWM_OSSUPD (*(WoReg*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */\r
+#define REG_PWM_OSCUPD (*(WoReg*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */\r
+#define REG_PWM_FMR (*(RwReg*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */\r
+#define REG_PWM_FSR (*(RoReg*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */\r
+#define REG_PWM_FCR (*(WoReg*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */\r
+#define REG_PWM_FPV (*(RwReg*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */\r
+#define REG_PWM_FPE (*(RwReg*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */\r
+#define REG_PWM_ELMR (*(RwReg*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */\r
+#define REG_PWM_SMMR (*(RwReg*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */\r
+#define REG_PWM_WPCR (*(WoReg*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */\r
+#define REG_PWM_WPSR (*(RoReg*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */\r
+#define REG_PWM_TPR (*(RwReg*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */\r
+#define REG_PWM_TCR (*(RwReg*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */\r
+#define REG_PWM_TNPR (*(RwReg*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */\r
+#define REG_PWM_TNCR (*(RwReg*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */\r
+#define REG_PWM_PTCR (*(WoReg*)0x40020120U) /**< \brief (PWM) Transfer Control Register */\r
+#define REG_PWM_PTSR (*(RoReg*)0x40020124U) /**< \brief (PWM) Transfer Status Register */\r
+#define REG_PWM_CMPV0 (*(RwReg*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */\r
+#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */\r
+#define REG_PWM_CMPM0 (*(RwReg*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */\r
+#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */\r
+#define REG_PWM_CMPV1 (*(RwReg*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */\r
+#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */\r
+#define REG_PWM_CMPM1 (*(RwReg*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */\r
+#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */\r
+#define REG_PWM_CMPV2 (*(RwReg*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */\r
+#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */\r
+#define REG_PWM_CMPM2 (*(RwReg*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */\r
+#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */\r
+#define REG_PWM_CMPV3 (*(RwReg*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */\r
+#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */\r
+#define REG_PWM_CMPM3 (*(RwReg*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */\r
+#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */\r
+#define REG_PWM_CMPV4 (*(RwReg*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */\r
+#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */\r
+#define REG_PWM_CMPM4 (*(RwReg*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */\r
+#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */\r
+#define REG_PWM_CMPV5 (*(RwReg*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */\r
+#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */\r
+#define REG_PWM_CMPM5 (*(RwReg*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */\r
+#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */\r
+#define REG_PWM_CMPV6 (*(RwReg*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */\r
+#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */\r
+#define REG_PWM_CMPM6 (*(RwReg*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */\r
+#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */\r
+#define REG_PWM_CMPV7 (*(RwReg*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */\r
+#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */\r
+#define REG_PWM_CMPM7 (*(RwReg*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */\r
+#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */\r
+#define REG_PWM_CMR0 (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */\r
+#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */\r
+#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */\r
+#define REG_PWM_CPRD0 (*(RwReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */\r
+#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */\r
+#define REG_PWM_CCNT0 (*(RoReg*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */\r
+#define REG_PWM_DT0 (*(RwReg*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */\r
+#define REG_PWM_DTUPD0 (*(WoReg*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */\r
+#define REG_PWM_CMR1 (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */\r
+#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */\r
+#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */\r
+#define REG_PWM_CPRD1 (*(RwReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */\r
+#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */\r
+#define REG_PWM_CCNT1 (*(RoReg*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */\r
+#define REG_PWM_DT1 (*(RwReg*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */\r
+#define REG_PWM_DTUPD1 (*(WoReg*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */\r
+#define REG_PWM_CMR2 (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */\r
+#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */\r
+#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */\r
+#define REG_PWM_CPRD2 (*(RwReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */\r
+#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */\r
+#define REG_PWM_CCNT2 (*(RoReg*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */\r
+#define REG_PWM_DT2 (*(RwReg*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */\r
+#define REG_PWM_DTUPD2 (*(WoReg*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */\r
+#define REG_PWM_CMR3 (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */\r
+#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */\r
+#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */\r
+#define REG_PWM_CPRD3 (*(RwReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */\r
+#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */\r
+#define REG_PWM_CCNT3 (*(RoReg*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */\r
+#define REG_PWM_DT3 (*(RwReg*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */\r
+#define REG_PWM_DTUPD3 (*(WoReg*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_PWM_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RSTC_INSTANCE_\r
+#define _SAM4S_RSTC_INSTANCE_\r
+\r
+/* ========== Register definition for RSTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */\r
+#else\r
+#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */\r
+#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */\r
+#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_RSTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RTC_INSTANCE_\r
+#define _SAM4S_RTC_INSTANCE_\r
+\r
+/* ========== Register definition for RTC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */\r
+#else\r
+#define REG_RTC_CR (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */\r
+#define REG_RTC_MR (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */\r
+#define REG_RTC_TIMR (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */\r
+#define REG_RTC_CALR (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */\r
+#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */\r
+#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */\r
+#define REG_RTC_SR (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */\r
+#define REG_RTC_SCCR (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */\r
+#define REG_RTC_IER (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */\r
+#define REG_RTC_IDR (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */\r
+#define REG_RTC_IMR (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */\r
+#define REG_RTC_VER (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_RTC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_RTT_INSTANCE_\r
+#define _SAM4S_RTT_INSTANCE_\r
+\r
+/* ========== Register definition for RTT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */\r
+#else\r
+#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */\r
+#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */\r
+#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */\r
+#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_RTT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SMC_INSTANCE_\r
+#define _SAM4S_SMC_INSTANCE_\r
+\r
+/* ========== Register definition for SMC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SMC_SETUP0 (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_OCMS (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#else\r
+#define REG_SMC_SETUP0 (*(RwReg*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */\r
+#define REG_SMC_PULSE0 (*(RwReg*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */\r
+#define REG_SMC_CYCLE0 (*(RwReg*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */\r
+#define REG_SMC_MODE0 (*(RwReg*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */\r
+#define REG_SMC_SETUP1 (*(RwReg*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */\r
+#define REG_SMC_PULSE1 (*(RwReg*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */\r
+#define REG_SMC_CYCLE1 (*(RwReg*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */\r
+#define REG_SMC_MODE1 (*(RwReg*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */\r
+#define REG_SMC_SETUP2 (*(RwReg*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */\r
+#define REG_SMC_PULSE2 (*(RwReg*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */\r
+#define REG_SMC_CYCLE2 (*(RwReg*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */\r
+#define REG_SMC_MODE2 (*(RwReg*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */\r
+#define REG_SMC_SETUP3 (*(RwReg*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */\r
+#define REG_SMC_PULSE3 (*(RwReg*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */\r
+#define REG_SMC_CYCLE3 (*(RwReg*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */\r
+#define REG_SMC_MODE3 (*(RwReg*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */\r
+#define REG_SMC_SETUP4 (*(RwReg*)0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */\r
+#define REG_SMC_PULSE4 (*(RwReg*)0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */\r
+#define REG_SMC_CYCLE4 (*(RwReg*)0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */\r
+#define REG_SMC_MODE4 (*(RwReg*)0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */\r
+#define REG_SMC_OCMS (*(RwReg*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */\r
+#define REG_SMC_KEY1 (*(WoReg*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */\r
+#define REG_SMC_KEY2 (*(WoReg*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */\r
+#define REG_SMC_WPMR (*(RwReg*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */\r
+#define REG_SMC_WPSR (*(RoReg*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_SMC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SPI_INSTANCE_\r
+#define _SAM4S_SPI_INSTANCE_\r
+\r
+/* ========== Register definition for SPI peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */\r
+#else\r
+#define REG_SPI_CR (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */\r
+#define REG_SPI_MR (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */\r
+#define REG_SPI_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */\r
+#define REG_SPI_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */\r
+#define REG_SPI_SR (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */\r
+#define REG_SPI_IER (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */\r
+#define REG_SPI_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */\r
+#define REG_SPI_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */\r
+#define REG_SPI_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */\r
+#define REG_SPI_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */\r
+#define REG_SPI_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */\r
+#define REG_SPI_RPR (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */\r
+#define REG_SPI_RCR (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */\r
+#define REG_SPI_TPR (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */\r
+#define REG_SPI_TCR (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */\r
+#define REG_SPI_RNPR (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */\r
+#define REG_SPI_RNCR (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */\r
+#define REG_SPI_TNPR (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */\r
+#define REG_SPI_TNCR (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */\r
+#define REG_SPI_PTCR (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */\r
+#define REG_SPI_PTSR (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_SPI_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SSC_INSTANCE_\r
+#define _SAM4S_SSC_INSTANCE_\r
+\r
+/* ========== Register definition for SSC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */\r
+#define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */\r
+#define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */\r
+#define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */\r
+#define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */\r
+#define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */\r
+#define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */\r
+#define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */\r
+#define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */\r
+#define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */\r
+#else\r
+#define REG_SSC_CR (*(WoReg*)0x40004000U) /**< \brief (SSC) Control Register */\r
+#define REG_SSC_CMR (*(RwReg*)0x40004004U) /**< \brief (SSC) Clock Mode Register */\r
+#define REG_SSC_RCMR (*(RwReg*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */\r
+#define REG_SSC_RFMR (*(RwReg*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */\r
+#define REG_SSC_TCMR (*(RwReg*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */\r
+#define REG_SSC_TFMR (*(RwReg*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */\r
+#define REG_SSC_RHR (*(RoReg*)0x40004020U) /**< \brief (SSC) Receive Holding Register */\r
+#define REG_SSC_THR (*(WoReg*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */\r
+#define REG_SSC_RSHR (*(RoReg*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */\r
+#define REG_SSC_TSHR (*(RwReg*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */\r
+#define REG_SSC_RC0R (*(RwReg*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */\r
+#define REG_SSC_RC1R (*(RwReg*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */\r
+#define REG_SSC_SR (*(RoReg*)0x40004040U) /**< \brief (SSC) Status Register */\r
+#define REG_SSC_IER (*(WoReg*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */\r
+#define REG_SSC_IDR (*(WoReg*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */\r
+#define REG_SSC_IMR (*(RoReg*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */\r
+#define REG_SSC_WPMR (*(RwReg*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */\r
+#define REG_SSC_WPSR (*(RoReg*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */\r
+#define REG_SSC_RPR (*(RwReg*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */\r
+#define REG_SSC_RCR (*(RwReg*)0x40004104U) /**< \brief (SSC) Receive Counter Register */\r
+#define REG_SSC_TPR (*(RwReg*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */\r
+#define REG_SSC_TCR (*(RwReg*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */\r
+#define REG_SSC_RNPR (*(RwReg*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */\r
+#define REG_SSC_RNCR (*(RwReg*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */\r
+#define REG_SSC_TNPR (*(RwReg*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */\r
+#define REG_SSC_TNCR (*(RwReg*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */\r
+#define REG_SSC_PTCR (*(WoReg*)0x40004120U) /**< \brief (SSC) Transfer Control Register */\r
+#define REG_SSC_PTSR (*(RoReg*)0x40004124U) /**< \brief (SSC) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_SSC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_SUPC_INSTANCE_\r
+#define _SAM4S_SUPC_INSTANCE_\r
+\r
+/* ========== Register definition for SUPC peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#else\r
+#define REG_SUPC_CR (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */\r
+#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */\r
+#define REG_SUPC_MR (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */\r
+#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */\r
+#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */\r
+#define REG_SUPC_SR (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_SUPC_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TC0_INSTANCE_\r
+#define _SAM4S_TC0_INSTANCE_\r
+\r
+/* ========== Register definition for TC0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (0x400100D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#else\r
+#define REG_TC0_CCR0 (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */\r
+#define REG_TC0_CMR0 (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */\r
+#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC0_CV0 (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */\r
+#define REG_TC0_RA0 (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */\r
+#define REG_TC0_RB0 (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */\r
+#define REG_TC0_RC0 (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */\r
+#define REG_TC0_SR0 (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */\r
+#define REG_TC0_IER0 (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC0_IDR0 (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC0_IMR0 (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC0_CCR1 (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */\r
+#define REG_TC0_CMR1 (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */\r
+#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC0_CV1 (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */\r
+#define REG_TC0_RA1 (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */\r
+#define REG_TC0_RB1 (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */\r
+#define REG_TC0_RC1 (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */\r
+#define REG_TC0_SR1 (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */\r
+#define REG_TC0_IER1 (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC0_IDR1 (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC0_IMR1 (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC0_CCR2 (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */\r
+#define REG_TC0_CMR2 (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */\r
+#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC0_CV2 (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */\r
+#define REG_TC0_RA2 (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */\r
+#define REG_TC0_RB2 (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */\r
+#define REG_TC0_RC2 (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */\r
+#define REG_TC0_SR2 (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */\r
+#define REG_TC0_IER2 (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC0_IDR2 (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC0_IMR2 (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC0_BCR (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */\r
+#define REG_TC0_BMR (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */\r
+#define REG_TC0_QIER (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */\r
+#define REG_TC0_QIDR (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */\r
+#define REG_TC0_QIMR (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */\r
+#define REG_TC0_QISR (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */\r
+#define REG_TC0_FMR (*(RwReg*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */\r
+#define REG_TC0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_TC0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TC1_INSTANCE_\r
+#define _SAM4S_TC1_INSTANCE_\r
+\r
+/* ========== Register definition for TC1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (0x400140D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#else\r
+#define REG_TC1_CCR0 (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */\r
+#define REG_TC1_CMR0 (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */\r
+#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */\r
+#define REG_TC1_CV0 (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */\r
+#define REG_TC1_RA0 (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */\r
+#define REG_TC1_RB0 (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */\r
+#define REG_TC1_RC0 (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */\r
+#define REG_TC1_SR0 (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */\r
+#define REG_TC1_IER0 (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */\r
+#define REG_TC1_IDR0 (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */\r
+#define REG_TC1_IMR0 (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */\r
+#define REG_TC1_CCR1 (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */\r
+#define REG_TC1_CMR1 (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */\r
+#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */\r
+#define REG_TC1_CV1 (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */\r
+#define REG_TC1_RA1 (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */\r
+#define REG_TC1_RB1 (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */\r
+#define REG_TC1_RC1 (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */\r
+#define REG_TC1_SR1 (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */\r
+#define REG_TC1_IER1 (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */\r
+#define REG_TC1_IDR1 (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */\r
+#define REG_TC1_IMR1 (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */\r
+#define REG_TC1_CCR2 (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */\r
+#define REG_TC1_CMR2 (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */\r
+#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */\r
+#define REG_TC1_CV2 (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */\r
+#define REG_TC1_RA2 (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */\r
+#define REG_TC1_RB2 (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */\r
+#define REG_TC1_RC2 (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */\r
+#define REG_TC1_SR2 (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */\r
+#define REG_TC1_IER2 (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */\r
+#define REG_TC1_IDR2 (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */\r
+#define REG_TC1_IMR2 (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */\r
+#define REG_TC1_BCR (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */\r
+#define REG_TC1_BMR (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */\r
+#define REG_TC1_QIER (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */\r
+#define REG_TC1_QIDR (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */\r
+#define REG_TC1_QIMR (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */\r
+#define REG_TC1_QISR (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */\r
+#define REG_TC1_FMR (*(RwReg*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */\r
+#define REG_TC1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_TC1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TWI0_INSTANCE_\r
+#define _SAM4S_TWI0_INSTANCE_\r
+\r
+/* ========== Register definition for TWI0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (0x40018104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (0x40018120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (0x40018124U) /**< \brief (TWI0) Transfer Status Register */\r
+#else\r
+#define REG_TWI0_CR (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */\r
+#define REG_TWI0_MMR (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */\r
+#define REG_TWI0_SMR (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */\r
+#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */\r
+#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */\r
+#define REG_TWI0_SR (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */\r
+#define REG_TWI0_IER (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */\r
+#define REG_TWI0_IDR (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */\r
+#define REG_TWI0_IMR (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */\r
+#define REG_TWI0_RHR (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */\r
+#define REG_TWI0_THR (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */\r
+#define REG_TWI0_RPR (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */\r
+#define REG_TWI0_RCR (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */\r
+#define REG_TWI0_TPR (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */\r
+#define REG_TWI0_TCR (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */\r
+#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */\r
+#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */\r
+#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */\r
+#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */\r
+#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */\r
+#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_TWI0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_TWI1_INSTANCE_\r
+#define _SAM4S_TWI1_INSTANCE_\r
+\r
+/* ========== Register definition for TWI1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */\r
+#else\r
+#define REG_TWI1_CR (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */\r
+#define REG_TWI1_MMR (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */\r
+#define REG_TWI1_SMR (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */\r
+#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */\r
+#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */\r
+#define REG_TWI1_SR (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */\r
+#define REG_TWI1_IER (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */\r
+#define REG_TWI1_IDR (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */\r
+#define REG_TWI1_IMR (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */\r
+#define REG_TWI1_RHR (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */\r
+#define REG_TWI1_THR (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */\r
+#define REG_TWI1_RPR (*(RwReg*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */\r
+#define REG_TWI1_RCR (*(RwReg*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */\r
+#define REG_TWI1_TPR (*(RwReg*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */\r
+#define REG_TWI1_TCR (*(RwReg*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */\r
+#define REG_TWI1_RNPR (*(RwReg*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */\r
+#define REG_TWI1_RNCR (*(RwReg*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */\r
+#define REG_TWI1_TNPR (*(RwReg*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */\r
+#define REG_TWI1_TNCR (*(RwReg*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */\r
+#define REG_TWI1_PTCR (*(WoReg*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */\r
+#define REG_TWI1_PTSR (*(RoReg*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_TWI1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_UART0_INSTANCE_\r
+#define _SAM4S_UART0_INSTANCE_\r
+\r
+/* ========== Register definition for UART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#else\r
+#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */\r
+#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */\r
+#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */\r
+#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */\r
+#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */\r
+#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */\r
+#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */\r
+#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */\r
+#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */\r
+#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */\r
+#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */\r
+#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */\r
+#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */\r
+#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */\r
+#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */\r
+#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */\r
+#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */\r
+#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */\r
+#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_UART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_UART1_INSTANCE_\r
+#define _SAM4S_UART1_INSTANCE_\r
+\r
+/* ========== Register definition for UART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (0x400E0904U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (0x400E0920U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (0x400E0924U) /**< \brief (UART1) Transfer Status Register */\r
+#else\r
+#define REG_UART1_CR (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */\r
+#define REG_UART1_MR (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */\r
+#define REG_UART1_IER (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */\r
+#define REG_UART1_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */\r
+#define REG_UART1_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */\r
+#define REG_UART1_SR (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */\r
+#define REG_UART1_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */\r
+#define REG_UART1_THR (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */\r
+#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */\r
+#define REG_UART1_RPR (*(RwReg*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */\r
+#define REG_UART1_RCR (*(RwReg*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */\r
+#define REG_UART1_TPR (*(RwReg*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */\r
+#define REG_UART1_TCR (*(RwReg*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */\r
+#define REG_UART1_RNPR (*(RwReg*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */\r
+#define REG_UART1_RNCR (*(RwReg*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */\r
+#define REG_UART1_TNPR (*(RwReg*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */\r
+#define REG_UART1_TNCR (*(RwReg*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */\r
+#define REG_UART1_PTCR (*(WoReg*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */\r
+#define REG_UART1_PTSR (*(RoReg*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_UART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_UDP_INSTANCE_\r
+#define _SAM4S_UDP_INSTANCE_\r
+\r
+/* ========== Register definition for UDP peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_UDP_FRM_NUM (0x40034000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (0x40034004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (0x40034008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (0x40034074U) /**< \brief (UDP) Transceiver Control Register */\r
+#else\r
+#define REG_UDP_FRM_NUM (*(RoReg*)0x40034000U) /**< \brief (UDP) Frame Number Register */\r
+#define REG_UDP_GLB_STAT (*(RwReg*)0x40034004U) /**< \brief (UDP) Global State Register */\r
+#define REG_UDP_FADDR (*(RwReg*)0x40034008U) /**< \brief (UDP) Function Address Register */\r
+#define REG_UDP_IER (*(WoReg*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */\r
+#define REG_UDP_IDR (*(WoReg*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */\r
+#define REG_UDP_IMR (*(RoReg*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */\r
+#define REG_UDP_ISR (*(RoReg*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */\r
+#define REG_UDP_ICR (*(WoReg*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */\r
+#define REG_UDP_RST_EP (*(RwReg*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */\r
+#define REG_UDP_CSR (*(RwReg*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */\r
+#define REG_UDP_FDR (*(RwReg*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */\r
+#define REG_UDP_TXVC (*(RwReg*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_UDP_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_USART0_INSTANCE_\r
+#define _SAM4S_USART0_INSTANCE_\r
+\r
+/* ========== Register definition for USART0 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */\r
+#define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */\r
+#else\r
+#define REG_USART0_CR (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */\r
+#define REG_USART0_MR (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */\r
+#define REG_USART0_IER (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */\r
+#define REG_USART0_IDR (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */\r
+#define REG_USART0_IMR (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */\r
+#define REG_USART0_CSR (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */\r
+#define REG_USART0_RHR (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */\r
+#define REG_USART0_THR (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */\r
+#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */\r
+#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */\r
+#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */\r
+#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */\r
+#define REG_USART0_NER (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */\r
+#define REG_USART0_IF (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */\r
+#define REG_USART0_MAN (*(RwReg*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */\r
+#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */\r
+#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */\r
+#define REG_USART0_VERSION (*(RoReg*)0x400240FCU) /**< \brief (USART0) Version Register */\r
+#define REG_USART0_RPR (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */\r
+#define REG_USART0_RCR (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */\r
+#define REG_USART0_TPR (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */\r
+#define REG_USART0_TCR (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */\r
+#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */\r
+#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */\r
+#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */\r
+#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */\r
+#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */\r
+#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_USART0_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_USART1_INSTANCE_\r
+#define _SAM4S_USART1_INSTANCE_\r
+\r
+/* ========== Register definition for USART1 peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */\r
+#define REG_USART1_RPR (0x40028100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (0x40028104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (0x40028120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (0x40028124U) /**< \brief (USART1) Transfer Status Register */\r
+#else\r
+#define REG_USART1_CR (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */\r
+#define REG_USART1_MR (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */\r
+#define REG_USART1_IER (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */\r
+#define REG_USART1_IDR (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */\r
+#define REG_USART1_IMR (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */\r
+#define REG_USART1_CSR (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */\r
+#define REG_USART1_RHR (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */\r
+#define REG_USART1_THR (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */\r
+#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */\r
+#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */\r
+#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */\r
+#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */\r
+#define REG_USART1_NER (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */\r
+#define REG_USART1_IF (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */\r
+#define REG_USART1_MAN (*(RwReg*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */\r
+#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */\r
+#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */\r
+#define REG_USART1_VERSION (*(RoReg*)0x400280FCU) /**< \brief (USART1) Version Register */\r
+#define REG_USART1_RPR (*(RwReg*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */\r
+#define REG_USART1_RCR (*(RwReg*)0x40028104U) /**< \brief (USART1) Receive Counter Register */\r
+#define REG_USART1_TPR (*(RwReg*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */\r
+#define REG_USART1_TCR (*(RwReg*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */\r
+#define REG_USART1_RNPR (*(RwReg*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */\r
+#define REG_USART1_RNCR (*(RwReg*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */\r
+#define REG_USART1_TNPR (*(RwReg*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */\r
+#define REG_USART1_TNCR (*(RwReg*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */\r
+#define REG_USART1_PTCR (*(WoReg*)0x40028120U) /**< \brief (USART1) Transfer Control Register */\r
+#define REG_USART1_PTSR (*(RoReg*)0x40028124U) /**< \brief (USART1) Transfer Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_USART1_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_WDT_INSTANCE_\r
+#define _SAM4S_WDT_INSTANCE_\r
+\r
+/* ========== Register definition for WDT peripheral ========== */\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */\r
+#else\r
+#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */\r
+#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */\r
+#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+\r
+#endif /* _SAM4S_WDT_INSTANCE_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S16C_PIO_\r
+#define _SAM4S16C_PIO_\r
+\r
+#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */\r
+#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */\r
+#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */\r
+#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */\r
+#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */\r
+#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */\r
+#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */\r
+#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */\r
+#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */\r
+#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */\r
+#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */\r
+#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */\r
+#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */\r
+#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */\r
+#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */\r
+#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */\r
+#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */\r
+#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */\r
+#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */\r
+#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */\r
+#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */\r
+#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */\r
+#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */\r
+#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */\r
+#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */\r
+#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */\r
+#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */\r
+#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */\r
+#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */\r
+#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */\r
+#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */\r
+#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */\r
+#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */\r
+#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */\r
+#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */\r
+#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */\r
+#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */\r
+#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */\r
+#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */\r
+#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */\r
+#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */\r
+#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */\r
+#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */\r
+#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */\r
+#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */\r
+#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */\r
+#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */\r
+#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */\r
+#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */\r
+#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */\r
+#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */\r
+#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */\r
+#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */\r
+#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */\r
+#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */\r
+#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */\r
+#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */\r
+#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */\r
+#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */\r
+#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */\r
+#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */\r
+#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */\r
+#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */\r
+#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */\r
+#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */\r
+#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */\r
+#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */\r
+#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */\r
+#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */\r
+#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */\r
+#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */\r
+#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */\r
+#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */\r
+#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */\r
+#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */\r
+#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */\r
+#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */\r
+#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */\r
+#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */\r
+/* ========== Pio definition for ADC peripheral ========== */\r
+#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */\r
+#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */\r
+#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */\r
+#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */\r
+#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */\r
+#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */\r
+#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */\r
+#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */\r
+#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */\r
+#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */\r
+#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */\r
+#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */\r
+#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */\r
+#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */\r
+#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */\r
+#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */\r
+#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */\r
+#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */\r
+#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */\r
+#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */\r
+#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */\r
+/* ========== Pio definition for DACC peripheral ========== */\r
+#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */\r
+#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */\r
+#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */\r
+/* ========== Pio definition for EBI peripheral ========== */\r
+#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */\r
+#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */\r
+#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */\r
+#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */\r
+#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */\r
+#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */\r
+#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */\r
+#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */\r
+#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */\r
+#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */\r
+#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */\r
+#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */\r
+#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */\r
+#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */\r
+#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */\r
+#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */\r
+#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */\r
+#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */\r
+#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */\r
+#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */\r
+#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */\r
+#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */\r
+#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */\r
+#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */\r
+#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */\r
+#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */\r
+#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */\r
+#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */\r
+#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */\r
+#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */\r
+#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */\r
+#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */\r
+#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */\r
+#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */\r
+#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */\r
+#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */\r
+#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */\r
+#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */\r
+#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */\r
+#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */\r
+#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */\r
+/* ========== Pio definition for HSMCI peripheral ========== */\r
+#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */\r
+#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */\r
+#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */\r
+#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */\r
+#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */\r
+#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */\r
+/* ========== Pio definition for PIOA peripheral ========== */\r
+#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */\r
+#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */\r
+#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */\r
+#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */\r
+#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */\r
+#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */\r
+#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */\r
+#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */\r
+#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */\r
+#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */\r
+#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */\r
+/* ========== Pio definition for PMC peripheral ========== */\r
+#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */\r
+#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */\r
+#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */\r
+#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */\r
+/* ========== Pio definition for PWM peripheral ========== */\r
+#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */\r
+#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */\r
+#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */\r
+#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */\r
+#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */\r
+#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */\r
+#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */\r
+#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */\r
+#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */\r
+#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */\r
+/* ========== Pio definition for SPI peripheral ========== */\r
+#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */\r
+#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */\r
+#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */\r
+#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */\r
+#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */\r
+#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */\r
+#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */\r
+/* ========== Pio definition for SSC peripheral ========== */\r
+#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */\r
+#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */\r
+#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */\r
+#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */\r
+#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */\r
+#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */\r
+/* ========== Pio definition for TC0 peripheral ========== */\r
+#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */\r
+#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */\r
+#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */\r
+#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */\r
+#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */\r
+#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */\r
+#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */\r
+#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */\r
+#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */\r
+/* ========== Pio definition for TC1 peripheral ========== */\r
+#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */\r
+#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */\r
+#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */\r
+#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */\r
+#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */\r
+#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */\r
+#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */\r
+#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */\r
+#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */\r
+/* ========== Pio definition for TWI0 peripheral ========== */\r
+#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */\r
+#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */\r
+/* ========== Pio definition for TWI1 peripheral ========== */\r
+#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */\r
+#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */\r
+/* ========== Pio definition for UART0 peripheral ========== */\r
+#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */\r
+#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */\r
+/* ========== Pio definition for UART1 peripheral ========== */\r
+#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */\r
+#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */\r
+/* ========== Pio definition for USART0 peripheral ========== */\r
+#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */\r
+#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */\r
+#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */\r
+#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */\r
+#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */\r
+/* ========== Pio definition for USART1 peripheral ========== */\r
+#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */\r
+#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */\r
+#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */\r
+#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */\r
+#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */\r
+#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */\r
+#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */\r
+#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */\r
+#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */\r
+/* ========== Pio indexes ========== */\r
+#define PIO_PA0_IDX 0\r
+#define PIO_PA1_IDX 1\r
+#define PIO_PA2_IDX 2\r
+#define PIO_PA3_IDX 3\r
+#define PIO_PA4_IDX 4\r
+#define PIO_PA5_IDX 5\r
+#define PIO_PA6_IDX 6\r
+#define PIO_PA7_IDX 7\r
+#define PIO_PA8_IDX 8\r
+#define PIO_PA9_IDX 9\r
+#define PIO_PA10_IDX 10\r
+#define PIO_PA11_IDX 11\r
+#define PIO_PA12_IDX 12\r
+#define PIO_PA13_IDX 13\r
+#define PIO_PA14_IDX 14\r
+#define PIO_PA15_IDX 15\r
+#define PIO_PA16_IDX 16\r
+#define PIO_PA17_IDX 17\r
+#define PIO_PA18_IDX 18\r
+#define PIO_PA19_IDX 19\r
+#define PIO_PA20_IDX 20\r
+#define PIO_PA21_IDX 21\r
+#define PIO_PA22_IDX 22\r
+#define PIO_PA23_IDX 23\r
+#define PIO_PA24_IDX 24\r
+#define PIO_PA25_IDX 25\r
+#define PIO_PA26_IDX 26\r
+#define PIO_PA27_IDX 27\r
+#define PIO_PA28_IDX 28\r
+#define PIO_PA29_IDX 29\r
+#define PIO_PA30_IDX 30\r
+#define PIO_PA31_IDX 31\r
+#define PIO_PB0_IDX 32\r
+#define PIO_PB1_IDX 33\r
+#define PIO_PB2_IDX 34\r
+#define PIO_PB3_IDX 35\r
+#define PIO_PB4_IDX 36\r
+#define PIO_PB5_IDX 37\r
+#define PIO_PB6_IDX 38\r
+#define PIO_PB7_IDX 39\r
+#define PIO_PB8_IDX 40\r
+#define PIO_PB9_IDX 41\r
+#define PIO_PB10_IDX 42\r
+#define PIO_PB11_IDX 43\r
+#define PIO_PB12_IDX 44\r
+#define PIO_PB13_IDX 45\r
+#define PIO_PB14_IDX 46\r
+#define PIO_PC0_IDX 64\r
+#define PIO_PC1_IDX 65\r
+#define PIO_PC2_IDX 66\r
+#define PIO_PC3_IDX 67\r
+#define PIO_PC4_IDX 68\r
+#define PIO_PC5_IDX 69\r
+#define PIO_PC6_IDX 70\r
+#define PIO_PC7_IDX 71\r
+#define PIO_PC8_IDX 72\r
+#define PIO_PC9_IDX 73\r
+#define PIO_PC10_IDX 74\r
+#define PIO_PC11_IDX 75\r
+#define PIO_PC12_IDX 76\r
+#define PIO_PC13_IDX 77\r
+#define PIO_PC14_IDX 78\r
+#define PIO_PC15_IDX 79\r
+#define PIO_PC16_IDX 80\r
+#define PIO_PC17_IDX 81\r
+#define PIO_PC18_IDX 82\r
+#define PIO_PC19_IDX 83\r
+#define PIO_PC20_IDX 84\r
+#define PIO_PC21_IDX 85\r
+#define PIO_PC22_IDX 86\r
+#define PIO_PC23_IDX 87\r
+#define PIO_PC24_IDX 88\r
+#define PIO_PC25_IDX 89\r
+#define PIO_PC26_IDX 90\r
+#define PIO_PC27_IDX 91\r
+#define PIO_PC28_IDX 92\r
+#define PIO_PC29_IDX 93\r
+#define PIO_PC30_IDX 94\r
+#define PIO_PC31_IDX 95\r
+\r
+#endif /* _SAM4S16C_PIO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S_\r
+#define _SAM4S_\r
+\r
+#if defined __SAM4S8B__\r
+ #include "sam4s8b.h"\r
+#elif defined __SAM4S8C__\r
+ #include "sam4s8c.h"\r
+#elif defined __SAM4S16B__\r
+ #include "sam4s16b.h"\r
+#elif defined __SAM4S16C__\r
+ #include "sam4s16c.h"\r
+#else\r
+ #error Library does not support the specified device.\r
+#endif\r
+\r
+#endif /* _SAM4S_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * Copyright (c) 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM4S16C_\r
+#define _SAM4S16C_\r
+\r
+/** \addtogroup SAM4S16C_definitions SAM4S16C definitions\r
+ This file defines all structures and symbols for SAM4S16C:\r
+ - registers and bitfields\r
+ - peripheral base address\r
+ - peripheral ID\r
+ - PIO definitions\r
+*/\r
+/*@{*/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#include <stdint.h>\r
+#ifndef __cplusplus\r
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#else\r
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */\r
+#endif\r
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */\r
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */\r
+#endif\r
+\r
+/* ************************************************************************** */\r
+/* CMSIS DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_cmsis CMSIS Definitions */\r
+/*@{*/\r
+\r
+/**< Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ******************************/\r
+ NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */\r
+/****** SAM4S16C specific Interrupt Numbers *********************************/\r
+\r
+ SUPC_IRQn = 0, /**< 0 SAM4S16C Supply Controller (SUPC) */\r
+ RSTC_IRQn = 1, /**< 1 SAM4S16C Reset Controller (RSTC) */\r
+ RTC_IRQn = 2, /**< 2 SAM4S16C Real Time Clock (RTC) */\r
+ RTT_IRQn = 3, /**< 3 SAM4S16C Real Time Timer (RTT) */\r
+ WDT_IRQn = 4, /**< 4 SAM4S16C Watchdog Timer (WDT) */\r
+ PMC_IRQn = 5, /**< 5 SAM4S16C Power Management Controller (PMC) */\r
+ EFC_IRQn = 6, /**< 6 SAM4S16C Enhanced Embedded Flash Controller (EFC) */\r
+ UART0_IRQn = 8, /**< 8 SAM4S16C UART 0 (UART0) */\r
+ UART1_IRQn = 9, /**< 9 SAM4S16C UART 1 (UART1) */\r
+ SMC_IRQn = 10, /**< 10 SAM4S16C Static Memory Controller (SMC) */\r
+ PIOA_IRQn = 11, /**< 11 SAM4S16C Parallel I/O Controller A (PIOA) */\r
+ PIOB_IRQn = 12, /**< 12 SAM4S16C Parallel I/O Controller B (PIOB) */\r
+ PIOC_IRQn = 13, /**< 13 SAM4S16C Parallel I/O Controller C (PIOC) */\r
+ USART0_IRQn = 14, /**< 14 SAM4S16C USART 0 (USART0) */\r
+ USART1_IRQn = 15, /**< 15 SAM4S16C USART 1 (USART1) */\r
+ HSMCI_IRQn = 18, /**< 18 SAM4S16C Multimedia Card Interface (HSMCI) */\r
+ TWI0_IRQn = 19, /**< 19 SAM4S16C Two Wire Interface 0 (TWI0) */\r
+ TWI1_IRQn = 20, /**< 20 SAM4S16C Two Wire Interface 1 (TWI1) */\r
+ SPI_IRQn = 21, /**< 21 SAM4S16C Serial Peripheral Interface (SPI) */\r
+ SSC_IRQn = 22, /**< 22 SAM4S16C Synchronous Serial Controller (SSC) */\r
+ TC0_IRQn = 23, /**< 23 SAM4S16C Timer/Counter 0 (TC0) */\r
+ TC1_IRQn = 24, /**< 24 SAM4S16C Timer/Counter 1 (TC1) */\r
+ TC2_IRQn = 25, /**< 25 SAM4S16C Timer/Counter 2 (TC2) */\r
+ TC3_IRQn = 26, /**< 26 SAM4S16C Timer/Counter 3 (TC3) */\r
+ TC4_IRQn = 27, /**< 27 SAM4S16C Timer/Counter 4 (TC4) */\r
+ TC5_IRQn = 28, /**< 28 SAM4S16C Timer/Counter 5 (TC5) */\r
+ ADC_IRQn = 29, /**< 29 SAM4S16C Analog To Digital Converter (ADC) */\r
+ DACC_IRQn = 30, /**< 30 SAM4S16C Digital To Analog Converter (DACC) */\r
+ PWM_IRQn = 31, /**< 31 SAM4S16C Pulse Width Modulation (PWM) */\r
+ CRCCU_IRQn = 32, /**< 32 SAM4S16C CRC Calculation Unit (CRCCU) */\r
+ ACC_IRQn = 33, /**< 33 SAM4S16C Analog Comparator (ACC) */\r
+ UDP_IRQn = 34 /**< 34 SAM4S16C USB Device Port (UDP) */\r
+} IRQn_Type;\r
+\r
+typedef struct _DeviceVectors\r
+{\r
+ /* Stack pointer */\r
+ void* pvStack;\r
+\r
+ /* Cortex-M handlers */\r
+ void* pfnReset_Handler;\r
+ void* pfnNMI_Handler;\r
+ void* pfnHardFault_Handler;\r
+ void* pfnMemManage_Handler;\r
+ void* pfnBusFault_Handler;\r
+ void* pfnUsageFault_Handler;\r
+ void* pfnReserved1_Handler;\r
+ void* pfnReserved2_Handler;\r
+ void* pfnReserved3_Handler;\r
+ void* pfnReserved4_Handler;\r
+ void* pfnSVC_Handler;\r
+ void* pfnDebugMon_Handler;\r
+ void* pfnReserved5_Handler;\r
+ void* pfnPendSV_Handler;\r
+ void* pfnSysTick_Handler;\r
+\r
+ /* Peripheral handlers */\r
+ void* pfnSUPC_Handler; /* 0 Supply Controller */\r
+ void* pfnRSTC_Handler; /* 1 Reset Controller */\r
+ void* pfnRTC_Handler; /* 2 Real Time Clock */\r
+ void* pfnRTT_Handler; /* 3 Real Time Timer */\r
+ void* pfnWDT_Handler; /* 4 Watchdog Timer */\r
+ void* pfnPMC_Handler; /* 5 Power Management Controller */\r
+ void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */\r
+ void* pvReserved7;\r
+ void* pfnUART0_Handler; /* 8 UART 0 */\r
+ void* pfnUART1_Handler; /* 9 UART 1 */\r
+ void* pfnSMC_Handler; /* 10 Static Memory Controller */\r
+ void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */\r
+ void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */\r
+ void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */\r
+ void* pfnUSART0_Handler; /* 14 USART 0 */\r
+ void* pfnUSART1_Handler; /* 15 USART 1 */\r
+ void* pvReserved16;\r
+ void* pvReserved17;\r
+ void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */\r
+ void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */\r
+ void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */\r
+ void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */\r
+ void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */\r
+ void* pfnTC0_Handler; /* 23 Timer/Counter 0 */\r
+ void* pfnTC1_Handler; /* 24 Timer/Counter 1 */\r
+ void* pfnTC2_Handler; /* 25 Timer/Counter 2 */\r
+ void* pfnTC3_Handler; /* 26 Timer/Counter 3 */\r
+ void* pfnTC4_Handler; /* 27 Timer/Counter 4 */\r
+ void* pfnTC5_Handler; /* 28 Timer/Counter 5 */\r
+ void* pfnADC_Handler; /* 29 Analog To Digital Converter */\r
+ void* pfnDACC_Handler; /* 30 Digital To Analog Converter */\r
+ void* pfnPWM_Handler; /* 31 Pulse Width Modulation */\r
+ void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */\r
+ void* pfnACC_Handler; /* 33 Analog Comparator */\r
+ void* pfnUDP_Handler; /* 34 USB Device Port */\r
+} DeviceVectors;\r
+\r
+/* Cortex-M4 core handlers */\r
+void Reset_Handler ( void );\r
+void NMI_Handler ( void );\r
+void HardFault_Handler ( void );\r
+void MemManage_Handler ( void );\r
+void BusFault_Handler ( void );\r
+void UsageFault_Handler ( void );\r
+void SVC_Handler ( void );\r
+void DebugMon_Handler ( void );\r
+void PendSV_Handler ( void );\r
+void SysTick_Handler ( void );\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler ( void );\r
+void ADC_Handler ( void );\r
+void CRCCU_Handler ( void );\r
+void DACC_Handler ( void );\r
+void EFC_Handler ( void );\r
+void HSMCI_Handler ( void );\r
+void PIOA_Handler ( void );\r
+void PIOB_Handler ( void );\r
+void PIOC_Handler ( void );\r
+void PMC_Handler ( void );\r
+void PWM_Handler ( void );\r
+void RSTC_Handler ( void );\r
+void RTC_Handler ( void );\r
+void RTT_Handler ( void );\r
+void SMC_Handler ( void );\r
+void SPI_Handler ( void );\r
+void SSC_Handler ( void );\r
+void SUPC_Handler ( void );\r
+void TC0_Handler ( void );\r
+void TC1_Handler ( void );\r
+void TC2_Handler ( void );\r
+void TC3_Handler ( void );\r
+void TC4_Handler ( void );\r
+void TC5_Handler ( void );\r
+void TWI0_Handler ( void );\r
+void TWI1_Handler ( void );\r
+void UART0_Handler ( void );\r
+void UART1_Handler ( void );\r
+void UDP_Handler ( void );\r
+void USART0_Handler ( void );\r
+void USART1_Handler ( void );\r
+void WDT_Handler ( void );\r
+\r
+/**\r
+ * \brief Configuration of the Cortex-M4 Processor and Core Peripherals\r
+ */\r
+\r
+#define __CM4_REV 0x0000 /**< SAM4S16C core revision number ([15:8] revision number, [7:0] patch number) */\r
+#define __MPU_PRESENT 1 /**< SAM4S16C does provide a MPU */\r
+#define __FPU_PRESENT 0 /**< SAM4S16C does not provide a FPU */\r
+#define __NVIC_PRIO_BITS 4 /**< SAM4S16C uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */\r
+\r
+/*\r
+ * \brief CMSIS includes\r
+ */\r
+\r
+#include <core_cm4.h>\r
+#if !defined DONT_USE_CMSIS_INIT\r
+#include "system_sam4s.h"\r
+#endif /* DONT_USE_CMSIS_INIT */\r
+\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_api Peripheral Software API */\r
+/*@{*/\r
+\r
+#include "component/component_acc.h"\r
+#include "component/component_adc.h"\r
+#include "component/component_chipid.h"\r
+#include "component/component_crccu.h"\r
+#include "component/component_dacc.h"\r
+#include "component/component_efc.h"\r
+#include "component/component_gpbr.h"\r
+#include "component/component_hsmci.h"\r
+#include "component/component_matrix.h"\r
+#include "component/component_pdc.h"\r
+#include "component/component_pio.h"\r
+#include "component/component_pmc.h"\r
+#include "component/component_pwm.h"\r
+#include "component/component_rstc.h"\r
+#include "component/component_rtc.h"\r
+#include "component/component_rtt.h"\r
+#include "component/component_smc.h"\r
+#include "component/component_spi.h"\r
+#include "component/component_ssc.h"\r
+#include "component/component_supc.h"\r
+#include "component/component_tc.h"\r
+#include "component/component_twi.h"\r
+#include "component/component_uart.h"\r
+#include "component/component_udp.h"\r
+#include "component/component_usart.h"\r
+#include "component/component_wdt.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* REGISTER ACCESS DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_reg Registers Access Definitions */\r
+/*@{*/\r
+\r
+#include "instance/instance_hsmci.h"\r
+#include "instance/instance_ssc.h"\r
+#include "instance/instance_spi.h"\r
+#include "instance/instance_tc0.h"\r
+#include "instance/instance_tc1.h"\r
+#include "instance/instance_twi0.h"\r
+#include "instance/instance_twi1.h"\r
+#include "instance/instance_pwm.h"\r
+#include "instance/instance_usart0.h"\r
+#include "instance/instance_usart1.h"\r
+#include "instance/instance_udp.h"\r
+#include "instance/instance_adc.h"\r
+#include "instance/instance_dacc.h"\r
+#include "instance/instance_acc.h"\r
+#include "instance/instance_crccu.h"\r
+#include "instance/instance_smc.h"\r
+#include "instance/instance_matrix.h"\r
+#include "instance/instance_pmc.h"\r
+#include "instance/instance_uart0.h"\r
+#include "instance/instance_chipid.h"\r
+#include "instance/instance_uart1.h"\r
+#include "instance/instance_efc.h"\r
+#include "instance/instance_pioa.h"\r
+#include "instance/instance_piob.h"\r
+#include "instance/instance_pioc.h"\r
+#include "instance/instance_rstc.h"\r
+#include "instance/instance_supc.h"\r
+#include "instance/instance_rtt.h"\r
+#include "instance/instance_wdt.h"\r
+#include "instance/instance_rtc.h"\r
+#include "instance/instance_gpbr.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PERIPHERAL ID DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_id Peripheral Ids Definitions */\r
+/*@{*/\r
+\r
+#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */\r
+#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */\r
+#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */\r
+#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */\r
+#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */\r
+#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */\r
+#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */\r
+#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */\r
+#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */\r
+#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */\r
+#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */\r
+#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */\r
+#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */\r
+#define ID_USART0 (14) /**< \brief USART 0 (USART0) */\r
+#define ID_USART1 (15) /**< \brief USART 1 (USART1) */\r
+#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */\r
+#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */\r
+#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */\r
+#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */\r
+#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */\r
+#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */\r
+#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */\r
+#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */\r
+#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */\r
+#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */\r
+#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */\r
+#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */\r
+#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */\r
+#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */\r
+#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */\r
+#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */\r
+#define ID_UDP (34) /**< \brief USB Device Port (UDP) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* BASE ADDRESS DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_base Peripheral Base Address Definitions */\r
+/*@{*/\r
+\r
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))\r
+#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */\r
+#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */\r
+#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */\r
+#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */\r
+#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */\r
+#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */\r
+#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */\r
+#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */\r
+#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */\r
+#else\r
+#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */\r
+#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */\r
+#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */\r
+#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */\r
+#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */\r
+#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */\r
+#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */\r
+#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */\r
+#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */\r
+#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */\r
+#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */\r
+#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */\r
+#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */\r
+#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */\r
+#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */\r
+#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */\r
+#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */\r
+#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */\r
+#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */\r
+#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */\r
+#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */\r
+#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */\r
+#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */\r
+#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */\r
+#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */\r
+#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */\r
+#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */\r
+#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */\r
+#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */\r
+#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */\r
+#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */\r
+#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */\r
+#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */\r
+#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */\r
+#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */\r
+#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */\r
+#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */\r
+#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */\r
+#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */\r
+#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */\r
+#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */\r
+#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */\r
+#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */\r
+#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */\r
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* PIO DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+/** \addtogroup SAM4S16C_pio Peripheral Pio Definitions */\r
+/*@{*/\r
+\r
+#include "pio/pio_sam4s16c.h"\r
+/*@}*/\r
+\r
+/* ************************************************************************** */\r
+/* MEMORY MAPPING DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+\r
+#define IFLASH_SIZE (0x100000u)\r
+#define IFLASH_PAGE_SIZE (512u)\r
+#define IFLASH_LOCK_REGION_SIZE (8192u)\r
+#define IFLASH_NB_OF_PAGES (2048u)\r
+#define IFLASH_NB_OF_LOCK_BITS (128u)\r
+#define IRAM_SIZE (0x20000u)\r
+\r
+#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */\r
+#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */\r
+#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */\r
+#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */\r
+#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */\r
+#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */\r
+#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */\r
+\r
+/* ************************************************************************** */\r
+/* ELECTRICAL DEFINITIONS FOR SAM4S16C */\r
+/* ************************************************************************** */\r
+\r
+/* Device characteristics */\r
+#define CHIP_FREQ_SLCK_RC_MIN (20000UL)\r
+#define CHIP_FREQ_SLCK_RC (32000UL)\r
+#define CHIP_FREQ_SLCK_RC_MAX (44000UL)\r
+#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)\r
+#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)\r
+#define CHIP_FREQ_CPU_MAX (120000000UL)\r
+#define CHIP_FREQ_XTAL_32K (32768UL)\r
+#define CHIP_FREQ_XTAL_12M (12000000UL)\r
+\r
+/* Embedded Flash Write Wait State */\r
+#define CHIP_FLASH_WRITE_WAIT_STATE (6U)\r
+\r
+/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */\r
+#define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */\r
+#define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */\r
+#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */\r
+#define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */\r
+#define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/\r
+\r
+#endif /* _SAM4S16C_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the default exception handlers.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ * \par Purpose\r
+ *\r
+ * This file provides basic support for Cortex-M processor based \r
+ * microcontrollers.\r
+ *\r
+ * \note\r
+ * The exception handler has weak aliases.\r
+ * As they are weak aliases, any function with the same name will override\r
+ * this definition.\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#ifdef __GNUC__\r
+/* Cortex-M3 core handlers */\r
+void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+\r
+/* Peripherals handlers */\r
+void ACC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void ADC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void CRCCU_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void DACC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void EFC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void HSMCI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOA_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOB_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PIOC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PMC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void PWM_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RSTC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void RTT_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SMC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SPI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SSC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void SUPC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC2_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC3_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC4_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TC5_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void TWI1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UART1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART0_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void USART1_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void UDP_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+void WDT_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));\r
+#endif /* __GNUC__ */\r
+\r
+#ifdef __ICCARM__\r
+/* Cortex-M3 core handlers */\r
+#pragma weak Reset_Handler=Dummy_Handler\r
+#pragma weak NMI_Handler=Dummy_Handler\r
+#pragma weak HardFault_Handler=Dummy_Handler\r
+#pragma weak MemManage_Handler=Dummy_Handler\r
+#pragma weak BusFault_Handler=Dummy_Handler\r
+#pragma weak UsageFault_Handler=Dummy_Handler\r
+#pragma weak SVC_Handler=Dummy_Handler\r
+#pragma weak DebugMon_Handler=Dummy_Handler\r
+#pragma weak PendSV_Handler=Dummy_Handler\r
+#pragma weak SysTick_Handler=Dummy_Handler\r
+\r
+/* Peripherals handlers */\r
+#pragma weak ACC_Handler=Dummy_Handler\r
+#pragma weak ADC_Handler=Dummy_Handler\r
+#pragma weak CRCCU_Handler=Dummy_Handler\r
+#pragma weak DACC_Handler=Dummy_Handler\r
+#pragma weak EFC_Handler=Dummy_Handler\r
+#pragma weak HSMCI_Handler=Dummy_Handler\r
+#pragma weak PIOA_Handler=Dummy_Handler\r
+#pragma weak PIOB_Handler=Dummy_Handler\r
+#pragma weak PIOC_Handler=Dummy_Handler\r
+#pragma weak PMC_Handler=Dummy_Handler\r
+#pragma weak PWM_Handler=Dummy_Handler\r
+#pragma weak RSTC_Handler=Dummy_Handler\r
+#pragma weak RTC_Handler=Dummy_Handler\r
+#pragma weak RTT_Handler=Dummy_Handler\r
+#pragma weak SMC_Handler=Dummy_Handler\r
+#pragma weak SPI_Handler=Dummy_Handler\r
+#pragma weak SSC_Handler=Dummy_Handler\r
+#pragma weak SUPC_Handler=Dummy_Handler\r
+#pragma weak TC0_Handler=Dummy_Handler\r
+#pragma weak TC1_Handler=Dummy_Handler\r
+#pragma weak TC2_Handler=Dummy_Handler\r
+#pragma weak TC3_Handler=Dummy_Handler\r
+#pragma weak TC4_Handler=Dummy_Handler\r
+#pragma weak TC5_Handler=Dummy_Handler\r
+#pragma weak TWI0_Handler=Dummy_Handler\r
+#pragma weak TWI1_Handler=Dummy_Handler\r
+#pragma weak UART0_Handler=Dummy_Handler\r
+#pragma weak UART1_Handler=Dummy_Handler\r
+#pragma weak USART0_Handler=Dummy_Handler\r
+#pragma weak USART1_Handler=Dummy_Handler\r
+#pragma weak UDP_Handler=Dummy_Handler\r
+#pragma weak WDT_Handler=Dummy_Handler\r
+#endif /* __ICCARM__ */\r
+\r
+/**\r
+ * \brief Default interrupt handler for unused IRQs.\r
+ */\r
+void Dummy_Handler(void)\r
+{\r
+ while (1) {\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief This file contains the interface for default exception handlers.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef EXCEPTIONS_H_INCLUDED\r
+#define EXCEPTIONS_H_INCLUDED\r
+\r
+#include "sam4s.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Function prototype for exception table items (interrupt handler). */\r
+typedef void (*IntFunc) (void);\r
+\r
+/* Default empty handler */\r
+void Dummy_Handler(void);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* EXCEPTIONS_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Startup file for SAM4S.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "exceptions.h"\r
+#include "sam4s.h"\r
+#include "system_sam4s.h"\r
+\r
+/* Initialize segments */\r
+extern uint32_t _sfixed;\r
+extern uint32_t _efixed;\r
+extern uint32_t _etext;\r
+extern uint32_t _srelocate;\r
+extern uint32_t _erelocate;\r
+extern uint32_t _szero;\r
+extern uint32_t _ezero;\r
+extern uint32_t _sstack;\r
+extern uint32_t _estack;\r
+\r
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */\r
+int main(void);\r
+/** \endcond */\r
+\r
+void __libc_init_array(void);\r
+\r
+/* Exception Table */\r
+__attribute__ ((section(".vectors")))\r
+IntFunc exception_table[] = {\r
+\r
+ /* Configure Initial Stack Pointer, using linker-generated symbols */\r
+ (IntFunc) (&_estack),\r
+ Reset_Handler,\r
+\r
+ NMI_Handler,\r
+ HardFault_Handler,\r
+ MemManage_Handler,\r
+ BusFault_Handler,\r
+ UsageFault_Handler,\r
+ 0, 0, 0, 0, /* Reserved */\r
+ SVC_Handler,\r
+ DebugMon_Handler,\r
+ 0, /* Reserved */\r
+ PendSV_Handler,\r
+ SysTick_Handler,\r
+\r
+ /* Configurable interrupts */\r
+ SUPC_Handler, /* 0 Supply Controller */\r
+ RSTC_Handler, /* 1 Reset Controller */\r
+ RTC_Handler, /* 2 Real Time Clock */\r
+ RTT_Handler, /* 3 Real Time Timer */\r
+ WDT_Handler, /* 4 Watchdog Timer */\r
+ PMC_Handler, /* 5 PMC */\r
+ EFC_Handler, /* 6 EFC */\r
+ Dummy_Handler, /* 7 Reserved */\r
+ UART0_Handler, /* 8 UART0 */\r
+ UART1_Handler, /* 9 UART1 */\r
+ SMC_Handler, /* 10 SMC */\r
+ PIOA_Handler, /* 11 Parallel IO Controller A */\r
+ PIOB_Handler, /* 12 Parallel IO Controller B */\r
+ PIOC_Handler, /* 13 Parallel IO Controller C */\r
+ USART0_Handler, /* 14 USART 0 */\r
+ USART1_Handler, /* 15 USART 1 */\r
+ Dummy_Handler, /* 16 Reserved */\r
+ Dummy_Handler, /* 17 Reserved */\r
+ HSMCI_Handler, /* 18 HSMCI */\r
+ TWI0_Handler, /* 19 TWI 0 */\r
+ TWI1_Handler, /* 20 TWI 1 */\r
+ SPI_Handler, /* 21 SPI */\r
+ SSC_Handler, /* 22 SSC */\r
+ TC0_Handler, /* 23 Timer Counter 0 */\r
+ TC1_Handler, /* 24 Timer Counter 1 */\r
+ TC2_Handler, /* 25 Timer Counter 2 */\r
+ TC3_Handler, /* 26 Timer Counter 3 */\r
+ TC4_Handler, /* 27 Timer Counter 4 */\r
+ TC5_Handler, /* 28 Timer Counter 5 */\r
+ ADC_Handler, /* 29 ADC controller */\r
+ DACC_Handler, /* 30 DACC controller */\r
+ PWM_Handler, /* 31 PWM */\r
+ CRCCU_Handler, /* 32 CRC Calculation Unit */\r
+ ACC_Handler, /* 33 Analog Comparator */\r
+ UDP_Handler, /* 34 USB Device Port */\r
+ Dummy_Handler /* 35 not used */\r
+};\r
+\r
+/* TEMPORARY PATCH FOR SCB */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+/**\r
+ * \brief This is the code that gets called on processor reset.\r
+ * To initialize the device, and call the main() routine.\r
+ */\r
+void Reset_Handler(void)\r
+{\r
+ uint32_t *pSrc, *pDest;\r
+\r
+ /* Initialize the relocate segment */\r
+ pSrc = &_etext;\r
+ pDest = &_srelocate;\r
+\r
+ if (pSrc != pDest) {\r
+ for (; pDest < &_erelocate;) {\r
+ *pDest++ = *pSrc++;\r
+ }\r
+ }\r
+\r
+ /* Clear the zero segment */\r
+ for (pDest = &_szero; pDest < &_ezero;) {\r
+ *pDest++ = 0;\r
+ }\r
+\r
+ /* Set the vector table base address */\r
+ pSrc = (uint32_t *) & _sfixed;\r
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);\r
+\r
+ if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {\r
+ SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;\r
+ }\r
+\r
+ /* Initialize the C library */\r
+ __libc_init_array();\r
+\r
+ /* Branch to main function */\r
+ main();\r
+\r
+ /* Infinite loop */\r
+ while (1);\r
+}\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#include "system_sam4s.h"\r
+#include "sam4s.h"\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+/* Clock Settings (120MHz) */\r
+#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))\r
+#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE \\r
+ | CKGR_PLLAR_MULA(0x13U) \\r
+ | CKGR_PLLAR_PLLACOUNT(0x3fU) \\r
+ | CKGR_PLLAR_DIVA(0x1U))\r
+#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK)\r
+\r
+#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */\r
+\r
+/* FIXME: should be generated by sock */\r
+uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+/**\r
+ * \brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemFrequency variable.\r
+ */\r
+void SystemInit(void)\r
+{\r
+ /* Set FWS according to SYS_BOARD_MCKR configuration */\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
+\r
+ /* Initialize main oscillator */\r
+ if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {\r
+ }\r
+ }\r
+\r
+ /* Switch to 3-20MHz Xtal oscillator */\r
+ PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | \r
+ CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;\r
+\r
+ while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {\r
+ }\r
+ PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | \r
+ PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Initialize PLLA */\r
+ PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;\r
+ while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {\r
+ }\r
+\r
+ /* Switch to main clock */\r
+ PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ /* Switch to PLLA */\r
+ PMC->PMC_MCKR = SYS_BOARD_MCKR;\r
+ while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {\r
+ }\r
+\r
+ SystemCoreClock = CHIP_FREQ_CPU_MAX;\r
+}\r
+\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ /* Determine clock frequency according to clock register values */\r
+ switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {\r
+ case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */\r
+ if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_32K;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_SLCK_RC;\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ break;\r
+ case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */\r
+ case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */\r
+ if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {\r
+ SystemCoreClock = CHIP_FREQ_XTAL_12M;\r
+ } else {\r
+ SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;\r
+\r
+ switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {\r
+ case CKGR_MOR_MOSCRCF_4_MHz:\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_8_MHz:\r
+ SystemCoreClock *= 2U;\r
+ break;\r
+ case CKGR_MOR_MOSCRCF_12_MHz:\r
+ SystemCoreClock *= 3U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> \r
+ CKGR_PLLAR_MULA_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> \r
+ CKGR_PLLAR_DIVA_Pos));\r
+ } else {\r
+ SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >> \r
+ CKGR_PLLBR_MULB_Pos) + 1U);\r
+ SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> \r
+ CKGR_PLLBR_DIVB_Pos));\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {\r
+ SystemCoreClock /= 3U;\r
+ } else {\r
+ SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);\r
+ }\r
+}\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk)\r
+{\r
+ /* Set FWS for embedded Flash access according to operating frequency */\r
+ if (ul_clk < CHIP_FREQ_FWS_0) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(0);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_1) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(1);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_2) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(2);\r
+ } else if (ul_clk < CHIP_FREQ_FWS_3) {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(3);\r
+ } else {\r
+ EFC->EEFC_FMR = EEFC_FMR_FWS(4);\r
+ }\r
+}\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Provides the low-level initialization functions that called \r
+ * on chip startup.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef SYSTEM_SAM4S_H_INCLUDED\r
+#define SYSTEM_SAM4S_H_INCLUDED\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#include <stdint.h>\r
+\r
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the System and update the SystemCoreClock variable.\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock with current core Clock \r
+ * retrieved from cpu registers.\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
+/** \r
+ * Initialize flash.\r
+ */\r
+void system_init_flash(uint32_t ul_clk);\r
+\r
+/* @cond 0 */\r
+/**INDENT-OFF**/\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+/**INDENT-ON**/\r
+/* @endcond */\r
+\r
+#endif /* SYSTEM_SAM4S_H_INCLUDED */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Commonly used includes, types and macros.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef UTILS_COMPILER_H\r
+#define UTILS_COMPILER_H\r
+\r
+/**\r
+ * \defgroup group_sam_utils Compiler abstraction layer and code utilities\r
+ *\r
+ * Compiler abstraction layer and code utilities for AT91SAM.\r
+ * This module provides various abstraction layers and utilities to make code compatible between different compilers.\r
+ *\r
+ * \{\r
+ */\r
+#include <stddef.h>\r
+\r
+#if (defined __ICCARM__)\r
+# include <intrinsics.h>\r
+#endif\r
+\r
+#include "parts.h"\r
+#include "preprocessor.h"\r
+\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+\r
+#ifndef __ASSEMBLY__ // Not defined for assembling.\r
+\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+\r
+#ifdef __ICCARM__\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GCC to IAR Embedded Workbench.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+/**\r
+ * \def barrier\r
+ * \brief Memory barrier\r
+ */\r
+#define barrier() __DMB()\r
+\r
+/**\r
+ * \brief Emit the compiler pragma \a arg.\r
+ *\r
+ * \param arg The pragma directive as it would appear after \e \#pragma\r
+ * (i.e. not stringified).\r
+ */\r
+#define COMPILER_PRAGMA(arg) _Pragma(#arg)\r
+\r
+/**\r
+ * \def COMPILER_PACK_SET(alignment)\r
+ * \brief Set maximum alignment for subsequent struct and union\r
+ * definitions to \a alignment.\r
+ */\r
+#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))\r
+\r
+/**\r
+ * \def COMPILER_PACK_RESET()\r
+ * \brief Set default alignment for subsequent struct and union\r
+ * definitions.\r
+ */\r
+#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())\r
+\r
+\r
+/**\r
+ * \brief Set aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))\r
+#elif (defined __ICCARM__)\r
+# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)\r
+#endif\r
+\r
+/**\r
+ * \brief Set word-aligned boundary.\r
+ */\r
+#if (defined __GNUC__) || defined(__CC_ARM)\r
+#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))\r
+#elif (defined __ICCARM__)\r
+#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)\r
+#endif\r
+\r
+/**\r
+ * \def __always_inline\r
+ * \brief The function should always be inlined.\r
+ *\r
+ * This annotation instructs the compiler to ignore its inlining\r
+ * heuristics and inline the function no matter how big it thinks it\r
+ * becomes.\r
+ */\r
+#if defined(__CC_ARM)\r
+# define __always_inline __forceinline\r
+#elif (defined __GNUC__)\r
+# define __always_inline __attribute__((__always_inline__))\r
+#elif (defined __ICCARM__)\r
+# define __always_inline _Pragma("inline=forced")\r
+#endif\r
+\r
+/*! \brief This macro is used to test fatal errors.\r
+ *\r
+ * The macro tests if the expression is false. If it is, a fatal error is\r
+ * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO\r
+ * is defined, a unit test version of the macro is used, to allow execution\r
+ * of further tests after a false expression.\r
+ *\r
+ * \param expr Expression to evaluate and supposed to be nonzero.\r
+ */\r
+#if defined(_ASSERT_ENABLE_)\r
+# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)\r
+ // Assert() is defined in unit_test/suite.h\r
+# include "unit_test/suite.h"\r
+# else\r
+#undef TEST_SUITE_DEFINE_ASSERT_MACRO\r
+# define Assert(expr) \\r
+ {\\r
+ if (!(expr)) while (true);\\r
+ }\r
+# endif\r
+#else\r
+# define Assert(expr) ((void) 0)\r
+#endif\r
+\r
+/* Define attribute */\r
+#if defined ( __CC_ARM ) /* Keil µVision 4 */\r
+# define WEAK __attribute__ ((weak))\r
+#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */\r
+# define WEAK __weak\r
+#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */\r
+# define WEAK __attribute__ ((weak))\r
+#endif\r
+\r
+/* Define NO_INIT attribute */\r
+#if defined ( __CC_ARM )\r
+# define NO_INIT __attribute__((zero_init))\r
+#elif defined ( __ICCARM__ )\r
+# define NO_INIT __no_init\r
+#elif defined ( __GNUC__ )\r
+# define NO_INIT __attribute__((section(".no_init")))\r
+#endif\r
+\r
+#include "interrupt.h"\r
+\r
+/*! \name Usual Types\r
+ */\r
+//! @{\r
+typedef unsigned char Bool; //!< Boolean.\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+typedef unsigned char bool; //!< Boolean.\r
+#endif\r
+#endif\r
+typedef int8_t S8 ; //!< 8-bit signed integer.\r
+typedef uint8_t U8 ; //!< 8-bit unsigned integer.\r
+typedef int16_t S16; //!< 16-bit signed integer.\r
+typedef uint16_t U16; //!< 16-bit unsigned integer.\r
+typedef uint16_t le16_t;\r
+typedef uint16_t be16_t;\r
+typedef int32_t S32; //!< 32-bit signed integer.\r
+typedef uint32_t U32; //!< 32-bit unsigned integer.\r
+typedef uint32_t le32_t;\r
+typedef uint32_t be32_t;\r
+typedef int64_t S64; //!< 64-bit signed integer.\r
+typedef uint64_t U64; //!< 64-bit unsigned integer.\r
+typedef float F32; //!< 32-bit floating-point number.\r
+typedef double F64; //!< 64-bit floating-point number.\r
+typedef uint32_t iram_size_t;\r
+//! @}\r
+\r
+\r
+/*! \name Status Types\r
+ */\r
+//! @{\r
+typedef bool Status_bool_t; //!< Boolean status.\r
+typedef U8 Status_t; //!< 8-bit-coded status.\r
+//! @}\r
+\r
+\r
+/*! \name Aliasing Aggregate Types\r
+ */\r
+//! @{\r
+\r
+//! 16-bit union.\r
+typedef union\r
+{\r
+ S16 s16 ;\r
+ U16 u16 ;\r
+ S8 s8 [2];\r
+ U8 u8 [2];\r
+} Union16;\r
+\r
+//! 32-bit union.\r
+typedef union\r
+{\r
+ S32 s32 ;\r
+ U32 u32 ;\r
+ S16 s16[2];\r
+ U16 u16[2];\r
+ S8 s8 [4];\r
+ U8 u8 [4];\r
+} Union32;\r
+\r
+//! 64-bit union.\r
+typedef union\r
+{\r
+ S64 s64 ;\r
+ U64 u64 ;\r
+ S32 s32[2];\r
+ U32 u32[2];\r
+ S16 s16[4];\r
+ U16 u16[4];\r
+ S8 s8 [8];\r
+ U8 u8 [8];\r
+} Union64;\r
+\r
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} UnionPtr;\r
+\r
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} UnionVPtr;\r
+\r
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} UnionCPtr;\r
+\r
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef union\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} UnionCVPtr;\r
+\r
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ S64 *s64ptr;\r
+ U64 *u64ptr;\r
+ S32 *s32ptr;\r
+ U32 *u32ptr;\r
+ S16 *s16ptr;\r
+ U16 *u16ptr;\r
+ S8 *s8ptr ;\r
+ U8 *u8ptr ;\r
+} StructPtr;\r
+\r
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ volatile S64 *s64ptr;\r
+ volatile U64 *u64ptr;\r
+ volatile S32 *s32ptr;\r
+ volatile U32 *u32ptr;\r
+ volatile S16 *s16ptr;\r
+ volatile U16 *u16ptr;\r
+ volatile S8 *s8ptr ;\r
+ volatile U8 *u8ptr ;\r
+} StructVPtr;\r
+\r
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const S64 *s64ptr;\r
+ const U64 *u64ptr;\r
+ const S32 *s32ptr;\r
+ const U32 *u32ptr;\r
+ const S16 *s16ptr;\r
+ const U16 *u16ptr;\r
+ const S8 *s8ptr ;\r
+ const U8 *u8ptr ;\r
+} StructCPtr;\r
+\r
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.\r
+typedef struct\r
+{\r
+ const volatile S64 *s64ptr;\r
+ const volatile U64 *u64ptr;\r
+ const volatile S32 *s32ptr;\r
+ const volatile U32 *u32ptr;\r
+ const volatile S16 *s16ptr;\r
+ const volatile U16 *u16ptr;\r
+ const volatile S8 *s8ptr ;\r
+ const volatile U8 *u8ptr ;\r
+} StructCVPtr;\r
+\r
+//! @}\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/*! \name Usual Constants\r
+ */\r
+//! @{\r
+#define DISABLE 0\r
+#define ENABLE 1\r
+#ifndef __cplusplus\r
+#if !defined(__bool_true_false_are_defined)\r
+#define false 0\r
+#define true 1\r
+#endif\r
+#endif\r
+#define PASS 0\r
+#define FAIL 1\r
+#define LOW 0\r
+#define HIGH 1\r
+//! @}\r
+\r
+\r
+#ifndef __ASSEMBLY__ // not for assembling.\r
+\r
+//! \name Optimization Control\r
+//@{\r
+\r
+/**\r
+ * \def likely(exp)\r
+ * \brief The expression \a exp is likely to be true\r
+ */\r
+#ifndef likely\r
+# define likely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def unlikely(exp)\r
+ * \brief The expression \a exp is unlikely to be true\r
+ */\r
+#ifndef unlikely\r
+# define unlikely(exp) (exp)\r
+#endif\r
+\r
+/**\r
+ * \def is_constant(exp)\r
+ * \brief Determine if an expression evaluates to a constant value.\r
+ *\r
+ * \param exp Any expression\r
+ *\r
+ * \return true if \a exp is constant, false otherwise.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define is_constant(exp) __builtin_constant_p(exp)\r
+#else\r
+# define is_constant(exp) (0)\r
+#endif\r
+\r
+//! @}\r
+\r
+/*! \name Bit-Field Handling\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read bits from.\r
+ * \param mask Bit-mask indicating bits to read.\r
+ *\r
+ * \return Read bits.\r
+ */\r
+#define Rd_bits( value, mask) ((value) & (mask))\r
+\r
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write bits to.\r
+ * \param mask Bit-mask indicating bits to write.\r
+ * \param bits Bits to write.\r
+ *\r
+ * \return Resulting value with written bits.\r
+ */\r
+#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\\r
+ ((bits ) & (mask)))\r
+\r
+/*! \brief Tests the bits of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value of which to test bits.\r
+ * \param mask Bit-mask indicating bits to test.\r
+ *\r
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.\r
+ */\r
+#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)\r
+\r
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to clear bits.\r
+ * \param mask Bit-mask indicating bits to clear.\r
+ *\r
+ * \return Resulting value with cleared bits.\r
+ */\r
+#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))\r
+\r
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to set bits.\r
+ * \param mask Bit-mask indicating bits to set.\r
+ *\r
+ * \return Resulting value with set bits.\r
+ */\r
+#define Set_bits(lvalue, mask) ((lvalue) |= (mask))\r
+\r
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue of which to toggle bits.\r
+ * \param mask Bit-mask indicating bits to toggle.\r
+ *\r
+ * \return Resulting value with toggled bits.\r
+ */\r
+#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))\r
+\r
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.\r
+ *\r
+ * \param value Value to read a bit-field from.\r
+ * \param mask Bit-mask indicating the bit-field to read.\r
+ *\r
+ * \return Read bit-field.\r
+ */\r
+#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))\r
+\r
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.\r
+ *\r
+ * \param lvalue C lvalue to write a bit-field to.\r
+ * \param mask Bit-mask indicating the bit-field to write.\r
+ * \param bitfield Bit-field to write.\r
+ *\r
+ * \return Resulting value with written bit-field.\r
+ */\r
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Zero-Bit Counting\r
+ *\r
+ * Under GCC, __builtin_clz and __builtin_ctz behave like macros when\r
+ * applied to constant expressions (values known at compile time), so they are\r
+ * more optimized than the use of the corresponding assembly instructions and\r
+ * they can be used as constant expressions e.g. to initialize objects having\r
+ * static storage duration, and like the corresponding assembly instructions\r
+ * when applied to non-constant expressions (values unknown at compile time), so\r
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz\r
+ * ensure a possible and optimized behavior for both constant and non-constant\r
+ * expressions.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the leading zero bits.\r
+ *\r
+ * \return The count of leading zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define clz(u) __builtin_clz(u)\r
+#elif (defined __ICCARM__)\r
+# define clz(u) __CLZ(u)\r
+#else\r
+# define clz(u) (((u) == 0) ? 32 : \\r
+ ((u) & (1ul << 31)) ? 0 : \\r
+ ((u) & (1ul << 30)) ? 1 : \\r
+ ((u) & (1ul << 29)) ? 2 : \\r
+ ((u) & (1ul << 28)) ? 3 : \\r
+ ((u) & (1ul << 27)) ? 4 : \\r
+ ((u) & (1ul << 26)) ? 5 : \\r
+ ((u) & (1ul << 25)) ? 6 : \\r
+ ((u) & (1ul << 24)) ? 7 : \\r
+ ((u) & (1ul << 23)) ? 8 : \\r
+ ((u) & (1ul << 22)) ? 9 : \\r
+ ((u) & (1ul << 21)) ? 10 : \\r
+ ((u) & (1ul << 20)) ? 11 : \\r
+ ((u) & (1ul << 19)) ? 12 : \\r
+ ((u) & (1ul << 18)) ? 13 : \\r
+ ((u) & (1ul << 17)) ? 14 : \\r
+ ((u) & (1ul << 16)) ? 15 : \\r
+ ((u) & (1ul << 15)) ? 16 : \\r
+ ((u) & (1ul << 14)) ? 17 : \\r
+ ((u) & (1ul << 13)) ? 18 : \\r
+ ((u) & (1ul << 12)) ? 19 : \\r
+ ((u) & (1ul << 11)) ? 20 : \\r
+ ((u) & (1ul << 10)) ? 21 : \\r
+ ((u) & (1ul << 9)) ? 22 : \\r
+ ((u) & (1ul << 8)) ? 23 : \\r
+ ((u) & (1ul << 7)) ? 24 : \\r
+ ((u) & (1ul << 6)) ? 25 : \\r
+ ((u) & (1ul << 5)) ? 26 : \\r
+ ((u) & (1ul << 4)) ? 27 : \\r
+ ((u) & (1ul << 3)) ? 28 : \\r
+ ((u) & (1ul << 2)) ? 29 : \\r
+ ((u) & (1ul << 1)) ? 30 : \\r
+ 31)\r
+#endif\r
+\r
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.\r
+ *\r
+ * \param u Value of which to count the trailing zero bits.\r
+ *\r
+ * \return The count of trailing zero bits in \a u.\r
+ */\r
+#if (defined __GNUC__) || (defined __CC_ARM)\r
+# define ctz(u) __builtin_ctz(u)\r
+#else\r
+# define ctz(u) ((u) & (1ul << 0) ? 0 : \\r
+ (u) & (1ul << 1) ? 1 : \\r
+ (u) & (1ul << 2) ? 2 : \\r
+ (u) & (1ul << 3) ? 3 : \\r
+ (u) & (1ul << 4) ? 4 : \\r
+ (u) & (1ul << 5) ? 5 : \\r
+ (u) & (1ul << 6) ? 6 : \\r
+ (u) & (1ul << 7) ? 7 : \\r
+ (u) & (1ul << 8) ? 8 : \\r
+ (u) & (1ul << 9) ? 9 : \\r
+ (u) & (1ul << 10) ? 10 : \\r
+ (u) & (1ul << 11) ? 11 : \\r
+ (u) & (1ul << 12) ? 12 : \\r
+ (u) & (1ul << 13) ? 13 : \\r
+ (u) & (1ul << 14) ? 14 : \\r
+ (u) & (1ul << 15) ? 15 : \\r
+ (u) & (1ul << 16) ? 16 : \\r
+ (u) & (1ul << 17) ? 17 : \\r
+ (u) & (1ul << 18) ? 18 : \\r
+ (u) & (1ul << 19) ? 19 : \\r
+ (u) & (1ul << 20) ? 20 : \\r
+ (u) & (1ul << 21) ? 21 : \\r
+ (u) & (1ul << 22) ? 22 : \\r
+ (u) & (1ul << 23) ? 23 : \\r
+ (u) & (1ul << 24) ? 24 : \\r
+ (u) & (1ul << 25) ? 25 : \\r
+ (u) & (1ul << 26) ? 26 : \\r
+ (u) & (1ul << 27) ? 27 : \\r
+ (u) & (1ul << 28) ? 28 : \\r
+ (u) & (1ul << 29) ? 29 : \\r
+ (u) & (1ul << 30) ? 30 : \\r
+ (u) & (1ul << 31) ? 31 : \\r
+ 32)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Bit Reversing\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reverses the bits of \a u8.\r
+ *\r
+ * \param u8 U8 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u8 with reversed bits.\r
+ */\r
+#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))\r
+\r
+/*! \brief Reverses the bits of \a u16.\r
+ *\r
+ * \param u16 U16 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u16 with reversed bits.\r
+ */\r
+#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))\r
+\r
+/*! \brief Reverses the bits of \a u32.\r
+ *\r
+ * \param u32 U32 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u32 with reversed bits.\r
+ */\r
+#define bit_reverse32(u32) __RBIT(u32)\r
+\r
+/*! \brief Reverses the bits of \a u64.\r
+ *\r
+ * \param u64 U64 of which to reverse the bits.\r
+ *\r
+ * \return Value resulting from \a u64 with reversed bits.\r
+ */\r
+#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\\r
+ ((U64)bit_reverse32((U64)(u64)) << 32)))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Alignment\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tests alignment of the number \a val with the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.\r
+ */\r
+#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Alignment of the number \a val with respect to the \a n boundary.\r
+ */\r
+#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )\r
+\r
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.\r
+ *\r
+ * \param lval Input/output lvalue.\r
+ * \param n Boundary.\r
+ * \param alg Alignment.\r
+ *\r
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.\r
+ */\r
+#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )\r
+\r
+/*! \brief Aligns the number \a val with the upper \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.\r
+ */\r
+#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))\r
+\r
+/*! \brief Aligns the number \a val with the lower \a n boundary.\r
+ *\r
+ * \param val Input value.\r
+ * \param n Boundary.\r
+ *\r
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.\r
+ */\r
+#define Align_down(val, n ) ( (val) & ~((n) - 1))\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Mathematics\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC does not\r
+ * provide built-in functions to access the assembly instructions abs, min and\r
+ * max and it does not produce them by itself in most cases, so two sets of\r
+ * macros are defined here:\r
+ * - Abs, Min and Max to apply to constant expressions (values known at\r
+ * compile time);\r
+ * - abs, min and max to apply to non-constant expressions (values unknown at\r
+ * compile time), abs is found in stdlib.h.\r
+ */\r
+//! @{\r
+\r
+/*! \brief Takes the absolute value of \a a.\r
+ *\r
+ * \param a Input value.\r
+ *\r
+ * \return Absolute value of \a a.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Abs(a) (((a) < 0 ) ? -(a) : (a))\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Min(a, b) (((a) < (b)) ? (a) : (b))\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Max(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+// abs() is already defined by stdlib.h\r
+\r
+/*! \brief Takes the minimal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Minimal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define min(a, b) Min(a, b)\r
+\r
+/*! \brief Takes the maximal value of \a a and \a b.\r
+ *\r
+ * \param a Input value.\r
+ * \param b Input value.\r
+ *\r
+ * \return Maximal value of \a a and \a b.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define max(a, b) Max(a, b)\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Calls the routine at address \a addr.\r
+ *\r
+ * It generates a long call opcode.\r
+ *\r
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if\r
+ * it is invoked from the CPU supervisor mode.\r
+ *\r
+ * \param addr Address of the routine to call.\r
+ *\r
+ * \note It may be used as a long jump opcode in some special cases.\r
+ */\r
+#define Long_call(addr) ((*(void (*)(void))(addr))())\r
+\r
+\r
+/*! \name MCU Endianism Handling\r
+ * ARM is MCU little endianism.\r
+ */\r
+//! @{\r
+#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
+\r
+#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
+#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
+#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.\r
+#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.\r
+#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+ \r
+#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
+#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
+#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.\r
+#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.\r
+#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.\r
+#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.\r
+#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
+#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.\r
+#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.\r
+#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.\r
+#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.\r
+#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.\r
+#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.\r
+#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.\r
+#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.\r
+#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
+#define BE16(x) Swap16(x)\r
+#define LE16(x) (x)\r
+\r
+#define le16_to_cpu(x) (x)\r
+#define cpu_to_le16(x) (x)\r
+#define LE16_TO_CPU(x) (x)\r
+#define CPU_TO_LE16(x) (x)\r
+\r
+#define be16_to_cpu(x) Swap16(x)\r
+#define cpu_to_be16(x) Swap16(x)\r
+#define BE16_TO_CPU(x) Swap16(x)\r
+#define CPU_TO_BE16(x) Swap16(x)\r
+\r
+#define le32_to_cpu(x) (x)\r
+#define cpu_to_le32(x) (x)\r
+#define LE32_TO_CPU(x) (x)\r
+#define CPU_TO_LE32(x) (x)\r
+\r
+#define be32_to_cpu(x) swap32(x)\r
+#define cpu_to_be32(x) swap32(x)\r
+#define BE32_TO_CPU(x) swap32(x)\r
+#define CPU_TO_BE32(x) swap32(x)\r
+//! @}\r
+\r
+\r
+/*! \name Endianism Conversion\r
+ *\r
+ * The same considerations as for clz and ctz apply here but GCC's\r
+ * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when\r
+ * applied to constant expressions, so two sets of macros are defined here:\r
+ * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known\r
+ * at compile time);\r
+ * - swap16, swap32 and swap64 to apply to non-constant expressions (values\r
+ * unknown at compile time).\r
+ */\r
+//! @{\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\\r
+ ((U16)(u16) << 8)))\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\\r
+ ((U32)Swap16((U32)(u32)) << 16)))\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values known at compile time.\r
+ */\r
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\\r
+ ((U64)Swap32((U64)(u64)) << 32)))\r
+\r
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).\r
+ *\r
+ * \param u16 U16 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u16 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#define swap16(u16) Swap16(u16)\r
+\r
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).\r
+ *\r
+ * \param u32 U32 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u32 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))\r
+#else\r
+# define swap32(u32) Swap32(u32)\r
+#endif\r
+\r
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).\r
+ *\r
+ * \param u64 U64 of which to toggle the endianism.\r
+ *\r
+ * \return Value resulting from \a u64 with toggled endianism.\r
+ *\r
+ * \note More optimized if only used with values unknown at compile time.\r
+ */\r
+#if (defined __GNUC__)\r
+# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))\r
+#else\r
+# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\\r
+ ((U64)swap32((U64)(u64)) << 32)))\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
+/**\r
+ * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using\r
+ * integer arithmetic.\r
+ *\r
+ * \param a An integer\r
+ * \param b Another integer\r
+ *\r
+ * \return (\a a / \a b) rounded up to the nearest integer.\r
+ */\r
+#define div_ceil(a, b) (((a) + (b) - 1) / (b))\r
+\r
+#endif // #ifndef __ASSEMBLY__\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif /* UTILS_COMPILER_H */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM.\r
+ *\r
+ * This file defines common SAM series.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_IO_\r
+#define _SAM_IO_\r
+\r
+/* SAM3 family */\r
+\r
+/* SAM3S series */\r
+#if (SAM3S)\r
+# if (SAM3S8 || SAM3SD8)\r
+# include "sam3s8.h"\r
+# else\r
+# include "sam3s.h"\r
+# endif\r
+#endif\r
+\r
+/* SAM3U series */\r
+#if (SAM3U)\r
+# include "sam3u.h"\r
+#endif\r
+\r
+/* SAM3N series */\r
+#if (SAM3N)\r
+# include "sam3n.h"\r
+#endif\r
+\r
+/* SAM3XA series */\r
+#if (SAM3XA)\r
+# include "sam3xa.h"\r
+#endif\r
+\r
+/* SAM4S series */\r
+#if (SAM4S)\r
+# include "sam4s.h"\r
+#endif\r
+\r
+#endif /* _SAM_IO_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Flash Linker script for SAM.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ * \r
+ * 1. Redistributions of source code must retain the above copyright notice, \r
+ * this list of conditions and the following disclaimer.\r
+ * \r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ * \r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ * \r
+ * 4. This software may only be redistributed and used in connection with an \r
+ * Atmel microcontroller product.\r
+ * \r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+SEARCH_DIR(.)\r
+\r
+/* Memory Spaces Definitions */\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* flash, 1024K */\r
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* sram, 128K */\r
+}\r
+\r
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */\r
+STACK_SIZE = 0x3000;\r
+\r
+/* Section Definitions */\r
+SECTIONS\r
+{\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ _sfixed = .;\r
+ KEEP(*(.vectors .vectors.*))\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.glue_7t) *(.glue_7)\r
+ *(.rodata .rodata* .gnu.linkonce.r.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+\r
+ /* Support C constructors, and C destructors in both user code\r
+ and the C library. This also provides support for C++ code. */\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ _efixed = .; /* End of text section */\r
+ } > rom\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > rom\r
+ PROVIDE_HIDDEN (__exidx_end = .);\r
+\r
+ . = ALIGN(4);\r
+ _etext = .;\r
+\r
+ .relocate : AT (_etext)\r
+ {\r
+ . = ALIGN(4);\r
+ _srelocate = .;\r
+ *(.ramfunc .ramfunc.*);\r
+ *(.data .data.*);\r
+ . = ALIGN(4);\r
+ _erelocate = .;\r
+ } > ram\r
+\r
+ /* .bss section which is used for uninitialized data */\r
+ .bss (NOLOAD) :\r
+ {\r
+ . = ALIGN(4);\r
+ _sbss = . ;\r
+ _szero = .;\r
+ *(.bss .bss.*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = . ;\r
+ _ezero = .;\r
+ } > ram\r
+\r
+ /* stack section */\r
+ .stack (NOLOAD):\r
+ {\r
+ . = ALIGN(8);\r
+ _sstack = .;\r
+ . = . + STACK_SIZE;\r
+ . = ALIGN(8);\r
+ _estack = .;\r
+ } > ram\r
+\r
+ . = ALIGN(4);\r
+ _end = . ;\r
+}\r
--- /dev/null
+# List of available make goals:\r
+#\r
+# all Default target, builds the project\r
+# clean Clean up the project\r
+# rebuild Rebuild the project\r
+# debug_flash Builds the project and debug in flash\r
+# debug_sram Builds the project and debug in sram\r
+#\r
+# doc Build the documentation\r
+# cleandoc Clean up the documentation\r
+# rebuilddoc Rebuild the documentation\r
+#\r
+# \file\r
+#\r
+# Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+#\r
+# \asf_license_start\r
+#\r
+# Redistribution and use in source and binary forms, with or without\r
+# modification, are permitted provided that the following conditions are met:\r
+#\r
+# 1. Redistributions of source code must retain the above copyright notice,\r
+# this list of conditions and the following disclaimer.\r
+#\r
+# 2. Redistributions in binary form must reproduce the above copyright notice,\r
+# this list of conditions and the following disclaimer in the documentation\r
+# and/or other materials provided with the distribution.\r
+#\r
+# 3. The name of Atmel may not be used to endorse or promote products derived\r
+# from this software without specific prior written permission.\r
+#\r
+# 4. This software may only be redistributed and used in connection with an\r
+# Atmel microcontroller product.\r
+#\r
+# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+# POSSIBILITY OF SUCH DAMAGE.\r
+#\r
+# \asf_license_stop\r
+#\r
+\r
+# Include the config.mk file from the current working path, e.g., where the\r
+# user called make.\r
+include config.mk\r
+\r
+# Tool to use to generate documentation from the source code\r
+DOCGEN ?= doxygen\r
+\r
+# Look for source files relative to the top-level source directory\r
+VPATH := $(PRJ_PATH)\r
+\r
+# Output target file\r
+project_type := $(PROJECT_TYPE)\r
+\r
+# Output target file\r
+ifeq ($(project_type),flash)\r
+target := $(TARGET_FLASH)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)\r
+else\r
+target := $(TARGET_SRAM)\r
+linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)\r
+debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)\r
+endif\r
+\r
+# Output project name (target name minus suffix)\r
+project := $(basename $(target))\r
+\r
+# Output target file (typically ELF or static library)\r
+ifeq ($(suffix $(target)),.a)\r
+target_type := lib\r
+else\r
+ifeq ($(suffix $(target)),.elf)\r
+target_type := elf\r
+else\r
+$(error "Target type $(target_type) is not supported")\r
+endif\r
+endif\r
+\r
+# Allow override of operating system detection. The user can add OS=Linux or\r
+# OS=Windows on the command line to explicit set the host OS.\r
+#\r
+# This allows to work around broken uname utility on certain systems.\r
+ifdef OS\r
+ ifeq ($(strip $(OS)), Linux)\r
+ os_type := Linux\r
+ endif\r
+ ifeq (Windows,$(findstring Windows,$(OS)))\r
+ os_type := windows32_64\r
+ endif\r
+endif\r
+\r
+#os_type ?= $(strip $(shell uname))\r
+\r
+#ifeq ($(os_type),windows32)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),windows64)\r
+#os := Windows\r
+#else\r
+#ifeq ($(os_type),)\r
+#os := Windows\r
+#else\r
+## Default to Linux style operating system. Both Cygwin and mingw are fully\r
+## compatible (for this Makefile) with Linux.\r
+#os := Linux\r
+#endif\r
+#endif\r
+#endif\r
+\r
+ifeq ($(os_type),windows32_64)\r
+os := Windows\r
+else\r
+ifeq ($(os_type),Linux)\r
+os := Linux\r
+else\r
+os := Linux\r
+endif\r
+endif\r
+\r
+# Output documentation directory and configuration file.\r
+docdir := ../doxygen/html\r
+doccfg := ../doxygen/doxyfile.doxygen\r
+\r
+CROSS ?= arm-none-eabi-\r
+AR := $(CROSS)ar\r
+AS := $(CROSS)as\r
+CC := $(CROSS)gcc\r
+CPP := $(CROSS)gcc -E\r
+CXX := $(CROSS)g++\r
+LD := $(CROSS)g++\r
+NM := $(CROSS)nm\r
+OBJCOPY := $(CROSS)objcopy\r
+OBJDUMP := $(CROSS)objdump\r
+SIZE := $(CROSS)size\r
+GDB := $(CROSS)gdb\r
+\r
+RM := cs-rm -f\r
+ifeq ($(os),Windows)\r
+#RMDIR := rmdir /S /Q\r
+RMDIR := cs-rm -rf\r
+else\r
+RMDIR := rmdir -p --ignore-fail-on-non-empty\r
+endif\r
+\r
+# Strings for beautifying output\r
+MSG_CLEAN_FILES = "RM *.o *.d"\r
+MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"\r
+MSG_CLEAN_DOC = "RMDIR $(docdir)"\r
+MSG_MKDIR = "MKDIR $(dir $@)"\r
+\r
+MSG_INFO = "INFO "\r
+\r
+MSG_ARCHIVING = "AR $@"\r
+MSG_ASSEMBLING = "AS $@"\r
+MSG_BINARY_IMAGE = "OBJCOPY $@"\r
+MSG_COMPILING = "CC $@"\r
+MSG_COMPILING_CXX = "CXX $@"\r
+MSG_EXTENDED_LISTING = "OBJDUMP $@"\r
+MSG_IHEX_IMAGE = "OBJCOPY $@"\r
+MSG_LINKING = "LN $@"\r
+MSG_PREPROCESSING = "CPP $@"\r
+MSG_SIZE = "SIZE $@"\r
+MSG_SYMBOL_TABLE = "NM $@"\r
+\r
+MSG_GENERATING_DOC = "DOXYGEN $(docdir)"\r
+\r
+# Don't use make's built-in rules and variables\r
+MAKEFLAGS += -rR\r
+\r
+# Don't print 'Entering directory ...'\r
+MAKEFLAGS += --no-print-directory\r
+\r
+# Function for reversing the order of a list\r
+reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))\r
+\r
+# Hide command output by default, but allow the user to override this\r
+# by adding V=1 on the command line.\r
+#\r
+# This is inspired by the Kbuild system used by the Linux kernel.\r
+ifdef V\r
+ ifeq ("$(origin V)", "command line")\r
+ VERBOSE = $(V)\r
+ endif\r
+endif\r
+ifndef VERBOSE\r
+ VERBOSE = 0\r
+endif\r
+\r
+ifeq ($(VERBOSE), 1)\r
+ Q =\r
+else\r
+# Q = @\r
+ Q =\r
+endif\r
+\r
+arflags-gnu-y := $(ARFLAGS)\r
+asflags-gnu-y := $(ASFLAGS)\r
+cflags-gnu-y := $(CFLAGS)\r
+cxxflags-gnu-y := $(CXXFLAGS)\r
+cppflags-gnu-y := $(CPPFLAGS)\r
+cpuflags-gnu-y :=\r
+dbgflags-gnu-y := $(DBGFLAGS)\r
+libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))\r
+ldflags-gnu-y := $(LDFLAGS)\r
+flashflags-gnu-y :=\r
+clean-files :=\r
+clean-dirs :=\r
+\r
+clean-files += $(wildcard $(target) $(project).map)\r
+clean-files += $(wildcard $(project).hex $(project).bin)\r
+clean-files += $(wildcard $(project).lss $(project).sym)\r
+clean-files += $(wildcard $(build))\r
+\r
+# Use pipes instead of temporary files for communication between processes\r
+cflags-gnu-y += -pipe\r
+asflags-gnu-y += -pipe\r
+ldflags-gnu-y += -pipe\r
+\r
+# Archiver flags.\r
+arflags-gnu-y += rcs\r
+\r
+# Always enable warnings. And be very careful about implicit\r
+# declarations.\r
+cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes\r
+cflags-gnu-y += -Werror-implicit-function-declaration\r
+cxxflags-gnu-y += -Wall\r
+# IAR doesn't allow arithmetic on void pointers, so warn about that.\r
+cflags-gnu-y += -Wpointer-arith\r
+cxxflags-gnu-y += -Wpointer-arith\r
+\r
+# Preprocessor flags.\r
+cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))\r
+asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')\r
+\r
+# CPU specific flags.\r
+cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__\r
+\r
+# Dependency file flags.\r
+depflags = -MD -MP -MQ $@\r
+\r
+# Debug specific flags.\r
+ifdef BUILD_DEBUG_LEVEL\r
+dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)\r
+else\r
+dbgflags-gnu-y += -g3\r
+endif\r
+\r
+# Optimization specific flags.\r
+ifdef BUILD_OPTIMIZATION\r
+optflags-gnu-y = -O$(BUILD_OPTIMIZATION)\r
+else\r
+optflags-gnu-y = $(OPTIMIZATION)\r
+endif\r
+\r
+# Always preprocess assembler files.\r
+asflags-gnu-y += -x assembler-with-cpp\r
+# Compile C files using the GNU99 standard.\r
+cflags-gnu-y += -std=gnu99\r
+# Compile C++ files using the GNU++98 standard.\r
+cxxflags-gnu-y += -std=gnu++98\r
+\r
+\r
+# Separate each function and data into its own separate section to allow\r
+# garbage collection of unused sections.\r
+cflags-gnu-y += -ffunction-sections -fdata-sections\r
+cxxflags-gnu-y += -ffunction-sections -fdata-sections\r
+\r
+# Various cflags.\r
+cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int\r
+cflags-gnu-y += -Wmain -Wparentheses\r
+cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused\r
+cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal\r
+# -Wundef\r
+cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings\r
+cflags-gnu-y += -Wsign-compare -Waggregate-return \r
+cflags-gnu-y += -Wmissing-declarations\r
+cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations\r
+cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long\r
+cflags-gnu-y += -Wunreachable-code\r
+cflags-gnu-y += -Wcast-align\r
+cflags-gnu-y += --param max-inline-insns-single=500\r
+\r
+# To reduce application size use only integer printf function.\r
+cflags-gnu-y += -Dprintf=iprintf\r
+\r
+# Garbage collect unreferred sections when linking.\r
+ldflags-gnu-y += -Wl,--gc-sections\r
+\r
+# Use the linker script if provided by the project.\r
+ifneq ($(strip $(linker_script)),)\r
+ldflags-gnu-y += -Wl,-T $(linker_script)\r
+endif\r
+\r
+# Output a link map file and a cross reference table\r
+ldflags-gnu-y += -Wl,-Map=$(project).map,--cref\r
+\r
+# Add library search paths relative to the top level directory.\r
+ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))\r
+\r
+a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__\r
+c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)\r
+cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)\r
+l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)\r
+ar_flags = $(arflags-gnu-y)\r
+\r
+# Source files list and part informations must already be included before\r
+# running this makefile\r
+\r
+# If a custom build directory is specified, use it -- force trailing / in directory name.\r
+ifdef BUILD_DIR\r
+ build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)\r
+else\r
+ build-dir =\r
+endif\r
+\r
+# Create object files list from source files list.\r
+obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))\r
+# Create dependency files list from source files list.\r
+dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))\r
+\r
+clean-files += $(wildcard $(obj-y))\r
+clean-files += $(dep-files)\r
+\r
+clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))\r
+\r
+.PHONY: all\r
+\r
+# Default target.\r
+.PHONY: all\r
+ifeq ($(project_type),all)\r
+all:\r
+ $(MAKE) all PROJECT_TYPE=flash\r
+ $(MAKE) all PROJECT_TYPE=sram\r
+else\r
+ifeq ($(target_type),lib)\r
+all: $(target) $(project).lss $(project).sym\r
+else\r
+ifeq ($(target_type),elf)\r
+all: $(target) $(project).lss $(project).sym $(project).hex $(project).bin\r
+endif\r
+endif\r
+endif\r
+\r
+# Default target.\r
+.PHONY: os\r
+os:\r
+ @echo OS '$(OS)'\r
+ @echo os type '$(os_type)'\r
+ @echo os '$(os)'\r
+ @echo '$(findstring Windows,$(OS))'\r
+\r
+# Clean up the project.\r
+.PHONY: clean\r
+clean:\r
+ @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))\r
+ $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)\r
+ @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))\r
+# Remove created directories, and make sure we only remove existing\r
+# directories, since recursive rmdir might help us a bit on the way.\r
+ifeq ($(os),Windows)\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))\r
+else\r
+ $(Q)$(if $(strip $(clean-dirs)), \\r
+ for directory in $(strip $(clean-dirs)); do \\r
+ if [ -d "$$directory" ]; then \\r
+ $(RMDIR) $$directory; \\r
+ fi \\r
+ done \\r
+ )\r
+endif\r
+\r
+# Rebuild the project.\r
+.PHONY: rebuild\r
+rebuild: clean all\r
+\r
+# Debug the project in flash.\r
+.PHONY: debug_flash\r
+debug_flash: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)\r
+\r
+# Debug the project in sram.\r
+.PHONY: debug_sram\r
+debug_sram: all\r
+ $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)\r
+\r
+.PHONY: objfiles\r
+objfiles: $(obj-y)\r
+\r
+# Create object files from C source files.\r
+$(build-dir)%.o: %.c $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING)\r
+ $(Q)$(CC) $(c_flags) -c $< -o $@\r
+\r
+# Create object files from C++ source files.\r
+$(build-dir)%.o: %.cpp $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_COMPILING_CXX)\r
+ $(Q)$(CXX) $(cxx_flags) -c $< -o $@\r
+\r
+# Preprocess and assemble: create object files from assembler source files.\r
+$(build-dir)%.o: %.S $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk\r
+ @echo $(MSG_MKDIR)\r
+ifeq ($(os),Windows)\r
+ -mkdir $(subst /,\,$(dir $@))\r
+else\r
+ -mkdir -p $(dir $@)\r
+endif\r
+ @echo $(MSG_ASSEMBLING)\r
+ $(Q)$(CC) $(a_flags) -c $< -o $@\r
+\r
+# Include all dependency files to add depedency to all header files in use.\r
+include $(dep-files)\r
+\r
+ifeq ($(target_type),lib)\r
+# Archive object files into an archive\r
+$(target): $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_ARCHIVING)\r
+ $(Q)$(AR) $(ar_flags) $@ $(obj-y)\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Bxt $@\r
+else\r
+ifeq ($(target_type),elf)\r
+# Link the object files into an ELF file. Also make sure the target is rebuilt\r
+# if the common Makefile.in or project config.mk is changed.\r
+$(target): $(linker_script) $(PRJ_PATH)/sam/utils/make/Makefile.in config.mk $(obj-y)\r
+ @echo $(MSG_LINKING)\r
+ @echo $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@\r
+ @echo $(MSG_SIZE)\r
+ $(Q)$(SIZE) -Ax $@\r
+ $(Q)$(SIZE) -Bx $@\r
+endif\r
+endif\r
+\r
+# Create extended function listing from target output file.\r
+%.lss: $(target)\r
+ @echo $(MSG_EXTENDED_LISTING)\r
+ $(Q)$(OBJDUMP) -h -S $< > $@\r
+\r
+# Create symbol table from target output file.\r
+%.sym: $(target)\r
+ @echo $(MSG_SYMBOL_TABLE)\r
+ $(Q)$(NM) -n $< > $@\r
+\r
+# Create Intel HEX image from ELF output file.\r
+%.hex: $(target)\r
+ @echo $(MSG_IHEX_IMAGE)\r
+ $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@\r
+\r
+# Create binary image from ELF output file.\r
+%.bin: $(target)\r
+ @echo $(MSG_BINARY_IMAGE)\r
+ $(Q)$(OBJCOPY) -O binary $< $@\r
+\r
+# Provide information about the detected host operating system.\r
+.SECONDARY: info-os\r
+info-os:\r
+ @echo $(MSG_INFO)$(os) build host detected\r
+\r
+# Build Doxygen generated documentation.\r
+.PHONY: doc\r
+doc:\r
+ @echo $(MSG_GENERATING_DOC)\r
+ $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))\r
+\r
+# Clean Doxygen generated documentation.\r
+.PHONY: cleandoc\r
+cleandoc:\r
+ @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))\r
+ $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))\r
+\r
+# Rebuild the Doxygen generated documentation.\r
+.PHONY: rebuilddoc\r
+rebuilddoc: cleandoc doc\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Arch file for SAM.\r
+ *\r
+ * This file defines common SAM series.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _SAM_PARTS_\r
+#define _SAM_PARTS_\r
+\r
+/* Convenience macro for checking GCC and IAR part definitions */\r
+#define part_is_defined(part) (defined(__ ## part ## __))\r
+\r
+/* SAM3 family */\r
+\r
+/* SAM3S series */\r
+#define SAM3S1 ( \\r
+ part_is_defined( SAM3S1A ) || \\r
+ part_is_defined( SAM3S1B ) || \\r
+ part_is_defined( SAM3S1C ) )\r
+\r
+#define SAM3S2 ( \\r
+ part_is_defined( SAM3S2A ) || \\r
+ part_is_defined( SAM3S2B ) || \\r
+ part_is_defined( SAM3S2C ) )\r
+\r
+#define SAM3S4 ( \\r
+ part_is_defined( SAM3S4A ) || \\r
+ part_is_defined( SAM3S4B ) || \\r
+ part_is_defined( SAM3S4C ) )\r
+\r
+#define SAM3S8 ( \\r
+ part_is_defined( SAM3S8B ) || \\r
+ part_is_defined( SAM3S8C ) )\r
+\r
+#define SAM3SD8 ( \\r
+ part_is_defined( SAM3SD8B ) || \\r
+ part_is_defined( SAM3SD8C ) )\r
+\r
+#define SAM3U1 ( \\r
+ part_is_defined( SAM3U1C ) || \\r
+ part_is_defined( SAM3U1E ) )\r
+\r
+#define SAM3U2 ( \\r
+ part_is_defined( SAM3U2C ) || \\r
+ part_is_defined( SAM3U2E ) )\r
+\r
+#define SAM3U4 ( \\r
+ part_is_defined( SAM3U4C ) || \\r
+ part_is_defined( SAM3U4E ) )\r
+\r
+#define SAM3N1 ( \\r
+ part_is_defined( SAM3N1A ) || \\r
+ part_is_defined( SAM3N1B ) || \\r
+ part_is_defined( SAM3N1C ) )\r
+\r
+#define SAM3N2 ( \\r
+ part_is_defined( SAM3N2A ) || \\r
+ part_is_defined( SAM3N2B ) || \\r
+ part_is_defined( SAM3N2C ) )\r
+\r
+#define SAM3N4 ( \\r
+ part_is_defined( SAM3N4A ) || \\r
+ part_is_defined( SAM3N4B ) || \\r
+ part_is_defined( SAM3N4C ) )\r
+ \r
+#define SAM3X4 ( \\r
+ part_is_defined( SAM3X4C ) || \\r
+ part_is_defined( SAM3X4E ) )\r
+\r
+#define SAM3X8 ( \\r
+ part_is_defined( SAM3X8C ) || \\r
+ part_is_defined( SAM3X8E ) || \\r
+ part_is_defined( SAM3X8H ) )\r
+\r
+#define SAM3A4 ( \\r
+ part_is_defined( SAM3A4C ) )\r
+\r
+#define SAM3A8 ( \\r
+ part_is_defined( SAM3A8C ) )\r
+\r
+#define SAM4S8 ( \\r
+ part_is_defined( SAM4S8B ) || \\r
+ part_is_defined( SAM4S8C ) )\r
+\r
+#define SAM4S16 ( \\r
+ part_is_defined( SAM4S16B ) || \\r
+ part_is_defined( SAM4S16C ) )\r
+\r
+/* Entire SAM3S Family */\r
+#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)\r
+\r
+/* Entire SAM3U Family */\r
+#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)\r
+\r
+/* Entire SAM3N Family */\r
+#define SAM3N (SAM3N1 || SAM3N2 || SAM3N4)\r
+\r
+/* Entire SAM3XA Family */\r
+#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)\r
+\r
+/* SAM9 family */\r
+\r
+/* SAM7 family */\r
+\r
+/* Entire SAM4S Family */\r
+#define SAM4S (SAM4S8 || SAM4S16)\r
+\r
+/* Global SAM product line */\r
+#define SAM ( SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S)\r
+\r
+#ifdef SAM\r
+ #include "io.h"\r
+#endif\r
+\r
+#endif /* _SAM_PARTS_ */\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor macro repeating utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _MREPEAT_H_\r
+#define _MREPEAT_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+#include "preprocessor.h"\r
+\r
+\r
+//! Maximal number of repetitions supported by MREPEAT.\r
+#define MREPEAT_LIMIT 256\r
+\r
+/*! \brief Macro repeat.\r
+ *\r
+ * This macro represents a horizontal repetition construct.\r
+ *\r
+ * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.\r
+ * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with\r
+ * the current repetition number and the auxiliary data argument.\r
+ * \param data Auxiliary data passed to macro.\r
+ *\r
+ * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>\r
+ */\r
+#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)\r
+\r
+#define MREPEAT0( macro, data)\r
+#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)\r
+#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)\r
+#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)\r
+#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)\r
+#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)\r
+#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)\r
+#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)\r
+#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)\r
+#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)\r
+#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)\r
+#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)\r
+#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)\r
+#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)\r
+#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)\r
+#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)\r
+#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)\r
+#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)\r
+#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)\r
+#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)\r
+#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)\r
+#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)\r
+#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)\r
+#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)\r
+#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)\r
+#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)\r
+#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)\r
+#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)\r
+#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)\r
+#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)\r
+#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)\r
+#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)\r
+#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)\r
+#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)\r
+#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)\r
+#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)\r
+#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)\r
+#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)\r
+#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)\r
+#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)\r
+#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)\r
+#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)\r
+#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)\r
+#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)\r
+#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)\r
+#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)\r
+#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)\r
+#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)\r
+#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)\r
+#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)\r
+#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)\r
+#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)\r
+#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)\r
+#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)\r
+#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)\r
+#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)\r
+#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)\r
+#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)\r
+#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)\r
+#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)\r
+#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)\r
+#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)\r
+#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)\r
+#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)\r
+#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)\r
+#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)\r
+#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)\r
+#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)\r
+#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)\r
+#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)\r
+#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)\r
+#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)\r
+#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)\r
+#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)\r
+#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)\r
+#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)\r
+#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)\r
+#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)\r
+#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)\r
+#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)\r
+#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)\r
+#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)\r
+#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)\r
+#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)\r
+#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)\r
+#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)\r
+#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)\r
+#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)\r
+#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)\r
+#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)\r
+#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)\r
+#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)\r
+#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)\r
+#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)\r
+#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)\r
+#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)\r
+#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)\r
+#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)\r
+#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)\r
+#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)\r
+#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)\r
+#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)\r
+#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)\r
+#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)\r
+#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)\r
+#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)\r
+#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)\r
+#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)\r
+#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)\r
+#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)\r
+#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)\r
+#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)\r
+#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)\r
+#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)\r
+#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)\r
+#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)\r
+#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)\r
+#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)\r
+#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)\r
+#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)\r
+#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)\r
+#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)\r
+#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)\r
+#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)\r
+#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)\r
+#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)\r
+#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)\r
+#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)\r
+#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)\r
+#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)\r
+#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)\r
+#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)\r
+#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)\r
+#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)\r
+#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)\r
+#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)\r
+#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)\r
+#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)\r
+#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)\r
+#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)\r
+#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)\r
+#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)\r
+#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)\r
+#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)\r
+#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)\r
+#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)\r
+#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)\r
+#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)\r
+#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)\r
+#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)\r
+#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)\r
+#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)\r
+#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)\r
+#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)\r
+#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)\r
+#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)\r
+#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)\r
+#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)\r
+#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)\r
+#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)\r
+#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)\r
+#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)\r
+#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)\r
+#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)\r
+#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)\r
+#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)\r
+#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)\r
+#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)\r
+#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)\r
+#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)\r
+#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)\r
+#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)\r
+#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)\r
+#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)\r
+#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)\r
+#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)\r
+#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)\r
+#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)\r
+#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)\r
+#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)\r
+#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)\r
+#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)\r
+#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)\r
+#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)\r
+#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)\r
+#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)\r
+#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)\r
+#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)\r
+#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)\r
+#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)\r
+#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)\r
+#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)\r
+#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)\r
+#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)\r
+#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)\r
+#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)\r
+#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)\r
+#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)\r
+#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)\r
+#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)\r
+#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)\r
+#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)\r
+#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)\r
+#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)\r
+#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)\r
+#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)\r
+#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)\r
+#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)\r
+#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)\r
+#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)\r
+#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)\r
+#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)\r
+#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)\r
+#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)\r
+#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)\r
+#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)\r
+#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)\r
+#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)\r
+#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)\r
+#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)\r
+#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)\r
+#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)\r
+#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)\r
+#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)\r
+#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)\r
+#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)\r
+#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)\r
+#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)\r
+#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)\r
+#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)\r
+#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)\r
+#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)\r
+#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)\r
+#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)\r
+#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)\r
+#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)\r
+#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)\r
+#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)\r
+#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)\r
+#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)\r
+#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)\r
+#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)\r
+#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)\r
+#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)\r
+#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)\r
+#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)\r
+#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)\r
+#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)\r
+#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)\r
+#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)\r
+#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)\r
+#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)\r
+#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)\r
+#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)\r
+#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)\r
+#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)\r
+#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _MREPEAT_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _PREPROCESSOR_H_\r
+#define _PREPROCESSOR_H_\r
+\r
+#include "tpaste.h"\r
+#include "stringz.h"\r
+#include "mrepeat.h"\r
+\r
+\r
+#endif // _PREPROCESSOR_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor stringizing utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _STRINGZ_H_\r
+#define _STRINGZ_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_stringz Preprocessor - Stringize\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \brief Stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
+ *\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
+ * writing "A0".\r
+ */\r
+#define STRINGZ(x) #x\r
+\r
+/*! \brief Absolute stringize.\r
+ *\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the token is \#defined.\r
+ *\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
+ * equivalent to writing "A0".\r
+ */\r
+#define ASTRINGZ(x) STRINGZ(x)\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _STRINGZ_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Preprocessor token pasting utils.\r
+ *\r
+ * Copyright (c) 2010-2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef _TPASTE_H_\r
+#define _TPASTE_H_\r
+\r
+/**\r
+ * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste\r
+ *\r
+ * \ingroup group_sam_utils\r
+ *\r
+ * \{\r
+ */\r
+\r
+/*! \name Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
+ *\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
+ * equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define TPASTE2( a, b) a##b\r
+#define TPASTE3( a, b, c) a##b##c\r
+#define TPASTE4( a, b, c, d) a##b##c##d\r
+#define TPASTE5( a, b, c, d, e) a##b##c##d##e\r
+#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f\r
+#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g\r
+#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h\r
+#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i\r
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j\r
+//! @}\r
+\r
+/*! \name Absolute Token Paste\r
+ *\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
+ *\r
+ * No restriction of use if the tokens are \#defined.\r
+ *\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
+ * as 32 is equivalent to writing U32.\r
+ */\r
+//! @{\r
+#define ATPASTE2( a, b) TPASTE2( a, b)\r
+#define ATPASTE3( a, b, c) TPASTE3( a, b, c)\r
+#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)\r
+#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)\r
+#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)\r
+#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)\r
+#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)\r
+#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)\r
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)\r
+//! @}\r
+\r
+/**\r
+ * \}\r
+ */\r
+\r
+#endif // _TPASTE_H_\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Status code definitions.\r
+ *\r
+ * This file defines various status codes returned by functions,\r
+ * indicating success or failure as well as what kind of failure.\r
+ *\r
+ * Copyright (c) 2011 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef STATUS_CODES_H_INCLUDED\r
+#define STATUS_CODES_H_INCLUDED\r
+\r
+/**\r
+ * Status code that may be returned by shell commands and protocol\r
+ * implementations.\r
+ *\r
+ * \note Any change to these status codes and the corresponding\r
+ * message strings is strictly forbidden. New codes can be added,\r
+ * however, but make sure that any message string tables are updated\r
+ * at the same time.\r
+ */\r
+enum status_code {\r
+ STATUS_OK = 0, //!< Success\r
+ ERR_IO_ERROR = -1, //!< I/O error\r
+ ERR_FLUSHED = -2, //!< Request flushed from queue\r
+ ERR_TIMEOUT = -3, //!< Operation timed out\r
+ ERR_BAD_DATA = -4, //!< Data integrity check failed\r
+ ERR_PROTOCOL = -5, //!< Protocol error\r
+ ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device\r
+ ERR_NO_MEMORY = -7, //!< Insufficient memory\r
+ ERR_INVALID_ARG = -8, //!< Invalid argument\r
+ ERR_BAD_ADDRESS = -9, //!< Bad address\r
+ ERR_BUSY = -10, //!< Resource is busy\r
+ ERR_BAD_FORMAT = -11, //!< Data format not recognized\r
+\r
+ /**\r
+ * \brief Operation in progress\r
+ *\r
+ * This status code is for driver-internal use when an operation\r
+ * is currently being performed.\r
+ *\r
+ * \note Drivers should never return this status code to any\r
+ * callers. It is strictly for internal use.\r
+ */\r
+ OPERATION_IN_PROGRESS = -128,\r
+};\r
+\r
+typedef enum status_code status_code_t;\r
+\r
+#endif /* STATUS_CODES_H_INCLUDED */\r
--- /dev/null
+/* ---------------------------------------------------------------------- \r
+ * Copyright (C) 2010 ARM Limited. All rights reserved. \r
+ * \r
+ * $Date: 15. July 2011 \r
+ * $Revision: V1.0.10 \r
+ * \r
+ * Project: CMSIS DSP Library \r
+ * Title: arm_math.h\r
+ * \r
+ * Description: Public header file for CMSIS DSP Library\r
+ * \r
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0\r
+ * \r
+ * Version 1.0.10 2011/7/15 \r
+ * Big Endian support added and Merged M0 and M3/M4 Source code. \r
+ * \r
+ * Version 1.0.3 2010/11/29 \r
+ * Re-organized the CMSIS folders and updated documentation. \r
+ * \r
+ * Version 1.0.2 2010/11/11 \r
+ * Documentation updated. \r
+ * \r
+ * Version 1.0.1 2010/10/05 \r
+ * Production release and review comments incorporated. \r
+ * \r
+ * Version 1.0.0 2010/09/20 \r
+ * Production release and review comments incorporated. \r
+ * -------------------------------------------------------------------- */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * <b>Introduction</b>\r
+ *\r
+ * This user manual describes the CMSIS DSP software library, \r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of modules each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values. \r
+ *\r
+ * <b>Processor Support</b>\r
+ *\r
+ * The library is completely written in C and is fully CMSIS compliant. \r
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics. \r
+ *\r
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,\r
+ * with the DSP intrinsics being emulated through software. \r
+ *\r
+ *\r
+ * <b>Toolchain Support</b>\r
+ *\r
+ * The library has been developed and tested with MDK-ARM version 4.21. \r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * <b>Using the Library</b>\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\r
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\r
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\r
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\r
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\r
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)\r
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single \r
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. \r
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or \r
+ * ARM_MATH_CM0 depending on the target processor in the application.\r
+ *\r
+ * <b>Examples</b>\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * <b>Building the Library</b>\r
+ *\r
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.\r
+ * - arm_cortexM0b_math.uvproj\r
+ * - arm_cortexM0l_math.uvproj\r
+ * - arm_cortexM3b_math.uvproj\r
+ * - arm_cortexM3l_math.uvproj \r
+ * - arm_cortexM4b_math.uvproj\r
+ * - arm_cortexM4l_math.uvproj\r
+ * - arm_cortexM4bf_math.uvproj\r
+ * - arm_cortexM4lf_math.uvproj\r
+ *\r
+ * Each library project have differant pre-processor macros.\r
+ *\r
+ * <b>ARM_MATH_CMx:</b>\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.\r
+ *\r
+ * <b>ARM_MATH_BIG_ENDIAN:</b>\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * <b>ARM_MATH_MATRIX_CHECK:</b>\r
+ * Define macro for checking on the input and output sizes of matrices\r
+ *\r
+ * <b>ARM_MATH_ROUNDING:</b>\r
+ * Define macro for rounding on support functions\r
+ *\r
+ * <b>__FPU_PRESENT:</b>\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries \r
+ *\r
+ *\r
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.\r
+ *\r
+ * <b>Copyright Notice</b>\r
+ *\r
+ * Copyright (C) 2010 ARM Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the #define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+#else\r
+#include "ARMCM4.h"\r
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+ #include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#define PI 3.14159265358979f\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define TABLE_SIZE 256\r
+#define TABLE_SPACING_Q31 0x800000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#define __SIMD32(addr) (*(int32_t **) & (addr))\r
+\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else \r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+ \r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ static __INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ static __INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ static __INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ static __INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+\r
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )\r
+#define __CLZ __clz\r
+#endif \r
+\r
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )\r
+\r
+ static __INLINE uint32_t __CLZ(q31_t data);\r
+\r
+\r
+ static __INLINE uint32_t __CLZ(q31_t data)\r
+ {\r
+ uint32_t count = 0;\r
+ uint32_t mask = 0x80000000;\r
+\r
+ while((data & mask) == 0)\r
+ {\r
+ count += 1u;\r
+ mask = mask >> 1u;\r
+ }\r
+\r
+ return(count);\r
+\r
+ }\r
+\r
+#endif \r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ static __INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out, tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 1;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 1;\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t) (in >> 24u);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0u; i < 2u; i++)\r
+ {\r
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);\r
+ tempVal = 0x7FFFFFFF - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);\r
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.\r
+ */\r
+ static __INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+\r
+ uint32_t out = 0, tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if(in > 0)\r
+ {\r
+ signBits = __CLZ(in) - 17;\r
+ }\r
+ else\r
+ {\r
+ signBits = __CLZ(-in) - 17;\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = in << signBits;\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = in >> 8;\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0; i < 2; i++)\r
+ {\r
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFF - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinisic function for only M0 processors\r
+ */\r
+#if defined(ARM_MATH_CM0)\r
+\r
+ static __INLINE q31_t __SSAT(\r
+ q31_t x,\r
+ uint32_t y)\r
+ {\r
+ int32_t posMax, negMin;\r
+ uint32_t i;\r
+\r
+ posMax = 1;\r
+ for (i = 0; i < (y - 1); i++)\r
+ {\r
+ posMax = posMax * 2;\r
+ }\r
+\r
+ if(x > 0)\r
+ {\r
+ posMax = (posMax - 1);\r
+\r
+ if(x > posMax)\r
+ {\r
+ x = posMax;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ negMin = -posMax;\r
+\r
+ if(x < negMin)\r
+ {\r
+ x = negMin;\r
+ }\r
+ }\r
+ return (x);\r
+\r
+\r
+ }\r
+\r
+#endif /* end of ARM_MATH_CM0 */\r
+\r
+\r
+\r
+ /*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q7_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((q31_t) (r + s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);\r
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);\r
+\r
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |\r
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB8(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s, t, u;\r
+\r
+ r = (char) x;\r
+ s = (char) y;\r
+\r
+ r = __SSAT((r - s), 8);\r
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;\r
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;\r
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;\r
+\r
+ sum =\r
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r + s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHADD16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (s >> 1));\r
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = __SSAT(r - s, 16);\r
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSUB16(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t diff;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (s >> 1));\r
+ s = (((x >> 17) - (y >> 17)) << 16);\r
+\r
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return diff;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHASX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) - (y >> 17));\r
+ s = (((x >> 17) + (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum = 0;\r
+\r
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +\r
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SHSAX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ q31_t sum;\r
+ q31_t r, s;\r
+\r
+ r = (short) x;\r
+ s = (short) y;\r
+\r
+ r = ((r >> 1) + (y >> 17));\r
+ s = (((x >> 17) - (s >> 1)) << 16);\r
+\r
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);\r
+\r
+ return sum;\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSDX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) -\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUADX(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return ((q31_t)(((short) x * (short) (y >> 16)) +\r
+ ((short) (x >> 16) * (short) y)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QADD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x + y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __QSUB(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+ return clip_q63_to_q31((q63_t) x - y);\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLAD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLADX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMLSDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q31_t sum)\r
+ {\r
+\r
+ return (sum - ((short) (x >> 16) * (short) (y)) +\r
+ ((short) x * (short) (y >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALD(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +\r
+ ((short) x * (short) y));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ static __INLINE q63_t __SMLALDX(\r
+ q31_t x,\r
+ q31_t y,\r
+ q63_t sum)\r
+ {\r
+\r
+ return (sum + ((short) (x >> 16) * (short) y)) +\r
+ ((short) x * (short) (y >> 16));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUAD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ static __INLINE q31_t __SMUSD(\r
+ q31_t x,\r
+ q31_t y)\r
+ {\r
+\r
+ return (-((x >> 16) * (y >> 16)) +\r
+ (((x << 16) >> 16) * ((y << 16) >> 16)));\r
+ }\r
+\r
+\r
+\r
+\r
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ * @return none\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return none.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+\r
+\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @param[in] *pState points to the array for storing intermediate results \r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] *pSrcA points to the first input matrix structure\r
+ * @param[in] *pSrcB points to the second input matrix structure\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] *pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] *pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] *pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t *pData);\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t *pData);\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] *pData points to the matrix data array.\r
+ * @return none\r
+ */\r
+\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t *pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ #ifdef ARM_MATH_CM0 \r
+ q15_t A1;\r
+ q15_t A2; \r
+ #else \r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+ #endif \r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] *S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ \r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @return none\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ * @return none.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the q15 PID Control structure\r
+ * @return none\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues;\r
+ float32_t x1;\r
+ float32_t xSpacing;\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point CFFT/CIFFT.\r
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point CFFT/CIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.\r
+ */\r
+ \r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+\r
+\r
+ /*----------------------------------------------------------------------\r
+ * Internal functions prototypes FFT function\r
+ ----------------------------------------------------------------------*/\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to the twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the floating-point CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @param[in] onebyfftLen value of 1/fftLen.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_inverse_f32(\r
+ float32_t * pSrc,\r
+ uint16_t fftLen,\r
+ float32_t * pCoef,\r
+ uint16_t twidCoefModifier,\r
+ float32_t onebyfftLen);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.\r
+ * @param[in] fftSize length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.\r
+ * @param[in] *pBitRevTab points to the bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_f32(\r
+ float32_t *pSrc,\r
+ uint16_t fftSize,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_q31(\r
+ q31_t *pSrc,\r
+ uint32_t fftLen,\r
+ q31_t *pCoef,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q31 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+ \r
+ void arm_radix4_butterfly_inverse_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ q31_t * pCoef,\r
+ uint32_t twidCoefModifier);\r
+ \r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q31(\r
+ q31_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief Core function for the Q15 CIFFT butterfly process.\r
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.\r
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_radix4_butterfly_inverse_q15(\r
+ q15_t *pSrc16,\r
+ uint32_t fftLen,\r
+ q15_t *pCoef16,\r
+ uint32_t twidCoefModifier);\r
+\r
+ /**\r
+ * @brief In-place bit reversal function.\r
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.\r
+ * @param[in] fftLen length of the FFT.\r
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table\r
+ * @param[in] *pBitRevTab points to bit reversal table.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_bitreversal_q15(\r
+ q15_t * pSrc,\r
+ uint32_t fftLen,\r
+ uint16_t bitRevFactor,\r
+ uint16_t *pBitRevTab);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ \r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint32_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 RFFT/RIFFT.\r
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.\r
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point RFFT/RIFFT.\r
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.\r
+ * @param[in] fftLenReal length of the FFT.\r
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.\r
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.\r
+ */\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point RFFT/RIFFT.\r
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.\r
+ * @param[in] *pSrc points to the input buffer.\r
+ * @param[out] *pDst points to the output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[out] *pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] *result output result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector. \r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector. \r
+ * @param[in] value input value to be filled\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/** \r
+ * @brief Convolution of floating-point sequences. \r
+ * @param[in] *pSrcA points to the first input sequence. \r
+ * @param[in] srcALen length of the first input sequence. \r
+ * @param[in] *pSrcB points to the second input sequence. \r
+ * @param[in] srcBLen length of the second input sequence. \r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r
+ * @return none. \r
+ */ \r
+\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+/** \r
+ * @brief Convolution of Q15 sequences. \r
+ * @param[in] *pSrcA points to the first input sequence. \r
+ * @param[in] srcALen length of the first input sequence. \r
+ * @param[in] *pSrcB points to the second input sequence. \r
+ * @param[in] srcBLen length of the second input sequence. \r
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. \r
+ * @return none. \r
+ */\r
+\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] *S points to an instance of the filter data structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] *S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] *pCoeffs points to the filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @return none\r
+ */\r
+\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. \r
+ * @param[in] *pState points to the state buffer. The array is of length numStages. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t *pkCoeffs,\r
+ float32_t *pvCoeffs,\r
+ float32_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t *pkCoeffs,\r
+ q31_t *pvCoeffs,\r
+ q31_t *pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t *pkCoeffs,\r
+ q15_t *pvCoeffs,\r
+ q15_t *pState,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to the coefficient buffer.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+\r
+ } arm_lms_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t *pCoeffs,\r
+ q31_t *pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[in] *pRef points to the block of reference data.\r
+ * @param[out] *pOut points to the block of output data.\r
+ * @param[out] *pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] *pCoeffs points to coefficient buffer.\r
+ * @param[in] *pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] *pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] *pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] *pSrc points to the block of input data.\r
+ * @param[out] *pDst points to the block of output data\r
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] *pCoeffs points to the array of filter coefficients.\r
+ * @param[in] *pState points to the state buffer.\r
+ * @param[in] *pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ * @return none\r
+ */\r
+\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t *pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /*\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees \r
+ * @param[out] *pSinVal points to the processed sine output. \r
+ * @param[out] *pCosVal points to the processed cos output. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t *pSinVal,\r
+ float32_t *pCcosVal);\r
+\r
+ /*\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees \r
+ * @param[out] *pSinVal points to the processed sine output. \r
+ * @param[out] *pCosVal points to the processed cosine output. \r
+ * @return none.\r
+ */\r
+\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t *pSinVal,\r
+ q31_t *pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] *pSrc points to the input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control \r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ * \r
+ * \par \r
+ * \image html PID.gif "Proportional Integral Derivative Controller" \r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs. \r
+ * The proportional value determines the reaction to the current error, \r
+ * the integral value determines the reaction based on the sum of recent errors, \r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure \r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. \r
+ * A separate instance structure must be defined for each PID Controller. \r
+ * There are separate instance structure declarations for each of the 3 supported data types. \r
+ * \r
+ * \par Reset Functions \r
+ * There is also an associated reset function for each data type which clears the state array. \r
+ *\r
+ * \par Initialization Functions \r
+ * There is also an associated initialization function for each data type. \r
+ * The initialization function performs the following operations: \r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer. \r
+ * \r
+ * \par \r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. \r
+ *\r
+ * \par Fixed-Point Behavior \r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions. \r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. \r
+ * Refer to the function specific documentation below for usage guidelines. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] *S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+\r
+\r
+ static __INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b> \r
+ * \par \r
+ * The function is implemented using an internal 64-bit accumulator. \r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. \r
+ * Thus, if the accumulator result overflows it wraps around rather than clip. \r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. \r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. \r
+ */\r
+\r
+ static __INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31u);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b> \r
+ * \par \r
+ * The function is implemented using a 64-bit internal accumulator. \r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. \r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. \r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. \r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. \r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+\r
+ static __INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ #ifdef ARM_MATH_CM0\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0 )* in ;\r
+\r
+ #else\r
+ \r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD(S->A0, in);\r
+ \r
+ #endif\r
+\r
+ #ifdef ARM_MATH_CM0\r
+ \r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0] ;\r
+ acc += (q31_t) S->A2 * S->state[1] ;\r
+\r
+ #else\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);\r
+\r
+ #endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+ \r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] *src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+ \r
+ \r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ \r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ * \r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version \r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+ static __INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] *pSrc input pointer\r
+ * @param[out] *pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ \r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents \r
+ * from the stationary to the moving reference frame and control the spatial relationship between \r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the \r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components, \r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the \r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+\r
+ static __INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version \r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] *pId points to output rotor reference frame d\r
+ * @param[out] *pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ \r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output. \r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components, \r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the \r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ */\r
+\r
+ static __INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version \r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ * @return none.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+\r
+\r
+ static __INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+ \r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par \r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ * \r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table \r
+ * if x is below input range and returns last value of table if x is above range. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+\r
+ static __INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (x - S->x1) / xSpacing;\r
+\r
+ if(i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if(i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues-1]; \r
+ }\r
+ else\r
+ { \r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i +1) * xSpacing;\r
+ \r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+ \r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); \r
+ \r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,\r
+ q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+ \r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20);\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+ \r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+ \r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+ \r
+ /* Convert y to 1.31 format */\r
+ return (y << 1u);\r
+\r
+ }\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12. \r
+ *\r
+ */\r
+\r
+\r
+ static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */ \r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u); \r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ { \r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+ \r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+ \r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+ \r
+ /* convert y to 1.15 format */\r
+ return (y >> 20);\r
+ }\r
+\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+\r
+\r
+ static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+ \r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & 0xFFF00000) >> 20u);\r
+\r
+\r
+ if(index >= (nValues - 1))\r
+ {\r
+ return(pYData[nValues - 1]);\r
+ }\r
+ else if(index < 0)\r
+ {\r
+ return(pYData[0]);\r
+ }\r
+ else\r
+ {\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+ \r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1u];\r
+ \r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+ \r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+ \r
+ /* convert y to 1.7(q7) format */\r
+ return (y >> 20u);\r
+\r
+ }\r
+\r
+ }\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types. \r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+\r
+ static __INLINE arm_status arm_sqrt_f32(\r
+ float32_t in, float32_t *pOut)\r
+ {\r
+ if(in > 0)\r
+ {\r
+\r
+// #if __FPU_USED\r
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+ #else \r
+ *pOut = sqrtf(in);\r
+ #endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in, q31_t *pOut);\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] *pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in, q15_t *pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+\r
+ static __INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0u;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if(wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ static __INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while(i > 0u)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if(dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if(rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output value.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] *pSrc points to the complex input vector\r
+ * @param[out] *pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] *realResult real part of the result returned here\r
+ * @param[out] *imagResult imaginary part of the result returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] *pSrcCmplx points to the complex input vector\r
+ * @param[in] *pSrcReal points to the real input vector\r
+ * @param[out] *pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] *pResult is output pointer\r
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.\r
+ * @return none.\r
+ */\r
+\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] *pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] *pResult maximum value returned here\r
+ * @param[out] *pIndex index of maximum value returned here\r
+ * @return none.\r
+ */\r
+\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] *pSrcA points to the first input vector\r
+ * @param[in] *pSrcB points to the second input vector\r
+ * @param[out] *pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @return none.\r
+ */\r
+\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none. \r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector. \r
+ * @param[in] *pSrc points to the floating-point input vector \r
+ * @param[out] *pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector \r
+ * @return none\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] *pSrc is input pointer\r
+ * @param[out] *pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @return none.\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components. \r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. \r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ \r
+ static __INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+ \r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex-1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20u);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20u);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11u;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return (acc << 2u);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return (acc >> 36);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] *S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+\r
+ static __INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & 0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & 0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))\r
+ {\r
+ return(0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + nCols * (cI)];\r
+ x2 = pYData[(rI) + nCols * (cI) + 1u];\r
+\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + nCols * (cI + 1)];\r
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return (acc >> 40);\r
+\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4.h\r
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+ * processor based microcontrollers. This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM4_H_GENERIC\r
+#define __CORE_CM4_H_GENERIC\r
+\r
+\r
+/** \mainpage CMSIS Cortex-M4\r
+\r
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.\r
+ It consists of:\r
+\r
+ - Cortex-M Core Register Definitions\r
+ - Cortex-M functions\r
+ - Cortex-M instructions\r
+ - Cortex-M SIMD instructions\r
+\r
+ The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease\r
+ access to the Cortex-M Core\r
+ */\r
+\r
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates following MISRA-C2004 Rules:\r
+ \r
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'. \r
+\r
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+ \r
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code. \r
+\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core\r
+ - Cortex-M core Revision Number\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM4 definitions */\r
+#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x04) /*!< Cortex core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ /* add preprocessor checks to define __FPU_USED */\r
+ #define __FPU_USED 0\r
+#endif\r
+\r
+#include <stdint.h> /*!< standard types definitions */\r
+#include <core_cmInstr.h> /*!< Core Instruction Access */\r
+#include <core_cmFunc.h> /*!< Core Function Access */\r
+#include <core_cm4_simd.h> /*!< Compiler specific SIMD Intrinsics */\r
+\r
+#endif /* __CORE_CM4_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM4_H_DEPENDANT\r
+#define __CORE_CM4_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM4_REV\r
+ #define __CM4_REV 0x0000\r
+ #warning "__CM4_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+/*@} end of group CMSIS_core_definitions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register CMSIS Core Register\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE CMSIS Core\r
+ Type definitions for the Cortex-M Core Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC CMSIS NVIC\r
+ Type definitions for the Cortex-M NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB CMSIS SCB\r
+ Type definitions for the Cortex-M System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB\r
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */\r
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */\r
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick CMSIS SysTick\r
+ Type definitions for the Cortex-M System Timer Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM CMSIS ITM\r
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __O union\r
+ {\r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */\r
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU CMSIS MPU\r
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU CMSIS FPU\r
+ Type definitions for the Cortex-M Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register */\r
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register */\r
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register */\r
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug\r
+ Type definitions for the Cortex-M Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions\r
+ @{\r
+ */\r
+\r
+/** \brief Set Priority Grouping\r
+\r
+ This function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Priority grouping field\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/** \brief Get Priority Grouping\r
+\r
+ This function gets the priority grouping from NVIC Interrupt Controller.\r
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+\r
+ \return Priority grouping field\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ This function enables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to enable\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */\r
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ This function disables a device specific interrupt in the NVIC interrupt controller.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the external interrupt to disable\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ This function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for get pending\r
+ \return 0 Interrupt status is not pending\r
+ \return 1 Interrupt status is pending\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ This function sets the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for set pending\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ This function clears the pending bit for the specified interrupt.\r
+ The interrupt number cannot be a negative value.\r
+\r
+ \param [in] IRQn Number of the interrupt for clear pending\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Get Active Interrupt\r
+\r
+ This function reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Number of the interrupt for get active\r
+ \return 0 Interrupt status is not active\r
+ \return 1 Interrupt status is active\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ This function sets the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ Note: The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Number of the interrupt for set priority\r
+ \param [in] priority Priority to set\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ This function reads the priority for the specified interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+ The returned priority value is automatically aligned to the implemented\r
+ priority bits of the microcontroller.\r
+\r
+ \param [in] IRQn Number of the interrupt for get priority\r
+ \return Interrupt Priority\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief Encode Priority\r
+\r
+ This function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The returned priority value can be used for NVIC_SetPriority(...) function\r
+\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)\r
+ \param [in] SubPriority Sub priority value (starting from 0)\r
+ \return Encoded priority for the interrupt\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/** \brief Decode Priority\r
+\r
+ This function decodes an interrupt priority value with the given priority group to\r
+ preemptive priority value and sub priority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ The priority value can be retrieved with NVIC_GetPriority(...) function\r
+\r
+ \param [in] Priority Priority value\r
+ \param [in] PriorityGroup Used priority group\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)\r
+ \param [out] pSubPriority Sub priority value (starting from 0)\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ This function initiate a system reset request to reset the MCU.\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ This function initialises the system tick timer and its interrupt and start the system tick timer.\r
+ Counter is in free running mode to generate periodical interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/** \brief ITM Send Character\r
+\r
+ This function transmits a character via the ITM channel 0.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \param [in] ch Character to transmit\r
+ \return Character to transmit\r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Receive Character\r
+\r
+ This function inputs a character via external variable ITM_RxBuffer.\r
+ It just returns when no debugger is connected that has booked the output.\r
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
+\r
+ \return Received character\r
+ \return -1 No character received\r
+ */\r
+static __INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/** \brief ITM Check Character\r
+\r
+ This function checks external variable ITM_RxBuffer whether a character is available or not.\r
+ It returns '1' if a character is available and '0' if no character is available.\r
+\r
+ \return 0 No character available\r
+ \return 1 Character available\r
+ */\r
+static __INLINE int32_t ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM4_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm4_simd.h\r
+ * @brief CMSIS Cortex-M4 SIMD Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#ifndef __CORE_CM4_SIMD_H\r
+#define __CORE_CM4_SIMD_H\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/\r
+/* intrinsic __SADD8 see intrinsics.h */\r
+/* intrinsic __QADD8 see intrinsics.h */\r
+/* intrinsic __SHADD8 see intrinsics.h */\r
+/* intrinsic __UADD8 see intrinsics.h */\r
+/* intrinsic __UQADD8 see intrinsics.h */\r
+/* intrinsic __UHADD8 see intrinsics.h */\r
+/* intrinsic __SSUB8 see intrinsics.h */\r
+/* intrinsic __QSUB8 see intrinsics.h */\r
+/* intrinsic __SHSUB8 see intrinsics.h */\r
+/* intrinsic __USUB8 see intrinsics.h */\r
+/* intrinsic __UQSUB8 see intrinsics.h */\r
+/* intrinsic __UHSUB8 see intrinsics.h */\r
+/* intrinsic __SADD16 see intrinsics.h */\r
+/* intrinsic __QADD16 see intrinsics.h */\r
+/* intrinsic __SHADD16 see intrinsics.h */\r
+/* intrinsic __UADD16 see intrinsics.h */\r
+/* intrinsic __UQADD16 see intrinsics.h */\r
+/* intrinsic __UHADD16 see intrinsics.h */\r
+/* intrinsic __SSUB16 see intrinsics.h */\r
+/* intrinsic __QSUB16 see intrinsics.h */\r
+/* intrinsic __SHSUB16 see intrinsics.h */\r
+/* intrinsic __USUB16 see intrinsics.h */\r
+/* intrinsic __UQSUB16 see intrinsics.h */\r
+/* intrinsic __UHSUB16 see intrinsics.h */\r
+/* intrinsic __SASX see intrinsics.h */\r
+/* intrinsic __QASX see intrinsics.h */\r
+/* intrinsic __SHASX see intrinsics.h */\r
+/* intrinsic __UASX see intrinsics.h */\r
+/* intrinsic __UQASX see intrinsics.h */\r
+/* intrinsic __UHASX see intrinsics.h */\r
+/* intrinsic __SSAX see intrinsics.h */\r
+/* intrinsic __QSAX see intrinsics.h */\r
+/* intrinsic __SHSAX see intrinsics.h */\r
+/* intrinsic __USAX see intrinsics.h */\r
+/* intrinsic __UQSAX see intrinsics.h */\r
+/* intrinsic __UHSAX see intrinsics.h */\r
+/* intrinsic __USAD8 see intrinsics.h */\r
+/* intrinsic __USADA8 see intrinsics.h */\r
+/* intrinsic __SSAT16 see intrinsics.h */\r
+/* intrinsic __USAT16 see intrinsics.h */\r
+/* intrinsic __UXTB16 see intrinsics.h */\r
+/* intrinsic __SXTB16 see intrinsics.h */\r
+/* intrinsic __UXTAB16 see intrinsics.h */\r
+/* intrinsic __SXTAB16 see intrinsics.h */\r
+/* intrinsic __SMUAD see intrinsics.h */\r
+/* intrinsic __SMUADX see intrinsics.h */\r
+/* intrinsic __SMLAD see intrinsics.h */\r
+/* intrinsic __SMLADX see intrinsics.h */\r
+/* intrinsic __SMLALD see intrinsics.h */\r
+/* intrinsic __SMLALDX see intrinsics.h */\r
+/* intrinsic __SMUSD see intrinsics.h */\r
+/* intrinsic __SMUSDX see intrinsics.h */\r
+/* intrinsic __SMLSD see intrinsics.h */\r
+/* intrinsic __SMLSDX see intrinsics.h */\r
+/* intrinsic __SMLSLD see intrinsics.h */\r
+/* intrinsic __SMLSLDX see intrinsics.h */\r
+/* intrinsic __SEL see intrinsics.h */\r
+/* intrinsic __QADD see intrinsics.h */\r
+/* intrinsic __QSUB see intrinsics.h */\r
+/* intrinsic __PKHBT see intrinsics.h */\r
+/* intrinsic __PKHTB see intrinsics.h */\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+ \r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLALD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLALDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SMLSLD(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+#define __SMLSLDX(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \\r
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+\r
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+/* not yet supported */\r
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/\r
+\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CORE_CM4_SIMD_H */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V2.10\r
+ * @date 26. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface \r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+ \r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/** \brief Get ISPR Register\r
+\r
+ This function returns the content of the ISPR Register.\r
+\r
+ \return ISPR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+ \r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+ \r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V2.10\r
+ * @date 19. July 2011\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+static __INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz \r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor, \r
+ so that all instructions following the ISB are fetched from cache or \r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier. \r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before \r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint16_t result;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint8_t result;\r
+ \r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+* -------------------------------------------------------------------\r
+* Copyright (C) 2011 ARM Limited. All rights reserved. \r
+* \r
+* Date: 25 July 2011 \r
+* Revision: V2.10 \r
+* \r
+* Project: Cortex Microcontroller Software Interface Standard (CMSIS)\r
+* Title: Release Note for CMSIS\r
+*\r
+* -------------------------------------------------------------------\r
+\r
+\r
+NOTE - Open the index.html file to access CMSIS documentation\r
+\r
+\r
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all \r
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects \r
+and reduces time-to-market for new embedded applications.\r
+\r
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").\r
+Any user of the software package is bound to the terms and conditions of the end user license agreement.\r
+\r
+\r
+You will find the following sub-directories:\r
+\r
+Documentation - Contains CMSIS documentation.\r
+ \r
+DSP_Lib - MDK project files, Examples and source files etc.. to build the \r
+ CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.\r
+\r
+Include - CMSIS Core Support and CMSIS DSP Include Files.\r
+\r
+Lib - CMSIS DSP Binaries \r
+---\r
--- /dev/null
+END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE\r
+STANDARD (CMSIS) SPECIFICATION AND SOFTWARE\r
+\r
+THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A\r
+SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE\r
+CMSIS SPECIFICATION, EXAMPLE CODE, DSP LIBRARY SPECIFICATION AND DSP LIBRARY\r
+IMPLEMENTATION AS SUCH TERMS ARE DEFINED BELOW (COLLECTIVELY, THE "ARM\r
+DELIVERABLES"). ARM IS ONLY WILLING TO LICENSE THE ARM DELIVERABLES TO YOU ON CONDITION\r
+THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING\r
+OR OTHERWISE USING OR COPYING THE ARM DELIVERABLES YOU INDICATE THAT YOU AGREE TO\r
+BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS\r
+LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE THE ARM DELIVERABLES AND YOU MAY NOT\r
+INSTALL, USE OR COPY THE ARM DELIVERABLES.\r
+\r
+"CMSIS Specification" means any documentation and C programming language files defining the application\r
+programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface\r
+Standard (CMSIS) as well as the System View Description (SVD) documentation and associated XML schema\r
+file. Notwithstanding the foregoing, "CMSIS Specification" shall not include (i) the implementation of other\r
+published specifications referenced in the CMSIS Specification; (ii) any enabling technologies that may be\r
+necessary to make or use any product or portion thereof that complies with the CMSIS Specification, but are not\r
+themselves expressly set forth in the CMSIS Specification (e.g. compiler front ends, code generators, back ends,\r
+libraries or other compiler, assembler or linker technologies; validation or debug software or hardware;\r
+applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii)\r
+maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of\r
+integrated circuit designs.\r
+\r
+"DSP Library Implementation" means any C programming language source code implementing the functionality\r
+of the digital signal processor (DSP) algorithms and the application programming interface as defined in the DSP\r
+Library Specification. The DSP Library Implementation makes use of CMSIS application programming interface\r
+and therefore is targeted at Cortex-M class processors.\r
+\r
+"DSP Library Specification" means the DSP library documentation and C programming language file defining the\r
+application programming interface of the DSP Library Implementation. Notwithstanding the foregoing, "DSP\r
+Library Specification" shall not include (i) the implementation of other published specifications referenced in the\r
+DSP Library Specification; (ii) any enabling technologies that may be necessary to make or use any product or\r
+portion thereof that complies with the DSP Library Specification, but are not themselves expressly set forth in the\r
+DSP Library Specification (e.g. compiler front ends, code generators, back ends, libraries or other compiler,\r
+assembler or linker technologies; validation or debug software or hardware; applications, operating system or\r
+driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of\r
+integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.\r
+\r
+"Example Code" means any files in C, C++ or ARM assembly programming languages, associated project and\r
+configuration files that demonstrate the usage of the CMSIS Specification, the DSP Library Specification and the\r
+DSP Library Implementation, for microprocessors or device specific software applications that are for use with\r
+microprocessors.\r
+\r
+1. LICENCE GRANTS.\r
+\r
+1.1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, nontransferable\r
+licence, to;\r
+\r
+(i) use and copy the CMSIS Specification for the purpose of developing, having developed, manufacturing,\r
+having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the\r
+CMSIS Specification, provided that you preserve any copyright notices which are included with, or in, the CMSIS\r
+Specification and provided that you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(ii) use, copy, and modify (solely to the extent necessary to incorporate the whole or any part of the DSP Library\r
+Specification into your documentation), the DSP Library Specification, for the purpose of developing, having\r
+developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing\r
+products that comply with the DSP Library Specification, and distribute and have distributed any documentation\r
+created by or for you that has been derived from the DSP Library Specification with such products, provided that\r
+you preserve any copyright notices which are included with, or in, the DSP Library Specification and provided that\r
+you do not use ARM's name, logo or trademarks to market such products;\r
+\r
+(iii) use, copy, modify and sublicense the Example Code solely for the purpose of developing, having developed,\r
+manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that\r
+comply with either or both the CMSIS Specification and the DSP Library Specification, provided that you preserve\r
+any copyright notices which are included with, or in, the Example Code and that you do not use ARM's name,\r
+logo or trademarks to market such products;\r
+\r
+(iv) use, copy and modify (provided that the logical functionality and the application programming interface of the\r
+DSP Library Implementation are maintained) the DSP Library Implementation, solely for the purposes of\r
+developing; (a) software applications for use with microprocessors manufactured or simulated under licence from\r
+ARM ("Software Applications"); and (b) tools that are designed to develop software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM ("Tools"); and\r
+\r
+(v) subject to clause 1.1(vi) below; (a) distribute and sublicense the use of the DSP Library Implementation\r
+(including any modified forms thereof created under Clause 1.1(iv) above) in binary or source format, solely as\r
+incorporated into Software Library Applications and Tools to third parties; and (b) sublicense to such third parties\r
+the right to use and copy the Tools for the purposes of developing and distribute software programs for use with\r
+microprocessors manufactured or simulated under licence from ARM.\r
+\r
+(vi) CONDITIONS ON REDISTRIBUTION: If you choose to redistribute the whole or any part of the DSP Library\r
+Implementation as incorporated into Software Library Applications or Tools, you agree to; (a) ensure that the\r
+DSP Library Implementation is licensed for use only as part of Software Library Applications and Tools and only\r
+for use with microprocessors manufactured or simulated under licence from ARM; (b) not to use ARM's name,\r
+logo or trademarks to market Software Applications and Tools; and (c) include valid copyright notices on\r
+Software Applications and Tools, and preserve any copyright notices which are included with, or in, the DSP\r
+Library Implementation.\r
+\r
+2. RESTRICTIONS ON USE OF THE ARM DELIVERABLES.\r
+\r
+PERMITTED USERS: The ARM Deliverables shall be used only by you (either a single individual, or single legal\r
+entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby\r
+agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that\r
+such sub-contractors; (i) are contractually obligated to use the ARM Deliverables only for your benefit, and (ii)\r
+agree to assign all their work product and any rights they create therein in the supply of such work to you.\r
+COPYRIGHT AND RESERVATION OF RIGHTS: The ARM Deliverables are owned by ARM or its licensors and\r
+are protected by copyright and other intellectual property laws and international treaties. The ARM Deliverables\r
+are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the ARM\r
+Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as\r
+granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except\r
+the ARM Deliverables.\r
+\r
+3. SUPPORT.\r
+\r
+ARM is not obligated to support the ARM Deliverables but may do so entirely at ARM's discretion.\r
+\r
+4. NO WARRANTY\r
+\r
+YOU AGREE THAT THE ARM DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY\r
+DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS,\r
+IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NONINFRINGEMENT,\r
+SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE ARM\r
+DELIVERABLES MAY CONTAIN ERRORS. ARM RESERVES THE RIGHT TO INCORPORATE\r
+MODIFICATIONS TO THE ARM DELIVERABLES IN LATER REVISIONS OF THEM, AND TO MAKE\r
+IMPROVEMENTS OR CHANGES IN THE ARM DELIVERABLES AT ANY TIME.\r
+\r
+5. LIMITATION OF LIABILITY.\r
+\r
+THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN\r
+CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS\r
+LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF\r
+ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN\r
+THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.\r
+\r
+6. U.S. GOVERNMENT END USERS.\r
+US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this\r
+commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.\r
+\r
+7. TERM AND TERMINATION.\r
+\r
+7.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 7.2 or Clause 7.3\r
+below.\r
+\r
+7.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this\r
+Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate\r
+this Licence at any time.\r
+\r
+7.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you\r
+asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the ARM\r
+Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate)\r
+patent is Necessary to implement the CMSIS Specification or DSP Library Specification. In this Licence; (i)\r
+"affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via\r
+voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert"\r
+means to allege infringement in legal or administrative proceedings, or proceedings before any other competent\r
+trade, arbitral or international authority; (iii) "Necessary" means with respect to any claims of any patent, those\r
+claims which, without the appropriate permission of the patent owner, will be infringed when implementing the\r
+CMSIS Specification or DSP Library Specification because no alternative, commercially reasonable, noninfringing\r
+way of implementing the CMSIS Specification or DSP Library Specification is known.\r
+\r
+7.4 Upon termination of this Licence, you shall stop using the ARM Deliverables and destroy all copies of the\r
+ARM Deliverables in your possession. The provisions of clauses 5, 6, 7, and 8 shall survive termination of this\r
+Licence.\r
+\r
+8. GENERAL.\r
+\r
+This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by\r
+you and ARM, this is the only agreement between you and ARM relating to the ARM Deliverables and it may only\r
+be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence\r
+may not be modified by purchase orders, advertising or other representation by any person. If any clause or\r
+sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisions of this\r
+Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless\r
+waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of\r
+this Licence in the future. This Licence may not be assigned without the prior written consent of ARM.\r
+\r
+ARM contract reference LEC-PRE-00489\r
--- /dev/null
+/**\r
+ * \file\r
+ *\r
+ * \brief Board configuration.\r
+ *\r
+ * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved.\r
+ *\r
+ * \asf_license_start\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of Atmel may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * 4. This software may only be redistributed and used in connection with an\r
+ * Atmel microcontroller product.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE\r
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR\r
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\r
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ * POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * \asf_license_stop\r
+ *\r
+ */\r
+\r
+#ifndef CONF_BOARD_H\r
+#define CONF_BOARD_H\r
+\r
+/* Configure UART pins */\r
+#define CONF_BOARD_UART_CONSOLE\r
+\r
+/* Configure ADC example pins */\r
+//#define CONF_BOARD_ADC\r
+\r
+/* Configure PWM LED0 pin */\r
+//#define CONF_BOARD_PWM_LED0\r
+\r
+/* Configure PWM LED1 pin */\r
+//#define CONF_BOARD_PWM_LED1\r
+\r
+/* Configure PWM LED2 pin */\r
+//#define CONF_BOARD_PWM_LED2\r
+\r
+/* Configure SPI pins */\r
+//#define CONF_BOARD_SPI\r
+//#define CONF_BOARD_SPI_NPCS0\r
+//#define CONF_BOARD_SPI_NPCS1\r
+//#define CONF_BOARD_SPI_NPCS2\r
+//#define CONF_BOARD_SPI_NPCS3\r
+\r
+/* Configure USART RXD pin */\r
+//#define CONF_BOARD_USART_RXD\r
+\r
+/* Configure USART TXD pin */\r
+//#define CONF_BOARD_USART_TXD\r
+\r
+/* Configure USART CTS pin */\r
+//#define CONF_BOARD_USART_CTS\r
+\r
+/* Configure USART RTS pin */\r
+//#define CONF_BOARD_USART_RTS\r
+\r
+/* Configure USART synchronous communication SCK pin */\r
+//#define CONF_BOARD_USART_SCK\r
+\r
+/* Configure ADM33312 enable pin */\r
+//#define CONF_BOARD_ADM3312_EN\r
+\r
+/* Configure IrDA transceiver shutdown pin */\r
+//#define CONF_BOARD_TFDU4300_SD\r
+\r
+/* Configure RS485 transceiver RE pin */\r
+//#define CONF_BOARD_ADM3485_RE\r
+\r
+/* Configure LCD EBI pins */\r
+//#define CONF_BOARD_ILI9325\r
+\r
+/* Configure Backlight control pin */\r
+//#define CONF_BOARD_AAT3155\r
+\r
+/* Configure Touchscreen SPI pins */\r
+//#define CONF_BOARD_ADS7843\r
+\r
+#endif // CONF_BOARD_H\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions.\r
+ *\r
+ * \r
+ * Additional code:\r
+ * \r
+ * This demo does not contain a non-kernel interrupt service routine that\r
+ * can be used as an example for application writers to use as a reference.\r
+ * Therefore, the framework of a dummy (not installed) handler is provided\r
+ * in this file. The dummy function is called Dummy_IRQHandler(). Please\r
+ * ensure to read the comments in the function itself, but more importantly,\r
+ * the notes on the function contained on the documentation page for this demo\r
+ * that is found on the FreeRTOS.org web site.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Atmel library includes. */\r
+#include <asf.h>\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Set up the hardware ready to run this demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/* \r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. \r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+extern void SystemCoreClockUpdate( void );\r
+\r
+ /* Ensure SystemCoreClock variable is set. */\r
+ SystemCoreClockUpdate();\r
+\r
+ /* Ensure all priority bits are assigned as preemption priority bits. */\r
+ NVIC_SetPriorityGrouping( 0 );\r
+ \r
+ /* Atmel library function to setup for the evaluation kit being used. */\r
+ board_init();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if \r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef JUST_AN_EXAMPLE_ISR\r
+\r
+void Dummy_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt if necessary. */\r
+ Dummy_ClearITPendingBit();\r
+ \r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. A semaphore is used for this purpose. Note\r
+ lHigherPriorityTaskWoken is initialised to zero. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+ \r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the current Running state task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the \r
+ portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
+ ensure this interrupt returns directly to the unblocked, higher priority, \r
+ task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+#endif /* JUST_AN_EXAMPLE_ISR */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles the LED. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Common demo includes. */\r
+#include "partest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The hardware only has a single LED. Simply toggle it.\r
+ */\r
+extern void vMainToggleLED( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( 0 );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+ \r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong? *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ \r
+ http://www.FreeRTOS.org - Documentation, training, latest information, \r
+ license and contact details.\r
+ \r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool.\r
+\r
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
+ the code with commercial support, indemnification, and middleware, under \r
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also\r
+ provide a safety engineered and independently SIL3 certified version under \r
+ the SafeRTOS brand: http://www.SafeRTOS.com.\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates all the demo application tasks and a software timer, then\r
+ * starts the scheduler. The web documentation provides more details of the \r
+ * standard demo application tasks, which provide no particular functionality, \r
+ * but do provide a good example of how to use the FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill both the core and floating point registers with\r
+ * known values, then check that each register maintains its expected value for\r
+ * the lifetime of the task. Each task uses a different set of values. The reg\r
+ * test tasks execute with a very low priority, so get preempted very\r
+ * frequently. A register containing an unexpected value is indicative of an\r
+ * error in the context switching mechanism.\r
+ *\r
+ * "Check" timer - The check software timer period is initially set to three\r
+ * seconds. The callback function associated with the check software timer\r
+ * checks that all the standard demo tasks, and the register check tasks, are\r
+ * not only still executing, but are executing without reporting any errors. If\r
+ * the check software timer discovers that a task has either stalled, or\r
+ * reported an error, then it changes its own execution period from the initial\r
+ * three seconds, to just 200ms. The check software timer callback function\r
+ * also toggles the single LED each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ */\r
+\r
+/* Standard includes. */\r
+#include <stdio.h>\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "timers.h"\r
+#include "semphr.h"\r
+\r
+/* Standard demo application includes. */\r
+#include "integer.h"\r
+#include "PollQ.h"\r
+#include "semtest.h"\r
+#include "dynamic.h"\r
+#include "BlockQ.h"\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "GenQTest.h"\r
+#include "recmutex.h"\r
+#include "death.h"\r
+#include "partest.h"\r
+\r
+/* Atmel library includes. */\r
+#include "asf.h"\r
+\r
+/* Priorities for the demo application tasks. */\r
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )\r
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )\r
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )\r
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The period after which the check timer will expire, in ms, provided no errors\r
+have been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire, in ms, if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The LED toggles by the check timer. */\r
+#define mainCHECK_LED ( 3 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xCheckTimer = NULL;\r
+\r
+ /* Start all the other standard demo/test tasks. The have not particular\r
+ functionality, but do demonstrate how to use the FreeRTOS API and test the\r
+ kernel port. */\r
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );\r
+ vStartDynamicPriorityTasks();\r
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );\r
+ vStartRecursiveMutexTasks();\r
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+ \r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ ); \r
+ \r
+ if( xCheckTimer != NULL )\r
+ {\r
+ xTimerStart( xCheckTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* The set of tasks created by the following function call have to be \r
+ created last as they keep account of the number of tasks they expect to see \r
+ running. */\r
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );\r
+\r
+ /* Start the scheduler. */\r
+ vTaskStartScheduler();\r
+ \r
+ /* If all is well, the scheduler will now be running, and the following line\r
+ will never be reached. If the following line does execute, then there was\r
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks\r
+ to be created. See the memory management section on the FreeRTOS web site\r
+ for more details. */\r
+ for( ;; ); \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo tasks (other than the flash tasks) to ensure\r
+ that they are all still running, and that none have detected an error. */\r
+\r
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xIsCreateTaskStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xArePollingQueuesStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+\r
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+ {\r
+ ulErrorFound = pdTRUE;\r
+ }\r
+ \r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+ \r
+ /* Have any errors been latch in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+ \r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
projects / freertos / commitdiff