--- /dev/null
+;/************************************************************************/\r
+;/* (C) Fujitsu Semiconductor Europe GmbH */\r
+;/* */\r
+;/* The following software deliverable is intended for and must only be */\r
+;/* used for reference and in an evaluation laboratory environment. */\r
+;/* It is provided on an as-is basis without charge and is subject to */\r
+;/* alterations. */\r
+;/* It is the user's obligation to fully test the software in its */\r
+;/* environment and to ensure proper functionality, qualification and */\r
+;/* compliance with component specifications. */\r
+;/* */\r
+;/* In the event the software deliverable includes the use of open */\r
+;/* source components, the provisions of the governing open source */\r
+;/* license agreement shall apply with respect to such software */\r
+;/* deliverable. */\r
+;/* FSEU does not warrant that the deliverables do not infringe any */\r
+;/* third party intellectual property right (IPR). In the event that */\r
+;/* the deliverables infringe a third party IPR it is the sole */\r
+;/* responsibility of the customer to obtain necessary licenses to */\r
+;/* continue the usage of the deliverable. */\r
+;/* */\r
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
+;/* warranties, whether express or implied, in particular, but not */\r
+;/* limited to, warranties of merchantability and fitness for a */\r
+;/* particular purpose for which the deliverable is not designated. */\r
+;/* */\r
+;/* To the maximum extent permitted by applicable law, FSEU's liability */\r
+;/* is restricted to intention and gross negligence. */\r
+;/* FSEU is not liable for consequential damages. */\r
+;/* */\r
+;/* (V1.4) */\r
+;/************************************************************************/\r
+;/* Startup for ARM */\r
+;/* Version V1.03 */\r
+;/* Date 2011-05-17 */\r
+;/* Target-mcu MB9A310 */\r
+;/************************************************************************/\r
+\r
+; Stack Configuration\r
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+\r
+Stack_Size EQU 0x00000200\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; Heap Configuration\r
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+\r
+; Vector Table Mapped to Address 0 at Reset\r
+\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+__Vectors DCD __initial_sp ; Top of Stack\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD NMI_Handler ; NMI Handler\r
+ DCD HardFault_Handler ; Hard Fault Handler\r
+ DCD MemManage_Handler ; MPU Fault Handler\r
+ DCD BusFault_Handler ; Bus Fault Handler\r
+ DCD UsageFault_Handler ; Usage Fault Handler\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD 0 ; Reserved\r
+ DCD SVC_Handler ; SVCall Handler\r
+ DCD DebugMon_Handler ; Debug Monitor Handler\r
+ DCD 0 ; Reserved\r
+ DCD PendSV_Handler ; PendSV Handler\r
+ DCD SysTick_Handler ; SysTick Handler\r
+\r
+ DCD CSV_Handler ; 0: Clock Super Visor\r
+ DCD SWDT_Handler ; 1: Software Watchdog Timer\r
+ DCD LVD_Handler ; 2: Low Voltage Detector\r
+ DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF\r
+ DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7\r
+ DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15\r
+ DCD DT_Handler ; 6: Dual Timer / Quad Decoder\r
+ DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0\r
+ DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0\r
+ DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1\r
+ DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1\r
+ DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2\r
+ DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2\r
+ DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3\r
+ DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3\r
+ DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4\r
+ DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4\r
+ DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5\r
+ DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5\r
+ DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6\r
+ DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6\r
+ DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7\r
+ DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7\r
+ DCD PPG_Handler ; 23: PPG\r
+ DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter\r
+ DCD ADC0_IRQHandler ; 25: ADC0\r
+ DCD ADC1_IRQHandler ; 26: ADC1\r
+ DCD ADC2_IRQHandler ; 27: ADC2\r
+ DCD MFT_FRT_IRQHandler ; 28: Free-run Timer\r
+ DCD MFT_IPC_IRQHandler ; 29: Input Capture\r
+ DCD MFT_OPC_IRQHandler ; 30: Output Compare\r
+ DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7\r
+ DCD DummyHandler ; 32: Reserved\r
+ DCD DummyHandler ; 33: Reserved\r
+ DCD USBF_Handler ; 34: USB Function\r
+ DCD USB_Handler ; 35: USB Function / USB HOST\r
+ DCD DummyHandler ; 36: Reserved\r
+ DCD DummyHandler ; 37: Reserved\r
+ DCD DMAC0_Handler ; 38: DMAC ch.0\r
+ DCD DMAC1_Handler ; 39: DMAC ch.1\r
+ DCD DMAC2_Handler ; 40: DMAC ch.2\r
+ DCD DMAC3_Handler ; 41: DMAC ch.3\r
+ DCD DMAC4_Handler ; 42: DMAC ch.4\r
+ DCD DMAC5_Handler ; 43: DMAC ch.5\r
+ DCD DMAC6_Handler ; 44: DMAC ch.6\r
+ DCD DMAC7_Handler ; 45: DMAC ch.7\r
+ DCD DummyHandler ; 46: Reserved\r
+ DCD DummyHandler ; 47: Reserved\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+ AREA |.text|, CODE, READONLY\r
+\r
+\r
+; Reset Handler\r
+\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT SystemInit\r
+ IMPORT __main\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =__main\r
+ BX R0\r
+ ENDP\r
+\r
+\r
+; Dummy Exception Handlers (infinite loops which can be modified)\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+MemManage_Handler\\r
+ PROC\r
+ EXPORT MemManage_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+BusFault_Handler\\r
+ PROC\r
+ EXPORT BusFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+UsageFault_Handler\\r
+ PROC\r
+ EXPORT UsageFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+DebugMon_Handler\\r
+ PROC\r
+ EXPORT DebugMon_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+Default_Handler PROC\r
+\r
+ EXPORT CSV_Handler [WEAK]\r
+ EXPORT SWDT_Handler [WEAK]\r
+ EXPORT LVD_Handler [WEAK]\r
+ EXPORT MFT_WG_IRQHandler [WEAK]\r
+ EXPORT INT0_7_Handler [WEAK]\r
+ EXPORT INT8_15_Handler [WEAK]\r
+ EXPORT DT_Handler [WEAK]\r
+ EXPORT MFS0RX_IRQHandler [WEAK]\r
+ EXPORT MFS0TX_IRQHandler [WEAK]\r
+ EXPORT MFS1RX_IRQHandler [WEAK]\r
+ EXPORT MFS1TX_IRQHandler [WEAK]\r
+ EXPORT MFS2RX_IRQHandler [WEAK]\r
+ EXPORT MFS2TX_IRQHandler [WEAK]\r
+ EXPORT MFS3RX_IRQHandler [WEAK]\r
+ EXPORT MFS3TX_IRQHandler [WEAK]\r
+ EXPORT MFS4RX_IRQHandler [WEAK]\r
+ EXPORT MFS4TX_IRQHandler [WEAK]\r
+ EXPORT MFS5RX_IRQHandler [WEAK]\r
+ EXPORT MFS5TX_IRQHandler [WEAK]\r
+ EXPORT MFS6RX_IRQHandler [WEAK]\r
+ EXPORT MFS6TX_IRQHandler [WEAK]\r
+ EXPORT MFS7RX_IRQHandler [WEAK]\r
+ EXPORT MFS7TX_IRQHandler [WEAK]\r
+ EXPORT PPG_Handler [WEAK]\r
+ EXPORT TIM_IRQHandler [WEAK]\r
+ EXPORT ADC0_IRQHandler [WEAK]\r
+ EXPORT ADC1_IRQHandler [WEAK]\r
+ EXPORT ADC2_IRQHandler [WEAK]\r
+ EXPORT MFT_FRT_IRQHandler [WEAK]\r
+ EXPORT MFT_IPC_IRQHandler [WEAK]\r
+ EXPORT MFT_OPC_IRQHandler [WEAK]\r
+ EXPORT BT_IRQHandler [WEAK]\r
+ EXPORT USBF_Handler [WEAK]\r
+ EXPORT USB_Handler [WEAK]\r
+ EXPORT DMAC0_Handler [WEAK]\r
+ EXPORT DMAC1_Handler [WEAK]\r
+ EXPORT DMAC2_Handler [WEAK]\r
+ EXPORT DMAC3_Handler [WEAK]\r
+ EXPORT DMAC4_Handler [WEAK]\r
+ EXPORT DMAC5_Handler [WEAK]\r
+ EXPORT DMAC6_Handler [WEAK]\r
+ EXPORT DMAC7_Handler [WEAK]\r
+ EXPORT DummyHandler [WEAK]\r
+\r
+CSV_Handler\r
+SWDT_Handler\r
+LVD_Handler\r
+MFT_WG_IRQHandler\r
+INT0_7_Handler\r
+INT8_15_Handler\r
+DT_Handler\r
+MFS0RX_IRQHandler\r
+MFS0TX_IRQHandler\r
+MFS1RX_IRQHandler\r
+MFS1TX_IRQHandler\r
+MFS2RX_IRQHandler\r
+MFS2TX_IRQHandler\r
+MFS3RX_IRQHandler\r
+MFS3TX_IRQHandler\r
+MFS4RX_IRQHandler\r
+MFS4TX_IRQHandler\r
+MFS5RX_IRQHandler\r
+MFS5TX_IRQHandler\r
+MFS6RX_IRQHandler\r
+MFS6TX_IRQHandler\r
+MFS7RX_IRQHandler\r
+MFS7TX_IRQHandler\r
+PPG_Handler\r
+TIM_IRQHandler\r
+ADC0_IRQHandler\r
+ADC1_IRQHandler\r
+ADC2_IRQHandler\r
+MFT_FRT_IRQHandler\r
+MFT_IPC_IRQHandler\r
+MFT_OPC_IRQHandler\r
+BT_IRQHandler\r
+USBF_Handler\r
+USB_Handler\r
+DMAC0_Handler\r
+DMAC1_Handler\r
+DMAC2_Handler\r
+DMAC3_Handler\r
+DMAC4_Handler\r
+DMAC5_Handler\r
+DMAC6_Handler\r
+DMAC7_Handler\r
+DummyHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+\r
+ ALIGN\r
+\r
+\r
+; User Initial Stack & Heap\r
+\r
+ IF :DEF:__MICROLIB\r
+ \r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+ \r
+ ELSE\r
+ \r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+ END\r
+++ /dev/null
-;/************************************************************************/\r
-;/* (C) Fujitsu Semiconductor Europe GmbH */\r
-;/* */\r
-;/* The following software deliverable is intended for and must only be */\r
-;/* used for reference and in an evaluation laboratory environment. */\r
-;/* It is provided on an as-is basis without charge and is subject to */\r
-;/* alterations. */\r
-;/* It is the user\92s obligation to fully test the software in its */\r
-;/* environment and to ensure proper functionality, qualification and */\r
-;/* compliance with component specifications. */\r
-;/* */\r
-;/* In the event the software deliverable includes the use of open */\r
-;/* source components, the provisions of the governing open source */\r
-;/* license agreement shall apply with respect to such software */\r
-;/* deliverable. */\r
-;/* FSEU does not warrant that the deliverables do not infringe any */\r
-;/* third party intellectual property right (IPR). In the event that */\r
-;/* the deliverables infringe a third party IPR it is the sole */\r
-;/* responsibility of the customer to obtain necessary licenses to */\r
-;/* continue the usage of the deliverable. */\r
-;/* */\r
-;/* To the maximum extent permitted by applicable law FSEU disclaims all */\r
-;/* warranties, whether express or implied, in particular, but not */\r
-;/* limited to, warranties of merchantability and fitness for a */\r
-;/* particular purpose for which the deliverable is not designated. */\r
-;/* */\r
-;/* To the maximum extent permitted by applicable law, FSEU's liability */\r
-;/* is restricted to intention and gross negligence. */\r
-;/* FSEU is not liable for consequential damages. */\r
-;/* */\r
-;/* (V1.4) */\r
-;/************************************************************************/\r
-;/* Startup for ARM */\r
-;/* Version V1.02 */\r
-;/* Date 2011-01-12 */\r
-;/* Target-mcu MB9B5xx */\r
-;/************************************************************************/\r
-\r
-; Stack Configuration\r
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-\r
-Stack_Size EQU 0x00000200\r
-\r
- AREA STACK, NOINIT, READWRITE, ALIGN=3\r
-Stack_Mem SPACE Stack_Size\r
-__initial_sp\r
-\r
-\r
-; Heap Configuration\r
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-\r
-Heap_Size EQU 0x00000000\r
-\r
- AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem SPACE Heap_Size\r
-__heap_limit\r
-\r
-\r
- PRESERVE8\r
- THUMB\r
-\r
-\r
-; Vector Table Mapped to Address 0 at Reset\r
-\r
- AREA RESET, DATA, READONLY\r
- EXPORT __Vectors\r
- EXPORT __Vectors_End\r
- EXPORT __Vectors_Size\r
-\r
-__Vectors DCD __initial_sp ; Top of Stack\r
- DCD Reset_Handler ; Reset Handler\r
- DCD NMI_Handler ; NMI Handler\r
- DCD HardFault_Handler ; Hard Fault Handler\r
- DCD MemManage_Handler ; MPU Fault Handler\r
- DCD BusFault_Handler ; Bus Fault Handler\r
- DCD UsageFault_Handler ; Usage Fault Handler\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD 0 ; Reserved\r
- DCD SVC_Handler ; SVCall Handler\r
- DCD DebugMon_Handler ; Debug Monitor Handler\r
- DCD 0 ; Reserved\r
- DCD PendSV_Handler ; PendSV Handler\r
- DCD SysTick_Handler ; SysTick Handler\r
-\r
- DCD CSV_Handler ; 0: Clock Super Visor\r
- DCD SWDT_Handler ; 1: Software Watchdog Timer\r
- DCD LVD_Handler ; 2: Low Voltage Detector\r
- DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF\r
- DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7\r
- DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15\r
- DCD DT_Handler ; 6: Dual Timer / Quad Decoder\r
- DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0\r
- DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0\r
- DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1\r
- DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1\r
- DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2\r
- DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2\r
- DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3\r
- DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3\r
- DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4\r
- DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4\r
- DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5\r
- DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5\r
- DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6\r
- DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6\r
- DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7\r
- DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7\r
- DCD PPG_Handler ; 23: PPG\r
- DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter\r
- DCD ADC0_IRQHandler ; 25: ADC0\r
- DCD ADC1_IRQHandler ; 26: ADC1\r
- DCD ADC2_IRQHandler ; 27: ADC2\r
- DCD MFT_FRT_IRQHandler ; 28: Free-run Timer\r
- DCD MFT_IPC_IRQHandler ; 29: Input Capture\r
- DCD MFT_OPC_IRQHandler ; 30: Output Compare\r
- DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7\r
- DCD CAN0_IRQHandler ; 32: CAN ch.0\r
- DCD CAN1_IRQHandler ; 33: CAN ch.1\r
- DCD USBF_Handler ; 34: USB Function\r
- DCD USB_Handler ; 35: USB Function / USB HOST\r
- DCD DummyHandler ; 36: Reserved\r
- DCD DummyHandler ; 37: Reserved\r
- DCD DMAC0_Handler ; 38: DMAC ch.0\r
- DCD DMAC1_Handler ; 39: DMAC ch.1\r
- DCD DMAC2_Handler ; 40: DMAC ch.2\r
- DCD DMAC3_Handler ; 41: DMAC ch.3\r
- DCD DMAC4_Handler ; 42: DMAC ch.4\r
- DCD DMAC5_Handler ; 43: DMAC ch.5\r
- DCD DMAC6_Handler ; 44: DMAC ch.6\r
- DCD DMAC7_Handler ; 45: DMAC ch.7\r
- DCD DummyHandler ; 46: Reserved\r
- DCD DummyHandler ; 47: Reserved\r
-__Vectors_End\r
-\r
-__Vectors_Size EQU __Vectors_End - __Vectors\r
-\r
- AREA |.text|, CODE, READONLY\r
-\r
-\r
-; Reset Handler\r
-\r
-Reset_Handler PROC\r
- EXPORT Reset_Handler [WEAK]\r
- IMPORT SystemInit\r
- IMPORT __main\r
- LDR R0, =SystemInit\r
- BLX R0\r
- LDR R0, =__main\r
- BX R0\r
- ENDP\r
-\r
-\r
-; Dummy Exception Handlers (infinite loops which can be modified)\r
-\r
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-MemManage_Handler\\r
- PROC\r
- EXPORT MemManage_Handler [WEAK]\r
- B .\r
- ENDP\r
-BusFault_Handler\\r
- PROC\r
- EXPORT BusFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-UsageFault_Handler\\r
- PROC\r
- EXPORT UsageFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-SVC_Handler PROC\r
- EXPORT SVC_Handler [WEAK]\r
- B .\r
- ENDP\r
-DebugMon_Handler\\r
- PROC\r
- EXPORT DebugMon_Handler [WEAK]\r
- B .\r
- ENDP\r
-PendSV_Handler PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- B .\r
- ENDP\r
-SysTick_Handler PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- B .\r
- ENDP\r
-\r
-Default_Handler PROC\r
-\r
- EXPORT CSV_Handler [WEAK]\r
- EXPORT SWDT_Handler [WEAK]\r
- EXPORT LVD_Handler [WEAK]\r
- EXPORT MFT_WG_IRQHandler [WEAK]\r
- EXPORT INT0_7_Handler [WEAK]\r
- EXPORT INT8_15_Handler [WEAK]\r
- EXPORT DT_Handler [WEAK]\r
- EXPORT MFS0RX_IRQHandler [WEAK]\r
- EXPORT MFS0TX_IRQHandler [WEAK]\r
- EXPORT MFS1RX_IRQHandler [WEAK]\r
- EXPORT MFS1TX_IRQHandler [WEAK]\r
- EXPORT MFS2RX_IRQHandler [WEAK]\r
- EXPORT MFS2TX_IRQHandler [WEAK]\r
- EXPORT MFS3RX_IRQHandler [WEAK]\r
- EXPORT MFS3TX_IRQHandler [WEAK]\r
- EXPORT MFS4RX_IRQHandler [WEAK]\r
- EXPORT MFS4TX_IRQHandler [WEAK]\r
- EXPORT MFS5RX_IRQHandler [WEAK]\r
- EXPORT MFS5TX_IRQHandler [WEAK]\r
- EXPORT MFS6RX_IRQHandler [WEAK]\r
- EXPORT MFS6TX_IRQHandler [WEAK]\r
- EXPORT MFS7RX_IRQHandler [WEAK]\r
- EXPORT MFS7TX_IRQHandler [WEAK]\r
- EXPORT PPG_Handler [WEAK]\r
- EXPORT TIM_IRQHandler [WEAK]\r
- EXPORT ADC0_IRQHandler [WEAK]\r
- EXPORT ADC1_IRQHandler [WEAK]\r
- EXPORT ADC2_IRQHandler [WEAK]\r
- EXPORT MFT_FRT_IRQHandler [WEAK]\r
- EXPORT MFT_IPC_IRQHandler [WEAK]\r
- EXPORT MFT_OPC_IRQHandler [WEAK]\r
- EXPORT BT_IRQHandler [WEAK]\r
- EXPORT CAN0_IRQHandler [WEAK]\r
- EXPORT CAN1_IRQHandler [WEAK]\r
- EXPORT USBF_Handler [WEAK]\r
- EXPORT USB_Handler [WEAK]\r
- EXPORT DMAC0_Handler [WEAK]\r
- EXPORT DMAC1_Handler [WEAK]\r
- EXPORT DMAC2_Handler [WEAK]\r
- EXPORT DMAC3_Handler [WEAK]\r
- EXPORT DMAC4_Handler [WEAK]\r
- EXPORT DMAC5_Handler [WEAK]\r
- EXPORT DMAC6_Handler [WEAK]\r
- EXPORT DMAC7_Handler [WEAK]\r
- EXPORT DummyHandler [WEAK]\r
-\r
-CSV_Handler\r
-SWDT_Handler\r
-LVD_Handler\r
-MFT_WG_IRQHandler\r
-INT0_7_Handler\r
-INT8_15_Handler\r
-DT_Handler\r
-MFS0RX_IRQHandler\r
-MFS0TX_IRQHandler\r
-MFS1RX_IRQHandler\r
-MFS1TX_IRQHandler\r
-MFS2RX_IRQHandler\r
-MFS2TX_IRQHandler\r
-MFS3RX_IRQHandler\r
-MFS3TX_IRQHandler\r
-MFS4RX_IRQHandler\r
-MFS4TX_IRQHandler\r
-MFS5RX_IRQHandler\r
-MFS5TX_IRQHandler\r
-MFS6RX_IRQHandler\r
-MFS6TX_IRQHandler\r
-MFS7RX_IRQHandler\r
-MFS7TX_IRQHandler\r
-PPG_Handler\r
-TIM_IRQHandler\r
-ADC0_IRQHandler\r
-ADC1_IRQHandler\r
-ADC2_IRQHandler\r
-MFT_FRT_IRQHandler\r
-MFT_IPC_IRQHandler\r
-MFT_OPC_IRQHandler\r
-BT_IRQHandler\r
-CAN0_IRQHandler\r
-CAN1_IRQHandler\r
-USBF_Handler\r
-USB_Handler\r
-DMAC0_Handler\r
-DMAC1_Handler\r
-DMAC2_Handler\r
-DMAC3_Handler\r
-DMAC4_Handler\r
-DMAC5_Handler\r
-DMAC6_Handler\r
-DMAC7_Handler\r
-DummyHandler\r
-\r
- B .\r
-\r
- ENDP\r
-\r
-\r
- ALIGN\r
-\r
-\r
-; User Initial Stack & Heap\r
-\r
- IF :DEF:__MICROLIB\r
- \r
- EXPORT __initial_sp\r
- EXPORT __heap_base\r
- EXPORT __heap_limit\r
- \r
- ELSE\r
- \r
- IMPORT __use_two_region_memory\r
- EXPORT __user_initial_stackheap\r
-__user_initial_stackheap\r
-\r
- LDR R0, = Heap_Mem\r
- LDR R1, =(Stack_Mem + Stack_Size)\r
- LDR R2, = (Heap_Mem + Heap_Size)\r
- LDR R3, = Stack_Mem\r
- BX LR\r
-\r
- ALIGN\r
-\r
- ENDIF\r
-\r
-\r
- END\r
projects / freertos / commitdiff