/* Hardware includes. */\r
#include <xintc_i.h>\r
#include <xil_exception.h>\r
-#include <microblaze_exceptions_i.h>\r
#include <microblaze_exceptions_g.h>\r
\r
/* Tasks are started with a critical section nesting of 0 - however prior\r
*/\r
static portBASE_TYPE prvInitialiseInterruptController( void );\r
\r
-static void prvExceptionHandler( void *pvExceptionID );\r
-\r
/*\r
* Call an application provided callback to set up the periodic interrupt used\r
* for the RTOS tick. Using an application callback allows the application\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvExceptionHandler( void *pvExceptionID )\r
-{\r
-volatile unsigned long ulExceptionID;\r
-\r
- ulExceptionID = ( unsigned long ) pvExceptionID;\r
- for( ;; )\r
- {\r
- portNOP();\r
- }\r
-\r
- ( void ) ulExceptionID;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
static portBASE_TYPE prvInitialiseInterruptController( void )\r
{\r
portBASE_TYPE xStatus;\r
/* Service all pending interrupts each time the handler is entered. */\r
XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );\r
\r
- /* Install exception handlers. */\r
- #if MICROBLAZE_EXCEPTIONS_ENABLED == 1\r
-\r
- #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
- microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, prvExceptionHandler, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
- #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
-\r
- #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, prvExceptionHandler, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
- #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
- #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, prvExceptionHandler, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
- #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_FPU, prvExceptionHandler, ( void * ) XEXC_ID_FPU );\r
- #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
-\r
- #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
- microblaze_register_exception_handler( XEXC_ID_FSL, prvExceptionHandler, ( void * ) XEXC_ID_FSL );\r
- #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
-\r
+ /* Install exception handlers if the MicroBlaze is configured to handle\r
+ exceptions, and the application defined constant\r
+ configINSTALL_EXCEPTION_HANDLERS is set to 1. */\r
+ #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )\r
+ {\r
+ vPortExceptionsInstallHandlers();\r
+ }\r
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */\r
\r
/* Start the interrupt controller. Interrupts are enabled when the\r
\r
configASSERT( ( xStatus == ( portBASE_TYPE ) XST_SUCCESS ) )\r
\r
-/*_RB_ Exception test code.\r
+/*_RB_ Exception test code. */\r
+#if 0\r
+This does not cause the bralid address to be in the r17 register.\r
__asm volatile (\r
"bralid r15, 1234 \n"\r
"or r0, r0, r0 \n"\r
);\r
-*/\r
+#endif\r
+#if 0\r
+ xStatus /= 0;\r
+#endif\r
\r
return xStatus;\r
}\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware includes. */\r
+#include <microblaze_exceptions_i.h>\r
+#include <microblaze_exceptions_g.h>\r
+\r
+#define portexR3_STACK_OFFSET 4\r
+#define portexR4_STACK_OFFSET 5\r
+#define portexR5_STACK_OFFSET 6\r
+#define portexR6_STACK_OFFSET 7\r
+#define portexR7_STACK_OFFSET 8\r
+#define portexR8_STACK_OFFSET 9\r
+#define portexR9_STACK_OFFSET 10\r
+#define portexR10_STACK_OFFSET 11\r
+#define portexR11_STACK_OFFSET 12\r
+#define portexR12_STACK_OFFSET 13\r
+#define portexR15_STACK_OFFSET 16\r
+#define portexR18_STACK_OFFSET 18\r
+#define portexR19_STACK_OFFSET -1\r
+\r
+#define portexESR_DS_MASK 0x00001000UL\r
+\r
+\r
+/* Exclude the entire file if the MicroBlaze is not configured to handle\r
+exceptions, or the application defined configuration item \r
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */\r
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )\r
+\r
+/* These are global volatiles to allow their inspection by a debugger. */\r
+unsigned long *pulStackPointerOnFunctionEntry = NULL;\r
+\r
+static xPortRegisterDump xRegisterDump;\r
+\r
+void vPortExceptionHandler( void *pvExceptionID );\r
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExceptionHandler( void *pvExceptionID )\r
+{\r
+extern void *pxCurrentTCB;\r
+\r
+ xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;\r
+ xRegisterDump.pcCurrentTaskName = pcTaskGetTaskName( NULL );\r
+\r
+ configASSERT( pulStackPointerOnFunctionEntry );\r
+\r
+ /* Obtain the values of registers that were stacked prior to this function\r
+ being called, and may have changed since they were stacked. */
+ xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];\r
+ xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];\r
+ xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];\r
+ xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];\r
+ xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];\r
+ xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];\r
+ xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];\r
+ xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];\r
+ xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];\r
+ xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];\r
+ xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];\r
+\r
+ /* Obtain the value of all other registers. */\r
+ //xRegisterDump.ulR1 =\r
+ xRegisterDump.ulR2_small_data_area = mfgpr( R2 );\r
+ xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );\r
+ xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );\r
+ xRegisterDump.ulR15_return_address_from_subroutine = mfgpr( R15 );\r
+ xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );\r
+ xRegisterDump.ulR17_return_address_from_some_exceptions = mfgpr( R17 );\r
+ xRegisterDump.ulR18 = mfgpr( R18 );\r
+ xRegisterDump.ulR20 = mfgpr( R20 );\r
+ xRegisterDump.ulR21 = mfgpr( R21 );\r
+ xRegisterDump.ulR22 = mfgpr( R22 );\r
+ xRegisterDump.ulR23 = mfgpr( R23 );\r
+ xRegisterDump.ulR24 = mfgpr( R24 );\r
+ xRegisterDump.ulR25 = mfgpr( R25 );\r
+ xRegisterDump.ulR26 = mfgpr( R26 );\r
+ xRegisterDump.ulR27 = mfgpr( R27 );\r
+ xRegisterDump.ulR28 = mfgpr( R28 );\r
+ xRegisterDump.ulR29 = mfgpr( R29 );\r
+ xRegisterDump.ulR30 = mfgpr( R30 );\r
+ xRegisterDump.ulR31 = mfgpr( R31 );\r
+\r
+ xRegisterDump.ulESR = mfesr();\r
+ if( ( xRegisterDump.ulESR * portexESR_DS_MASK ) != 0UL )\r
+ {\r
+ xRegisterDump.ulPC = mfbtr();\r
+ }\r
+ else\r
+ {\r
+ xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_some_exceptions - 4;\r
+ }\r
+\r
+ // xRegisterDump.ulSP =;\r
+\r
+ // PC changes\r
+ // MSR changes\r
+ // BTR changes\r
+\r
+ switch( ( unsigned long ) pvExceptionID )\r
+ {\r
+ case XEXC_ID_FSL :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FSL";\r
+ break;\r
+\r
+ case XEXC_ID_UNALIGNED_ACCESS :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_UNALIGNED_ACCESS";\r
+ break;\r
+\r
+ case XEXC_ID_ILLEGAL_OPCODE :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_ILLEGAL_OPCODE";\r
+ break;\r
+\r
+ case XEXC_ID_M_AXI_I_EXCEPTION :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";\r
+ break;\r
+\r
+ case XEXC_ID_M_AXI_D_EXCEPTION :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";\r
+ break;\r
+\r
+ case XEXC_ID_DIV_BY_ZERO :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_DIV_BY_ZERO";\r
+ break;\r
+\r
+ case XEXC_ID_FPU :\r
+ /*_RB_ More decoding required here and in other exceptions. */\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU";\r
+ break;\r
+\r
+ case XEXC_ID_STACK_VIOLATION :\r
+ xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";\r
+ break;\r
+ }\r
+\r
+ /* Must not attempt to leave this function! */\r
+ for( ;; )\r
+ {\r
+ portNOP();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExceptionsInstallHandlers( void )\r
+{\r
+ #if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1\r
+ microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );\r
+ #endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/\r
+\r
+ #if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );\r
+ #endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );\r
+ #endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );\r
+ #endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );\r
+ #endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/\r
+\r
+ #if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1\r
+ microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );\r
+ #endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Exclude the entire file if the MicroBlaze is not configured to handle\r
+exceptions, or the application defined configuration item \r
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */\r
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */\r
+\r
+\r
+\r