# elf file.elf Link: create ELF output file from object files.
# lss file.lss Create extended listing from target output file.
# sym file.sym Create symbol table from target output file.
+# hex file.hex Create Intel HEX image from ELF output file.
# bin file.bin Create binary image from ELF output file.
# sizes Display target size information.
+# isp Use ISP instead of JTAGICE mkII when programming.
# cpuinfo Get CPU information.
# halt Stop CPU execution.
+# chiperase Perform a JTAG Chip Erase command.
+# erase Perform a flash chip erase.
# program Program MCU memory from ELF output file.
-# reset Reset CPU.
+# secureflash Protect chip by setting security bit.
+# reset Reset MCU.
# debug Open a debug connection with the MCU.
# run Start CPU execution.
# readregs Read CPU registers.
CPPFILES = $(CSRCS:.c=.i)
CC = avr32-gcc
-CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS)
+CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x)
AS = avr32-as
-ASFLAGS = $(DEBUG) $(AS_EXTRA_FLAGS)
+ASFLAGS = $(DEBUG) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o)
LD = avr32-ld
SYM = $(TGTFILE:$(TGTTYPE)=.sym)
OBJCOPY = avr32-objcopy
+HEX = $(TGTFILE:$(TGTTYPE)=.hex)
BIN = $(TGTFILE:$(TGTTYPE)=.bin)
SIZE = avr32-size
-SUDO = $(shell if [ -x /usr/bin/sudo ]; then echo sudo; fi)
-
SLEEP = sleep
SLEEPUSB = 9
PROGRAM = avr32program
+ISP = batchisp
+ISPFLAGS = -device at32$(PART) -hardware usb -operation
+
DBGPROXY = avr32gdbproxy
DOCGEN = doxygen
MSG_LINKING = Linking to \`$@\'.
MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'.
MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'.
+MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'.
MSG_BINARY_IMAGE = Creating binary image to \`$@\'.
MSG_GETTING_CPU_INFO = Getting CPU information.
MSG_HALTING = Stopping CPU execution.
-MSG_PROGRAMMING = Programming MCU memory from \`$<\'.
-MSG_RESETTING = Resetting CPU.
+MSG_ERASING_CHIP = Performing a JTAG Chip Erase command.
+MSG_ERASING = Performing a flash chip erase.
+MSG_PROGRAMMING = Programming MCU memory from \`$(TGTFILE)\'.
+MSG_SECURING_FLASH = Protecting chip by setting security bit.
+MSG_RESETTING = Resetting MCU.
MSG_DEBUGGING = Opening debug connection with MCU.
MSG_RUNNING = Starting CPU execution.
MSG_READING_CPU_REGS = Reading CPU registers.
# Default goal: build the project.
ifeq ($(TGTTYPE),.a)
.PHONY: all
-all: ccversion a lss sym
+all: ccversion a lss sym sizes
else
ifeq ($(TGTTYPE),.elf)
.PHONY: all
-all: ccversion elf lss sym bin sizes
+all: ccversion elf lss sym hex bin sizes
else
$(error $(ERR_TARGET_TYPE))
endif
clean:
@echo $(MSG_CLEANING)
-$(VERBOSE_CMD)$(RM) $(BIN)
+ -$(VERBOSE_CMD)$(RM) $(HEX)
-$(VERBOSE_CMD)$(RM) $(SYM)
-$(VERBOSE_CMD)$(RM) $(LSS)
-$(VERBOSE_CMD)$(RM) $(TGTFILE)
sym: $(SYM)
ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+.PHONY: hex
+hex: $(HEX)
+
# Create binary image from ELF output file.
.PHONY: bin
bin: $(BIN)
+
endif
# Display target size information.
sizes: $(TGTFILE)
@echo
@echo
+ifeq ($(TGTTYPE),.a)
+ @$(SIZE) -Bxt $<
+else
+ifeq ($(TGTTYPE),.elf)
@$(SIZE) -Ax $<
+ @$(SIZE) -Bx $<
+endif
+endif
+ @echo
+ @echo
ifeq ($(TGTTYPE),.elf)
+# Use ISP instead of JTAGICE mkII when programming.
+.PHONY: isp
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
+isp: all
+else
+isp:
+ @:
+endif
+
+ifeq ($(findstring isp,$(MAKECMDGOALS)),)
+
# Get CPU information.
.PHONY: cpuinfo
cpuinfo:
@echo
@echo $(MSG_GETTING_CPU_INFO)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB cpuinfo
-ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
+ $(VERBOSE_CMD)$(PROGRAM) cpuinfo
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
@$(SLEEP) $(SLEEPUSB)
else
@echo
# Stop CPU execution.
.PHONY: halt
halt:
-ifeq ($(filter cpuinfo program reset run readregs,$(MAKECMDGOALS)),)
+ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_HALTING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB halt
+ $(VERBOSE_CMD)$(PROGRAM) halt
ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
+endif
+
+# Perform a JTAG Chip Erase command.
+.PHONY: chiperase
+chiperase:
+ @echo
+ @echo $(MSG_ERASING_CHIP)
+ $(VERBOSE_CMD)$(PROGRAM) chiperase
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(filter chiperase program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
endif
# Program MCU memory from ELF output file.
.PHONY: program
-program: $(TGTFILE)
+program: all
@echo
@echo $(MSG_PROGRAMMING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB program $(FLASH:%=-f%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $<
-ifneq ($(call LastWord,$(filter cpuinfo program debug readregs,$(MAKECMDGOALS))),program)
+ $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TGTFILE)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
-# Reset CPU.
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(PROGRAM) secureflash
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Reset MCU.
.PHONY: reset
reset:
ifeq ($(filter program run,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_RESETTING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB reset
-ifneq ($(call LastWord,$(filter cpuinfo reset debug readregs,$(MAKECMDGOALS))),reset)
+ $(VERBOSE_CMD)$(PROGRAM) reset
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
endif
# Open a debug connection with the MCU.
debug:
@echo
@echo $(MSG_DEBUGGING)
- $(VERBOSE_CMD)$(SUDO) $(DBGPROXY) -cUSB $(patsubst cfi@%,-f%,$(FLASH:internal@%=-f%))
-ifneq ($(call LastWord,$(filter cpuinfo halt program reset debug run readregs,$(MAKECMDGOALS))),debug)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug)
@$(SLEEP) $(SLEEPUSB)
else
@echo
ifeq ($(findstring program,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_RUNNING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
-ifneq ($(call LastWord,$(filter cpuinfo debug run readregs,$(MAKECMDGOALS))),run)
+ $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
endif
# Read CPU registers.
readregs:
@echo
@echo $(MSG_READING_CPU_REGS)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB readregs
-ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),readregs)
+ $(VERBOSE_CMD)$(PROGRAM) readregs
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
+else
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(findstring program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck
+ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase)
+ @echo
+endif
+else
+ @:
+endif
+
+# Program MCU memory from ELF output file.
+.PHONY: program
+program: all
+ @echo
+ @echo $(MSG_PROGRAMMING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TGTFILE) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0))
+ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program)
+ @echo
+endif
+
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)
+ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash)
+ @echo
+endif
+
+# Reset MCU.
+.PHONY: reset
+reset:
+ @:
+
+# Open a debug connection with the MCU.
+.PHONY: debug
+debug:
+ @echo
+ @echo $(MSG_DEBUGGING)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug)
+ @echo
+endif
+
+# Start CPU execution.
+.PHONY: run
+run:
+ifeq ($(filter program secureflash,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RUNNING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0
+ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run)
+ @echo
+endif
+else
+ @:
+endif
+
+endif
+
endif
# Build the documentation.
# Display main executed commands.
.PHONY: verbose
-ifeq ($(MAKECMDGOALS),verbose)
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
verbose: all
else
verbose:
- @echo > /dev/null
+ @:
endif
ifneq ($(findstring verbose,$(MAKECMDGOALS)),)
# Prefix displaying the following command if and only if verbose is a goal.
$(VERBOSE_NL)
ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+$(HEX): $(TGTFILE)
+ @echo $(MSG_IHEX_IMAGE)
+ $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@
+ $(VERBOSE_NL)
+
# Create binary image from ELF output file.
$(BIN): $(TGTFILE)
@echo $(MSG_BINARY_IMAGE)
$(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@
$(VERBOSE_NL)
+
endif
# CPU architecture: {ap|uc}
ARCH = uc
-# Part: {none|ap7000|ap7010|ap7020|uc3a0256|uc3a0512|uc3a1128|uc3a1256|uc3a1512}
+# Part: {none|ap7xxx|uc3xxxxx}
PART = uc3a0512
-# Flash memories: [type@address,size]...
+# Flash memories: [{cfi|internal}@address,size]...
FLASH = internal@0x80000000,512Kb
+# Clock source to use when programming: [{xtal|extclk|int}]
+PROG_CLOCK = xtal
+
# Device/Platform/Board include path
PLATFORM_INC_PATH = \
$(BRDS_PATH)/
# Definitions: [-D name[=definition]...] [-U name...]
# Things that might be added to DEFS:
-# BOARD Board used: {EVK1100}
+# BOARD Board used: {EVKxxxx}
+# EXT_BOARD Extension board used (if any): {EXTxxxx}
DEFS = -D BOARD=EVK1100
# Include path
INC_PATH = \
$(UTIL_PATH)/ \
$(UTIL_PATH)/PREPROCESSOR/ \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \
$(DRVR_PATH)/INTC/ \
$(DRVR_PATH)/PM/ \
$(DRVR_PATH)/GPIO/ \
$(DRVR_PATH)/GPIO/gpio.c \
$(DRVR_PATH)/TC/tc.c \
../../../../Source/portable/GCC/AVR32_UC3/port.c \
- ../../../../Source/portable/MemMang/heap_3.c \
+ ../../../../Source/portable/MemMang/heap_2.c \
../../../../Source/list.c \
../../../../Source/queue.c \
../../../../Source/tasks.c \
# Assembler source files
ASSRCS = \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \
../../../../Source/portable/GCC/AVR32_UC3/exception.S
# Library path
LIBS =
# Linker script file if any
-LINKER_SCRIPT =
+LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...]
# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
CPP_EXTRA_FLAGS =
# Extra flags to use when compiling
-C_EXTRA_FLAGS = -DGCC_AVR32_PORT
+C_EXTRA_FLAGS =
# Extra flags to use when assembling
AS_EXTRA_FLAGS =
# Extra flags to use when linking
-LD_EXTRA_FLAGS = -Wl,--gc-sections
+LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline
# Documentation path
DOC_PATH = \
# Documentation configuration file
DOC_CFG = \
- ../../doxyfile.doxygen
+ ../doxyfile.doxygen
--- /dev/null
+target extended-remote :4711\r
+symbol uc3a0512-rtosdemo.elf\r
+\r
+b _handle_Unrecoverable_Exception\r
+b _handle_TLB_Multiple_Hit\r
+b _handle_Bus_Error_Data_Fetch\r
+b _handle_Bus_Error_Instruction_Fetch\r
+b _handle_NMI\r
+b _handle_Instruction_Address\r
+b _handle_ITLB_Protection\r
+b _handle_Breakpoint\r
+b _handle_Illegal_Opcode\r
+b _handle_Unimplemented_Instruction\r
+b _handle_Privilege_Violation\r
+b _handle_Floating_Point\r
+b _handle_Coprocessor_Absent\r
+b _handle_Data_Address_Read\r
+b _handle_Data_Address_Write\r
+b _handle_DTLB_Protection_Read\r
+b _handle_DTLB_Protection_Write\r
+b _handle_DTLB_Modified\r
+b _handle_ITLB_Miss\r
+b _handle_DTLB_Miss_Read\r
+b _handle_DTLB_Miss_Write\r
+\r
+define current_task\r
+printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName\r
+printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack\r
+end\r
</settings>\r
<settings>\r
<name>JTAGICEMKIIAVR32</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <archiveVersion>3</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CJtagIceMkIIDaisyChainAfterBits</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<debuggerPlugins>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
</debuggerPlugins>\r
</settings>\r
<settings>\r
<name>JTAGICEMKIIAVR32</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <archiveVersion>3</archiveVersion>\r
<data>\r
- <version>0</version>\r
+ <version>1</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>0</debug>\r
<option>\r
<name>CJtagIceMkIIDaisyChainAfterBits</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
</settings>\r
<debuggerPlugins>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
<loadFlag>0</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
<plugin>\r
- <file>$EW_DIR$\common\plugins\Stack\Stack.ewplugin</file>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
<loadFlag>1</loadFlag>\r
</plugin>\r
</debuggerPlugins>\r
</settings>\r
<settings>\r
<name>ICCAVR32</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <archiveVersion>3</archiveVersion>\r
<data>\r
- <version>4</version>\r
+ <version>5</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>1</debug>\r
<option>\r
<name>CCDefines</name>\r
<state>BOARD=EVK1100</state>\r
- <state>IAR_AVR32_PORT</state>\r
</option>\r
<option>\r
<name>CCPreprocFile</name>\r
<name>CCCharIs</name>\r
<state>1</state>\r
</option>\r
- <option>\r
- <name>CCOptSizeSpeed</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptimization</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
<option>\r
<name>CCAllowList</name>\r
<version>0</version>\r
<name>CCLangSelect</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCOptSizeSpeedSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptimizationSlave</name>\r
- <version>0</version>\r
- <state>1</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>CCModuleType</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>1</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<settings>\r
<name>JAVATOC</name>\r
<archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>JavaToCDummy</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
+ <data/>\r
</settings>\r
<settings>\r
<name>CUSTOM</name>\r
</option>\r
<option>\r
<name>FormatVariant</name>\r
- <version>7</version>\r
+ <version>8</version>\r
<state>2</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>XclOverride</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>XclFile</name>\r
- <state>$TOOLKIT_DIR$\config\lnkuc3a0512.xcl</state>\r
+ <state>$PROJ_DIR$\..\..\UTILS\LINKER_SCRIPTS\AT32UC3A\0512\IAR\lnkuc3a0512.xcl</state>\r
</option>\r
<option>\r
<name>XclFileSlave</name>\r
</option>\r
<option>\r
<name>xcProgramEntryLabel</name>\r
- <state>__program_start</state>\r
+ <state>__trampoline</state>\r
</option>\r
<option>\r
<name>DebugInformation</name>\r
</option>\r
<option>\r
<name>AllowExtraOutput</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>GenerateExtraOutput</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>XExtraOutOverride</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>ExtraOutputFile</name>\r
- <state>rtosdemo.a82</state>\r
+ <state>rtosdemo.hex</state>\r
</option>\r
<option>\r
<name>ExtraOutputFormat</name>\r
</option>\r
<option>\r
<name>ExtraFormatVariant</name>\r
- <version>7</version>\r
+ <version>8</version>\r
<state>2</state>\r
</option>\r
<option>\r
<name>xcOverrideProgramEntryLabel</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>xcProgramEntryLabelSelect</name>\r
</settings>\r
<settings>\r
<name>ICCAVR32</name>\r
- <archiveVersion>2</archiveVersion>\r
+ <archiveVersion>3</archiveVersion>\r
<data>\r
- <version>4</version>\r
+ <version>5</version>\r
<wantNonLocal>1</wantNonLocal>\r
<debug>0</debug>\r
<option>\r
<name>CCDefines</name>\r
<state>BOARD=EVK1100</state>\r
- <state>IAR_AVR32_PORT</state>\r
</option>\r
<option>\r
<name>CCPreprocFile</name>\r
<name>CCCharIs</name>\r
<state>1</state>\r
</option>\r
- <option>\r
- <name>CCOptSizeSpeed</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptimization</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
<option>\r
<name>CCAllowList</name>\r
<version>0</version>\r
<name>CCLangSelect</name>\r
<state>0</state>\r
</option>\r
- <option>\r
- <name>CCOptSizeSpeedSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CCOptimizationSlave</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
<option>\r
<name>CCLibConfigHeader</name>\r
<state>1</state>\r
<name>CCModuleType</name>\r
<state>0</state>\r
</option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>3</state>\r
+ </option>\r
</data>\r
</settings>\r
<settings>\r
<settings>\r
<name>JAVATOC</name>\r
<archiveVersion>0</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>0</debug>\r
- <option>\r
- <name>JavaToCDummy</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
+ <data/>\r
</settings>\r
<settings>\r
<name>CUSTOM</name>\r
</option>\r
<option>\r
<name>FormatVariant</name>\r
- <version>7</version>\r
+ <version>8</version>\r
<state>2</state>\r
</option>\r
<option>\r
</option>\r
<option>\r
<name>XclOverride</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>XclFile</name>\r
- <state>$TOOLKIT_DIR$\config\lnkuc3a0512.xcl</state>\r
+ <state>$PROJ_DIR$\..\..\UTILS\LINKER_SCRIPTS\AT32UC3A\0512\IAR\lnkuc3a0512.xcl</state>\r
</option>\r
<option>\r
<name>XclFileSlave</name>\r
</option>\r
<option>\r
<name>xcProgramEntryLabel</name>\r
- <state>__program_start</state>\r
+ <state>__trampoline</state>\r
</option>\r
<option>\r
<name>DebugInformation</name>\r
</option>\r
<option>\r
<name>AllowExtraOutput</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>GenerateExtraOutput</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>XExtraOutOverride</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>ExtraOutputFile</name>\r
- <state>rtosdemo.a82</state>\r
+ <state>rtosdemo.hex</state>\r
</option>\r
<option>\r
<name>ExtraOutputFormat</name>\r
</option>\r
<option>\r
<name>ExtraFormatVariant</name>\r
- <version>7</version>\r
+ <version>8</version>\r
<state>2</state>\r
</option>\r
<option>\r
<name>xcOverrideProgramEntryLabel</name>\r
- <state>0</state>\r
+ <state>1</state>\r
</option>\r
<option>\r
<name>xcProgramEntryLabelSelect</name>\r
<file>\r
<name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\read.c</name>\r
</file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\SERVICES\USB\CLASS\DFU\EXAMPLES\ISP\BOOT\trampoline.s82</name>\r
+ </file>\r
<file>\r
<name>$PROJ_DIR$\..\..\..\..\Source\portable\IAR\AVR32_UC3\write.c</name>\r
</file>\r
--- /dev/null
+# Doxyfile 1.4.7
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = "AVR32 UC3 - FreeRTOS Real Time Kernel"
+PROJECT_NUMBER =
+OUTPUT_DIRECTORY = ../DOC
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = YES
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF =
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = YES
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = YES
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 4
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = YES
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = YES
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = NO
+SHOW_DIRECTORIES = NO
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = YES
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = ./../ ./../../../Source ./../../Common/include ./../../Common/Minimal
+FILE_PATTERNS = *.c \
+ *.h \
+ *.S
+RECURSIVE = YES
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS =
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH = ./../
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = YES
+INLINE_SOURCES = YES
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION = YES
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = YES
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT =
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = YES
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = RTF
+COMPACT_RTF = NO
+RTF_HYPERLINKS = YES
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = YES
+EXPAND_ONLY_PREDEF = YES
+SEARCH_INCLUDES = YES
+INCLUDE_PATH = ../../../../../BOARDS/
+INCLUDE_FILE_PATTERNS =
+PREDEFINED = __GNUC__=4 \
+ __attribute__()= \
+ __AVR32__=1 \
+ __AVR32_UC3A0512__=1 \
+ __AVR32_ABI_COMPILER__ \
+ BOARD=EVK1100
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = NO
+COLLABORATION_GRAPH = NO
+GROUP_GRAPHS = NO
+UML_LOOK = YES
+TEMPLATE_RELATIONS = YES
+INCLUDE_GRAPH = NO
+INCLUDED_BY_GRAPH = NO
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = NO
+DIRECTORY_GRAPH = NO
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 0
+DOT_TRANSPARENT = NO
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
--- /dev/null
+# Hey Emacs, this is a -*- makefile -*-
+
+# Goals available on make command line:
+#
+# [all] Default goal: build the project.
+# clean Clean up the project.
+# rebuild Rebuild the project.
+# ccversion Display CC version information.
+# cppfiles file.i Generate preprocessed files from C source files.
+# asfiles file.x Generate preprocessed assembler files from C and assembler source files.
+# objfiles file.o Generate object files from C and assembler source files.
+# a file.a Archive: create A output file from object files.
+# elf file.elf Link: create ELF output file from object files.
+# lss file.lss Create extended listing from target output file.
+# sym file.sym Create symbol table from target output file.
+# hex file.hex Create Intel HEX image from ELF output file.
+# bin file.bin Create binary image from ELF output file.
+# sizes Display target size information.
+# isp Use ISP instead of JTAGICE mkII when programming.
+# cpuinfo Get CPU information.
+# halt Stop CPU execution.
+# chiperase Perform a JTAG Chip Erase command.
+# erase Perform a flash chip erase.
+# program Program MCU memory from ELF output file.
+# secureflash Protect chip by setting security bit.
+# reset Reset MCU.
+# debug Open a debug connection with the MCU.
+# run Start CPU execution.
+# readregs Read CPU registers.
+# doc Build the documentation.
+# cleandoc Clean up the documentation.
+# rebuilddoc Rebuild the documentation.
+# verbose Display main executed commands.
+
+# Copyright (c) 2007, Atmel Corporation All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation and/
+# or other materials provided with the distribution.
+#
+# 3. The name of ATMEL may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# ENVIRONMENT SETTINGS
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+FirstWord = $(if $(1),$(word 1,$(1)))
+LastWord = $(if $(1),$(word $(words $(1)),$(1)))
+
+MAKE = make
+MAKECFG = config.mk
+TGTTYPE = $(suffix $(TARGET))
+TGTFILE = $(PART)-$(TARGET)
+
+RM = rm -Rf
+
+AR = avr32-ar
+ARFLAGS = rcs
+
+CPP = $(CC) -E
+CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \
+ $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS)
+DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d)
+CPPFILES = $(CSRCS:.c=.i)
+
+CC = avr32-gcc
+CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
+ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x)
+
+AS = avr32-as
+ASFLAGS = $(DEBUG) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
+OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o)
+
+LD = avr32-ld
+LDFLAGS = -march=$(ARCH) -mpart=$(PART) \
+ $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS)
+LOADLIBES =
+LDLIBS = $(LIBS:%=-l%)
+
+OBJDUMP = avr32-objdump
+LSS = $(TGTFILE:$(TGTTYPE)=.lss)
+
+NM = avr32-nm
+SYM = $(TGTFILE:$(TGTTYPE)=.sym)
+
+OBJCOPY = avr32-objcopy
+HEX = $(TGTFILE:$(TGTTYPE)=.hex)
+BIN = $(TGTFILE:$(TGTTYPE)=.bin)
+
+SIZE = avr32-size
+
+SLEEP = sleep
+SLEEPUSB = 9
+
+PROGRAM = avr32program
+
+ISP = batchisp
+ISPFLAGS = -device at32$(PART) -hardware usb -operation
+
+DBGPROXY = avr32gdbproxy
+
+DOCGEN = doxygen
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# MESSAGES
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)'
+MSG_CLEANING = Cleaning project.
+MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'.
+MSG_COMPILING = Compiling \`$<\' to \`$@\'.
+MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'.
+MSG_ARCHIVING = Archiving to \`$@\'.
+MSG_LINKING = Linking to \`$@\'.
+MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'.
+MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'.
+MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'.
+MSG_BINARY_IMAGE = Creating binary image to \`$@\'.
+MSG_GETTING_CPU_INFO = Getting CPU information.
+MSG_HALTING = Stopping CPU execution.
+MSG_ERASING_CHIP = Performing a JTAG Chip Erase command.
+MSG_ERASING = Performing a flash chip erase.
+MSG_PROGRAMMING = Programming MCU memory from \`$(TGTFILE)\'.
+MSG_SECURING_FLASH = Protecting chip by setting security bit.
+MSG_RESETTING = Resetting MCU.
+MSG_DEBUGGING = Opening debug connection with MCU.
+MSG_RUNNING = Starting CPU execution.
+MSG_READING_CPU_REGS = Reading CPU registers.
+MSG_CLEANING_DOC = Cleaning documentation.
+MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'.
+
+
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+# MAKE RULES
+# ** ** ** *** ** ** ** ** ** ** ** ** ** ** **
+
+# Include the make configuration file.
+include $(MAKECFG)
+
+# ** ** TOP-LEVEL RULES ** **
+
+# Default goal: build the project.
+ifeq ($(TGTTYPE),.a)
+.PHONY: all
+all: ccversion a lss sym sizes
+else
+ifeq ($(TGTTYPE),.elf)
+.PHONY: all
+all: ccversion elf lss sym hex bin sizes
+else
+$(error $(ERR_TARGET_TYPE))
+endif
+endif
+
+# Clean up the project.
+.PHONY: clean
+clean:
+ @echo $(MSG_CLEANING)
+ -$(VERBOSE_CMD)$(RM) $(BIN)
+ -$(VERBOSE_CMD)$(RM) $(HEX)
+ -$(VERBOSE_CMD)$(RM) $(SYM)
+ -$(VERBOSE_CMD)$(RM) $(LSS)
+ -$(VERBOSE_CMD)$(RM) $(TGTFILE)
+ -$(VERBOSE_CMD)$(RM) $(OBJFILES)
+ -$(VERBOSE_CMD)$(RM) $(ASFILES)
+ -$(VERBOSE_CMD)$(RM) $(CPPFILES)
+ -$(VERBOSE_CMD)$(RM) $(DPNDFILES)
+ $(VERBOSE_NL)
+
+# Rebuild the project.
+.PHONY: rebuild
+rebuild: clean all
+
+# Display CC version information.
+.PHONY: ccversion
+ccversion:
+ @echo
+ @echo
+ @$(CC) --version
+
+# Generate preprocessed files from C source files.
+.PHONY: cppfiles
+cppfiles: $(CPPFILES)
+
+# Generate preprocessed assembler files from C and assembler source files.
+.PHONY: asfiles
+asfiles: $(ASFILES)
+
+# Generate object files from C and assembler source files.
+.PHONY: objfiles
+objfiles: $(OBJFILES)
+
+ifeq ($(TGTTYPE),.a)
+# Archive: create A output file from object files.
+.PHONY: a
+a: $(TGTFILE)
+else
+ifeq ($(TGTTYPE),.elf)
+# Link: create ELF output file from object files.
+.PHONY: elf
+elf: $(TGTFILE)
+endif
+endif
+
+# Create extended listing from target output file.
+.PHONY: lss
+lss: $(LSS)
+
+# Create symbol table from target output file.
+.PHONY: sym
+sym: $(SYM)
+
+ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+.PHONY: hex
+hex: $(HEX)
+
+# Create binary image from ELF output file.
+.PHONY: bin
+bin: $(BIN)
+
+endif
+
+# Display target size information.
+.PHONY: sizes
+sizes: $(TGTFILE)
+ @echo
+ @echo
+ifeq ($(TGTTYPE),.a)
+ @$(SIZE) -Bxt $<
+else
+ifeq ($(TGTTYPE),.elf)
+ @$(SIZE) -Ax $<
+ @$(SIZE) -Bx $<
+endif
+endif
+ @echo
+ @echo
+
+ifeq ($(TGTTYPE),.elf)
+
+# Use ISP instead of JTAGICE mkII when programming.
+.PHONY: isp
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
+isp: all
+else
+isp:
+ @:
+endif
+
+ifeq ($(findstring isp,$(MAKECMDGOALS)),)
+
+# Get CPU information.
+.PHONY: cpuinfo
+cpuinfo:
+ @echo
+ @echo $(MSG_GETTING_CPU_INFO)
+ $(VERBOSE_CMD)$(PROGRAM) cpuinfo
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Stop CPU execution.
+.PHONY: halt
+halt:
+ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_HALTING)
+ $(VERBOSE_CMD)$(PROGRAM) halt
+ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
+endif
+
+# Perform a JTAG Chip Erase command.
+.PHONY: chiperase
+chiperase:
+ @echo
+ @echo $(MSG_ERASING_CHIP)
+ $(VERBOSE_CMD)$(PROGRAM) chiperase
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(filter chiperase program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
+endif
+
+# Program MCU memory from ELF output file.
+.PHONY: program
+program: all
+ @echo
+ @echo $(MSG_PROGRAMMING)
+ $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TGTFILE)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(PROGRAM) secureflash
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Reset MCU.
+.PHONY: reset
+reset:
+ifeq ($(filter program run,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RESETTING)
+ $(VERBOSE_CMD)$(PROGRAM) reset
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
+endif
+
+# Open a debug connection with the MCU.
+.PHONY: debug
+debug:
+ @echo
+ @echo $(MSG_DEBUGGING)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Start CPU execution.
+.PHONY: run
+run:
+ifeq ($(findstring program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RUNNING)
+ $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
+endif
+
+# Read CPU registers.
+.PHONY: readregs
+readregs:
+ @echo
+ @echo $(MSG_READING_CPU_REGS)
+ $(VERBOSE_CMD)$(PROGRAM) readregs
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+else
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(findstring program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck
+ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase)
+ @echo
+endif
+else
+ @:
+endif
+
+# Program MCU memory from ELF output file.
+.PHONY: program
+program: all
+ @echo
+ @echo $(MSG_PROGRAMMING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TGTFILE) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0))
+ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program)
+ @echo
+endif
+
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)
+ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash)
+ @echo
+endif
+
+# Reset MCU.
+.PHONY: reset
+reset:
+ @:
+
+# Open a debug connection with the MCU.
+.PHONY: debug
+debug:
+ @echo
+ @echo $(MSG_DEBUGGING)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug)
+ @echo
+endif
+
+# Start CPU execution.
+.PHONY: run
+run:
+ifeq ($(filter program secureflash,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RUNNING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0
+ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run)
+ @echo
+endif
+else
+ @:
+endif
+
+endif
+
+endif
+
+# Build the documentation.
+.PHONY: doc
+doc:
+ @echo
+ @echo $(MSG_GENERATING_DOC)
+ $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG))
+ @echo
+
+# Clean up the documentation.
+.PHONY: cleandoc
+cleandoc:
+ @echo $(MSG_CLEANING_DOC)
+ -$(VERBOSE_CMD)$(RM) $(DOC_PATH)
+ $(VERBOSE_NL)
+
+# Rebuild the documentation.
+.PHONY: rebuilddoc
+rebuilddoc: cleandoc doc
+
+# Display main executed commands.
+.PHONY: verbose
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
+verbose: all
+else
+verbose:
+ @:
+endif
+ifneq ($(findstring verbose,$(MAKECMDGOALS)),)
+# Prefix displaying the following command if and only if verbose is a goal.
+VERBOSE_CMD =
+# New line displayed if and only if verbose is a goal.
+VERBOSE_NL = @echo
+else
+VERBOSE_CMD = @
+VERBOSE_NL =
+endif
+
+# ** ** COMPILATION RULES ** **
+
+# Include silently the dependency files.
+-include $(DPNDFILES)
+
+# The dependency files are not built alone but along with first generation files.
+$(DPNDFILES):
+
+# First generation files depend on make files.
+$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG)
+
+ifeq ($(TGTTYPE),.elf)
+# Files resulting from linking depend on linker script.
+$(TGTFILE): $(LINKER_SCRIPT)
+endif
+
+# Preprocess: create preprocessed files from C source files.
+%.i: %.c %.d
+ @echo $(MSG_PREPROCESSING)
+ $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess & compile: create assembler files from C source files.
+%.x: %.c %.d
+ @echo $(MSG_COMPILING)
+ $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess: create preprocessed files from assembler source files.
+%.x: %.S %.d
+ @echo $(MSG_PREPROCESSING)
+ $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess, compile & assemble: create object files from C source files.
+%.o: %.c %.d
+ @echo $(MSG_COMPILING)
+ $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+# Preprocess & assemble: create object files from assembler source files.
+%.o: %.S %.d
+ @echo $(MSG_ASSEMBLING)
+ $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $<
+ @touch $*.d
+ @touch $@
+ $(VERBOSE_NL)
+
+.PRECIOUS: $(OBJFILES)
+ifeq ($(TGTTYPE),.a)
+# Archive: create A output file from object files.
+.SECONDARY: $(TGTFILE)
+$(TGTFILE): $(OBJFILES)
+ @echo $(MSG_ARCHIVING)
+ $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+)
+ $(VERBOSE_NL)
+else
+ifeq ($(TGTTYPE),.elf)
+# Link: create ELF output file from object files.
+.SECONDARY: $(TGTFILE)
+$(TGTFILE): $(OBJFILES)
+ @echo $(MSG_LINKING)
+ $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@
+ $(VERBOSE_NL)
+endif
+endif
+
+# Create extended listing from target output file.
+$(LSS): $(TGTFILE)
+ @echo $(MSG_EXTENDED_LISTING)
+ $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@
+ $(VERBOSE_NL)
+
+# Create symbol table from target output file.
+$(SYM): $(TGTFILE)
+ @echo $(MSG_SYMBOL_TABLE)
+ $(VERBOSE_CMD)$(NM) -n $< > $@
+ $(VERBOSE_NL)
+
+ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+$(HEX): $(TGTFILE)
+ @echo $(MSG_IHEX_IMAGE)
+ $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@
+ $(VERBOSE_NL)
+
+# Create binary image from ELF output file.
+$(BIN): $(TGTFILE)
+ @echo $(MSG_BINARY_IMAGE)
+ $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@
+ $(VERBOSE_NL)
+
+endif
--- /dev/null
+# Hey Emacs, this is a -*- makefile -*-
+
+# The purpose of this file is to define the build configuration variables used
+# by the generic Makefile. See Makefile header for further information.
+
+# Copyright (c) 2007, Atmel Corporation All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation and/
+# or other materials provided with the distribution.
+#
+# 3. The name of ATMEL may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# Base paths
+PRJ_PATH = ../..
+APPS_PATH = $(PRJ_PATH)/APPLICATIONS
+BRDS_PATH = $(PRJ_PATH)/BOARDS
+COMP_PATH = $(PRJ_PATH)/COMPONENTS
+DRVR_PATH = $(PRJ_PATH)/DRIVERS
+SERV_PATH = $(PRJ_PATH)/SERVICES
+UTIL_PATH = $(PRJ_PATH)/UTILS
+
+# CPU architecture: {ap|uc}
+ARCH = uc
+
+# Part: {none|ap7xxx|uc3xxxxx}
+PART = uc3b0256
+
+# Flash memories: [{cfi|internal}@address,size]...
+FLASH = internal@0x80000000,256Kb
+
+# Clock source to use when programming: [{xtal|extclk|int}]
+PROG_CLOCK = xtal
+
+# Device/Platform/Board include path
+PLATFORM_INC_PATH = \
+ $(BRDS_PATH)/
+
+# Target name: {*.a|*.elf}
+TARGET = rtosdemo.elf
+
+# Definitions: [-D name[=definition]...] [-U name...]
+# Things that might be added to DEFS:
+# BOARD Board used: {EVKxxxx}
+# EXT_BOARD Extension board used (if any): {EXTxxxx}
+DEFS = -D BOARD=EVK1101
+
+# Include path
+INC_PATH = \
+ $(UTIL_PATH)/ \
+ $(UTIL_PATH)/PREPROCESSOR/ \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \
+ $(DRVR_PATH)/INTC/ \
+ $(DRVR_PATH)/PM/ \
+ $(DRVR_PATH)/GPIO/ \
+ $(DRVR_PATH)/TC/ \
+ ../../../../Source/portable/GCC/AVR32_UC3/ \
+ ../../../../Source/include/ \
+ ../../../Common/include/ \
+ ../../
+
+# C source files
+CSRCS = \
+ $(BRDS_PATH)/EVK1101/led.c \
+ $(DRVR_PATH)/INTC/intc.c \
+ $(DRVR_PATH)/PM/pm.c \
+ $(DRVR_PATH)/GPIO/gpio.c \
+ $(DRVR_PATH)/TC/tc.c \
+ ../../../../Source/portable/GCC/AVR32_UC3/port.c \
+ ../../../../Source/portable/MemMang/heap_2.c \
+ ../../../../Source/list.c \
+ ../../../../Source/queue.c \
+ ../../../../Source/tasks.c \
+ ../../../Common/Minimal/BlockQ.c \
+ ../../../Common/Minimal/comtest.c \
+ ../../../Common/Minimal/death.c \
+ ../../../Common/Minimal/dynamic.c \
+ ../../../Common/Minimal/flash.c \
+ ../../../Common/Minimal/flop.c \
+ ../../../Common/Minimal/integer.c \
+ ../../../Common/Minimal/PollQ.c \
+ ../../../Common/Minimal/semtest.c \
+ ../../ParTest/ParTest.c \
+ ../../serial/serial.c \
+ ../../main.c
+
+# Assembler source files
+ASSRCS = \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \
+ ../../../../Source/portable/GCC/AVR32_UC3/exception.S
+
+# Library path
+LIB_PATH =
+
+# Libraries to link with the project
+LIBS =
+
+# Linker script file if any
+LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3B/0256/GCC/link_uc3b0256.lds
+
+# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...]
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+WARNINGS = -Wall
+
+# Options for debugging: [-g]...
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+DEBUG = -g
+
+# Options that control optimization: [-O[0|1|2|3|s]]...
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+OPTIMIZATION = -O0 -ffunction-sections -fdata-sections
+
+# Extra flags to use when preprocessing
+CPP_EXTRA_FLAGS =
+
+# Extra flags to use when compiling
+C_EXTRA_FLAGS =
+
+# Extra flags to use when assembling
+AS_EXTRA_FLAGS =
+
+# Extra flags to use when linking
+LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline
+
+# Documentation path
+DOC_PATH = \
+ ../../DOC/
+
+# Documentation configuration file
+DOC_CFG = \
+ ../doxyfile.doxygen
--- /dev/null
+target extended-remote :4711\r
+symbol uc3b0256-rtosdemo.elf\r
+\r
+b _handle_Unrecoverable_Exception\r
+b _handle_TLB_Multiple_Hit\r
+b _handle_Bus_Error_Data_Fetch\r
+b _handle_Bus_Error_Instruction_Fetch\r
+b _handle_NMI\r
+b _handle_Instruction_Address\r
+b _handle_ITLB_Protection\r
+b _handle_Breakpoint\r
+b _handle_Illegal_Opcode\r
+b _handle_Unimplemented_Instruction\r
+b _handle_Privilege_Violation\r
+b _handle_Floating_Point\r
+b _handle_Coprocessor_Absent\r
+b _handle_Data_Address_Read\r
+b _handle_Data_Address_Write\r
+b _handle_DTLB_Protection_Read\r
+b _handle_DTLB_Protection_Write\r
+b _handle_DTLB_Modified\r
+b _handle_ITLB_Miss\r
+b _handle_DTLB_Miss_Read\r
+b _handle_DTLB_Miss_Write\r
+\r
+define current_task\r
+printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName\r
+printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack\r
+end\r
--- /dev/null
+# Doxyfile 1.4.7
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = "AVR32 UC3 - FreeRTOS Real Time Kernel"
+PROJECT_NUMBER =
+OUTPUT_DIRECTORY = ../DOC
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+USE_WINDOWS_ENCODING = YES
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF =
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = YES
+MULTILINE_CPP_IS_BRIEF = NO
+DETAILS_AT_TOP = YES
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 4
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = NO
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = YES
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = NO
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = YES
+CASE_SENSE_NAMES = YES
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = YES
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = NO
+SHOW_DIRECTORIES = NO
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = YES
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = ./../ ./../../../Source ./../../Common/include ./../../Common/Minimal
+FILE_PATTERNS = *.c \
+ *.h \
+ *.S
+RECURSIVE = YES
+EXCLUDE =
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH =
+EXAMPLE_PATTERNS =
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH = ./../
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = YES
+INLINE_SOURCES = YES
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION = YES
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = YES
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT =
+HTML_FILE_EXTENSION = .html
+HTML_HEADER =
+HTML_FOOTER =
+HTML_STYLESHEET =
+HTML_ALIGN_MEMBERS = YES
+GENERATE_HTMLHELP = NO
+CHM_FILE =
+HHC_LOCATION =
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = YES
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = NO
+USE_PDFLATEX = NO
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = RTF
+COMPACT_RTF = NO
+RTF_HYPERLINKS = YES
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_SCHEMA =
+XML_DTD =
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = YES
+EXPAND_ONLY_PREDEF = YES
+SEARCH_INCLUDES = YES
+INCLUDE_PATH = ../../../../../BOARDS/
+INCLUDE_FILE_PATTERNS =
+PREDEFINED = __GNUC__=4 \
+ __attribute__()= \
+ __AVR32__=1 \
+ __AVR32_UC3B0256__=1 \
+ __AVR32_ABI_COMPILER__ \
+ BOARD=EVK1101
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = NO
+COLLABORATION_GRAPH = NO
+GROUP_GRAPHS = NO
+UML_LOOK = YES
+TEMPLATE_RELATIONS = YES
+INCLUDE_GRAPH = NO
+INCLUDED_BY_GRAPH = NO
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = NO
+DIRECTORY_GRAPH = NO
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_WIDTH = 1024
+MAX_DOT_GRAPH_HEIGHT = 1024
+MAX_DOT_GRAPH_DEPTH = 0
+DOT_TRANSPARENT = NO
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
// part.\r
//#define FRCOSC 115200 //!< RCOsc frequency: Hz.\r
\r
-#define FOSC32 32000 //!< Osc32 frequency: Hz.\r
+#define FOSC32 32768 //!< Osc32 frequency: Hz.\r
#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods.\r
\r
#define FOSC0 12000000 //!< Osc0 frequency: Hz.\r
# define USB_VBOF_ACTIVE_LEVEL LOW\r
#endif\r
\r
+//! USB overcurrent detection pin.\r
+#ifdef EVK1100_REVA\r
+# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18\r
+#else\r
+# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33\r
+#endif\r
+\r
//! @}\r
\r
\r
*/\r
//! @{\r
#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18\r
-#define DIP204_PWM_CHANNEL AVR32_PWM_CHID6\r
+#define DIP204_PWM_CHANNEL 6\r
#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN\r
#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION\r
//! @}\r
//! @}\r
\r
\r
-/*! \name SPI Connections of the SD/MMC Connector\r
+/*! \name GPIO and SPI Connections of the SD/MMC Connector\r
*/\r
//! @{\r
+#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02\r
+#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07\r
#define SD_MMC_SPI (&AVR32_SPI1)\r
#define SD_MMC_SPI_CS 1\r
#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "preprocessor.h"\r
#include "compiler.h"\r
#include "evk1100.h"\r
\r
\r
//! Saved state of all LEDs.\r
-static U32 LED_State = (1 << LED_COUNT) - 1;\r
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;\r
\r
\r
U32 LED_Read_Display(void)\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board header file.\r
+ *\r
+ * This file contains definitions and services related to the features of the\r
+ * EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _EVK1101_H_\r
+#define _EVK1101_H_\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+# include "led.h"\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+\r
+/*! \name Oscillator Definitions\r
+ */\r
+//! @{\r
+\r
+// RCOsc has no custom calibration by default. Set the following definition to\r
+// the appropriate value if a custom RCOsc calibration has been applied to your\r
+// part.\r
+//#define FRCOSC 115200 //!< RCOsc frequency: Hz.\r
+\r
+#define FOSC32 32768 //!< Osc32 frequency: Hz.\r
+#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods.\r
+\r
+#define FOSC0 12000000 //!< Osc0 frequency: Hz.\r
+#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods.\r
+\r
+// Osc1 crystal is not mounted by default. Set the following definitions to the\r
+// appropriate values if a custom Osc1 crystal is mounted on your board.\r
+//#define FOSC1 12000000 //!< Osc1 frequency: Hz.\r
+//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods.\r
+\r
+//! @}\r
+\r
+\r
+/*! \name USB Definitions\r
+ */\r
+//! @{\r
+\r
+//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and\r
+//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3bxxxx.h>.\r
+#define USB_ID AVR32_USBB_USB_ID_0_0\r
+\r
+//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and\r
+//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3bxxxx.h>.\r
+#define USB_VBOF AVR32_USBB_USB_VBOF_0_0\r
+\r
+//! Active level of the USB_VBOF output pin.\r
+#define USB_VBOF_ACTIVE_LEVEL LOW\r
+\r
+//! USB overcurrent detection pin.\r
+#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PA20\r
+\r
+//! @}\r
+\r
+\r
+//! Number of LEDs.\r
+#define LED_COUNT 4\r
+\r
+/*! \name GPIO Connections of LEDs\r
+ */\r
+//! @{\r
+#define LED0_GPIO AVR32_PIN_PA07\r
+#define LED1_GPIO AVR32_PIN_PA08\r
+#define LED2_GPIO AVR32_PIN_PA21\r
+#define LED3_GPIO AVR32_PIN_PA22\r
+//! @}\r
+\r
+/*! \name PWM Channels of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM 0\r
+#define LED1_PWM 1\r
+#define LED2_PWM 2\r
+#define LED3_PWM 6\r
+//! @}\r
+\r
+/*! \name PWM Functions of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM_FUNCTION AVR32_PWM_PWM_0_0_FUNCTION\r
+#define LED1_PWM_FUNCTION AVR32_PWM_PWM_1_0_FUNCTION\r
+#define LED2_PWM_FUNCTION AVR32_PWM_PWM_2_0_FUNCTION\r
+#define LED3_PWM_FUNCTION AVR32_PWM_PWM_6_0_FUNCTION\r
+//! @}\r
+\r
+/*! \name Color Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED_MONO0_GREEN LED0\r
+#define LED_MONO1_GREEN LED1\r
+#define LED_MONO2_GREEN LED2\r
+#define LED_MONO3_GREEN LED3\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of Push Buttons\r
+ */\r
+//! @{\r
+#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB02\r
+#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB03\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of the Joystick\r
+ */\r
+//! @{\r
+#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA13\r
+#define GPIO_JOYSTICK_LEFT AVR32_PIN_PB06\r
+#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PB09\r
+#define GPIO_JOYSTICK_UP AVR32_PIN_PB07\r
+#define GPIO_JOYSTICK_DOWN AVR32_PIN_PB08\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Temperature Sensor\r
+ */\r
+//! @{\r
+#define ADC_TEMPERATURE_CHANNEL 7\r
+#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_7_PIN\r
+#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_7_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Light Sensor\r
+ */\r
+//! @{\r
+#define ADC_LIGHT_CHANNEL 6\r
+#define ADC_LIGHT_PIN AVR32_ADC_AD_6_PIN\r
+#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_6_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connections of the Accelerometer\r
+ */\r
+//! @{\r
+#define ADC_ACC_X_CHANNEL 1\r
+#define ADC_ACC_X_PIN AVR32_ADC_AD_1_PIN\r
+#define ADC_ACC_X_FUNCTION AVR32_ADC_AD_1_FUNCTION\r
+#define ADC_ACC_Y_CHANNEL 2\r
+#define ADC_ACC_Y_PIN AVR32_ADC_AD_2_PIN\r
+#define ADC_ACC_Y_FUNCTION AVR32_ADC_AD_2_FUNCTION\r
+#define ADC_ACC_Z_CHANNEL 3\r
+#define ADC_ACC_Z_PIN AVR32_ADC_AD_3_PIN\r
+#define ADC_ACC_Z_FUNCTION AVR32_ADC_AD_3_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name PWM Connections of Audio\r
+ */\r
+//! @{\r
+#define AUDIO_LOW_PWM_CHANNEL 5\r
+#define AUDIO_LOW_PWM_PIN AVR32_PWM_PWM_5_0_PIN\r
+#define AUDIO_LOW_PWM_FUNCTION AVR32_PWM_PWM_5_0_FUNCTION\r
+#define AUDIO_HIGH_PWM_CHANNEL 6\r
+#define AUDIO_HIGH_PWM_PIN AVR32_PWM_PWM_6_1_PIN\r
+#define AUDIO_HIGH_PWM_FUNCTION AVR32_PWM_PWM_6_1_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the AT45DBX Data Flash Memory\r
+ */\r
+//! @{\r
+#define AT45DBX_SPI (&AVR32_SPI)\r
+#define AT45DBX_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN\r
+#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION\r
+#define AT45DBX_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN\r
+#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION\r
+#define AT45DBX_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN\r
+#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION\r
+#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI_NPCS_0_0_PIN\r
+#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI_NPCS_0_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name GPIO and SPI Connections of the SD/MMC Connector\r
+ */\r
+//! @{\r
+#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PB00\r
+#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PB01\r
+#define SD_MMC_SPI (&AVR32_SPI)\r
+#define SD_MMC_SPI_CS 1\r
+#define SD_MMC_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN\r
+#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION\r
+#define SD_MMC_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN\r
+#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION\r
+#define SD_MMC_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN\r
+#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION\r
+#define SD_MMC_SPI_NPCS_PIN AVR32_SPI_NPCS_1_0_PIN\r
+#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI_NPCS_1_0_FUNCTION\r
+//! @}\r
+\r
+\r
+#endif // _EVK1101_H_\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include <avr32/io.h>\r
+#include "preprocessor.h"\r
+#include "compiler.h"\r
+#include "evk1101.h"\r
+#include "led.h"\r
+\r
+\r
+//! Structure describing LED hardware connections.\r
+typedef const struct\r
+{\r
+ struct\r
+ {\r
+ U32 PORT; //!< LED GPIO port.\r
+ U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.\r
+ } GPIO; //!< LED GPIO descriptor.\r
+ struct\r
+ {\r
+ S32 CHANNEL; //!< LED PWM channel (< 0 if N/A).\r
+ S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).\r
+ } PWM; //!< LED PWM descriptor.\r
+} tLED_DESCRIPTOR;\r
+\r
+\r
+//! Hardware descriptors of all LEDs.\r
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =\r
+{\r
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \\r
+ { \\r
+ {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\\r
+ {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \\r
+ },\r
+ MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)\r
+#undef INSERT_LED_DESCRIPTOR\r
+};\r
+\r
+\r
+//! Saved state of all LEDs.\r
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;\r
+\r
+\r
+U32 LED_Read_Display(void)\r
+{\r
+ return LED_State;\r
+}\r
+\r
+\r
+void LED_Display(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ LED_State = leds;\r
+ for (led_descriptor = &LED_DESCRIPTOR[0];\r
+ led_descriptor < LED_DESCRIPTOR + LED_COUNT;\r
+ led_descriptor++)\r
+ {\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Mask(U32 mask)\r
+{\r
+ return Rd_bits(LED_State, mask);\r
+}\r
+\r
+\r
+void LED_Display_Mask(U32 mask, U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ mask &= (1 << LED_COUNT) - 1;\r
+ Wr_bits(LED_State, mask, leds);\r
+ while (mask)\r
+ {\r
+ led_shift = 1 + ctz(mask);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ leds >>= led_shift - 1;\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ mask >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+Bool LED_Test(U32 leds)\r
+{\r
+ return Tst_bits(LED_State, leds);\r
+}\r
+\r
+\r
+void LED_Off(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Clr_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_On(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Set_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_Toggle(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Tgl_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Field(U32 field)\r
+{\r
+ return Rd_bitfield(LED_State, field);\r
+}\r
+\r
+\r
+void LED_Display_Field(U32 field, U32 leds)\r
+{\r
+ LED_Display_Mask(field, leds << ctz(field));\r
+}\r
+\r
+\r
+U8 LED_Get_Intensity(U32 led)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+\r
+ // Check that the argument value is valid.\r
+ led = ctz(led);\r
+ led_descriptor = &LED_DESCRIPTOR[led];\r
+ if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;\r
+\r
+ // Return the duty cycle value if the LED PWM channel is enabled, else 0.\r
+ return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?\r
+ AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;\r
+}\r
+\r
+\r
+void LED_Set_Intensity(U32 leds, U8 intensity)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_pwm_channel_t *led_pwm_channel;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ // For each specified LED...\r
+ for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)\r
+ {\r
+ // Select the next specified LED and check that it has a PWM channel.\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ if (led_descriptor->PWM.CHANNEL < 0) continue;\r
+\r
+ // Initialize or update the LED PWM channel.\r
+ led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];\r
+ if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))\r
+ {\r
+ led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &\r
+ ~(AVR32_PWM_CALG_MASK |\r
+ AVR32_PWM_CPOL_MASK |\r
+ AVR32_PWM_CPD_MASK);\r
+ led_pwm_channel->cprd = 0x000000FF;\r
+ led_pwm_channel->cdty = intensity;\r
+ AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;\r
+ }\r
+ else\r
+ {\r
+ AVR32_PWM.isr;\r
+ while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));\r
+ led_pwm_channel->cupd = intensity;\r
+ }\r
+\r
+ // Switch the LED pin to its PWM function.\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (led_descriptor->PWM.FUNCTION & 0x1)\r
+ {\r
+ led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ if (led_descriptor->PWM.FUNCTION & 0x2)\r
+ {\r
+ led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED0 0x01\r
+#define LED1 0x02\r
+#define LED2 0x04\r
+#define LED3 0x08\r
+//! @}\r
+\r
+\r
+/*! \brief Gets the last state of all LEDs set through the LED API.\r
+ *\r
+ * \return State of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display(void);\r
+\r
+/*! \brief Sets the state of all LEDs.\r
+ *\r
+ * \param leds New state of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of all LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display(U32 leds);\r
+\r
+/*! \brief Gets the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param mask LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Mask(U32 mask);\r
+\r
+/*! \brief Sets the state of the specified LEDs.\r
+ *\r
+ * \param mask LEDs of which to set the state (1 bit per LED).\r
+ *\r
+ * \param leds New state of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Mask(U32 mask, U32 leds);\r
+\r
+/*! \brief Tests the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param leds LEDs of which to test the state (1 bit per LED).\r
+ *\r
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else\r
+ * \c FALSE.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern Bool LED_Test(U32 leds);\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn off (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Off(U32 leds);\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn on (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_On(U32 leds);\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param leds LEDs to toggle (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Toggle(U32 leds);\r
+\r
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through\r
+ * the LED API.\r
+ *\r
+ * \param field LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first\r
+ * specified LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Field(U32 field);\r
+\r
+/*! \brief Sets as a bit-field the state of the specified LEDs.\r
+ *\r
+ * \param field LEDs of which to set the state (1 bit per LED).\r
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with\r
+ * the first specified LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Field(U32 field, U32 leds);\r
+\r
+/*! \brief Gets the intensity of the specified LED.\r
+ *\r
+ * \param led LED of which to get the intensity (1 bit per LED; only the least\r
+ * significant set bit is used).\r
+ *\r
+ * \return Intensity of the specified LED (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channel of the specified LED is supposed to be used only by\r
+ * this module.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U8 LED_Get_Intensity(U32 led);\r
+\r
+/*! \brief Sets the intensity of the specified LEDs.\r
+ *\r
+ * \param leds LEDs of which to set the intensity (1 bit per LED).\r
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channels of the specified LEDs are supposed to be used only\r
+ * by this module.\r
+ *\r
+ * \note The pins of the specified LEDs are set to PWM output mode.\r
+ */\r
+extern void LED_Set_Intensity(U32 leds, U8 intensity);\r
+\r
+\r
+#endif // _LED_H_\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _BOARD_H_\r
#define _BOARD_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__ || __AAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board.\r
+//! @}\r
\r
#if BOARD == EVK1100\r
# include "EVK1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "EVK1101/evk1101.h"\r
#else\r
# error No known AVR32 board defined\r
#endif\r
\r
+#if EXT_BOARD == EXT1102\r
+# include "EXT1102/ext1102.h"\r
+#endif\r
+\r
\r
#ifndef FRCOSC\r
# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.\r
* This file defines a useful set of functions for the GPIO.\r
*\r
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices with a PWM module can be used.\r
+ * - Supported devices: All AVR32 devices with a GPIO module can be used.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#ifndef _GPIO_H_\r
#define _GPIO_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
\r
/*! \name Return Values of the GPIO API\r
\r
/*! \brief Enables a specific module mode for a pin.\r
*\r
- * \param pin The pin number.\r
- * \param function The pin function.\r
+ * \param pin The pin number.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the part\r
+ * number; e.g. x = a0512) for module pins. E.g., to enable a PWM\r
+ * channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM\r
+ * channel 3.\r
+ * \param function The pin function.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the\r
+ * part number; e.g. x = a0512) for module pin functions. E.g.,\r
+ * to enable a PWM channel output, the pin function can be\r
+ * AVR32_PWM_PWM_3_FUNCTION for PWM channel 3.\r
*\r
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
*/\r
\r
/*! \brief Enables the GPIO mode of a pin.\r
*\r
- * \param pin The pin number.\r
+ * \param pin The pin number.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the part\r
+ * number; e.g. x = a0512) for pin definitions. E.g., to enable the\r
+ * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as\r
+ * AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release\r
+ * module pins for GPIO.\r
*/\r
extern void gpio_enable_gpio_pin(unsigned int pin);\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "preprocessor.h"\r
#include "intc.h"\r
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.\r
//! Each line handler table contains a set of pointers to interrupt handlers.\r
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
-static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP];\r
+static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);\r
#undef DECL_INT_LINE_HANDLER_TABLE\r
\r
\r
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)\r
{\r
+ // Determine the group of the IRQ.\r
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;\r
\r
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#include "pm.h"\r
\r
\r
-void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
+/*! \name PM Writable Bit-Field Registers\r
+ */\r
+//! @{\r
+\r
+typedef union\r
{\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
- // Read\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
- // Modify\r
- oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;\r
- // Write\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
-}\r
+ unsigned long mcctrl;\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+} u_avr32_pm_mcctrl_t;\r
\r
+typedef union\r
+{\r
+ unsigned long cksel;\r
+ avr32_pm_cksel_t CKSEL;\r
+} u_avr32_pm_cksel_t;\r
\r
-void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+typedef union\r
+{\r
+ unsigned long pll;\r
+ avr32_pm_pll_t PLL;\r
+} u_avr32_pm_pll_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+} u_avr32_pm_oscctrl0_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+} u_avr32_pm_oscctrl1_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+} u_avr32_pm_oscctrl32_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long ier;\r
+ avr32_pm_ier_t IER;\r
+} u_avr32_pm_ier_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long idr;\r
+ avr32_pm_idr_t IDR;\r
+} u_avr32_pm_idr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long icr;\r
+ avr32_pm_icr_t ICR;\r
+} u_avr32_pm_icr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long gcctrl;\r
+ avr32_pm_gcctrl_t GCCTRL;\r
+} u_avr32_pm_gcctrl_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long rccr;\r
+ avr32_pm_rccr_t RCCR;\r
+} u_avr32_pm_rccr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long bgcr;\r
+ avr32_pm_bgcr_t BGCR;\r
+} u_avr32_pm_bgcr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long vregcr;\r
+ avr32_pm_vregcr_t VREGCR;\r
+} u_avr32_pm_vregcr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long bod;\r
+ avr32_pm_bod_t BOD;\r
+} u_avr32_pm_bod_t;\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Sets the mode of the oscillator 0.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).\r
+ */\r
+static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
// Read\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
// Modify\r
- oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
- AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;\r
+ u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;\r
// Write\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
+ pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
}\r
\r
\r
-void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
+ pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);\r
+}\r
\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
- // Modify\r
- mcctrl.MCCTRL.osc0en = 1;\r
- oscctrl0.OSCCTRL0.startup = startup;\r
- // Write back\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
- pm->mcctrl = mcctrl.mcctrl;\r
\r
- while(!pm->ISR.osc0rdy); //For osc output valid\r
+void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+{\r
+ pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);\r
}\r
\r
\r
-void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
+ pm_enable_clk0_no_wait(pm, startup);\r
+ pm_wait_for_clk0_ready(pm);\r
+}\r
\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
\r
- // Modify\r
- mcctrl.MCCTRL.osc0en = 0;\r
-\r
- // Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
+void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+{\r
+ pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;\r
}\r
\r
\r
void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
-\r
// Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
// Modify\r
- mcctrl.MCCTRL.osc0en = 1;\r
- oscctrl0.OSCCTRL0.startup=startup;\r
+ u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;\r
// Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
+ pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
+\r
+ pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;\r
}\r
\r
\r
void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.osc0rdy);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));\r
}\r
\r
\r
-void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
+/*! \brief Sets the mode of the oscillator 1.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).\r
+ */\r
+static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
// Read\r
- oscctrl1.oscctrl1= pm->oscctrl1;\r
+ u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
// Modify\r
- oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;\r
+ u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;\r
// Write\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
}\r
\r
\r
-void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
+void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
- // Read\r
- oscctrl1.oscctrl1= pm->oscctrl1;\r
- // Modify\r
- oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
- AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;\r
- // Write\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);\r
}\r
\r
\r
-void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
-\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl1.oscctrl1 = pm->oscctrl1;\r
+ pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);\r
+}\r
\r
- mcctrl.MCCTRL.osc1en = 1;\r
- oscctrl1.OSCCTRL1.startup=startup;\r
- // Write back\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
- pm->mcctrl = mcctrl.mcctrl;\r
\r
- while(!pm->ISR.osc1rdy);\r
+void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ pm_enable_clk1_no_wait(pm, startup);\r
+ pm_wait_for_clk1_ready(pm);\r
}\r
\r
\r
void pm_disable_clk1(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
+ pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;\r
+}\r
\r
\r
+void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
// Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
-\r
+ u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
// Modify\r
- mcctrl.MCCTRL.osc1en = 0;\r
-\r
+ u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;\r
// Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
+ pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
+\r
+ pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;\r
}\r
\r
\r
-void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
-\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl1.oscctrl1 = pm->oscctrl1;\r
-\r
- mcctrl.MCCTRL.osc1en = 1;\r
- oscctrl1.OSCCTRL1.startup=startup;\r
- // Write back\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
- pm->mcctrl = mcctrl.mcctrl;\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));\r
}\r
\r
\r
-void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
+/*! \brief Sets the mode of the 32-kHz oscillator.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).\r
+ */\r
+static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- while(!pm->ISR.osc1rdy);\r
+ // Read\r
+ u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
+ // Modify\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;\r
+ // Write\r
+ pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
}\r
\r
\r
void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } u_ctrl;\r
- u_ctrl.oscctrl32 = pm->oscctrl32;\r
- u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;\r
- pm->oscctrl32 = u_ctrl.oscctrl32;\r
+ pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);\r
}\r
\r
\r
void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } u_ctrl;\r
- u_ctrl.oscctrl32 = pm->oscctrl32;\r
- u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;\r
- pm->oscctrl32 = u_ctrl.oscctrl32;\r
+ pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);\r
}\r
\r
\r
void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
- // Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
- // Modify\r
- oscctrl32.OSCCTRL32.osc32en = 1;\r
- oscctrl32.OSCCTRL32.startup=startup;\r
- // Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
-\r
- while(!pm->ISR.osc32rdy);\r
+ pm_enable_clk32_no_wait(pm, startup);\r
+ pm_wait_for_clk32_ready(pm);\r
}\r
\r
\r
void pm_disable_clk32(volatile avr32_pm_t *pm)\r
{\r
- // To get rid of a GCC bug\r
- // This makes C code longer, but not ASM\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
- // Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
- // Modify\r
- oscctrl32.OSCCTRL32.osc32en = 0;\r
- // Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
+ pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;\r
}\r
\r
\r
void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
// Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
+ u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
// Modify\r
- oscctrl32.OSCCTRL32.osc32en = 1;\r
- oscctrl32.OSCCTRL32.startup=startup;\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;\r
// Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
+ pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
}\r
\r
\r
void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)\r
{\r
- // To get rid of a GCC bug\r
- // This makes C code longer, but not ASM\r
-\r
- while(!pm->ISR.osc32rdy);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));\r
}\r
\r
\r
unsigned int hsbdiv,\r
unsigned int hsbsel)\r
{\r
- // Force the compiler to generate only one 32 bits access\r
- union {\r
- avr32_pm_cksel_t selval ;\r
- unsigned long uword32;\r
- } cksel;\r
-\r
- cksel.uword32 = 0;\r
+ u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};\r
\r
- cksel.selval.cpudiv = hsbdiv;\r
- cksel.selval.cpusel = hsbsel;\r
- cksel.selval.hsbdiv = hsbdiv;\r
- cksel.selval.hsbsel = hsbsel;\r
- cksel.selval.pbbdiv = pbbdiv;\r
- cksel.selval.pbbsel = pbbsel;\r
- cksel.selval.pbadiv = pbadiv;\r
- cksel.selval.pbasel = pbasel;\r
+ u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;\r
+ u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;\r
+ u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;\r
+ u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;\r
+ u_avr32_pm_cksel.CKSEL.pbasel = pbasel;\r
+ u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;\r
+ u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;\r
+ u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;\r
\r
- pm->cksel = cksel.uword32;\r
+ pm->cksel = u_avr32_pm_cksel.cksel;\r
\r
// Wait for ckrdy bit and then clear it\r
- while(!(pm->ISR.ckrdy));\r
-\r
- return;\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));\r
}\r
\r
\r
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)\r
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1\r
unsigned int diven,\r
- unsigned int div) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
+ unsigned int div)\r
+{\r
+ u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};\r
\r
- u_gc.GCCTRL.oscsel = pll_osc;\r
- u_gc.GCCTRL.pllsel = osc_or_pll;\r
- u_gc.GCCTRL.diven = diven;\r
- u_gc.GCCTRL.div = div;\r
- u_gc.GCCTRL.cen = 0; // Disable GC first\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;\r
+ u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;\r
+ u_avr32_pm_gcctrl.GCCTRL.diven = diven;\r
+ u_avr32_pm_gcctrl.GCCTRL.div = div;\r
+\r
+ pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;\r
}\r
\r
\r
void pm_gc_enable(volatile avr32_pm_t *pm,\r
- unsigned int gc) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
- u_gc.gcctrl = pm->gcctrl[gc];\r
- u_gc.GCCTRL.cen = 1;\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ unsigned int gc)\r
+{\r
+ pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;\r
}\r
\r
\r
void pm_gc_disable(volatile avr32_pm_t *pm,\r
- unsigned int gc) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
- u_gc.gcctrl = pm->gcctrl[gc];\r
- u_gc.GCCTRL.cen = 0;\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ unsigned int gc)\r
+{\r
+ pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;\r
}\r
\r
\r
unsigned int mul,\r
unsigned int div,\r
unsigned int osc,\r
- unsigned int lockcount) {\r
-\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll=0;\r
-\r
- u_pll.PLL.pllmul = mul;\r
- u_pll.PLL.plldiv = div;\r
- u_pll.PLL.pllosc = osc;\r
- u_pll.PLL.pllcount = lockcount;\r
-\r
- u_pll.PLL.pllopt = 0;\r
+ unsigned int lockcount)\r
+{\r
+ u_avr32_pm_pll_t u_avr32_pm_pll = {0};\r
\r
- u_pll.PLL.plltest = 0;\r
+ u_avr32_pm_pll.PLL.pllosc = osc;\r
+ u_avr32_pm_pll.PLL.plldiv = div;\r
+ u_avr32_pm_pll.PLL.pllmul = mul;\r
+ u_avr32_pm_pll.PLL.pllcount = lockcount;\r
\r
- (pm->pll)[pll] = u_pll.pll;\r
+ pm->pll[pll] = u_avr32_pm_pll.pll;\r
}\r
\r
\r
unsigned int pll,\r
unsigned int pll_freq,\r
unsigned int pll_div2,\r
- unsigned int pll_wbwdisable) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll_wbwdisable)\r
+{\r
+ u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};\r
+ u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);\r
+ pm->pll[pll] = u_avr32_pm_pll.pll;\r
}\r
\r
\r
unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- return (pm->PLL)[pll].pllopt;\r
+ unsigned int pll)\r
+{\r
+ return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;\r
}\r
\r
\r
void pm_pll_enable(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllen = 1;\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll)\r
+{\r
+ pm->pll[pll] |= AVR32_PM_PLLEN_MASK;\r
}\r
\r
\r
void pm_pll_disable(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllen = 0;\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll)\r
+{\r
+ pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;\r
}\r
\r
\r
void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.lock0);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));\r
\r
// Bypass the lock signal of the PLL\r
pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;\r
\r
void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.lock1);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));\r
\r
// Bypass the lock signal of the PLL\r
pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;\r
\r
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
// Read\r
- mcctrl.mcctrl = pm->mcctrl;\r
+ u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};\r
// Modify\r
- mcctrl.MCCTRL.mcsel = clock;\r
- // Write Back\r
- pm->MCCTRL.mcsel = mcctrl.mcctrl;\r
+ u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;\r
+ // Write back\r
+ pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;\r
}\r
\r
\r
}\r
\r
\r
-void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long ier ;\r
- avr32_pm_ier_t IER ;\r
- } u_ier;\r
- u_ier.ier = 0;\r
- u_ier.IER.boddet = 1;\r
-\r
- pm->ier = u_ier.ier;\r
+void pm_bod_enable_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->ier = AVR32_PM_IER_BODDET_MASK;\r
}\r
\r
\r
-void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long idr ;\r
- avr32_pm_idr_t IDR ;\r
- } u_idr;\r
- u_idr.idr = 0;\r
- u_idr.IDR.boddet = 1;\r
-\r
- pm->idr = u_idr.idr;\r
+void pm_bod_disable_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->idr = AVR32_PM_IDR_BODDET_MASK;\r
}\r
\r
\r
-void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long icr ;\r
- avr32_pm_idr_t ICR ;\r
- } u_icr;\r
- u_icr.icr = 0;\r
- u_icr.ICR.boddet = 1;\r
-\r
- pm->icr = u_icr.icr;\r
+void pm_bod_clear_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->icr = AVR32_PM_ICR_BODDET_MASK;\r
}\r
\r
\r
-unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {\r
-\r
- return pm->ISR.boddet;\r
+unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)\r
+{\r
+ return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);\r
}\r
\r
\r
-unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {\r
-\r
- return pm->IMR.boddet;\r
+unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)\r
+{\r
+ return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);\r
}\r
\r
\r
-unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {\r
- union {\r
- unsigned long bod ;\r
- avr32_pm_bod_t BOD ;\r
- } u_bod;\r
-\r
- u_bod.bod = pm->bod;\r
-\r
- return (unsigned long) u_bod.BOD.level;\r
-\r
+unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)\r
+{\r
+ return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;\r
}\r
\r
\r
-void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {\r
- (pm->gplp)[gplp] = value;\r
-\r
+void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value)\r
+{\r
+ pm->gplp[gplp] = value;\r
}\r
\r
\r
-unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {\r
-\r
- return (pm->gplp)[gplp];\r
+unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp)\r
+{\r
+ return pm->gplp[gplp];\r
}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#ifndef _PM_H_\r
#define _PM_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-# include <avr32/uc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "preprocessor.h"\r
\r
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}\r
\r
\r
+/*! \brief Gets the MCU reset cause.\r
+ *\r
+ * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).\r
+ *\r
+ * \return The MCU reset cause which can be masked with the\r
+ * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)\r
+{\r
+ return pm->rcause;\r
+}\r
+\r
+\r
/*!\r
* \brief This function will enable the external clock mode of the oscillator 0.\r
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "tc.h"\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _TC_H_\r
#define _TC_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
\r
//! TC driver functions return value in case of invalid argument(s).\r
-#define TC_INVALID_ARGUMENT -1\r
+#define TC_INVALID_ARGUMENT (-1)\r
\r
//! Number of timer/counter channels.\r
#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a\r
* wanted baudrate as possible.\r
*\r
+ * \todo manage the FP fractal part to avoid big errors\r
+ *\r
* Baudrate calculation:\r
* \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or\r
- * \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling.\r
+ * \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling or\r
+ * \f$ baudrate = \frac{Selected Clock}{CD} \f$ with SYNC bit set to allow high speed.\r
*\r
* \param usart Base address of the USART instance.\r
* \param baudrate Wanted baudrate.\r
// Baudrate calculation.\r
if (baudrate < pba_hz / 16)\r
{\r
- // Use 16x oversampling.\r
- usart->mr &=~ AVR32_USART_MR_OVER_MASK;\r
- cd = pba_hz / (16 * baudrate);\r
+ // Use 16x oversampling, clear SYNC bit.\r
+ usart->mr &=~ (AVR32_USART_MR_OVER_MASK | AVR32_USART_MR_SYNC_MASK);\r
+ cd = (pba_hz + 8 * baudrate) / (16 * baudrate); \r
\r
if ((cd >65535)) return USART_INVALID_INPUT;\r
}\r
- else\r
+ else if (baudrate < pba_hz / 8)\r
{\r
// Use 8x oversampling.\r
usart->mr |= AVR32_USART_MR_OVER_MASK;\r
- cd = pba_hz / (8 * baudrate);\r
+ // clear SYNC bit\r
+ usart->mr &=~ AVR32_USART_MR_SYNC_MASK;\r
+ \r
+ cd = (pba_hz + 4 * baudrate) / (8 * baudrate);\r
\r
if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT;\r
}\r
+ else\r
+ {\r
+ // set SYNC to 1 \r
+ usart->mr |= AVR32_USART_MR_SYNC_MASK;\r
+ // use PBA/BaudRate\r
+ cd = (pba_hz / baudrate); \r
+ }\r
usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;\r
\r
return USART_SUCCESS;\r
\r
return USART_SUCCESS;\r
}\r
-\r
-\r
//! @}\r
\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _USART_H_\r
#define _USART_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
\r
\r
#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking.\r
//! @}\r
\r
+\r
/*! \name Channel Modes\r
*/\r
//! @{\r
int bit_order;\r
} iso7816_options_t;\r
\r
+//! Input parameters when initializing ISO7816 modes.\r
+typedef struct\r
+{\r
+ //! Set the frequency of the SPI clock.\r
+ unsigned long baudrate;\r
+\r
+ //! Number of bits to transmit as a character (5 to 9).\r
+ unsigned char charlength;\r
+\r
+ //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,\r
+ //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.\r
+ unsigned char channelmode; \r
+ \r
+ //! Which SPI mode to use when transmitting.\r
+ unsigned char spimode;\r
+} usart_spi_options_t;\r
+ \r
+ \r
+\r
+\r
\r
//------------------------------------------------------------------------------\r
/*! \name Initialization Functions\r
*/\r
extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz);\r
\r
+/*! \brief Sets up the USART to use the SPI mode as master.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
+\r
+/*! \brief Sets up the USART to use the SPI mode as slave.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
//! @}\r
\r
+//------------------------------------------------------------------------------\r
+/*! \brief Selects slave chip.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return Status.\r
+ * \retval USART_SUCCESS Success.\r
+ */\r
+extern int usart_spi_selectChip(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Unselects slave chip.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return Status.\r
+ * \retval USART_SUCCESS Success.\r
+ * \retval USART_FAILURE Time out.\r
+ */\r
+extern int usart_spi_unselectChip(volatile avr32_usart_t *usart);\r
\r
//------------------------------------------------------------------------------\r
/*! \name Read and Reset Error Status Bits\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* \brief FreeRTOS demonstration for AVR32 UC3.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
- *****************************************************************************/\r
+ ******************************************************************************/\r
\r
/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
*\r
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 8 )\r
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024*30 ) )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024*25 ) )\r
#define configMAX_TASK_NAME_LEN ( 16 )\r
#define configUSE_TRACE_FACILITY 0\r
#define configUSE_16_BIT_TICKS 0\r
/* Set the following definitions to 1 to include the API function, or zero\r
to exclude the API function. */\r
\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 0\r
\r
/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter\r
for the tick generation. Timer Counter will generate an accurate Tick;\r
otherwise the CPU will generate a tick but with time drift.\r
- configTICK_TC_CHANNEL is the TC channel.*/\r
+ configTICK_TC_CHANNEL is the TC channel. */\r
#define configTICK_USE_TC 1\r
#define configTICK_TC_CHANNEL 2\r
\r
+/* configHEAP_INIT is a boolean indicating whether to initialize the heap with\r
+ 0xA5 in order to be able to determine the maximal heap consumption. */\r
+#define configHEAP_INIT 0\r
+\r
/* Debug trace configuration.\r
configDBG is a boolean indicating whether to activate the debug trace. */\r
+#if BOARD == EVK1100\r
#define configDBG 1\r
#define configDBG_USART (&AVR32_USART1)\r
#define configDBG_USART_RX_PIN AVR32_USART1_RXD_0_PIN\r
#define configDBG_USART_TX_PIN AVR32_USART1_TXD_0_PIN\r
#define configDBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_FUNCTION\r
#define configDBG_USART_BAUDRATE 57600\r
+#define serialPORT_USART (&AVR32_USART0)\r
+#define serialPORT_USART_RX_PIN AVR32_USART0_RXD_0_PIN\r
+#define serialPORT_USART_RX_FUNCTION AVR32_USART0_RXD_0_FUNCTION\r
+#define serialPORT_USART_TX_PIN AVR32_USART0_TXD_0_PIN\r
+#define serialPORT_USART_TX_FUNCTION AVR32_USART0_TXD_0_FUNCTION\r
+#define serialPORT_USART_IRQ AVR32_USART0_IRQ\r
+#define serialPORT_USART_BAUDRATE 57600\r
+#elif BOARD == EVK1101\r
+#define configDBG 1\r
+#define configDBG_USART (&AVR32_USART1)\r
+#define configDBG_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN\r
+#define configDBG_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION\r
+#define configDBG_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN\r
+#define configDBG_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION\r
+#define configDBG_USART_BAUDRATE 57600\r
+#define serialPORT_USART (&AVR32_USART1)\r
+#define serialPORT_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN\r
+#define serialPORT_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION\r
+#define serialPORT_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN\r
+#define serialPORT_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION\r
+#define serialPORT_USART_IRQ AVR32_USART1_IRQ\r
+#define serialPORT_USART_BAUDRATE 57600\r
+#endif\r
+\r
\r
#endif /* FREERTOS_CONFIG_H */\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
\r
\r
-#if __GNUC__\r
- #include <avr32/io.h>\r
-#elif __ICCAVR32__\r
- #include <avr32/iouc3a0512.h>\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "FreeRTOS.h"\r
#include "task.h"\r
#include "partest.h"\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AVR32 UC3 ISP trampoline.\r
+ *\r
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII\r
+ * without having to take the general-purpose fuses into consideration, add this\r
+ * file to the project and change the program entry point to _trampoline.\r
+ *\r
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32UC devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "../conf_isp.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+ // This must be linked @ 0x80000000 if it is to be run upon reset.\r
+ .section .reset, "ax", @progbits\r
+\r
+\r
+ .global _trampoline\r
+ .type _trampoline, @function\r
+_trampoline:\r
+ // Jump to program start.\r
+ rjmp program_start\r
+\r
+ .org PROGRAM_START_OFFSET\r
+program_start:\r
+ // Jump to the C runtime startup routine.\r
+ lda.w pc, _stext\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AVR32 UC3 ISP trampoline.\r
+ *\r
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII\r
+ * without having to take the general-purpose fuses into consideration, add this\r
+ * file to the project and change the program entry point to __trampoline.\r
+ *\r
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: All AVR32UC devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "../conf_isp.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+ RSEG SSTACK:DATA:NOROOT(2)\r
+\r
+\r
+ // This must be linked @ 0x80000000 if it is to be run upon reset.\r
+ RSEG RESET:CODE:NOROOT(1)\r
+\r
+\r
+ PUBLIC __trampoline\r
+__trampoline:\r
+ // Jump to program start.\r
+ rjmp program_start\r
+\r
+ ORG PROGRAM_START_OFFSET\r
+program_start:\r
+ // Initialize the stack pointer.\r
+ lddpc sp, ??SPS\r
+ // Jump to the C runtime startup routine.\r
+ lddpc pc, ??cmain\r
+\r
+\r
+// Constant data area.\r
+\r
+ ALIGN 2\r
+\r
+??SPS:\r
+ DC32 SFE(SSTACK) & ~3\r
+\r
+ EXTERN ?main\r
+??cmain:\r
+ DC32 ?main\r
+\r
+\r
+ END\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file ******************************************************************\r
+ *\r
+ * \brief ISP configuration file.\r
+ *\r
+ * This file contains the possible external configuration of the ISP.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a USB module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ***************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _CONF_ISP_H_\r
+#define _CONF_ISP_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+\r
+//_____ D E F I N I T I O N S ______________________________________________\r
+\r
+#define PRODUCT_MANUFACTURER_ID 0x58\r
+#define PRODUCT_FAMILY_ID 0x20\r
+\r
+#define ISP_VERSION 0x00\r
+#define ISP_ID0 0x00\r
+#define ISP_ID1 0x00\r
+\r
+#define ISP_GPFB_FORCE 31\r
+#define ISP_GPFB_FORCE_MASK 0x80000000\r
+#define ISP_GPFB_FORCE_OFFSET 31\r
+#define ISP_GPFB_FORCE_SIZE 1\r
+\r
+#define ISP_GPFB_IO_COND_EN 30\r
+#define ISP_GPFB_IO_COND_EN_MASK 0x40000000\r
+#define ISP_GPFB_IO_COND_EN_OFFSET 30\r
+#define ISP_GPFB_IO_COND_EN_SIZE 1\r
+\r
+#define ISP_GPFB_BOD_EN 29\r
+#define ISP_GPFB_BOD_EN_MASK 0x20000000\r
+#define ISP_GPFB_BOD_EN_OFFSET 29\r
+#define ISP_GPFB_BOD_EN_SIZE 1\r
+\r
+#define ISP_CFG (*(volatile U32 *)ISP_CFG_ADDRESS)\r
+#define ISP_CFG_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)\r
+#define ISP_CFG_OFFSET 0x000001FC\r
+#define ISP_CFG_SIZE 4\r
+\r
+#define ISP_CFG_BOOT_KEY 17\r
+#define ISP_CFG_BOOT_KEY_MASK 0xFFFE0000\r
+#define ISP_CFG_BOOT_KEY_OFFSET 17\r
+#define ISP_CFG_BOOT_KEY_SIZE 15\r
+#define ISP_CFG_BOOT_KEY_VALUE 0x494F\r
+\r
+#define ISP_CFG_IO_COND_LEVEL 16\r
+#define ISP_CFG_IO_COND_LEVEL_MASK 0x00010000\r
+#define ISP_CFG_IO_COND_LEVEL_OFFSET 16\r
+#define ISP_CFG_IO_COND_LEVEL_SIZE 1\r
+\r
+#define ISP_CFG_IO_COND_PIN 8\r
+#define ISP_CFG_IO_COND_PIN_MASK 0x0000FF00\r
+#define ISP_CFG_IO_COND_PIN_OFFSET 8\r
+#define ISP_CFG_IO_COND_PIN_SIZE 8\r
+\r
+#define ISP_CFG_CRC8 0\r
+#define ISP_CFG_CRC8_MASK 0x000000FF\r
+#define ISP_CFG_CRC8_OFFSET 0\r
+#define ISP_CFG_CRC8_SIZE 8\r
+#define ISP_CFG_CRC8_POLYNOMIAL 0x107\r
+\r
+#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS)\r
+#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)\r
+#define ISP_KEY_OFFSET 0x00000000\r
+#define ISP_KEY_SIZE 4\r
+#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')\r
+\r
+#ifndef ISP_OSC\r
+ #define ISP_OSC 0\r
+#endif\r
+\r
+#define DFU_FRAME_LENGTH 2048\r
+\r
+#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)\r
+#define PROGRAM_START_OFFSET 0x00002000\r
+\r
+\r
+#endif // _CONF_ISP_H_\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
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+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
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+}
+
+SECTIONS
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+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
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+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
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+ PROVIDE (__fini_array_start = .);
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+ KEEP (*(.dtors))
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+ KEEP (*(.gnu.linkonce.d.*personality*))
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+ .bss :
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+ *(.bss .bss.* .gnu.linkonce.b.*)
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+ /* Align here to ensure that the .bss section occupies space up to
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+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
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+ .heap :
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+ . = (__heap_size__ == __max_heap_size__) ?
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+ /* GNU DWARF 1 extensions */
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+ /* SGI/MIPS DWARF 2 extensions */
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+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0512 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0512
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
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+ __max_heap_size__ = -1;
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+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
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+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
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+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0512:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8007FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0512\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
+ .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+ .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+ .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+ .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+ .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+ .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH
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+ .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+ .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+ .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
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+ .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH
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+ .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
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+ .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .plt : { *(.plt) } >FLASH AT>FLASH :FLASH
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
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+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
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+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
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+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
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+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
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+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
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+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
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+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
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+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
+ {
+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
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+ } >INTRAM AT>INTRAM :INTRAM
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+ /* Stabs debugging sections. */
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
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+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
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+ . = ORIGIN(INTRAM);
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+ /* Exception handling */
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+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
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+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
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+ .ctors :
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+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
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+ } >INTRAM AT>FLASH :FLASH
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+ KEEP (*crtbegin*.o(.dtors))
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+ KEEP (*(.dtors))
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+ PROVIDE (edata = .);
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+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
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+ .heap :
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+ . = (__heap_size__ == __max_heap_size__) ?
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1512 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1512
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
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+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1512:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8007FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1512\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B0128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B0128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
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+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
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+}
+
+SECTIONS
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+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
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+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
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+ .data :
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+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
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+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
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+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
+ {
+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
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+ } >INTRAM AT>INTRAM :INTRAM
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+ /* Stabs debugging sections. */
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+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
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+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
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+ /* GNU DWARF 1 extensions */
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+ /* DWARF 1.1 and DWARF 2 */
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+ /* DWARF 2 */
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+ /* SGI/MIPS DWARF 2 extensions */
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B0128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B0128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B0128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B0256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B0256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
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+ /* If this heap size is selected, all the INTRAM space from the end of the
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+ __max_heap_size__ = -1;
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+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
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+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
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+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
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+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B0256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B0256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B0256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B064 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B064
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
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+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
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+ .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
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+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .plt : { *(.plt) } >FLASH AT>FLASH :FLASH
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
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+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
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+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
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+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
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+ is in. */
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+ /* We don't want to include the .ctor section from
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+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
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+ KEEP (*crtbegin*.o(.dtors))
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+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
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+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
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+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
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+ . = (__heap_size__ == __max_heap_size__) ?
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+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B064 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B064:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00003FFF SRAM RAM\r
+ * 0x80000000 0x8000FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B064\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8000FFFF\r
+-Z@(CODE)EV100=80004100-8000FFFF\r
+-P(CODE)EVSEG=80004000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8000FFFF\r
+-P(CONST)DATA32_C=80000000-8000FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00003FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B1128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B1128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
+ KEEP (*(.init))
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+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
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+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
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+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
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+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
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+ .ctors :
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+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
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+ KEEP (*crtbegin*.o(.dtors))
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+ KEEP (*(.dtors))
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+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
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+ .heap :
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+ . = (__heap_size__ == __max_heap_size__) ?
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+ /* SGI/MIPS DWARF 2 extensions */
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
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+ *(.stack)
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+ _estack = .;
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+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B1128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B1128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B1128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B1256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B1256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
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+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
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+ /* Use a default stack size if stack size was not defined. */
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+
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+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
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+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B1256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B1256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B1256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B164 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B164
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
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+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
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+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ .ctors :
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+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
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+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+ .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
+ .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH
+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
+ {
+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+ __heap_size__;
+ } >INTRAM AT>INTRAM :INTRAM
+ __heap_end__ = .;
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B164 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B164:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00003FFF SRAM RAM\r
+ * 0x80000000 0x8000FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B164\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8000FFFF\r
+-Z@(CODE)EV100=80004100-8000FFFF\r
+-P(CODE)EVSEG=80004000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8000FFFF\r
+-P(CONST)DATA32_C=80000000-8000FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00003FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
/*! \brief Stringize.\r
*\r
- * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
*\r
- * May be used only within macros with the token passed as an argument if the token is #defined.\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
*\r
- * For example, writing STRINGZ(PIN) within a macro #defined by PIN_NAME(PIN)\r
- * and invoked as PIN_NAME(PIN0) with PIN0 #defined as A0 is equivalent to\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
* writing "A0".\r
*/\r
#define STRINGZ(x) #x\r
\r
/*! \brief Absolute stringize.\r
*\r
- * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
*\r
- * No restriction of use if the token is #defined.\r
+ * No restriction of use if the token is \#defined.\r
*\r
- * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 #defined as A0 is\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
* equivalent to writing "A0".\r
*/\r
#define ASTRINGZ(x) STRINGZ(x)\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
/*! \name Token Paste\r
*\r
- * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
*\r
- * May be used only within macros with the tokens passed as arguments if the tokens are #defined.\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
*\r
- * For example, writing TPASTE2(U, WIDTH) within a macro #defined by\r
- * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH #defined as 32 is\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
* equivalent to writing U32.\r
*/\r
//! @{\r
\r
/*! \name Absolute Token Paste\r
*\r
- * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
*\r
- * No restriction of use if the tokens are #defined.\r
+ * No restriction of use if the tokens are \#defined.\r
*\r
- * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH #defined\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
* as 32 is equivalent to writing U32.\r
*/\r
//! @{\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _COMPILER_H_\r
#define _COMPILER_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__ || __AAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-# include <avr32/uc3a0512.h>\r
-# if __ICCAVR32__\r
-# include <intrinsics.h>\r
-# endif\r
-#else\r
-# error Unknown compiler\r
+#include <avr32/io.h>\r
+#if __ICCAVR32__\r
+# include <intrinsics.h>\r
#endif\r
-\r
#include "preprocessor.h"\r
\r
\r
#include <stddef.h>\r
#include <stdlib.h>\r
\r
+\r
+#if __ICCAVR32__\r
+\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+\r
/*! \name Usual Types\r
*/\r
//! @{\r
typedef double F64; //!< 64-bit floating-point number.\r
//! @}\r
\r
+\r
/*! \name Status Types\r
*/\r
//! @{\r
typedef U8 Status_t; //!< 8-bit-coded status.\r
//! @}\r
\r
-#if __ICCAVR32__\r
-\r
-/*! \name Compiler Keywords\r
- *\r
- * Translation of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
- */\r
-//! @{\r
-#define __asm__ asm\r
-#define __inline__ inline\r
-#define __volatile__\r
-//! @}\r
-\r
-#endif\r
\r
/*! \name Aliasing Aggregate Types\r
*/\r
\r
#endif // __AVR32_ABI_COMPILER__\r
\r
+\r
//_____ M A C R O S ________________________________________________________\r
\r
/*! \name Usual Constants\r
#define SET 1\r
//! @}\r
\r
+\r
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
\r
-/*! \name Bit-Field Handling Macros\r
+/*! \name Bit-Field Handling\r
*/\r
//! @{\r
\r
\r
//! @}\r
\r
+\r
/*! \brief This macro is used to test fatal errors.\r
*\r
* The macro tests if the expression is FALSE. If it is, a fatal error is\r
#define Assert(expr)\r
#endif\r
\r
-/*! \name Zero-Bit Counting Macros\r
+\r
+/*! \name Zero-Bit Counting\r
*\r
* Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when\r
* applied to constant expressions (values known at compile time), so they are\r
\r
//! @}\r
\r
-/*! \name Alignment Macros\r
+\r
+/*! \name Alignment\r
*/\r
//! @{\r
\r
\r
//! @}\r
\r
-/*! \name Mathematics Macros\r
+\r
+/*! \name Mathematics\r
*\r
* The same considerations as for clz and ctz apply here but AVR32-GCC does not\r
* provide built-in functions to access the assembly instructions abs, min and\r
\r
//! @}\r
\r
+\r
/*! \brief Calls the routine at address \a addr.\r
*\r
* It generates a long call opcode.\r
(\\r
{\\r
__asm__ __volatile__ (\\r
- "lda.w r8, _start\n\t"\\r
- "lddpc r9, 1f\n\t"\\r
- "stm --sp, r8-r9\n\t"\\r
+ "lddpc r9, 3f\n\t"\\r
"mfsr r8, %[SR]\n\t"\\r
"bfextu r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\\r
"cp.w r8, 0b001\n\t"\\r
"breq 0f\n\t"\\r
+ "sub r8, pc, $ - 1f\n\t"\\r
+ "pushm r8-r9\n\t"\\r
"rete\n"\\r
"0:\n\t"\\r
- "rets\n\t"\\r
- ".balign 4\n"\\r
+ "mtsr %[SR], r9\n"\\r
"1:\n\t"\\r
+ "mov r0, 0\n\t"\\r
+ "mov r1, 0\n\t"\\r
+ "mov r2, 0\n\t"\\r
+ "mov r3, 0\n\t"\\r
+ "mov r4, 0\n\t"\\r
+ "mov r5, 0\n\t"\\r
+ "mov r6, 0\n\t"\\r
+ "mov r7, 0\n\t"\\r
+ "mov r8, 0\n\t"\\r
+ "mov r9, 0\n\t"\\r
+ "mov r10, 0\n\t"\\r
+ "mov r11, 0\n\t"\\r
+ "mov r12, 0\n\t"\\r
+ "mov sp, 0\n\t"\\r
+ "stdsp sp[0], sp\n\t"\\r
+ "ldmts sp, sp\n\t"\\r
+ "mov lr, 0\n\t"\\r
+ "lddpc pc, 2f\n\t"\\r
+ ".balign 4\n"\\r
+ "2:\n\t"\\r
+ ".word _start\n"\\r
+ "3:\n\t"\\r
".word %[RESET_SR]"\\r
:\\r
: [SR] "i" (AVR32_SR),\\r
{\\r
extern void *volatile __program_start;\\r
__asm__ __volatile__ (\\r
- "mov r8, LWRD(__program_start)\n\t"\\r
- "orh r8, HWRD(__program_start)\n\t"\\r
+ "mov r7, LWRD(__program_start)\n\t"\\r
+ "orh r7, HWRD(__program_start)\n\t"\\r
"mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
"orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
- "stm --sp, r8-r9\n\t"\\r
"mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\\r
"bfextu r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\\r
"cp.w r8, 001b\n\t"\\r
- "breq $ + 4\n\t"\\r
+ "breq $ + 10\n\t"\\r
+ "sub r8, pc, -12\n\t"\\r
+ "pushm r8-r9\n\t"\\r
"rete\n\t"\\r
- "rets"\\r
+ "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\\r
+ "mov r0, 0\n\t"\\r
+ "mov r1, 0\n\t"\\r
+ "mov r2, 0\n\t"\\r
+ "mov r3, 0\n\t"\\r
+ "mov r4, 0\n\t"\\r
+ "mov r5, 0\n\t"\\r
+ "mov r6, 0\n\t"\\r
+ "st.w r0[4], r7\n\t"\\r
+ "mov r7, 0\n\t"\\r
+ "mov r8, 0\n\t"\\r
+ "mov r9, 0\n\t"\\r
+ "mov r10, 0\n\t"\\r
+ "mov r11, 0\n\t"\\r
+ "mov r12, 0\n\t"\\r
+ "mov sp, 0\n\t"\\r
+ "stdsp sp[0], sp\n\t"\\r
+ "ldmts sp, sp\n\t"\\r
+ "mov lr, 0\n\t"\\r
+ "ld.w pc, lr[4]"\\r
);\\r
__program_start;\\r
-}\r
+ }\r
#endif\r
\r
-/*! \name CPU Status Register Macros\r
+\r
+/*! \name System Register Access\r
*/\r
//! @{\r
\r
-/*! \brief Disables all exceptions.\r
+/*! \brief Gets the value of the \a sysreg system register.\r
+ *\r
+ * \param sysreg Address of the system register of which to get the value.\r
+ *\r
+ * \return Value of the \a sysreg system register.\r
+ */\r
+#if __GNUC__\r
+ #define Get_system_register(sysreg) __builtin_mfsr(sysreg)\r
+#elif __ICCAVR32__\r
+ #define Get_system_register(sysreg) __get_system_register(sysreg)\r
+#endif\r
+\r
+/*! \brief Sets the value of the \a sysreg system register to \a value.\r
+ *\r
+ * \param sysreg Address of the system register of which to set the value.\r
+ * \param value Value to set the \a sysreg system register to.\r
+ */\r
+#if __GNUC__\r
+ #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)\r
+#elif __ICCAVR32__\r
+ #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name CPU Status Register Access\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tells whether exceptions are globally enabled.\r
+ *\r
+ * \return \c 1 if exceptions are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))\r
+\r
+/*! \brief Disables exceptions globally.\r
*/\r
#if __GNUC__\r
#define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
#define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))\r
#endif\r
\r
-/*! \brief Enables all exceptions.\r
+/*! \brief Enables exceptions globally.\r
*/\r
#if __GNUC__\r
#define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
#define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))\r
#endif\r
\r
-/*! \brief Disables all interrupts.\r
+/*! \brief Tells whether interrupts are globally enabled.\r
+ *\r
+ * \return \c 1 if interrupts are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))\r
+\r
+/*! \brief Disables interrupts globally.\r
*/\r
#if __GNUC__\r
#define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));})\r
#define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}\r
#endif\r
\r
-/*! \brief Enables all interrupts.\r
+/*! \brief Enables interrupts globally.\r
*/\r
#if __GNUC__\r
#define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})\r
#define Enable_global_interrupt() (__enable_interrupt())\r
#endif\r
\r
+/*! \brief Tells whether interrupt level \a int_lev is enabled.\r
+ *\r
+ * \param int_lev Interrupt level (0 to 3).\r
+ *\r
+ * \return \c 1 if interrupt level \a int_lev is enabled, else \c 0.\r
+ */\r
+#define Is_interrupt_level_enabled(int_lev) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_lev, M_MASK)))\r
+\r
/*! \brief Disables interrupt level \a int_lev.\r
*\r
* \param int_lev Interrupt level to disable (0 to 3).\r
\r
//! @}\r
\r
-/*! \name System Register Access Macros\r
- */\r
-//! @{\r
-\r
-/*! \brief Gets the value of the \a sysreg system register.\r
- *\r
- * \param sysreg Address of the system register of which to get the value.\r
- *\r
- * \return Value of the \a sysreg system register.\r
- */\r
-#if __GNUC__\r
- #define Get_system_register(sysreg) __builtin_mfsr(sysreg)\r
-#elif __ICCAVR32__\r
- #define Get_system_register(sysreg) __get_system_register(sysreg)\r
-#endif\r
-\r
-/*! \brief Sets the value of the \a sysreg system register to \a value.\r
- *\r
- * \param sysreg Address of the system register of which to set the value.\r
- * \param value Value to set the \a sysreg system register to.\r
- */\r
-#if __GNUC__\r
- #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)\r
-#elif __ICCAVR32__\r
- #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)\r
-#endif\r
-\r
-//! @}\r
-\r
#endif // __AVR32_ABI_COMPILER__\r
\r
+\r
//! Boolean evaluating MCU little endianism.\r
#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)\r
#define LITTLE_ENDIAN_MCU FALSE\r
//! Boolean evaluating MCU big endianism.\r
#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)\r
\r
+\r
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
\r
-/*! \name U16/U32/U64 MCU Endianism Handling Macros\r
+/*! \name MCU Endianism Handling\r
*/\r
//! @{\r
+\r
#if LITTLE_ENDIAN_MCU\r
+\r
#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+\r
#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
#define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.\r
#define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.\r
#define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.\r
#define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.\r
- #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
- #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
- #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
- #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+ #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+ #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+ #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+ #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
#define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.\r
#define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.\r
#define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.\r
#define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.\r
- #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 1st rank of \a u64.\r
- #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 2nd rank of \a u64.\r
- #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 3rd rank of \a u64.\r
- #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64.\r
+ #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64.\r
+ #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64.\r
#define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.\r
#define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.\r
#define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.\r
#define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.\r
#define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.\r
#define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.\r
- #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 1st rank of \a u64.\r
- #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 2nd rank of \a u64.\r
- #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 3rd rank of \a u64.\r
- #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 4th rank of \a u64.\r
- #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 5th rank of \a u64.\r
- #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 6th rank of \a u64.\r
- #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 7th rank of \a u64.\r
- #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 8th rank of \a u64.\r
+ #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64.\r
+ #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64.\r
+ #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64.\r
+ #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64.\r
+ #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64.\r
+ #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64.\r
+ #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64.\r
+ #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64.\r
+\r
#else // BIG_ENDIAN_MCU\r
+\r
#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.\r
#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.\r
+\r
#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.\r
#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.\r
#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.\r
#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.\r
#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.\r
#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.\r
- #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
- #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
- #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
- #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+ #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+ #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+ #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+ #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+\r
#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.\r
#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.\r
#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.\r
#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.\r
#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.\r
#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.\r
- #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 1st rank of \a u64.\r
- #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
- #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
- #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+ #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+ #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.\r
#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.\r
#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.\r
#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.\r
#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.\r
#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.\r
- #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 1st rank of \a u64.\r
- #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
- #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
- #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 4th rank of \a u64.\r
- #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 5th rank of \a u64.\r
- #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 6th rank of \a u64.\r
- #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 7th rank of \a u64.\r
- #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+ #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+ #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+ #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+ #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+ #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+ #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+ #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+ #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
#endif\r
+\r
//! @}\r
\r
-/*! \name Endianism Conversion Macros\r
+\r
+/*! \name Endianism Conversion\r
*\r
* The same considerations as for clz and ctz apply here but AVR32-GCC's\r
* __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when\r
\r
//! @}\r
\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
#endif // __AVR32_ABI_COMPILER__\r
\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
* For further information, visit\r
* <A href="http://www.atmel.com/products/AVR32/" >Atmel AVR32</A>. and\r
* <A href="http://www.freertos.org/" >FreeRTOS home page</A>.\n\r
- * Support e-mail address: avr32@atmel.com.\r
+ * Support and FAQ: http://support.atmel.no/\r
*/\r
//! @{\r
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )\r
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )\r
-#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )\r
+#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 15 )\r
//! @}\r
\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
\r
/*\r
- BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.\r
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART.\r
*/\r
\r
/* Scheduler includes. */\r
\r
/* Demo application includes. */\r
#include "serial.h"\r
-\r
-#if __GNUC__\r
- #include <avr32/io.h>\r
-#elif __ICCAVR32__\r
- #include <avr32/iouc3a0512.h>\r
-#else\r
- #error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "board.h"\r
#include "gpio.h"\r
\r
#pragma optimize = no_inline\r
#endif\r
\r
-static portBASE_TYPE prvUSART0_ISR_NonNakedBehaviour( void )\r
+static portBASE_TYPE prvUSART_ISR_NonNakedBehaviour( void )\r
{\r
/* Now we can declare the local variables. */\r
signed portCHAR cChar;\r
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;\r
unsigned portLONG ulStatus;\r
- volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
+ volatile avr32_usart_t *usart = serialPORT_USART;\r
portBASE_TYPE retstatus;\r
\r
/* What caused the interrupt? */\r
- ulStatus = usart0->csr & usart0->imr;\r
+ ulStatus = usart->csr & usart->imr;\r
\r
if (ulStatus & AVR32_USART_CSR_TXRDY_MASK)\r
{\r
{\r
/* A character was retrieved from the queue so can be sent to the\r
THR now. */\r
- usart0->thr = cChar;\r
+ usart->thr = cChar;\r
}\r
else\r
{\r
/* Queue empty, nothing to send so turn off the Tx interrupt. */\r
- usart0->idr = AVR32_USART_IDR_TXRDY_MASK;\r
+ usart->idr = AVR32_USART_IDR_TXRDY_MASK;\r
}\r
}\r
\r
if (ulStatus & AVR32_USART_CSR_RXRDY_MASK)\r
{\r
/* The interrupt was caused by the receiver getting data. */\r
- cChar = usart0->rhr; //TODO\r
+ cChar = usart->rhr; //TODO\r
\r
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
calls in a critical section . */\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * USART0 interrupt service routine.\r
+ * USART interrupt service routine.\r
*/\r
#if __GNUC__\r
__attribute__((__naked__))\r
#pragma shadow_registers = full // Naked.\r
#endif\r
\r
-static void vUSART0_ISR( void )\r
+static void vUSART_ISR( void )\r
{\r
/* This ISR can cause a context switch, so the first statement must be a\r
call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
variable declarations. */\r
portENTER_SWITCHING_ISR();\r
- \r
- prvUSART0_ISR_NonNakedBehaviour();\r
- \r
+\r
+ prvUSART_ISR_NonNakedBehaviour();\r
+\r
/* Exit the ISR. If a task was woken by either a character being received\r
or transmitted then a context switch will occur. */\r
portEXIT_SWITCHING_ISR();\r
*/\r
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
{\r
+static const gpio_map_t USART_GPIO_MAP =\r
+{\r
+ { serialPORT_USART_RX_PIN, serialPORT_USART_RX_FUNCTION },\r
+ { serialPORT_USART_TX_PIN, serialPORT_USART_TX_FUNCTION }\r
+};\r
+\r
xComPortHandle xReturn = serHANDLE;\r
-volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
-int cd; /* USART0 Clock Divider. */\r
+volatile avr32_usart_t *usart = serialPORT_USART;\r
+int cd; /* USART Clock Divider. */\r
\r
/* Create the rx and tx queues. */\r
vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );\r
\r
- /* Configure USART0. */\r
+ /* Configure USART. */\r
if( ( xRxedChars != serINVALID_QUEUE ) &&\r
( xCharsForTx != serINVALID_QUEUE ) &&\r
( ulWantedBaud != ( unsigned portLONG ) 0 ) )\r
portENTER_CRITICAL();\r
{\r
/**\r
- ** Reset USART0.\r
+ ** Reset USART.\r
**/\r
- /* Disable all USART0 interrupt sources to begin... */\r
- usart0->idr = 0xFFFFFFFF;\r
+ /* Disable all USART interrupt sources to begin... */\r
+ usart->idr = 0xFFFFFFFF;\r
\r
/* Reset mode and other registers that could cause unpredictable\r
behaviour after reset */\r
- usart0->mr = 0; /* Reset Mode register. */\r
- usart0->rtor = 0; /* Reset Receiver Time-out register. */\r
- usart0->ttgr = 0; /* Reset Transmitter Timeguard register. */\r
+ usart->mr = 0; /* Reset Mode register. */\r
+ usart->rtor = 0; /* Reset Receiver Time-out register. */\r
+ usart->ttgr = 0; /* Reset Transmitter Timeguard register. */\r
\r
/* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK\r
and turn off DTR and RTS */\r
- usart0->cr = AVR32_USART_CR_RSTRX_MASK |\r
+ usart->cr = AVR32_USART_CR_RSTRX_MASK |\r
AVR32_USART_CR_RSTTX_MASK |\r
AVR32_USART_CR_RXDIS_MASK |\r
AVR32_USART_CR_TXDIS_MASK |\r
AVR32_USART_CR_RTSDIS_MASK;\r
\r
/**\r
- ** Configure USART0.\r
+ ** Configure USART.\r
**/\r
- /* Enable USART0 RXD & TXD pins. */\r
- gpio_enable_module_pin(AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION);\r
- gpio_enable_module_pin(AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION);\r
+ /* Enable USART RXD & TXD pins. */\r
+ gpio_enable_module( USART_GPIO_MAP, sizeof( USART_GPIO_MAP ) / sizeof( USART_GPIO_MAP[0] ) );\r
\r
- /* Set the USART0 baudrate to be as close as possible to the wanted baudrate. */\r
+ /* Set the USART baudrate to be as close as possible to the wanted baudrate. */\r
/*\r
* ** BAUDRATE CALCULATION **\r
*\r
if( ulWantedBaud < ( configCPU_CLOCK_HZ / 16 ) )\r
{\r
/* Use 8x oversampling */\r
- usart
0->mr |= (1<<AVR32_USART_MR_OVER_OFFSET);
\r+ usart->mr |= (1<<AVR32_USART_MR_OVER_OFFSET);\r
cd = configCPU_CLOCK_HZ / (8*ulWantedBaud);\r
\r
- if( cd < 2 ) \r
+ if( cd < 2 )\r
{\r
return serINVALID_COMPORT_HANDLER;\r
}\r
\r
- usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
- } \r
- else \r
+ usart->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+ }\r
+ else\r
{\r
/* Use 16x oversampling */\r
- usart
0->mr &= ~(1<<AVR32_USART_MR_OVER_OFFSET);
\r+ usart->mr &= ~(1<<AVR32_USART_MR_OVER_OFFSET);\r
cd = configCPU_CLOCK_HZ / (16*ulWantedBaud);\r
\r
- if( cd > 65535 ) \r
+ if( cd > 65535 )\r
{\r
/* Baudrate is too low */\r
return serINVALID_COMPORT_HANDLER;\r
}\r
}\r
\r
- usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
+ usart->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);\r
\r
- /* Set the USART0 Mode register: Mode=Normal(0), Clk selection=MCK(0),\r
+ /* Set the USART Mode register: Mode=Normal(0), Clk selection=MCK(0),\r
CHRL=8, SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0,\r
MODE9=0, CKLO=0, OVER(previously done when setting the baudrate),\r
other fields not used in this mode. */\r
- usart0->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET ) |\r
+ usart->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET ) |\r
( 4 << AVR32_USART_MR_PAR_OFFSET ) |\r
( 1 << AVR32_USART_MR_NBSTOP_OFFSET);\r
\r
/* Write the Transmit Timeguard Register */\r
- usart0->ttgr = 0;\r
+ usart->ttgr = 0;\r
+\r
\r
- \r
- /* Register the USART0 interrupt handler to the interrupt controller and\r
- enable the USART0 interrupt. */\r
- INTC_register_interrupt((__int_handler)&vUSART0_ISR, AVR32_USART0_IRQ, INT1);\r
+ /* Register the USART interrupt handler to the interrupt controller and\r
+ enable the USART interrupt. */\r
+ INTC_register_interrupt((__int_handler)&vUSART_ISR, serialPORT_USART_IRQ, INT1);\r
\r
- /* Enable USART0 interrupt sources (but not Tx for now)... */\r
- usart0->ier = AVR32_USART_IER_RXRDY_MASK;\r
+ /* Enable USART interrupt sources (but not Tx for now)... */\r
+ usart->ier = AVR32_USART_IER_RXRDY_MASK;\r
\r
/* Enable receiver and transmitter... */\r
- usart0->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;\r
+ usart->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;\r
}\r
portEXIT_CRITICAL();\r
}\r
\r
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )\r
{\r
-volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
+volatile avr32_usart_t *usart = serialPORT_USART;\r
\r
/* Place the character in the queue of characters to be transmitted. */\r
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )\r
queue and send it. This does not need to be in a critical section as\r
if the interrupt has already removed the character the next interrupt\r
will simply turn off the Tx interrupt again. */\r
- usart0->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);\r
+ usart->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);\r
\r
return pdPASS;\r
}\r
# elf file.elf Link: create ELF output file from object files.
# lss file.lss Create extended listing from target output file.
# sym file.sym Create symbol table from target output file.
+# hex file.hex Create Intel HEX image from ELF output file.
# bin file.bin Create binary image from ELF output file.
# sizes Display target size information.
+# isp Use ISP instead of JTAGICE mkII when programming.
# cpuinfo Get CPU information.
# halt Stop CPU execution.
+# chiperase Perform a JTAG Chip Erase command.
+# erase Perform a flash chip erase.
# program Program MCU memory from ELF output file.
-# reset Reset CPU.
+# secureflash Protect chip by setting security bit.
+# reset Reset MCU.
# debug Open a debug connection with the MCU.
# run Start CPU execution.
# readregs Read CPU registers.
CPPFILES = $(CSRCS:.c=.i)
CC = avr32-gcc
-CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS)
+CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x)
AS = avr32-as
-ASFLAGS = $(DEBUG) $(AS_EXTRA_FLAGS)
+ASFLAGS = $(DEBUG) \
+ $(PLATFORM_INC_PATH:%=-Wa,-I%) $(INC_PATH:%=-Wa,-I%) $(AS_EXTRA_FLAGS)
OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o)
LD = avr32-ld
SYM = $(TGTFILE:$(TGTTYPE)=.sym)
OBJCOPY = avr32-objcopy
+HEX = $(TGTFILE:$(TGTTYPE)=.hex)
BIN = $(TGTFILE:$(TGTTYPE)=.bin)
SIZE = avr32-size
-SUDO = $(shell if [ -x /usr/bin/sudo ]; then echo sudo; fi)
-
SLEEP = sleep
SLEEPUSB = 9
PROGRAM = avr32program
-DBGPROXY = avr32gdbproxy
+ISP = batchisp
+ISPFLAGS = -device at32$(PART) -hardware usb -operation
+
+DBGPROXY = avr32gdbproxy
DOCGEN = doxygen
MSG_LINKING = Linking to \`$@\'.
MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'.
MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'.
+MSG_IHEX_IMAGE = Creating Intel HEX image to \`$@\'.
MSG_BINARY_IMAGE = Creating binary image to \`$@\'.
MSG_GETTING_CPU_INFO = Getting CPU information.
MSG_HALTING = Stopping CPU execution.
-MSG_PROGRAMMING = Programming MCU memory from \`$<\'.
-MSG_RESETTING = Resetting CPU.
+MSG_ERASING_CHIP = Performing a JTAG Chip Erase command.
+MSG_ERASING = Performing a flash chip erase.
+MSG_PROGRAMMING = Programming MCU memory from \`$(TGTFILE)\'.
+MSG_SECURING_FLASH = Protecting chip by setting security bit.
+MSG_RESETTING = Resetting MCU.
MSG_DEBUGGING = Opening debug connection with MCU.
MSG_RUNNING = Starting CPU execution.
MSG_READING_CPU_REGS = Reading CPU registers.
# Default goal: build the project.
ifeq ($(TGTTYPE),.a)
.PHONY: all
-all: ccversion a lss sym
+all: ccversion a lss sym sizes
else
ifeq ($(TGTTYPE),.elf)
.PHONY: all
-all: ccversion elf lss sym bin sizes
+all: ccversion elf lss sym hex bin sizes
else
$(error $(ERR_TARGET_TYPE))
endif
clean:
@echo $(MSG_CLEANING)
-$(VERBOSE_CMD)$(RM) $(BIN)
+ -$(VERBOSE_CMD)$(RM) $(HEX)
-$(VERBOSE_CMD)$(RM) $(SYM)
-$(VERBOSE_CMD)$(RM) $(LSS)
-$(VERBOSE_CMD)$(RM) $(TGTFILE)
sym: $(SYM)
ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+.PHONY: hex
+hex: $(HEX)
+
# Create binary image from ELF output file.
.PHONY: bin
bin: $(BIN)
+
endif
# Display target size information.
sizes: $(TGTFILE)
@echo
@echo
+ifeq ($(TGTTYPE),.a)
+ @$(SIZE) -Bxt $<
+else
+ifeq ($(TGTTYPE),.elf)
@$(SIZE) -Ax $<
+ @$(SIZE) -Bx $<
+endif
+endif
+ @echo
+ @echo
ifeq ($(TGTTYPE),.elf)
+# Use ISP instead of JTAGICE mkII when programming.
+.PHONY: isp
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
+isp: all
+else
+isp:
+ @:
+endif
+
+ifeq ($(findstring isp,$(MAKECMDGOALS)),)
+
# Get CPU information.
.PHONY: cpuinfo
cpuinfo:
@echo
@echo $(MSG_GETTING_CPU_INFO)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB cpuinfo
-ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
+ $(VERBOSE_CMD)$(PROGRAM) cpuinfo
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),cpuinfo)
@$(SLEEP) $(SLEEPUSB)
else
@echo
# Stop CPU execution.
.PHONY: halt
halt:
-ifeq ($(filter cpuinfo program reset run readregs,$(MAKECMDGOALS)),)
+ifeq ($(filter cpuinfo chiperase erase program secureflash reset run readregs,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_HALTING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB halt
+ $(VERBOSE_CMD)$(PROGRAM) halt
ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
+endif
+
+# Perform a JTAG Chip Erase command.
+.PHONY: chiperase
+chiperase:
+ @echo
+ @echo $(MSG_ERASING_CHIP)
+ $(VERBOSE_CMD)$(PROGRAM) chiperase
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash reset debug run readregs,$(MAKECMDGOALS))),chiperase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(filter chiperase program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(PROGRAM) erase $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo erase secureflash reset debug run readregs,$(MAKECMDGOALS))),erase)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+else
+ @:
endif
# Program MCU memory from ELF output file.
.PHONY: program
-program: $(TGTFILE)
+program: all
@echo
@echo $(MSG_PROGRAMMING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB program $(FLASH:%=-f%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $<
-ifneq ($(call LastWord,$(filter cpuinfo program debug readregs,$(MAKECMDGOALS))),program)
+ $(VERBOSE_CMD)$(PROGRAM) program $(FLASH:%=-f%) $(PROG_CLOCK:%=-c%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $(TGTFILE)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase program secureflash debug readregs,$(MAKECMDGOALS))),program)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
-# Reset CPU.
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(PROGRAM) secureflash
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),secureflash)
+ @$(SLEEP) $(SLEEPUSB)
+else
+ @echo
+endif
+
+# Reset MCU.
.PHONY: reset
reset:
ifeq ($(filter program run,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_RESETTING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB reset
-ifneq ($(call LastWord,$(filter cpuinfo reset debug readregs,$(MAKECMDGOALS))),reset)
+ $(VERBOSE_CMD)$(PROGRAM) reset
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash reset debug readregs,$(MAKECMDGOALS))),reset)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
endif
# Open a debug connection with the MCU.
debug:
@echo
@echo $(MSG_DEBUGGING)
- $(VERBOSE_CMD)$(SUDO) $(DBGPROXY) -cUSB $(patsubst cfi@%,-f%,$(FLASH:internal@%=-f%))
-ifneq ($(call LastWord,$(filter cpuinfo halt program reset debug run readregs,$(MAKECMDGOALS))),debug)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifneq ($(call LastWord,$(filter cpuinfo halt chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),debug)
@$(SLEEP) $(SLEEPUSB)
else
@echo
ifeq ($(findstring program,$(MAKECMDGOALS)),)
@echo
@echo $(MSG_RUNNING)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
-ifneq ($(call LastWord,$(filter cpuinfo debug run readregs,$(MAKECMDGOALS))),run)
+ $(VERBOSE_CMD)$(PROGRAM) run $(if $(findstring reset,$(MAKECMDGOALS)),-R)
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase secureflash debug run readregs,$(MAKECMDGOALS))),run)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
else
- @echo > /dev/null
+ @:
endif
# Read CPU registers.
readregs:
@echo
@echo $(MSG_READING_CPU_REGS)
- $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB readregs
-ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),readregs)
+ $(VERBOSE_CMD)$(PROGRAM) readregs
+ifneq ($(call LastWord,$(filter cpuinfo chiperase erase program secureflash reset debug run readregs,$(MAKECMDGOALS))),readregs)
@$(SLEEP) $(SLEEPUSB)
else
@echo
endif
+else
+
+# Perform a flash chip erase.
+.PHONY: erase
+erase:
+ifeq ($(findstring program,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_ERASING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck
+ifeq ($(call LastWord,$(filter erase secureflash debug run,$(MAKECMDGOALS))),erase)
+ @echo
+endif
+else
+ @:
+endif
+
+# Program MCU memory from ELF output file.
+.PHONY: program
+program: all
+ @echo
+ @echo $(MSG_PROGRAMMING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) erase f memory flash blankcheck loadbuffer $(TGTFILE) program verify $(if $(findstring run,$(MAKECMDGOALS)),$(if $(findstring secureflash,$(MAKECMDGOALS)),,start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0))
+ifeq ($(call LastWord,$(filter program secureflash debug,$(MAKECMDGOALS))),program)
+ @echo
+endif
+
+# Protect chip by setting security bit.
+.PHONY: secureflash
+secureflash:
+ @echo
+ @echo $(MSG_SECURING_FLASH)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) memory security addrange 0x0 0x0 fillbuffer 0x01 program $(if $(findstring run,$(MAKECMDGOALS)),start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0)
+ifeq ($(call LastWord,$(filter erase program secureflash debug,$(MAKECMDGOALS))),secureflash)
+ @echo
+endif
+
+# Reset MCU.
+.PHONY: reset
+reset:
+ @:
+
+# Open a debug connection with the MCU.
+.PHONY: debug
+debug:
+ @echo
+ @echo $(MSG_DEBUGGING)
+ $(VERBOSE_CMD)$(DBGPROXY) $(FLASH:%=-f%)
+ifeq ($(call LastWord,$(filter erase program secureflash debug run,$(MAKECMDGOALS))),debug)
+ @echo
+endif
+
+# Start CPU execution.
+.PHONY: run
+run:
+ifeq ($(filter program secureflash,$(MAKECMDGOALS)),)
+ @echo
+ @echo $(MSG_RUNNING)
+ $(VERBOSE_CMD)$(ISP) $(ISPFLAGS) start $(if $(findstring reset,$(MAKECMDGOALS)),,no)reset 0
+ifeq ($(call LastWord,$(filter erase debug run,$(MAKECMDGOALS))),run)
+ @echo
+endif
+else
+ @:
+endif
+
+endif
+
endif
# Build the documentation.
# Display main executed commands.
.PHONY: verbose
-ifeq ($(MAKECMDGOALS),verbose)
+ifeq ($(filter-out isp verbose,$(MAKECMDGOALS)),)
verbose: all
else
verbose:
- @echo > /dev/null
+ @:
endif
ifneq ($(findstring verbose,$(MAKECMDGOALS)),)
# Prefix displaying the following command if and only if verbose is a goal.
$(VERBOSE_NL)
ifeq ($(TGTTYPE),.elf)
+
+# Create Intel HEX image from ELF output file.
+$(HEX): $(TGTFILE)
+ @echo $(MSG_IHEX_IMAGE)
+ $(VERBOSE_CMD)$(OBJCOPY) -O ihex $< $@
+ $(VERBOSE_NL)
+
# Create binary image from ELF output file.
$(BIN): $(TGTFILE)
@echo $(MSG_BINARY_IMAGE)
$(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@
$(VERBOSE_NL)
+
endif
-# Hey Emacs, this is a -*- makefile -*-\r
-\r
-# The purpose of this file is to define the build configuration variables used\r
-# by the generic Makefile. See Makefile header for further information.\r
-\r
-# Copyright (c) 2007, Atmel Corporation All rights reserved.\r
-#\r
-# Redistribution and use in source and binary forms, with or without\r
-# modification, are permitted provided that the following conditions are met:\r
-#\r
-# 1. Redistributions of source code must retain the above copyright notice, this\r
-# list of conditions and the following disclaimer.\r
-#\r
-# 2. Redistributions in binary form must reproduce the above copyright notice,\r
-# this list of conditions and the following disclaimer in the documentation and/\r
-# or other materials provided with the distribution.\r
-#\r
-# 3. The name of ATMEL may not be used to endorse or promote products derived\r
-# from this software without specific prior written permission.\r
-#\r
-# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
-# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
-# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
-# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
-# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\r
-# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
-# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-\r
-\r
-# Base paths\r
-PRJ_PATH = ../..\r
-APPS_PATH = $(PRJ_PATH)/APPLICATIONS\r
-BRDS_PATH = $(PRJ_PATH)/BOARDS\r
-COMP_PATH = $(PRJ_PATH)/COMPONENTS\r
-DRVR_PATH = $(PRJ_PATH)/DRIVERS\r
-SERV_PATH = $(PRJ_PATH)/SERVICES\r
-UTIL_PATH = $(PRJ_PATH)/UTILS\r
-\r
-# Demo paths\r
-FREERTOS_PATH = ../../../..\r
-FREERTOS_PORT_PATH = $(FREERTOS_PATH)/Source/portable/GCC/AVR32_UC3\r
-FREERTOS_MEM_PATH = $(FREERTOS_PATH)/Source/portable/MemMang\r
-DEMO_PATH = ../..\r
-ETH_PATH = $(DEMO_PATH)/NETWORK\r
-WEB_PATH = $(ETH_PATH)/BasicWEB\r
-TFTP_PATH = $(ETH_PATH)/BasicTFTP\r
-SMTP_PATH = $(ETH_PATH)/BasicSMTP\r
-EMAC_PATH = $(ETH_PATH)/EMAC\r
-LWIP_PATH = $(FREERTOS_PATH)/Demo/Common/ethernet/lwIP\r
-LWIP_PORT_PATH = $(ETH_PATH)/lwip-port/AT32UC3A\r
-\r
-# CPU architecture: {ap|uc}\r
-ARCH = uc\r
-\r
-# Part: {none|ap7000|ap7010|ap7020|uc3a0256|uc3a0512|uc3a1128|uc3a1256|uc3a1512}\r
-PART = uc3a0512\r
-\r
-# Flash memories: [type@address,size]...\r
-FLASH = internal@0x80000000,512Kb\r
-\r
-# Device/Platform/Board include path\r
-PLATFORM_INC_PATH = \\r
- $(BRDS_PATH)/\r
-\r
-# Target name: {*.a|*.elf}\r
-TARGET = lwipdemo.elf\r
-\r
-# Definitions: [-D name[=definition]...] [-U name...]\r
-# Things that might be added to DEFS:\r
-# BOARD Board used: {EVK1100}\r
-DEFS = -D BOARD=EVK1100 -D FREERTOS_USED -D HTTP_USED=1 -D TFTP_USED=1 -D SMTP_USED=0\r
-\r
-# Include path\r
-INC_PATH = \\r
- $(UTIL_PATH)/ \\r
- $(UTIL_PATH)/PREPROCESSOR/ \\r
- $(DRVR_PATH)/INTC/ \\r
- $(DRVR_PATH)/TC/ \\r
- $(DRVR_PATH)/PM/ \\r
- $(DRVR_PATH)/GPIO/ \\r
- $(DRVR_PATH)/FLASHC/ \\r
- $(DEMO_PATH)/ \\r
- $(FREERTOS_PATH)/Source/include/ \\r
- $(FREERTOS_PATH)/Demo/Common/include/ \\r
- $(FREERTOS_PORT_PATH)/ \\r
- $(FREERTOS_MEM_PATH)/ \\r
- $(ETH_PATH)/ \\r
- $(EMAC_PATH)/ \\r
- $(LWIP_PATH)/include/ \\r
- $(LWIP_PATH)/include/ipv4/ \\r
- $(LWIP_PORT_PATH)/ \\r
- $(WEB_PATH)/ \\r
- $(TFTP_PATH)/ \\r
- $(SMTP_PATH)/\r
-\r
-# C source files\r
-\r
-LWIP_SRC = \\r
- $(LWIP_PATH)/core/inet.c \\r
- $(LWIP_PATH)/core/mem.c \\r
- $(LWIP_PATH)/core/memp.c \\r
- $(LWIP_PATH)/core/netif.c \\r
- $(LWIP_PATH)/core/pbuf.c \\r
- $(LWIP_PATH)/core/raw.c \\r
- $(LWIP_PATH)/core/stats.c \\r
- $(LWIP_PATH)/core/sys.c \\r
- $(LWIP_PATH)/core/tcp.c \\r
- $(LWIP_PATH)/core/tcp_in.c \\r
- $(LWIP_PATH)/core/tcp_out.c \\r
- $(LWIP_PATH)/core/ipv4/ip.c \\r
- $(LWIP_PATH)/core/ipv4/ip_addr.c \\r
- $(LWIP_PATH)/core/ipv4/icmp.c \\r
- $(LWIP_PATH)/api/sockets.c \\r
- $(LWIP_PATH)/api/tcpip.c \\r
- $(LWIP_PATH)/api/api_msg.c \\r
- $(LWIP_PATH)/api/err.c \\r
- $(LWIP_PATH)/api/api_lib.c \\r
- $(LWIP_PATH)/netif/etharp.c \\r
- $(LWIP_PATH)/core/udp.c \\r
- $(LWIP_PATH)/core/ipv4/ip_frag.c\r
-\r
-CSRCS = \\r
- $(BRDS_PATH)/EVK1100/led.c \\r
- $(DRVR_PATH)/INTC/intc.c \\r
- $(DRVR_PATH)/TC/tc.c \\r
- $(DRVR_PATH)/PM/pm.c \\r
- $(DRVR_PATH)/GPIO/gpio.c \\r
- $(DRVR_PATH)/FLASHC/flashc.c \\r
- $(DEMO_PATH)/main.c \\r
- $(DEMO_PATH)/PARTEST/ParTest.c \\r
- $(DEMO_PATH)/SERIAL/serial.c \\r
- $(FREERTOS_PATH)/Source/tasks.c \\r
- $(FREERTOS_PATH)/Source/queue.c \\r
- $(FREERTOS_PATH)/Source/list.c \\r
- $(FREERTOS_PATH)/Source/croutine.c \\r
- $(FREERTOS_PATH)/Demo/Common/Minimal/flash.c \\r
- $(FREERTOS_PORT_PATH)/port.c \\r
- $(FREERTOS_MEM_PATH)/heap_3.c \\r
- $(LWIP_SRC) \\r
- $(LWIP_PORT_PATH)/sys_arch.c \\r
- $(LWIP_PORT_PATH)/ethernetif.c \\r
- $(WEB_PATH)/BasicWEB.c \\r
- $(TFTP_PATH)/BasicTFTP.c \\r
- $(SMTP_PATH)/BasicSMTP.c \\r
- $(ETH_PATH)/ethernet.c \\r
- $(EMAC_PATH)/AVR32_EMAC.c \\r
- $(EMAC_PATH)/AVR32_EMAC_ISR.c \\r
- $(DEMO_PATH)/printf-stdarg.c\r
-\r
-# Assembler source files\r
-ASSRCS = \\r
- $(FREERTOS_PORT_PATH)/exception.S\r
-\r
-# Library path\r
-LIB_PATH =\r
-\r
-# Libraries to link with the project\r
-LIBS =\r
-\r
-# Linker script file if any\r
-LINKER_SCRIPT =\r
-\r
-# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...]\r
-# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
-WARNINGS = -Wall\r
-\r
-# Options for debugging: [-g]...\r
-# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
-DEBUG = -g\r
-\r
-# Options that control optimization: [-O[0|1|2|3|s]]...\r
-# For further details, refer to the chapter "GCC Command Options" of the GCC manual.\r
-OPTIMIZATION = -O0 -ffunction-sections -fdata-sections\r
-\r
-# Extra flags to use when preprocessing\r
-CPP_EXTRA_FLAGS =\r
-\r
-# Extra flags to use when compiling\r
-C_EXTRA_FLAGS =\r
-\r
-# Extra flags to use when assembling\r
-AS_EXTRA_FLAGS =\r
-\r
-# Extra flags to use when linking\r
-LD_EXTRA_FLAGS = -Wl,--gc-sections\r
-\r
-# Documentation path\r
-DOC_PATH = ./DOC/\r
-\r
-# Documentation configuration file\r
-DOC_CFG = ./doxyfile.doxygen\r
+# Hey Emacs, this is a -*- makefile -*-
+
+# The purpose of this file is to define the build configuration variables used
+# by the generic Makefile. See Makefile header for further information.
+
+# Copyright (c) 2007, Atmel Corporation All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation and/
+# or other materials provided with the distribution.
+#
+# 3. The name of ATMEL may not be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# Base paths
+PRJ_PATH = ../..
+APPS_PATH = $(PRJ_PATH)/APPLICATIONS
+BRDS_PATH = $(PRJ_PATH)/BOARDS
+COMP_PATH = $(PRJ_PATH)/COMPONENTS
+DRVR_PATH = $(PRJ_PATH)/DRIVERS
+SERV_PATH = $(PRJ_PATH)/SERVICES
+UTIL_PATH = $(PRJ_PATH)/UTILS
+
+# Demo paths
+FREERTOS_PATH = ../../../..
+FREERTOS_PORT_PATH = $(FREERTOS_PATH)/Source/portable/GCC/AVR32_UC3
+FREERTOS_MEM_PATH = $(FREERTOS_PATH)/Source/portable/MemMang
+DEMO_PATH = ../..
+ETH_PATH = $(DEMO_PATH)/NETWORK
+WEB_PATH = $(ETH_PATH)/BasicWEB
+TFTP_PATH = $(ETH_PATH)/BasicTFTP
+SMTP_PATH = $(ETH_PATH)/BasicSMTP
+LWIP_PATH = $(FREERTOS_PATH)/Demo/Common/ethernet/lwIP
+LWIP_PORT_PATH = $(ETH_PATH)/lwip-port/AT32UC3A
+
+# CPU architecture: {ap|uc}
+ARCH = uc
+
+# Part: {none|ap7xxx|uc3xxxxx}
+PART = uc3a0512
+
+# Flash memories: [{cfi|internal}@address,size]...
+FLASH = internal@0x80000000,512Kb
+
+# Clock source to use when programming: [{xtal|extclk|int}]
+PROG_CLOCK = xtal
+
+# Device/Platform/Board include path
+PLATFORM_INC_PATH = \
+ $(BRDS_PATH)/
+
+# Target name: {*.a|*.elf}
+TARGET = lwipdemo.elf
+
+# Definitions: [-D name[=definition]...] [-U name...]
+# Things that might be added to DEFS:
+# BOARD Board used: {EVKxxxx}
+# EXT_BOARD Extension board used (if any): {EXTxxxx}
+DEFS = -D BOARD=EVK1100 -D FREERTOS_USED -D HTTP_USED=1 -D TFTP_USED=1 -D SMTP_USED=0
+
+# Include path
+INC_PATH = \
+ $(UTIL_PATH)/ \
+ $(UTIL_PATH)/PREPROCESSOR/ \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/ \
+ $(DRVR_PATH)/INTC/ \
+ $(DRVR_PATH)/TC/ \
+ $(DRVR_PATH)/PM/ \
+ $(DRVR_PATH)/GPIO/ \
+ $(DRVR_PATH)/FLASHC/ \
+ $(DRVR_PATH)/MACB/ \
+ $(DEMO_PATH)/ \
+ $(FREERTOS_PATH)/Source/include/ \
+ $(FREERTOS_PATH)/Demo/Common/include/ \
+ $(FREERTOS_PORT_PATH)/ \
+ $(FREERTOS_MEM_PATH)/ \
+ $(ETH_PATH)/ \
+ $(LWIP_PATH)/include/ \
+ $(LWIP_PATH)/include/ipv4/ \
+ $(LWIP_PORT_PATH)/ \
+ $(WEB_PATH)/ \
+ $(TFTP_PATH)/ \
+ $(SMTP_PATH)/
+
+# C source files
+
+LWIP_SRC = \
+ $(LWIP_PATH)/core/inet.c \
+ $(LWIP_PATH)/core/mem.c \
+ $(LWIP_PATH)/core/memp.c \
+ $(LWIP_PATH)/core/netif.c \
+ $(LWIP_PATH)/core/pbuf.c \
+ $(LWIP_PATH)/core/raw.c \
+ $(LWIP_PATH)/core/stats.c \
+ $(LWIP_PATH)/core/sys.c \
+ $(LWIP_PATH)/core/tcp.c \
+ $(LWIP_PATH)/core/tcp_in.c \
+ $(LWIP_PATH)/core/tcp_out.c \
+ $(LWIP_PATH)/core/ipv4/ip.c \
+ $(LWIP_PATH)/core/ipv4/ip_addr.c \
+ $(LWIP_PATH)/core/ipv4/icmp.c \
+ $(LWIP_PATH)/api/sockets.c \
+ $(LWIP_PATH)/api/tcpip.c \
+ $(LWIP_PATH)/api/api_msg.c \
+ $(LWIP_PATH)/api/err.c \
+ $(LWIP_PATH)/api/api_lib.c \
+ $(LWIP_PATH)/netif/etharp.c \
+ $(LWIP_PATH)/core/udp.c \
+ $(LWIP_PATH)/core/ipv4/ip_frag.c
+
+CSRCS = \
+ $(BRDS_PATH)/EVK1100/led.c \
+ $(DRVR_PATH)/INTC/intc.c \
+ $(DRVR_PATH)/TC/tc.c \
+ $(DRVR_PATH)/PM/pm.c \
+ $(DRVR_PATH)/MACB/macb.c \
+ $(DRVR_PATH)/GPIO/gpio.c \
+ $(DRVR_PATH)/FLASHC/flashc.c \
+ $(DEMO_PATH)/main.c \
+ $(DEMO_PATH)/PARTEST/ParTest.c \
+ $(DEMO_PATH)/SERIAL/serial.c \
+ $(FREERTOS_PATH)/Source/tasks.c \
+ $(FREERTOS_PATH)/Source/queue.c \
+ $(FREERTOS_PATH)/Source/list.c \
+ $(FREERTOS_PATH)/Source/croutine.c \
+ $(FREERTOS_PATH)/Demo/Common/Minimal/flash.c \
+ $(FREERTOS_PORT_PATH)/port.c \
+ $(FREERTOS_MEM_PATH)/heap_3.c \
+ $(LWIP_SRC) \
+ $(LWIP_PORT_PATH)/sys_arch.c \
+ $(LWIP_PORT_PATH)/ethernetif.c \
+ $(WEB_PATH)/BasicWEB.c \
+ $(TFTP_PATH)/BasicTFTP.c \
+ $(SMTP_PATH)/BasicSMTP.c \
+ $(ETH_PATH)/ethernet.c \
+ $(DEMO_PATH)/printf-stdarg.c
+
+# Assembler source files
+ASSRCS = \
+ $(SERV_PATH)/USB/CLASS/DFU/EXAMPLES/ISP/BOOT/trampoline.S \
+ $(FREERTOS_PORT_PATH)/exception.S
+
+# Library path
+LIB_PATH =
+
+# Libraries to link with the project
+LIBS =
+
+# Linker script file if any
+LINKER_SCRIPT = $(UTIL_PATH)/LINKER_SCRIPTS/AT32UC3A/0512/GCC/link_uc3a0512.lds
+
+# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...]
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+WARNINGS = -Wall
+
+# Options for debugging: [-g]...
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+DEBUG = -g
+
+# Options that control optimization: [-O[0|1|2|3|s]]...
+# For further details, refer to the chapter "GCC Command Options" of the GCC manual.
+OPTIMIZATION = -O0 -ffunction-sections -fdata-sections
+
+# Extra flags to use when preprocessing
+CPP_EXTRA_FLAGS =
+
+# Extra flags to use when compiling
+C_EXTRA_FLAGS =
+
+# Extra flags to use when assembling
+AS_EXTRA_FLAGS =
+
+# Extra flags to use when linking
+LD_EXTRA_FLAGS = -Wl,--gc-sections -Wl,-e,_trampoline
+
+# Documentation path
+DOC_PATH = ./DOC/
+
+# Documentation configuration file
+DOC_CFG = ./doxyfile.doxygen
--- /dev/null
+target extended-remote 127.0.0.1:4711\r
+symbol uc3a0512-demo.elf\r
+\r
+\r
+define current_task\r
+printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName\r
+printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack\r
+end\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>AVR32</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CRunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CMacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DynDriver</name>\r
+ <state>JTAGICEMKIIAVR32</state>\r
+ </option>\r
+ <option>\r
+ <name>DDFOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DDFFile</name>\r
+ <state>$TOOLKIT_DIR$\config\iouc3a0512.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>DebuggerUseUbrofResetVector</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JTAGICEMKIIAVR32</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CJtagIceMkIIMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIPeripherals</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIISWBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIISuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIVerifyDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJTagIceMkIICommunicationLogging</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIICommLogFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIConnectionRage</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIConnectionPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIJtagFrequence</name>\r
+ <version>0</version>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIDaisyChain</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIDaisyChainBeforeDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIDaisyChainBeforeBits</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIDaisyChainAfterDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CJtagIceMkIIDaisyChainAfterBits</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoaders</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>SIMAVR32</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CSimMandatory</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>1</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>AVR32</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ProcessorCoreDyn</name>\r
+ <state>at32uc3a0512</state>\r
+ </option>\r
+ <option>\r
+ <name>ProcessorCoreSlave</name>\r
+ <state>at32uc3a0512</state>\r
+ </option>\r
+ <option>\r
+ <name>CodeModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>DataModel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>EnableSimdInstructions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EnableDspInstructions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>EnableRmwInstructions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GAllowUnaligned</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/EC++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>RTLibraryPath</name>\r
+ <state>$TOOLKIT_DIR$\lib\dlavr32allaf.r82</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath</name>\r
+ <state>$TOOLKIT_DIR$\lib\dlavr32allaf.h</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>No specifier n, no float.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>0</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>No specifier a or A.</state>\r
+ </option>\r
+ <option>\r
+ <name>GUnhandledInterrupts</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GUnhandledExceptions</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GEnableTrace</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GTraceBufferSize</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GSStackSize</name>\r
+ <state>0x1000</state>\r
+ </option>\r
+ <option>\r
+ <name>GCStackSize</name>\r
+ <state>0x1000</state>\r
+ </option>\r
+ <option>\r
+ <name>GHeapSize</name>\r
+ <state>0x7000</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCAVR32</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>5</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state>BOARD=EVK1100</state>\r
+ <state>HTTP_USED=1</state>\r
+ <state>SMTP_USED=0</state>\r
+ <state>TFTP_USED=1</state>\r
+ <state>FREERTOS_USED=1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state>Pe191, Pa082, Pe236, Pe171</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCore</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeModel</name>\r
+ <state>0</state>\r
+ </option>\r
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+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\tcp_in.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\tcp_out.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Common\ethernet\lwIP\api\tcpip.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\..\Common\ethernet\lwIP\core\udp.c</name>\r
+ </file>\r
+ </group>\r
+ <group>\r
+ <name>Services</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\NETWORK\BasicSMTP\BasicSMTP.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\NETWORK\BasicTFTP\BasicTFTP.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\NETWORK\BasicWEB\BasicWEB.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\NETWORK\ethernet.c</name>\r
+ </file>\r
+ </group>\r
+ </group>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\main.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\PARTEST\ParTest.c</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\..\..\SERIAL\serial.c</name>\r
+ </file>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+ <project>\r
+ <path>$WS_DIR$\lwipdemo.ewp</path>\r
+ </project>\r
+ <batchBuild/>\r
+</workspace>\r
+\r
+\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
// part.\r
//#define FRCOSC 115200 //!< RCOsc frequency: Hz.\r
\r
-#define FOSC32 32000 //!< Osc32 frequency: Hz.\r
+#define FOSC32 32768 //!< Osc32 frequency: Hz.\r
#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods.\r
\r
#define FOSC0 12000000 //!< Osc0 frequency: Hz.\r
# define USB_VBOF_ACTIVE_LEVEL LOW\r
#endif\r
\r
+//! USB overcurrent detection pin.\r
+#ifdef EVK1100_REVA\r
+# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PB18\r
+#else\r
+# define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PX33\r
+#endif\r
+\r
//! @}\r
\r
\r
*/\r
//! @{\r
#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18\r
-#define DIP204_PWM_CHANNEL AVR32_PWM_CHID6\r
+#define DIP204_PWM_CHANNEL 6\r
#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN\r
#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION\r
//! @}\r
//! @}\r
\r
\r
-/*! \name SPI Connections of the SD/MMC Connector\r
+/*! \name GPIO and SPI Connections of the SD/MMC Connector\r
*/\r
//! @{\r
+#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PA02\r
+#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PA07\r
#define SD_MMC_SPI (&AVR32_SPI1)\r
#define SD_MMC_SPI_CS 1\r
#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "preprocessor.h"\r
#include "compiler.h"\r
#include "evk1100.h"\r
\r
\r
//! Saved state of all LEDs.\r
-static U32 LED_State = (1 << LED_COUNT) - 1;\r
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;\r
\r
\r
U32 LED_Read_Display(void)\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board header file.\r
+ *\r
+ * This file contains definitions and services related to the features of the\r
+ * EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _EVK1101_H_\r
+#define _EVK1101_H_\r
+\r
+#include "compiler.h"\r
+\r
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
+# include "led.h"\r
+#endif // __AVR32_ABI_COMPILER__\r
+\r
+\r
+/*! \name Oscillator Definitions\r
+ */\r
+//! @{\r
+\r
+// RCOsc has no custom calibration by default. Set the following definition to\r
+// the appropriate value if a custom RCOsc calibration has been applied to your\r
+// part.\r
+//#define FRCOSC 115200 //!< RCOsc frequency: Hz.\r
+\r
+#define FOSC32 32768 //!< Osc32 frequency: Hz.\r
+#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods.\r
+\r
+#define FOSC0 12000000 //!< Osc0 frequency: Hz.\r
+#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods.\r
+\r
+// Osc1 crystal is not mounted by default. Set the following definitions to the\r
+// appropriate values if a custom Osc1 crystal is mounted on your board.\r
+//#define FOSC1 12000000 //!< Osc1 frequency: Hz.\r
+//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods.\r
+\r
+//! @}\r
+\r
+\r
+/*! \name USB Definitions\r
+ */\r
+//! @{\r
+\r
+//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and\r
+//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3bxxxx.h>.\r
+#define USB_ID AVR32_USBB_USB_ID_0_0\r
+\r
+//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.\r
+//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and\r
+//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3bxxxx.h>.\r
+#define USB_VBOF AVR32_USBB_USB_VBOF_0_0\r
+\r
+//! Active level of the USB_VBOF output pin.\r
+#define USB_VBOF_ACTIVE_LEVEL LOW\r
+\r
+//! USB overcurrent detection pin.\r
+#define USB_OVERCURRENT_DETECT_PIN AVR32_PIN_PA20\r
+\r
+//! @}\r
+\r
+\r
+//! Number of LEDs.\r
+#define LED_COUNT 4\r
+\r
+/*! \name GPIO Connections of LEDs\r
+ */\r
+//! @{\r
+#define LED0_GPIO AVR32_PIN_PA07\r
+#define LED1_GPIO AVR32_PIN_PA08\r
+#define LED2_GPIO AVR32_PIN_PA21\r
+#define LED3_GPIO AVR32_PIN_PA22\r
+//! @}\r
+\r
+/*! \name PWM Channels of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM 0\r
+#define LED1_PWM 1\r
+#define LED2_PWM 2\r
+#define LED3_PWM 6\r
+//! @}\r
+\r
+/*! \name PWM Functions of LEDs\r
+ */\r
+//! @{\r
+#define LED0_PWM_FUNCTION AVR32_PWM_PWM_0_0_FUNCTION\r
+#define LED1_PWM_FUNCTION AVR32_PWM_PWM_1_0_FUNCTION\r
+#define LED2_PWM_FUNCTION AVR32_PWM_PWM_2_0_FUNCTION\r
+#define LED3_PWM_FUNCTION AVR32_PWM_PWM_6_0_FUNCTION\r
+//! @}\r
+\r
+/*! \name Color Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED_MONO0_GREEN LED0\r
+#define LED_MONO1_GREEN LED1\r
+#define LED_MONO2_GREEN LED2\r
+#define LED_MONO3_GREEN LED3\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of Push Buttons\r
+ */\r
+//! @{\r
+#define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB02\r
+#define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB03\r
+//! @}\r
+\r
+\r
+/*! \name GPIO Connections of the Joystick\r
+ */\r
+//! @{\r
+#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA13\r
+#define GPIO_JOYSTICK_LEFT AVR32_PIN_PB06\r
+#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PB09\r
+#define GPIO_JOYSTICK_UP AVR32_PIN_PB07\r
+#define GPIO_JOYSTICK_DOWN AVR32_PIN_PB08\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Temperature Sensor\r
+ */\r
+//! @{\r
+#define ADC_TEMPERATURE_CHANNEL 7\r
+#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_7_PIN\r
+#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_7_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connection of the Light Sensor\r
+ */\r
+//! @{\r
+#define ADC_LIGHT_CHANNEL 6\r
+#define ADC_LIGHT_PIN AVR32_ADC_AD_6_PIN\r
+#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_6_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name ADC Connections of the Accelerometer\r
+ */\r
+//! @{\r
+#define ADC_ACC_X_CHANNEL 1\r
+#define ADC_ACC_X_PIN AVR32_ADC_AD_1_PIN\r
+#define ADC_ACC_X_FUNCTION AVR32_ADC_AD_1_FUNCTION\r
+#define ADC_ACC_Y_CHANNEL 2\r
+#define ADC_ACC_Y_PIN AVR32_ADC_AD_2_PIN\r
+#define ADC_ACC_Y_FUNCTION AVR32_ADC_AD_2_FUNCTION\r
+#define ADC_ACC_Z_CHANNEL 3\r
+#define ADC_ACC_Z_PIN AVR32_ADC_AD_3_PIN\r
+#define ADC_ACC_Z_FUNCTION AVR32_ADC_AD_3_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name PWM Connections of Audio\r
+ */\r
+//! @{\r
+#define AUDIO_LOW_PWM_CHANNEL 5\r
+#define AUDIO_LOW_PWM_PIN AVR32_PWM_PWM_5_0_PIN\r
+#define AUDIO_LOW_PWM_FUNCTION AVR32_PWM_PWM_5_0_FUNCTION\r
+#define AUDIO_HIGH_PWM_CHANNEL 6\r
+#define AUDIO_HIGH_PWM_PIN AVR32_PWM_PWM_6_1_PIN\r
+#define AUDIO_HIGH_PWM_FUNCTION AVR32_PWM_PWM_6_1_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name SPI Connections of the AT45DBX Data Flash Memory\r
+ */\r
+//! @{\r
+#define AT45DBX_SPI (&AVR32_SPI)\r
+#define AT45DBX_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN\r
+#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION\r
+#define AT45DBX_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN\r
+#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION\r
+#define AT45DBX_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN\r
+#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION\r
+#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI_NPCS_0_0_PIN\r
+#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI_NPCS_0_0_FUNCTION\r
+//! @}\r
+\r
+\r
+/*! \name GPIO and SPI Connections of the SD/MMC Connector\r
+ */\r
+//! @{\r
+#define SD_MMC_CARD_DETECT_PIN AVR32_PIN_PB00\r
+#define SD_MMC_WRITE_PROTECT_PIN AVR32_PIN_PB01\r
+#define SD_MMC_SPI (&AVR32_SPI)\r
+#define SD_MMC_SPI_CS 1\r
+#define SD_MMC_SPI_SCK_PIN AVR32_SPI_SCK_0_0_PIN\r
+#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI_SCK_0_0_FUNCTION\r
+#define SD_MMC_SPI_MISO_PIN AVR32_SPI_MISO_0_0_PIN\r
+#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI_MISO_0_0_FUNCTION\r
+#define SD_MMC_SPI_MOSI_PIN AVR32_SPI_MOSI_0_0_PIN\r
+#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI_MOSI_0_0_FUNCTION\r
+#define SD_MMC_SPI_NPCS_PIN AVR32_SPI_NPCS_1_0_PIN\r
+#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI_NPCS_1_0_FUNCTION\r
+//! @}\r
+\r
+\r
+#endif // _EVK1101_H_\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include <avr32/io.h>\r
+#include "preprocessor.h"\r
+#include "compiler.h"\r
+#include "evk1101.h"\r
+#include "led.h"\r
+\r
+\r
+//! Structure describing LED hardware connections.\r
+typedef const struct\r
+{\r
+ struct\r
+ {\r
+ U32 PORT; //!< LED GPIO port.\r
+ U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.\r
+ } GPIO; //!< LED GPIO descriptor.\r
+ struct\r
+ {\r
+ S32 CHANNEL; //!< LED PWM channel (< 0 if N/A).\r
+ S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).\r
+ } PWM; //!< LED PWM descriptor.\r
+} tLED_DESCRIPTOR;\r
+\r
+\r
+//! Hardware descriptors of all LEDs.\r
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =\r
+{\r
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \\r
+ { \\r
+ {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\\r
+ {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \\r
+ },\r
+ MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)\r
+#undef INSERT_LED_DESCRIPTOR\r
+};\r
+\r
+\r
+//! Saved state of all LEDs.\r
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;\r
+\r
+\r
+U32 LED_Read_Display(void)\r
+{\r
+ return LED_State;\r
+}\r
+\r
+\r
+void LED_Display(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ LED_State = leds;\r
+ for (led_descriptor = &LED_DESCRIPTOR[0];\r
+ led_descriptor < LED_DESCRIPTOR + LED_COUNT;\r
+ led_descriptor++)\r
+ {\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Mask(U32 mask)\r
+{\r
+ return Rd_bits(LED_State, mask);\r
+}\r
+\r
+\r
+void LED_Display_Mask(U32 mask, U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ mask &= (1 << LED_COUNT) - 1;\r
+ Wr_bits(LED_State, mask, leds);\r
+ while (mask)\r
+ {\r
+ led_shift = 1 + ctz(mask);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ leds >>= led_shift - 1;\r
+ if (leds & 1)\r
+ {\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= 1;\r
+ mask >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+Bool LED_Test(U32 leds)\r
+{\r
+ return Tst_bits(LED_State, leds);\r
+}\r
+\r
+\r
+void LED_Off(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Clr_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_On(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Set_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+void LED_Toggle(U32 leds)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ leds &= (1 << LED_COUNT) - 1;\r
+ Tgl_bits(LED_State, leds);\r
+ while (leds)\r
+ {\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;\r
+ led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;\r
+ leds >>= led_shift;\r
+ }\r
+}\r
+\r
+\r
+U32 LED_Read_Display_Field(U32 field)\r
+{\r
+ return Rd_bitfield(LED_State, field);\r
+}\r
+\r
+\r
+void LED_Display_Field(U32 field, U32 leds)\r
+{\r
+ LED_Display_Mask(field, leds << ctz(field));\r
+}\r
+\r
+\r
+U8 LED_Get_Intensity(U32 led)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor;\r
+\r
+ // Check that the argument value is valid.\r
+ led = ctz(led);\r
+ led_descriptor = &LED_DESCRIPTOR[led];\r
+ if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;\r
+\r
+ // Return the duty cycle value if the LED PWM channel is enabled, else 0.\r
+ return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?\r
+ AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;\r
+}\r
+\r
+\r
+void LED_Set_Intensity(U32 leds, U8 intensity)\r
+{\r
+ tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;\r
+ volatile avr32_pwm_channel_t *led_pwm_channel;\r
+ volatile avr32_gpio_port_t *led_gpio_port;\r
+ U8 led_shift;\r
+\r
+ // For each specified LED...\r
+ for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)\r
+ {\r
+ // Select the next specified LED and check that it has a PWM channel.\r
+ led_shift = 1 + ctz(leds);\r
+ led_descriptor += led_shift;\r
+ if (led_descriptor->PWM.CHANNEL < 0) continue;\r
+\r
+ // Initialize or update the LED PWM channel.\r
+ led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];\r
+ if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))\r
+ {\r
+ led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &\r
+ ~(AVR32_PWM_CALG_MASK |\r
+ AVR32_PWM_CPOL_MASK |\r
+ AVR32_PWM_CPD_MASK);\r
+ led_pwm_channel->cprd = 0x000000FF;\r
+ led_pwm_channel->cdty = intensity;\r
+ AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;\r
+ }\r
+ else\r
+ {\r
+ AVR32_PWM.isr;\r
+ while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));\r
+ led_pwm_channel->cupd = intensity;\r
+ }\r
+\r
+ // Switch the LED pin to its PWM function.\r
+ led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];\r
+ if (led_descriptor->PWM.FUNCTION & 0x1)\r
+ {\r
+ led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ if (led_descriptor->PWM.FUNCTION & 0x2)\r
+ {\r
+ led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ else\r
+ {\r
+ led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+ led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;\r
+ }\r
+}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AT32UC3B EVK1101 board LEDs support package.\r
+ *\r
+ * This file contains definitions and services related to the LED features of\r
+ * the EVK1101 board.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 AT32UC3B devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _LED_H_\r
+#define _LED_H_\r
+\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Identifiers of LEDs to Use with LED Functions\r
+ */\r
+//! @{\r
+#define LED0 0x01\r
+#define LED1 0x02\r
+#define LED2 0x04\r
+#define LED3 0x08\r
+//! @}\r
+\r
+\r
+/*! \brief Gets the last state of all LEDs set through the LED API.\r
+ *\r
+ * \return State of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display(void);\r
+\r
+/*! \brief Sets the state of all LEDs.\r
+ *\r
+ * \param leds New state of all LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of all LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display(U32 leds);\r
+\r
+/*! \brief Gets the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param mask LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Mask(U32 mask);\r
+\r
+/*! \brief Sets the state of the specified LEDs.\r
+ *\r
+ * \param mask LEDs of which to set the state (1 bit per LED).\r
+ *\r
+ * \param leds New state of the specified LEDs (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Mask(U32 mask, U32 leds);\r
+\r
+/*! \brief Tests the last state of the specified LEDs set through the LED API.\r
+ *\r
+ * \param leds LEDs of which to test the state (1 bit per LED).\r
+ *\r
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else\r
+ * \c FALSE.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern Bool LED_Test(U32 leds);\r
+\r
+/*! \brief Turns off the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn off (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Off(U32 leds);\r
+\r
+/*! \brief Turns on the specified LEDs.\r
+ *\r
+ * \param leds LEDs to turn on (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_On(U32 leds);\r
+\r
+/*! \brief Toggles the specified LEDs.\r
+ *\r
+ * \param leds LEDs to toggle (1 bit per LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Toggle(U32 leds);\r
+\r
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through\r
+ * the LED API.\r
+ *\r
+ * \param field LEDs of which to get the state (1 bit per LED).\r
+ *\r
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first\r
+ * specified LED).\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U32 LED_Read_Display_Field(U32 field);\r
+\r
+/*! \brief Sets as a bit-field the state of the specified LEDs.\r
+ *\r
+ * \param field LEDs of which to set the state (1 bit per LED).\r
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with\r
+ * the first specified LED).\r
+ *\r
+ * \note The pins of the specified LEDs are set to GPIO output mode.\r
+ */\r
+extern void LED_Display_Field(U32 field, U32 leds);\r
+\r
+/*! \brief Gets the intensity of the specified LED.\r
+ *\r
+ * \param led LED of which to get the intensity (1 bit per LED; only the least\r
+ * significant set bit is used).\r
+ *\r
+ * \return Intensity of the specified LED (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channel of the specified LED is supposed to be used only by\r
+ * this module.\r
+ *\r
+ * \note The GPIO pin configuration of all LEDs is left unchanged.\r
+ */\r
+extern U8 LED_Get_Intensity(U32 led);\r
+\r
+/*! \brief Sets the intensity of the specified LEDs.\r
+ *\r
+ * \param leds LEDs of which to set the intensity (1 bit per LED).\r
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).\r
+ *\r
+ * \warning The PWM channels of the specified LEDs are supposed to be used only\r
+ * by this module.\r
+ *\r
+ * \note The pins of the specified LEDs are set to PWM output mode.\r
+ */\r
+extern void LED_Set_Intensity(U32 leds, U8 intensity);\r
+\r
+\r
+#endif // _LED_H_\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _BOARD_H_\r
#define _BOARD_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__ || __AAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
+/*! \name Base Boards\r
+ */\r
+//! @{\r
#define EVK1100 1 //!< AT32UC3A EVK1100 board.\r
+#define EVK1101 2 //!< AT32UC3B EVK1101 board.\r
+//! @}\r
+\r
+/*! \name Extension Boards\r
+ */\r
+//! @{\r
+#define EXT1102 1 //!< AT32UC3B EXT1102 board.\r
+//! @}\r
\r
#if BOARD == EVK1100\r
# include "EVK1100/evk1100.h"\r
+#elif BOARD == EVK1101\r
+# include "EVK1101/evk1101.h"\r
#else\r
# error No known AVR32 board defined\r
#endif\r
\r
+#if EXT_BOARD == EXT1102\r
+# include "EXT1102/ext1102.h"\r
+#endif\r
+\r
\r
#ifndef FRCOSC\r
# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency.\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
- * \brief Flash Controller driver.\r
+ * \brief FLASHC driver for AVR32 UC3.\r
*\r
- * This file defines a useful set of functions for the flash controller\r
- * on AVR32A devices.\r
+ * AVR32 Flash Controller driver module.\r
*\r
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
- * - Supported devices: All AVR32A devices.\r
+ * - Supported devices: All AVR32 devices with a FLASHC module can be used.\r
+ * - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
- *****************************************************************************/\r
+ ******************************************************************************/\r
\r
/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
*\r
*/\r
\r
\r
+#include <avr32/io.h>\r
+#include <stddef.h>\r
+#include "compiler.h"\r
#include "flashc.h"\r
\r
-/*! Flash command key*/\r
-#define X_KEY 0xA5000000\r
-\r
\r
-/*! Get locke error.\r
- * \warning: Flash status register (FCR) is read, and Programmming error status may be automatically\r
- * cleared when reading FCR.\r
+/*! \name FLASHC Writable Bit-Field Registers\r
*/\r
-#define Flashc_get_lockerror() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCKE_MASK)>>AVR32_FLASHC_FSR_LOCKE_OFFSET)\r
+//! @{\r
+\r
+typedef union\r
+{\r
+ unsigned long fcr;\r
+ avr32_flashc_fcr_t FCR;\r
+} u_avr32_flashc_fcr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long fcmd;\r
+ avr32_flashc_fcmd_t FCMD;\r
+} u_avr32_flashc_fcmd_t;\r
\r
-/*! Get programming error.\r
- * \warning: Flash status register (FCR) is read, and locke error status may be automatically\r
- * cleared when reading FCR.\r
+//! @}\r
+\r
+\r
+/*! \name Flash Properties\r
*/\r
-#define Flashc_get_programming_error() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_PROGE_MASK)>>AVR32_FLASHC_FSR_PROGE_OFFSET)\r
+//! @{\r
+\r
+\r
+unsigned int flashc_get_flash_size(void)\r
+{\r
+ static const unsigned int FLASH_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] =\r
+ {\r
+ 32 << 10,\r
+ 64 << 10,\r
+ 128 << 10,\r
+ 256 << 10,\r
+ 384 << 10,\r
+ 512 << 10,\r
+ 768 << 10,\r
+ 1024 << 10\r
+ };\r
+ return FLASH_SIZE[(AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FSZ_MASK) >> AVR32_FLASHC_FSR_FSZ_OFFSET];\r
+}\r
+\r
+\r
+unsigned int flashc_get_page_count(void)\r
+{\r
+ return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE;\r
+}\r
+\r
\r
-/*! Check if page is erased (used with the quick page read command result)\r
- * \warning: Flash status register (FCR) is read, and error status may be automatically\r
- * cleared when reading FCR.\r
+unsigned int flashc_get_page_count_per_region(void)\r
+{\r
+ return flashc_get_page_count() / AVR32_FLASHC_REGIONS;\r
+}\r
+\r
+\r
+unsigned int flashc_get_page_region(int page_number)\r
+{\r
+ return ((page_number >= 0) ? page_number : flashc_get_page_number()) / flashc_get_page_count_per_region();\r
+}\r
+\r
+\r
+unsigned int flashc_get_region_first_page_number(unsigned int region)\r
+{\r
+ return region * flashc_get_page_count_per_region();\r
+}\r
+\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Control\r
*/\r
-#define Flashc_is_page_erased() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>>AVR32_FLASHC_FSR_QPRR_OFFSET)\r
+//! @{\r
\r
-/*! Set: No erase is performed before programming. */\r
-#define Flashc_set_no_erase_before_programming() (AVR32_FLASHC.fcr |= AVR32_FLASHC_FCR_NEBP_MASK)\r
\r
-/*! Set: Page erase is performed before programming. */\r
-#define Flashc_set_erase_before_programming() (AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FCR_NEBP_MASK)\r
+unsigned int flashc_get_wait_state(void)\r
+{\r
+ return (AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FWS_MASK) >> AVR32_FLASHC_FCR_FWS_OFFSET;\r
+}\r
\r
\r
-/*!\r
- * Memcopy function\r
- * \param *s1 destination\r
- * \param *s2 source\r
- * \param n word numbers to copy\r
+void flashc_set_wait_state(unsigned int wait_state)\r
+{\r
+ u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};\r
+ u_avr32_flashc_fcr.FCR.fws = wait_state;\r
+ AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;\r
+}\r
+\r
+\r
+Bool flashc_is_ready_int_enabled(void)\r
+{\r
+ return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FRDY_MASK) != 0);\r
+}\r
+\r
+\r
+void flashc_enable_ready_int(Bool enable)\r
+{\r
+ u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};\r
+ u_avr32_flashc_fcr.FCR.frdy = (enable != FALSE);\r
+ AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;\r
+}\r
+\r
+\r
+Bool flashc_is_lock_error_int_enabled(void)\r
+{\r
+ return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_LOCKE_MASK) != 0);\r
+}\r
+\r
+\r
+void flashc_enable_lock_error_int(Bool enable)\r
+{\r
+ u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};\r
+ u_avr32_flashc_fcr.FCR.locke = (enable != FALSE);\r
+ AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;\r
+}\r
+\r
+\r
+Bool flashc_is_prog_error_int_enabled(void)\r
+{\r
+ return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_PROGE_MASK) != 0);\r
+}\r
+\r
+\r
+void flashc_enable_prog_error_int(Bool enable)\r
+{\r
+ u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};\r
+ u_avr32_flashc_fcr.FCR.proge = (enable != FALSE);\r
+ AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;\r
+}\r
+\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Status\r
*/\r
-U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n) {\r
- register U32 *u32pdst;\r
- register U32 i;\r
- u32pdst = s1;\r
- for (i = n; i > 0; i--) *u32pdst++ = *s2++;\r
- return s1;\r
+//! @{\r
+\r
+\r
+Bool flashc_is_ready(void)\r
+{\r
+ return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK) != 0);\r
+}\r
+\r
+\r
+void flashc_default_wait_until_ready(void)\r
+{\r
+ while (!flashc_is_ready());\r
}\r
\r
-/*!\r
- * Set number of wait state for flash controller.\r
+\r
+void (*volatile flashc_wait_until_ready)(void) = flashc_default_wait_until_ready;\r
+\r
+\r
+/*! \brief Gets the error status of the FLASHC.\r
+ *\r
+ * \return The error status of the FLASHC built up from\r
+ * \c AVR32_FLASHC_FSR_LOCKE_MASK and \c AVR32_FLASHC_FSR_PROGE_MASK.\r
+ *\r
+ * \warning This hardware error status is cleared by all functions reading the\r
+ * Flash Status Register (FSR). This function is therefore not part of\r
+ * the driver's API which instead presents \ref flashc_is_lock_error\r
+ * and \ref flashc_is_programming_error.\r
*/\r
-int flashc_set_wait_state(U16 ws)\r
+static unsigned int flashc_get_error_status(void)\r
+{\r
+ return AVR32_FLASHC.fsr & (AVR32_FLASHC_FSR_LOCKE_MASK |\r
+ AVR32_FLASHC_FSR_PROGE_MASK);\r
+}\r
+\r
+\r
+//! Sticky error status of the FLASHC.\r
+//! This variable is updated by functions that issue FLASHC commands. It\r
+//! contains the cumulated FLASHC error status of all the FLASHC commands issued\r
+//! by a function.\r
+static unsigned int flashc_error_status = 0;\r
+\r
+\r
+Bool flashc_is_lock_error(void)\r
+{\r
+ return ((flashc_error_status & AVR32_FLASHC_FSR_LOCKE_MASK) != 0);\r
+}\r
+\r
+\r
+Bool flashc_is_programming_error(void)\r
{\r
- if (ws > 1 ) return FLASHC_INVALID_INPUT;\r
- if (ws == 0) AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FWS_MASK; // update flash control register FCR\r
- if (ws == 1) AVR32_FLASHC.fcr |= AVR32_FLASHC_FWS_MASK;\r
- return FLASHC_SUCCESS;\r
+ return ((flashc_error_status & AVR32_FLASHC_FSR_PROGE_MASK) != 0);\r
}\r
\r
\r
-/*!\r
- * Page write n\r
- * \param n page number\r
- * \warning Assuming the page address is already loaded\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Command Control\r
*/\r
-void flashc_page_write_n(U16 page_n) {\r
- register U32 u32Command;\r
- u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
- u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32Command;\r
+//! @{\r
+\r
+\r
+unsigned int flashc_get_command(void)\r
+{\r
+ return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_CMD_MASK) >> AVR32_FLASHC_FCMD_CMD_OFFSET;\r
+}\r
+\r
+\r
+unsigned int flashc_get_page_number(void)\r
+{\r
+ return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_PAGEN_MASK) >> AVR32_FLASHC_FCMD_PAGEN_OFFSET;\r
+}\r
+\r
+\r
+void flashc_issue_command(unsigned int command, int page_number)\r
+{\r
+ u_avr32_flashc_fcmd_t u_avr32_flashc_fcmd;\r
+ flashc_wait_until_ready();\r
+ u_avr32_flashc_fcmd.fcmd = AVR32_FLASHC.fcmd;\r
+ u_avr32_flashc_fcmd.FCMD.cmd = command;\r
+ if (page_number >= 0) u_avr32_flashc_fcmd.FCMD.pagen = page_number;\r
+ u_avr32_flashc_fcmd.FCMD.key = AVR32_FLASHC_FCMD_KEY_KEY;\r
+ AVR32_FLASHC.fcmd = u_avr32_flashc_fcmd.fcmd;\r
+ flashc_error_status = flashc_get_error_status();\r
+ flashc_wait_until_ready();\r
}\r
\r
-/* Page write\r
- * Assuming the page address is already loaded\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Global Commands\r
*/\r
-void flashc_page_write(U16 page_n) {\r
- register U32 u32Command;\r
- u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
- u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32Command;\r
+//! @{\r
+\r
+\r
+void flashc_no_operation(void)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_NOP, -1);\r
}\r
\r
-/* Clear page buffer */\r
-void flashc_clear_page_buffer(void){\r
- register U32 u32Command;\r
- u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_CPB; // key and command clear page buffer\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32Command;\r
+\r
+void flashc_erase_all(void)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EA, -1);\r
}\r
\r
-/* Page erase\r
- * Assuming the page address is already loaded\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Protection Mechanisms\r
*/\r
-void flashc_erase_page(U16 page_n){\r
- register U32 u32Command;\r
- u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_EP; // key and command,\r
- u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32Command;\r
+//! @{\r
+\r
+\r
+Bool flashc_is_security_bit_active(void)\r
+{\r
+ return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_SECURITY_MASK) != 0);\r
}\r
\r
-/* Erase all Pages */\r
-void flashc_erase_all(void){\r
- register U32 u32Command;\r
- u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_EA; // key and command,\r
- //u32Command |= ((page_n<<AVR32_FLASHC_FCMD_PAGEN_OFFSET) & AVR32_FLASHC_FCMD_PAGEN_MASK); // update page field\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32Command;\r
- flashc_busy_wait();\r
+\r
+void flashc_activate_security_bit(void)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_SSB, -1);\r
}\r
\r
-/* Erase a page and check if OK with the quick page read command */\r
-int flashc_erase_page_and_check(U16 page_n)\r
+\r
+unsigned int flashc_get_bootloader_protected_size(void)\r
{\r
- flashc_erase_page(page_n); // erase page page_n first\r
+ unsigned int bootprot = (1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1 -\r
+ flashc_read_gp_fuse_bitfield(AVR32_FLASHC_FGPFR_BOOTPROT_OFFSET,\r
+ AVR32_FLASHC_FGPFR_BOOTPROT_SIZE);\r
+ return (bootprot) ? AVR32_FLASHC_PAGE_SIZE << bootprot : 0;\r
+}\r
\r
- flashc_busy_wait();\r
\r
- AVR32_FLASHC.fcmd = X_KEY | ((page_n<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_FCMD_CMD_QPR; // qpr on current page number\r
- while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size)\r
+{\r
+ flashc_set_gp_fuse_bitfield(AVR32_FLASHC_FGPFR_BOOTPROT_OFFSET,\r
+ AVR32_FLASHC_FGPFR_BOOTPROT_SIZE,\r
+ (1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1 -\r
+ ((bootprot_size) ?\r
+ 32 - clz((((min(max(bootprot_size, AVR32_FLASHC_PAGE_SIZE << 1),\r
+ AVR32_FLASHC_PAGE_SIZE <<\r
+ ((1 << AVR32_FLASHC_FGPFR_BOOTPROT_SIZE) - 1)) +\r
+ AVR32_FLASHC_PAGE_SIZE - 1) /\r
+ AVR32_FLASHC_PAGE_SIZE) << 1) - 1) - 1 :\r
+ 0));\r
+ return flashc_get_bootloader_protected_size();\r
+}\r
\r
- if (Flashc_is_page_erased() == 0) // check QPRR bit in FCR to have the result of the quick page read\r
- return FLASHC_FAILURE;\r
- return FLASHC_SUCCESS;\r
+\r
+Bool flashc_is_external_privileged_fetch_locked(void)\r
+{\r
+ return (!flashc_read_gp_fuse_bit(AVR32_FLASHC_FGPFR_EPFL_OFFSET));\r
}\r
\r
-/*!\r
- * Page load and write\r
- * \warning Dest is a FLASH address at a page size boundary\r
- * (assuming the page is already erased)\r
- */\r
-void flashc_page_copy_write(U32 *u32dest, const U32 *src) {\r
- register U32 u32command,pagen;\r
- flashc_memcpy(u32dest, src, AVR32_FLASHC_PAGE_SIZE / 4); // copy Src to Dest (Dest is a FLASH address at a page boundary)\r
- pagen = (U32)(((U32)u32dest-AVR32_FLASH_ADDRESS)/AVR32_FLASHC_PAGE_SIZE); // memory page addr\r
- u32command = X_KEY | ((pagen<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) |AVR32_FLASHC_FCMD_CMD_WP; // key and command\r
- flashc_busy_wait();\r
- AVR32_FLASHC.fcmd = u32command;\r
+\r
+void flashc_lock_external_privileged_fetch(Bool lock)\r
+{\r
+ flashc_set_gp_fuse_bit(AVR32_FLASHC_FGPFR_EPFL_OFFSET, !lock);\r
}\r
\r
-/* Copy data into page buffer */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-static __inline__ void flash_fill_temp_buffer(U32 u32Data, U32 u32Address)\r
+\r
+Bool flashc_is_page_region_locked(int page_number)\r
+{\r
+ return flashc_is_region_locked(flashc_get_page_region(page_number));\r
+}\r
+\r
+\r
+Bool flashc_is_region_locked(unsigned int region)\r
{\r
- *((U32*)u32Address) = u32Data;\r
+ return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCK0_MASK << (region & (AVR32_FLASHC_REGIONS - 1))) != 0);\r
}\r
\r
-/* Read word from flash\r
- * addr should be 32-bit aligned.\r
+\r
+void flashc_lock_page_region(int page_number, Bool lock)\r
+{\r
+ flashc_issue_command((lock) ? AVR32_FLASHC_FCMD_CMD_LP : AVR32_FLASHC_FCMD_CMD_UP, page_number);\r
+}\r
+\r
+\r
+void flashc_lock_region(unsigned int region, Bool lock)\r
+{\r
+ flashc_lock_page_region(flashc_get_region_first_page_number(region), lock);\r
+}\r
+\r
+\r
+void flashc_lock_all_regions(Bool lock)\r
+{\r
+ unsigned int error_status = 0;\r
+ unsigned int region = AVR32_FLASHC_REGIONS;\r
+ while (region)\r
+ {\r
+ flashc_lock_region(--region, lock);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+}\r
+\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Access to General-Purpose Fuses\r
*/\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-static __inline__ U32 flash_rd_word(U32 const* addr)\r
+//! @{\r
+\r
+\r
+Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit)\r
+{\r
+ return ((AVR32_FLASHC.fgpfr & AVR32_FLASHC_FGPFR_GPF00_MASK << (gp_fuse_bit & 0x1F)) != 0);\r
+}\r
+\r
+\r
+U32 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width)\r
+{\r
+ return AVR32_FLASHC.fgpfr >> (AVR32_FLASHC_FGPFR_GPF00_OFFSET + (pos & 0x1F)) &\r
+ ((1 << min(width, 32)) - 1);\r
+}\r
+\r
+\r
+U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte)\r
+{\r
+ return AVR32_FLASHC.fgpfr >> (AVR32_FLASHC_FGPFR_GPF00_OFFSET + ((gp_fuse_byte & 0x03) << 3));\r
+}\r
+\r
+\r
+U32 flashc_read_all_gp_fuses(void)\r
+{\r
+ return AVR32_FLASHC.fgpfr;\r
+}\r
+\r
+\r
+Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EGPB, gp_fuse_bit & 0x1F);\r
+ return (check) ? flashc_read_gp_fuse_bit(gp_fuse_bit) : TRUE;\r
+}\r
+\r
+\r
+Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check)\r
+{\r
+ unsigned int error_status = 0;\r
+ unsigned int gp_fuse_bit;\r
+ pos &= 0x1F;\r
+ width = min(width, 32);\r
+ for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++)\r
+ {\r
+ flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+ return (check) ? (flashc_read_gp_fuse_bitfield(pos, width) == (1 << width) - 1) : TRUE;\r
+}\r
+\r
+\r
+Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check)\r
+{\r
+ unsigned int error_status;\r
+ unsigned int current_gp_fuse_byte;\r
+ U32 value = flashc_read_all_gp_fuses();\r
+ flashc_erase_all_gp_fuses(FALSE);\r
+ error_status = flashc_error_status;\r
+ for (current_gp_fuse_byte = 0; current_gp_fuse_byte < 4; current_gp_fuse_byte++, value >>= 8)\r
+ {\r
+ if (current_gp_fuse_byte != gp_fuse_byte)\r
+ {\r
+ flashc_write_gp_fuse_byte(current_gp_fuse_byte, value);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ }\r
+ flashc_error_status = error_status;\r
+ return (check) ? (flashc_read_gp_fuse_byte(gp_fuse_byte) == 0xFF) : TRUE;\r
+}\r
+\r
+\r
+Bool flashc_erase_all_gp_fuses(Bool check)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EAGPF, -1);\r
+ return (check) ? (flashc_read_all_gp_fuses() == 0xFFFFFFFF) : TRUE;\r
+}\r
+\r
+\r
+void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value)\r
+{\r
+ if (!value)\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WGPB, gp_fuse_bit & 0x1F);\r
+}\r
+\r
+\r
+void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value)\r
+{\r
+ unsigned int error_status = 0;\r
+ unsigned int gp_fuse_bit;\r
+ pos &= 0x1F;\r
+ width = min(width, 32);\r
+ for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1)\r
+ {\r
+ flashc_write_gp_fuse_bit(gp_fuse_bit, value & 0x01);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+}\r
+\r
+\r
+void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value)\r
{\r
- return *addr;\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_PGPFB, (gp_fuse_byte & 0x03) | value << 2);\r
}\r
\r
-/**\r
- * This function allows to write up to 65535 bytes in the flash memory.\r
- * This function manages alignement issue (byte and page alignements).\r
+\r
+void flashc_write_all_gp_fuses(U32 value)\r
+{\r
+ unsigned int error_status = 0;\r
+ unsigned int gp_fuse_byte;\r
+ for (gp_fuse_byte = 0; gp_fuse_byte < 4; gp_fuse_byte++, value >>= 8)\r
+ {\r
+ flashc_write_gp_fuse_byte(gp_fuse_byte, value);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+}\r
+\r
+\r
+void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value)\r
+{\r
+ if (value)\r
+ flashc_erase_gp_fuse_bit(gp_fuse_bit, FALSE);\r
+ else\r
+ flashc_write_gp_fuse_bit(gp_fuse_bit, FALSE);\r
+}\r
+\r
+\r
+void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value)\r
+{\r
+ unsigned int error_status = 0;\r
+ unsigned int gp_fuse_bit;\r
+ pos &= 0x1F;\r
+ width = min(width, 32);\r
+ for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1)\r
+ {\r
+ flashc_set_gp_fuse_bit(gp_fuse_bit, value & 0x01);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+}\r
+\r
+\r
+void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value)\r
+{\r
+ unsigned int error_status;\r
+ switch (value)\r
+ {\r
+ case 0xFF:\r
+ flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE);\r
+ break;\r
+ case 0x00:\r
+ flashc_write_gp_fuse_byte(gp_fuse_byte, 0x00);\r
+ break;\r
+ default:\r
+ flashc_erase_gp_fuse_byte(gp_fuse_byte, FALSE);\r
+ error_status = flashc_error_status;\r
+ flashc_write_gp_fuse_byte(gp_fuse_byte, value);\r
+ flashc_error_status |= error_status;\r
+ }\r
+}\r
+\r
+\r
+void flashc_set_all_gp_fuses(U32 value)\r
+{\r
+ unsigned int error_status;\r
+ switch (value)\r
+ {\r
+ case 0xFFFFFFFF:\r
+ flashc_erase_all_gp_fuses(FALSE);\r
+ break;\r
+ case 0x00000000:\r
+ flashc_write_all_gp_fuses(0x00000000);\r
+ break;\r
+ default:\r
+ flashc_erase_all_gp_fuses(FALSE);\r
+ error_status = flashc_error_status;\r
+ flashc_write_all_gp_fuses(value);\r
+ flashc_error_status |= error_status;\r
+ }\r
+}\r
+\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Access to Flash Pages\r
*/\r
-int flash_wr_block(U32 * src, U32 dst, U32 n)\r
+//! @{\r
+\r
+\r
+void flashc_clear_page_buffer(void)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_CPB, -1);\r
+}\r
+\r
+\r
+Bool flashc_is_page_erased(void)\r
+{\r
+ return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK) != 0);\r
+}\r
+\r
+\r
+Bool flashc_quick_page_read(int page_number)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPR, page_number);\r
+ return flashc_is_page_erased();\r
+}\r
+\r
+\r
+Bool flashc_erase_page(int page_number, Bool check)\r
+{\r
+ Bool page_erased = TRUE;\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EP, page_number);\r
+ if (check)\r
+ {\r
+ unsigned int error_status = flashc_error_status;\r
+ page_erased = flashc_quick_page_read(-1);\r
+ flashc_error_status |= error_status;\r
+ }\r
+ return page_erased;\r
+}\r
+\r
+\r
+Bool flashc_erase_all_pages(Bool check)\r
+{\r
+ Bool all_pages_erased = TRUE;\r
+ unsigned int error_status = 0;\r
+ unsigned int page_number = flashc_get_page_count();\r
+ while (page_number)\r
+ {\r
+ all_pages_erased &= flashc_erase_page(--page_number, check);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_error_status = error_status;\r
+ return all_pages_erased;\r
+}\r
+\r
+\r
+void flashc_write_page(int page_number)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WP, page_number);\r
+}\r
+\r
+\r
+Bool flashc_check_user_page_erase(void)\r
+{\r
+ volatile U64 *user_page_ptr = (U64 *)AVR32_FLASHC_USER_PAGE;\r
+ while (user_page_ptr < (U64 *)(AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE))\r
+ {\r
+ if (*user_page_ptr++ != 0xFFFFFFFFFFFFFFFFULL)\r
+ return FALSE;\r
+ }\r
+ return TRUE;\r
+}\r
+\r
+\r
+Bool flashc_erase_user_page(Bool check)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EUP, -1);\r
+ return (check) ? flashc_check_user_page_erase() : TRUE;\r
+}\r
+\r
+\r
+void flashc_write_user_page(void)\r
+{\r
+ flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WUP, -1);\r
+}\r
+\r
+\r
+volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase)\r
+{\r
+ return flashc_memset16(dst, src | (U16)src << 8, nbytes, erase);\r
+}\r
+\r
+\r
+volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase)\r
+{\r
+ return flashc_memset32(dst, src | (U32)src << 16, nbytes, erase);\r
+}\r
+\r
+\r
+volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase)\r
{\r
- U32 u32NbWord=0;\r
- U32 u32Temp=0;\r
- U32 u32SavePageAddr=0;\r
+ return flashc_memset64(dst, src | (U64)src << 32, nbytes, erase);\r
+}\r
+\r
+\r
+volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase)\r
+{\r
+ // Use aggregated pointers to have several alignments available for a same address.\r
+ UnionCVPtr flash_array_end;\r
+ UnionVPtr dest;\r
+ Union64 source = {0};\r
+ StructCVPtr dest_end;\r
+ UnionCVPtr flash_page_source_end;\r
+ Bool incomplete_flash_page_end;\r
+ Union64 flash_dword;\r
+ UnionVPtr tmp;\r
+ unsigned int error_status = 0;\r
+ unsigned int i;\r
+\r
+ // Reformat arguments.\r
+ flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size();\r
+ dest.u8ptr = dst;\r
+ for (i = (Get_align((U32)dest.u8ptr, sizeof(U64)) - 1) & (sizeof(U64) - 1);\r
+ src; i = (i - 1) & (sizeof(U64) - 1))\r
+ {\r
+ source.u8[i] = src;\r
+ src >>= 8;\r
+ }\r
+ dest_end.u8ptr = dest.u8ptr + nbytes;\r
+\r
+ // If destination is outside flash, go to next flash page if any.\r
+ if (dest.u8ptr < AVR32_FLASH)\r
+ {\r
+ dest.u8ptr = AVR32_FLASH;\r
+ }\r
+ else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE)\r
+ {\r
+ dest.u8ptr = AVR32_FLASHC_USER_PAGE;\r
+ }\r
+\r
+ // If end of destination is outside flash, move it to the end of the previous flash page if any.\r
+ if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE)\r
+ {\r
+ dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE;\r
+ }\r
+ else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr)\r
+ {\r
+ dest_end.u8ptr = flash_array_end.u8ptr;\r
+ }\r
+\r
+ // Align each end of destination pointer with its natural boundary.\r
+ dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16));\r
+ dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32));\r
+ dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64));\r
+\r
+ // While end of destination is not reached...\r
+ while (dest.u8ptr < dest_end.u8ptr)\r
+ {\r
+ // Clear the page buffer in order to prepare data for a flash page write.\r
+ flashc_clear_page_buffer();\r
+ error_status |= flashc_error_status;\r
+\r
+ // Determine where the source data will end in the current flash page.\r
+ flash_page_source_end.u64ptr =\r
+ (U64 *)min((U32)dest_end.u64ptr,\r
+ Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE);\r
\r
- U32 u32Address = dst-(dst%AVR32_FLASHC_PAGE_SIZE); // Compute the start of the page to be modified\r
+ // Determine if the current destination page has an incomplete end.\r
+ incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >=\r
+ Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE));\r
\r
- while(n) // While there is data to load from src buffer\r
- {\r
- // u32Address = dst-((dst&0xFFFFffff)%AVR32_FLASHC_PAGE_SIZE); // Compute the start of the page to be modified\r
- u32SavePageAddr = (u32Address-AVR32_FLASH_ADDRESS)/AVR32_FLASHC_PAGE_SIZE; //memorize page addr\r
+ // Use a flash double-word buffer to manage unaligned accesses.\r
+ flash_dword.u64 = source.u64;\r
\r
- // For each word in this page\r
- for(u32NbWord=0 ; u32NbWord<AVR32_FLASHC_PAGE_SIZE/4 ; u32NbWord++)\r
+ // If destination does not point to the beginning of the current flash page...\r
+ if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE))\r
+ {\r
+ // If page erase is requested...\r
+ if (erase)\r
{\r
- if(n) //Still some data to load from src\r
- {\r
- if(u32Address >= dst) //current address is inside the target range adr\r
- {\r
- u32Temp = * ((U32*)src); // load word from buffer src\r
- src++;\r
- n--;\r
- }\r
- else //current word addr out of dst target\r
- {\r
- u32Temp = flash_rd_word((U32 const*)u32Address); // load word from existing flash\r
- }\r
- }\r
- else //complete page with words from existing flash\r
- {\r
- u32Temp = flash_rd_word((U32 const*)u32Address);\r
- }\r
- flash_fill_temp_buffer(u32Temp, u32Address); // fill page buffer\r
- u32Address+=4; // one more word for u32Address\r
+ // Fill the beginning of the page buffer with the current flash page data.\r
+ for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE);\r
+ tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64));\r
+ tmp.u64ptr++)\r
+ *tmp.u64ptr = *tmp.u64ptr;\r
}\r
\r
- // u32Address = u32SavePageAddr*AVR32_FLASHC_PAGE_SIZE+AVR32_FLASH_ADDRESS;\r
+ // If destination is not 64-bit aligned...\r
+ if (!Test_align((U32)dest.u8ptr, sizeof(U64)))\r
+ {\r
+ // If page erase is requested...\r
+ if (erase)\r
+ {\r
+ // Fill the beginning of the flash double-word buffer with the current flash page data.\r
+ for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++)\r
+ flash_dword.u8[i] = *tmp.u8ptr++;\r
+ }\r
+ // If page erase is not requested...\r
+ else\r
+ {\r
+ // Erase the beginning of the flash double-word buffer.\r
+ for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++)\r
+ flash_dword.u8[i] = 0xFF;\r
+ }\r
+\r
+ // Align the destination pointer with its 64-bit boundary.\r
+ dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64));\r
+\r
+ // If the current destination double-word is not the last one...\r
+ if (dest.u64ptr < dest_end.u64ptr)\r
+ {\r
+ // Write the flash double-word buffer to the page buffer and reinitialize it.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ flash_dword.u64 = source.u64;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Write the source data to the page buffer with 64-bit alignment.\r
+ for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--)\r
+ *dest.u64ptr++ = source.u64;\r
\r
- /*\r
- // Done with QPR\r
- for(u32NbWord=0 ; u32NbWord<AVR32_FLASHC_PAGE_SIZE/4 ; u32NbWord++)\r
+ // If the current destination page has an incomplete end...\r
+ if (incomplete_flash_page_end)\r
+ {\r
+ // If page erase is requested...\r
+ if (erase)\r
{\r
- if(flash_rd_word((U32 farcode*)u32Address)!=0xFFFFffff) // check if the page is erased\r
- {\r
- Flash_page_erase(u32SavePageAddr);\r
- break;\r
- }\r
- u32Address+=4;\r
+ tmp.u8ptr = (volatile U8 *)dest_end.u8ptr;\r
+\r
+ // If end of destination is not 64-bit aligned...\r
+ if (!Test_align((U32)dest_end.u8ptr, sizeof(U64)))\r
+ {\r
+ // Fill the end of the flash double-word buffer with the current flash page data.\r
+ for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++)\r
+ flash_dword.u8[i] = *tmp.u8ptr++;\r
+\r
+ // Write the flash double-word buffer to the page buffer.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+\r
+ // Fill the end of the page buffer with the current flash page data.\r
+ for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++)\r
+ *tmp.u64ptr = *tmp.u64ptr;\r
}\r
- */\r
+ // If page erase is not requested but end of destination is not 64-bit aligned...\r
+ else if (!Test_align((U32)dest_end.u8ptr, sizeof(U64)))\r
+ {\r
+ // Erase the end of the flash double-word buffer.\r
+ for (i = Get_align((U32)dest_end.u8ptr, sizeof(U64)); i < sizeof(U64); i++)\r
+ flash_dword.u8[i] = 0xFF;\r
\r
- // Check if page is erased\r
- AVR32_FLASHC.fcmd = X_KEY | ((u32SavePageAddr<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_CMD_QPR; // qpr on current page number\r
- while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+ // Write the flash double-word buffer to the page buffer.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+ }\r
+\r
+ // If the current flash page is in the flash array...\r
+ if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE)\r
+ {\r
+ // Erase the current page if requested and write it from the page buffer.\r
+ if (erase)\r
+ {\r
+ flashc_erase_page(-1, FALSE);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_write_page(-1);\r
+ error_status |= flashc_error_status;\r
\r
- if ( (AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>> AVR32_FLASHC_FSR_QPRR_OFFSET == 0 ) // test QPR bit in FSR\r
- { // erase page\r
- AVR32_FLASHC.fcmd = X_KEY | ((u32SavePageAddr<<AVR32_FLASHC_PAGEN_OFFSET)&AVR32_FLASHC_PAGEN_MASK) | AVR32_FLASHC_FCMD_CMD_EP; //page n erase cmd\r
- while(!((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK)>>AVR32_FLASHC_FSR_FRDY_OFFSET));\r
+ // If the end of the flash array is reached, go to the User page.\r
+ if (dest.u8ptr >= flash_array_end.u8ptr)\r
+ dest.u8ptr = AVR32_FLASHC_USER_PAGE;\r
}\r
+ // If the current flash page is the User page...\r
+ else\r
+ {\r
+ // Erase the User page if requested and write it from the page buffer.\r
+ if (erase)\r
+ {\r
+ flashc_erase_user_page(FALSE);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_write_user_page();\r
+ error_status |= flashc_error_status;\r
+ }\r
+ }\r
\r
- flashc_page_write_n(u32SavePageAddr); // write the corresponding page number\r
- flashc_clear_page_buffer();\r
- } // end while (n)\r
- return FLASHC_SUCCESS;\r
+ // Update the FLASHC error status.\r
+ flashc_error_status = error_status;\r
+\r
+ // Return the initial destination pointer as the standard memset function does.\r
+ return dst;\r
}\r
\r
-/* Erase all flash with pages access */\r
-void flash_erase(void)\r
+\r
+volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase)\r
{\r
- U32 u32NbPage = flashc_get_page_count();\r
- while (u32NbPage) flashc_erase_page(--u32NbPage);\r
+ // Use aggregated pointers to have several alignments available for a same address.\r
+ UnionCVPtr flash_array_end;\r
+ UnionVPtr dest;\r
+ UnionCPtr source;\r
+ StructCVPtr dest_end;\r
+ UnionCVPtr flash_page_source_end;\r
+ Bool incomplete_flash_page_end;\r
+ Union64 flash_dword;\r
+ Bool flash_dword_pending = FALSE;\r
+ UnionVPtr tmp;\r
+ unsigned int error_status = 0;\r
+ unsigned int i, j;\r
+\r
+ // Reformat arguments.\r
+ flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size();\r
+ dest.u8ptr = dst;\r
+ source.u8ptr = src;\r
+ dest_end.u8ptr = dest.u8ptr + nbytes;\r
+\r
+ // If destination is outside flash, go to next flash page if any.\r
+ if (dest.u8ptr < AVR32_FLASH)\r
+ {\r
+ source.u8ptr += AVR32_FLASH - dest.u8ptr;\r
+ dest.u8ptr = AVR32_FLASH;\r
+ }\r
+ else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE)\r
+ {\r
+ source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr;\r
+ dest.u8ptr = AVR32_FLASHC_USER_PAGE;\r
+ }\r
+\r
+ // If end of destination is outside flash, move it to the end of the previous flash page if any.\r
+ if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE)\r
+ {\r
+ dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE;\r
+ }\r
+ else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr)\r
+ {\r
+ dest_end.u8ptr = flash_array_end.u8ptr;\r
+ }\r
+\r
+ // Align each end of destination pointer with its natural boundary.\r
+ dest_end.u16ptr = (U16 *)Align_down((U32)dest_end.u8ptr, sizeof(U16));\r
+ dest_end.u32ptr = (U32 *)Align_down((U32)dest_end.u16ptr, sizeof(U32));\r
+ dest_end.u64ptr = (U64 *)Align_down((U32)dest_end.u32ptr, sizeof(U64));\r
+\r
+ // While end of destination is not reached...\r
+ while (dest.u8ptr < dest_end.u8ptr)\r
+ {\r
+ // Clear the page buffer in order to prepare data for a flash page write.\r
+ flashc_clear_page_buffer();\r
+ error_status |= flashc_error_status;\r
+\r
+ // Determine where the source data will end in the current flash page.\r
+ flash_page_source_end.u64ptr =\r
+ (U64 *)min((U32)dest_end.u64ptr,\r
+ Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE);\r
+\r
+ // Determine if the current destination page has an incomplete end.\r
+ incomplete_flash_page_end = (Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >=\r
+ Align_down((U32)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE));\r
+\r
+ // If destination does not point to the beginning of the current flash page...\r
+ if (!Test_align((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE))\r
+ {\r
+ // If page erase is requested...\r
+ if (erase)\r
+ {\r
+ // Fill the beginning of the page buffer with the current flash page data.\r
+ for (tmp.u8ptr = (U8 *)Align_down((U32)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE);\r
+ tmp.u64ptr < (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64));\r
+ tmp.u64ptr++)\r
+ *tmp.u64ptr = *tmp.u64ptr;\r
+ }\r
+\r
+ // If destination is not 64-bit aligned...\r
+ if (!Test_align((U32)dest.u8ptr, sizeof(U64)))\r
+ {\r
+ // If page erase is requested...\r
+ if (erase)\r
+ {\r
+ // Fill the beginning of the flash double-word buffer with the current flash page data.\r
+ for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++)\r
+ flash_dword.u8[i] = *tmp.u8ptr++;\r
+ }\r
+ // If page erase is not requested...\r
+ else\r
+ {\r
+ // Erase the beginning of the flash double-word buffer.\r
+ for (i = 0; i < Get_align((U32)dest.u8ptr, sizeof(U64)); i++)\r
+ flash_dword.u8[i] = 0xFF;\r
+ }\r
+\r
+ // Fill the end of the flash double-word buffer with the source data.\r
+ for (; i < sizeof(U64); i++)\r
+ flash_dword.u8[i] = *source.u8ptr++;\r
+\r
+ // Align the destination pointer with its 64-bit boundary.\r
+ dest.u64ptr = (U64 *)Align_down((U32)dest.u8ptr, sizeof(U64));\r
+\r
+ // If the current destination double-word is not the last one...\r
+ if (dest.u64ptr < dest_end.u64ptr)\r
+ {\r
+ // Write the flash double-word buffer to the page buffer.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+ // If the current destination double-word is the last one, the flash\r
+ // double-word buffer must be kept for later.\r
+ else flash_dword_pending = TRUE;\r
+ }\r
+ }\r
+\r
+ // Read the source data with the maximal possible alignment and write it to\r
+ // the page buffer with 64-bit alignment.\r
+ switch (Get_align((U32)source.u8ptr, sizeof(U32)))\r
+ {\r
+ case 0:\r
+ for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--)\r
+ *dest.u64ptr++ = *source.u64ptr++;\r
+ break;\r
+\r
+ case sizeof(U16):\r
+ for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--)\r
+ {\r
+ for (j = 0; j < sizeof(U64) / sizeof(U16); j++) flash_dword.u16[j] = *source.u16ptr++;\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--)\r
+ {\r
+ for (j = 0; j < sizeof(U64); j++) flash_dword.u8[j] = *source.u8ptr++;\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+ }\r
+\r
+ // If the current destination page has an incomplete end...\r
+ if (incomplete_flash_page_end)\r
+ {\r
+ // If the flash double-word buffer is in use, do not initialize it.\r
+ if (flash_dword_pending) i = Get_align((U32)dest_end.u8ptr, sizeof(U64));\r
+ // If the flash double-word buffer is free...\r
+ else\r
+ {\r
+ // Fill the beginning of the flash double-word buffer with the source data.\r
+ for (i = 0; i < Get_align((U32)dest_end.u8ptr, sizeof(U64)); i++)\r
+ flash_dword.u8[i] = *source.u8ptr++;\r
+ }\r
+\r
+ // If page erase is requested...\r
+ if (erase)\r
+ {\r
+ tmp.u8ptr = (volatile U8 *)dest_end.u8ptr;\r
+\r
+ // If end of destination is not 64-bit aligned...\r
+ if (!Test_align((U32)dest_end.u8ptr, sizeof(U64)))\r
+ {\r
+ // Fill the end of the flash double-word buffer with the current flash page data.\r
+ for (; i < sizeof(U64); i++)\r
+ flash_dword.u8[i] = *tmp.u8ptr++;\r
+\r
+ // Write the flash double-word buffer to the page buffer.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+\r
+ // Fill the end of the page buffer with the current flash page data.\r
+ for (; !Test_align((U32)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++)\r
+ *tmp.u64ptr = *tmp.u64ptr;\r
+ }\r
+ // If page erase is not requested but end of destination is not 64-bit aligned...\r
+ else if (!Test_align((U32)dest_end.u8ptr, sizeof(U64)))\r
+ {\r
+ // Erase the end of the flash double-word buffer.\r
+ for (; i < sizeof(U64); i++)\r
+ flash_dword.u8[i] = 0xFF;\r
+\r
+ // Write the flash double-word buffer to the page buffer.\r
+ *dest.u64ptr++ = flash_dword.u64;\r
+ }\r
+ }\r
+\r
+ // If the current flash page is in the flash array...\r
+ if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE)\r
+ {\r
+ // Erase the current page if requested and write it from the page buffer.\r
+ if (erase)\r
+ {\r
+ flashc_erase_page(-1, FALSE);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_write_page(-1);\r
+ error_status |= flashc_error_status;\r
+\r
+ // If the end of the flash array is reached, go to the User page.\r
+ if (dest.u8ptr >= flash_array_end.u8ptr)\r
+ {\r
+ source.u8ptr += AVR32_FLASHC_USER_PAGE - dest.u8ptr;\r
+ dest.u8ptr = AVR32_FLASHC_USER_PAGE;\r
+ }\r
+ }\r
+ // If the current flash page is the User page...\r
+ else\r
+ {\r
+ // Erase the User page if requested and write it from the page buffer.\r
+ if (erase)\r
+ {\r
+ flashc_erase_user_page(FALSE);\r
+ error_status |= flashc_error_status;\r
+ }\r
+ flashc_write_user_page();\r
+ error_status |= flashc_error_status;\r
+ }\r
+ }\r
+\r
+ // Update the FLASHC error status.\r
+ flashc_error_status = error_status;\r
+\r
+ // Return the initial destination pointer as the standard memcpy function does.\r
+ return dst;\r
}\r
+\r
+\r
+//! @}\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
- * \brief Flash Controller driver .h file.\r
+ * \brief FLASHC driver for AVR32 UC3.\r
*\r
- * This file defines a useful set of functions for the flash controller\r
- * on AVR32A devices.\r
+ * AVR32 Flash Controller driver module.\r
*\r
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
- * - Supported devices: All AVR32A devices.\r
+ * - Supported devices: All AVR32 devices with a FLASHC module can be used.\r
+ * - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
- *****************************************************************************/\r
+ ******************************************************************************/\r
\r
/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
*\r
#ifndef _FLASHC_H_\r
#define _FLASHC_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-# include <avr32/uc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
+#include <stddef.h>\r
#include "compiler.h"\r
\r
\r
-/*! Value returned by function when it completed successfully */\r
-#define FLASHC_SUCCESS 0\r
-\r
-/*! Value returned by function when it was unable to complete successfully\r
- for some unspecified reason */\r
-#define FLASHC_FAILURE -1\r
-\r
-/*! Value returned by function when the input paramters are out of range */\r
-#define FLASHC_INVALID_INPUT 1\r
-\r
-\r
-/*! Get Flash size */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-extern __inline__ unsigned int flashc_get_flash_size(void)\r
-{\r
- static const unsigned int FLASHC_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] =\r
- {\r
- 32 << 10,\r
- 64 << 10,\r
- 128 << 10,\r
- 256 << 10,\r
- 384 << 10,\r
- 512 << 10,\r
- 768 << 10,\r
- 1024 << 10\r
- };\r
-\r
- return FLASHC_SIZE[Rd_bitfield(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FSZ_MASK)];\r
-}\r
-\r
-/*! Get Flash page count */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-extern __inline__ unsigned int flashc_get_page_count(void)\r
-{\r
- return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE;\r
-}\r
-\r
-/*! Get Flash page count per region */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-extern __inline__ unsigned int flashc_get_page_count_per_region(void)\r
-{\r
- return flashc_get_page_count() / 16;\r
-}\r
-\r
-/*! Wait flash ready status, the application must wait before running a new command.\r
- * Warning: Flash status register (FCR) is read, and error status may be automatically\r
- * cleared when reading FCR.\r
- */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-extern __inline__ void flashc_busy_wait(void)\r
-{\r
- while (!Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FRDY_MASK));\r
-}\r
-\r
-/*! Check if security bit is active.\r
- * \warning: Flash status register (FCR) is read, and error status may be automatically\r
- * cleared when reading FCR.\r
- */\r
-#if __GNUC__\r
-__attribute__((__always_inline__))\r
-#endif\r
-extern __inline__ Bool flashc_is_security_active(void)\r
-{\r
- return Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_SECURITY_MASK);\r
-}\r
-\r
-/*! \brief Memcopy function\r
- * \param *s1 destination\r
- * \param *s2 source\r
- * \param n number of words to copy\r
- */\r
-extern U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n);\r
-\r
-/*! \brief Set number of wait state\r
- * \param ws 0 if for no-wait state, for 1 wait-state\r
- * \return FLASHC_SUCCESS, FLASHC_INVALID_INPUT or FLASHC_FAILURE\r
- */\r
-extern int flashc_set_wait_state(U16 ws);\r
-\r
-/*! \brief Page write number n. Assuming page bubuffer is already loaded.\r
- * \param n Page number\r
- */\r
-extern void flashc_page_write_n(U16 n);\r
-\r
-/*! \brief Page write\r
- * Assuming the page address is already loaded\r
- */\r
-extern void flashc_page_write(U16 page_n);\r
-\r
-/*! \brief Clear page buffer\r
+//! Number of flash regions defined by the FLASHC.\r
+#define AVR32_FLASHC_REGIONS (AVR32_FLASHC_FLASH_SIZE /\\r
+ (AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE))\r
+\r
+\r
+/*! \name Flash Properties\r
*/\r
-extern void flashc_clear_page_buffer(void);\r
+//! @{\r
+\r
+/*! \brief Gets the size of the whole flash array.\r
+ *\r
+ * \return The size of the whole flash array in bytes.\r
+ */\r
+extern unsigned int flashc_get_flash_size(void);\r
+\r
+/*! \brief Gets the total number of pages in the flash array.\r
+ *\r
+ * \return The total number of pages in the flash array.\r
+ */\r
+extern unsigned int flashc_get_page_count(void);\r
+\r
+/*! \brief Gets the number of pages in each flash region.\r
+ *\r
+ * \return The number of pages in each flash region.\r
+ */\r
+extern unsigned int flashc_get_page_count_per_region(void);\r
+\r
+/*! \brief Gets the region number of a page.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ *\r
+ * \return The region number of the specified page.\r
+ */\r
+extern unsigned int flashc_get_page_region(int page_number);\r
+\r
+/*! \brief Gets the number of the first page of a region.\r
+ *\r
+ * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>.\r
+ *\r
+ * \return The number of the first page of the specified region.\r
+ */\r
+extern unsigned int flashc_get_region_first_page_number(unsigned int region);\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Control\r
+ */\r
+//! @{\r
+\r
+/*! \brief Gets the number of wait states of flash read accesses.\r
+ *\r
+ * \return The number of wait states of flash read accesses.\r
+ */\r
+extern unsigned int flashc_get_wait_state(void);\r
+\r
+/*! \brief Sets the number of wait states of flash read accesses.\r
+ *\r
+ * \param wait_state The number of wait states of flash read accesses: \c 0 to\r
+ * \c 1.\r
+ */\r
+extern void flashc_set_wait_state(unsigned int wait_state);\r
+\r
+/*! \brief Tells whether the Flash Ready interrupt is enabled.\r
+ *\r
+ * \return Whether the Flash Ready interrupt is enabled.\r
+ */\r
+extern Bool flashc_is_ready_int_enabled(void);\r
+\r
+/*! \brief Enables or disables the Flash Ready interrupt.\r
+ *\r
+ * \param enable Whether to enable the Flash Ready interrupt: \c TRUE or\r
+ * \c FALSE.\r
+ */\r
+extern void flashc_enable_ready_int(Bool enable);\r
+\r
+/*! \brief Tells whether the Lock Error interrupt is enabled.\r
+ *\r
+ * \return Whether the Lock Error interrupt is enabled.\r
+ */\r
+extern Bool flashc_is_lock_error_int_enabled(void);\r
+\r
+/*! \brief Enables or disables the Lock Error interrupt.\r
+ *\r
+ * \param enable Whether to enable the Lock Error interrupt: \c TRUE or\r
+ * \c FALSE.\r
+ */\r
+extern void flashc_enable_lock_error_int(Bool enable);\r
+\r
+/*! \brief Tells whether the Programming Error interrupt is enabled.\r
+ *\r
+ * \return Whether the Programming Error interrupt is enabled.\r
+ */\r
+extern Bool flashc_is_prog_error_int_enabled(void);\r
+\r
+/*! \brief Enables or disables the Programming Error interrupt.\r
+ *\r
+ * \param enable Whether to enable the Programming Error interrupt: \c TRUE or\r
+ * \c FALSE.\r
+ */\r
+extern void flashc_enable_prog_error_int(Bool enable);\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Status\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tells whether the FLASHC is ready to run a new command.\r
+ *\r
+ * \return Whether the FLASHC is ready to run a new command.\r
+ */\r
+extern Bool flashc_is_ready(void);\r
+\r
+/*! \brief Waits actively until the FLASHC is ready to run a new command.\r
+ *\r
+ * This is the default function assigned to \ref flashc_wait_until_ready.\r
+ */\r
+extern void flashc_default_wait_until_ready(void);\r
+\r
+//! Pointer to the function used by the driver when it needs to wait until the\r
+//! FLASHC is ready to run a new command.\r
+//! The default function is \ref flashc_default_wait_until_ready.\r
+//! The user may change this pointer to use another implementation.\r
+extern void (*volatile flashc_wait_until_ready)(void);\r
+\r
+/*! \brief Tells whether a Lock Error has occurred during the last function\r
+ * called that issued one or more FLASHC commands.\r
+ *\r
+ * \return Whether a Lock Error has occurred during the last function called\r
+ * that issued one or more FLASHC commands.\r
+ */\r
+extern Bool flashc_is_lock_error(void);\r
+\r
+/*! \brief Tells whether a Programming Error has occurred during the last\r
+ * function called that issued one or more FLASHC commands.\r
+ *\r
+ * \return Whether a Programming Error has occurred during the last function\r
+ * called that issued one or more FLASHC commands.\r
+ */\r
+extern Bool flashc_is_programming_error(void);\r
+\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Command Control\r
+ */\r
+//! @{\r
+\r
+/*! \brief Gets the last issued FLASHC command.\r
+ *\r
+ * \return The last issued FLASHC command.\r
+ */\r
+extern unsigned int flashc_get_command(void);\r
+\r
+/*! \brief Gets the current FLASHC page number.\r
+ *\r
+ * \return The current FLASHC page number.\r
+ */\r
+extern unsigned int flashc_get_page_number(void);\r
+\r
+/*! \brief Issues a FLASHC command.\r
+ *\r
+ * \param command The command: \c AVR32_FLASHC_FCMD_CMD_x.\r
+ * \param page_number The page number to apply the command to:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: use this to apply the command to the current page number\r
+ * or if the command does not apply to any page number;\r
+ * \arg this argument may have other meanings according to the command. See\r
+ * the FLASHC chapter of the MCU datasheet.\r
+ *\r
+ * \warning A Lock Error is issued if the command violates the protection\r
+ * mechanism.\r
+ *\r
+ * \warning A Programming Error is issued if the command is invalid.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_issue_command(unsigned int command, int page_number);\r
+\r
+//! @}\r
+\r
\r
-/*! \brief Page erase\r
- * Assuming the page address is already loaded\r
+/*! \name FLASHC Global Commands\r
+ */\r
+//! @{\r
+\r
+/*! \brief Issues a No Operation command to the FLASHC.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
*/\r
-extern void flashc_erase_page(U16 page_n);\r
+extern void flashc_no_operation(void);\r
\r
-/*! \brief Erase all Pages\r
+/*! \brief Issues an Erase All command to the FLASHC.\r
+ *\r
+ * This command erases all bits in the flash array, the general-purpose fuse\r
+ * bits and the Security bit. The User page is not erased.\r
+ *\r
+ * This command also ensures that all volatile memories, such as register file\r
+ * and RAMs, are erased before the Security bit is erased, i.e. deactivated.\r
+ *\r
+ * \warning A Lock Error is issued if at least one region is locked or the\r
+ * bootloader protection is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
*/\r
extern void flashc_erase_all(void);\r
\r
-/*! \brief Erase a page and check if erase is OK\r
+//! @}\r
+\r
+\r
+/*! \name FLASHC Protection Mechanisms\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tells whether the Security bit is active.\r
+ *\r
+ * \return Whether the Security bit is active.\r
+ */\r
+extern Bool flashc_is_security_bit_active(void);\r
+\r
+/*! \brief Activates the Security bit.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_activate_security_bit(void);\r
+\r
+/*! \brief Gets the bootloader protected size.\r
+ *\r
+ * \return The bootloader protected size in bytes.\r
+ */\r
+extern unsigned int flashc_get_bootloader_protected_size(void);\r
+\r
+/*! \brief Sets the bootloader protected size.\r
+ *\r
+ * \param bootprot_size The wanted bootloader protected size in bytes. If this\r
+ * size is not supported, the actual size will be the\r
+ * nearest greater available size or the maximal possible\r
+ * size if the requested size is too large.\r
+ *\r
+ * \return The actual bootloader protected size in bytes.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size);\r
+\r
+/*! \brief Tells whether external privileged fetch is locked.\r
+ *\r
+ * \return Whether external privileged fetch is locked.\r
+ */\r
+extern Bool flashc_is_external_privileged_fetch_locked(void);\r
+\r
+/*! \brief Locks or unlocks external privileged fetch.\r
+ *\r
+ * \param lock Whether to lock external privileged fetch: \c TRUE or \c FALSE.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_lock_external_privileged_fetch(Bool lock);\r
+\r
+/*! \brief Tells whether the region of a page is locked.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ *\r
+ * \return Whether the region of the specified page is locked.\r
+ */\r
+extern Bool flashc_is_page_region_locked(int page_number);\r
+\r
+/*! \brief Tells whether a region is locked.\r
+ *\r
+ * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>.\r
+ *\r
+ * \return Whether the specified region is locked.\r
*/\r
-extern int flashc_erase_page_and_check(U16 page_n);\r
+extern Bool flashc_is_region_locked(unsigned int region);\r
\r
-/*! \brief Page load and write\r
- * \warning Dest is a FLASH address at a page boundary\r
- * (assuming the page is already erased)\r
+/*! \brief Locks or unlocks the region of a page.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ * \param lock Whether to lock the region of the specified page: \c TRUE or\r
+ * \c FALSE.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
*/\r
-extern void flashc_page_copy_write(U32 *Dest, const U32 *Src) ;\r
+extern void flashc_lock_page_region(int page_number, Bool lock);\r
\r
-/*! \brief This function allows to write up to 65535 bytes in the flash memory.\r
- * This function manages alignement issue (byte and page alignements).\r
+/*! \brief Locks or unlocks a region.\r
+ *\r
+ * \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>.\r
+ * \param lock Whether to lock the specified region: \c TRUE or \c FALSE.\r
*\r
- * \param *src Address of data to write.\r
- * \param dst Start address in flash memory where write data\r
- * \param n Number of word to write\r
- * \return FLASHC_SUCCESS or FLASHC_FAILURE\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
*/\r
-extern int flash_wr_block(U32 * src, U32 dst, U32 n);\r
+extern void flashc_lock_region(unsigned int region, Bool lock);\r
+\r
+/*! \brief Locks or unlocks all regions.\r
+ *\r
+ * \param lock Whether to lock the regions: \c TRUE or \c FALSE.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_lock_all_regions(Bool lock);\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Access to General-Purpose Fuses\r
+ */\r
+//! @{\r
+\r
+/*! \brief Reads a general-purpose fuse bit.\r
+ *\r
+ * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31.\r
+ *\r
+ * \return The value of the specified general-purpose fuse bit.\r
+ */\r
+extern Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit);\r
+\r
+/*! \brief Reads a general-purpose fuse bit-field.\r
+ *\r
+ * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 31.\r
+ * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 32.\r
+ *\r
+ * \return The value of the specified general-purpose fuse bit-field.\r
+ */\r
+extern U32 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width);\r
+\r
+/*! \brief Reads a general-purpose fuse byte.\r
+ *\r
+ * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3.\r
+ *\r
+ * \return The value of the specified general-purpose fuse byte.\r
+ */\r
+extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte);\r
+\r
+/*! \brief Reads all general-purpose fuses.\r
+ *\r
+ * \return The value of all general-purpose fuses as a word.\r
+ */\r
+extern U32 flashc_read_all_gp_fuses(void);\r
+\r
+/*! \brief Erases a general-purpose fuse bit.\r
+ *\r
+ * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31.\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check);\r
+\r
+/*! \brief Erases a general-purpose fuse bit-field.\r
+ *\r
+ * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 31.\r
+ * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 32.\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check);\r
+\r
+/*! \brief Erases a general-purpose fuse byte.\r
+ *\r
+ * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3.\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check);\r
+\r
+/*! \brief Erases all general-purpose fuses.\r
+ *\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_all_gp_fuses(Bool check);\r
+\r
+/*! \brief Writes a general-purpose fuse bit.\r
+ *\r
+ * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31.\r
+ * \param value The value of the specified general-purpose fuse bit.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);\r
+\r
+/*! \brief Writes a general-purpose fuse bit-field.\r
+ *\r
+ * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 31.\r
+ * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 32.\r
+ * \param value The value of the specified general-purpose fuse bit-field.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value);\r
+\r
+/*! \brief Writes a general-purpose fuse byte.\r
+ *\r
+ * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3.\r
+ * \param value The value of the specified general-purpose fuse byte.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);\r
+\r
+/*! \brief Writes all general-purpose fuses.\r
+ *\r
+ * \param value The value of all general-purpose fuses as a word.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_all_gp_fuses(U32 value);\r
+\r
+/*! \brief Sets a general-purpose fuse bit with the appropriate erase and write\r
+ * operations.\r
+ *\r
+ * \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 31.\r
+ * \param value The value of the specified general-purpose fuse bit.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);\r
+\r
+/*! \brief Sets a general-purpose fuse bit-field with the appropriate erase and\r
+ * write operations.\r
+ *\r
+ * \param pos The bit-position of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 31.\r
+ * \param width The bit-width of the general-purpose fuse bit-field: \c 0 to\r
+ * \c 32.\r
+ * \param value The value of the specified general-purpose fuse bit-field.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active and the command\r
+ * is applied to BOOTPROT or EPFL fuses.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U32 value);\r
+\r
+/*! \brief Sets a general-purpose fuse byte with the appropriate erase and write\r
+ * operations.\r
+ *\r
+ * \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 3.\r
+ * \param value The value of the specified general-purpose fuse byte.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);\r
+\r
+/*! \brief Sets all general-purpose fuses with the appropriate erase and write\r
+ * operations.\r
+ *\r
+ * \param value The value of all general-purpose fuses as a word.\r
+ *\r
+ * \warning A Lock Error is issued if the Security bit is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_set_all_gp_fuses(U32 value);\r
+\r
+//! @}\r
+\r
+\r
+/*! \name Access to Flash Pages\r
+ */\r
+//! @{\r
+\r
+/*! \brief Clears the page buffer.\r
+ *\r
+ * This command resets all bits in the page buffer to one. Write accesses to the\r
+ * page buffer can only change page buffer bits from one to zero.\r
+ *\r
+ * \warning The page buffer is not automatically reset after a page write.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern void flashc_clear_page_buffer(void);\r
+\r
+/*! \brief Tells whether the page to which the last Quick Page Read command was\r
+ * applied was erased.\r
+ *\r
+ * \return Whether the page to which the last Quick Page Read command was\r
+ * applied was erased.\r
+ */\r
+extern Bool flashc_is_page_erased(void);\r
+\r
+/*! \brief Applies the Quick Page Read command to a page.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ *\r
+ * \return Whether the specified page is erased.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern Bool flashc_quick_page_read(int page_number);\r
+\r
+/*! \brief Erases a page.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to a page belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_page(int page_number, Bool check);\r
+\r
+/*! \brief Erases all pages within the flash array.\r
+ *\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \warning A Lock Error is issued if at least one region is locked or the\r
+ * bootloader protection is active.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_all_pages(Bool check);\r
+\r
+/*! \brief Writes a page from the page buffer.\r
+ *\r
+ * \param page_number The page number:\r
+ * \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within\r
+ * the flash array;\r
+ * \arg <tt>< 0</tt>: the current page number.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to a page belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \warning The page buffer is not automatically reset after a page write.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_page(int page_number);\r
+\r
+/*! \brief Checks whether the User page is erased.\r
+ *\r
+ * \return Whether the User page is erased.\r
+ */\r
+extern Bool flashc_check_user_page_erase(void);\r
+\r
+/*! \brief Erases the User page.\r
+ *\r
+ * \param check Whether to check erase: \c TRUE or \c FALSE.\r
+ *\r
+ * \return Whether the erase succeeded or always \c TRUE if erase check was not\r
+ * requested.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note An erase operation can only set bits.\r
+ */\r
+extern Bool flashc_erase_user_page(Bool check);\r
+\r
+/*! \brief Writes the User page from the page buffer.\r
+ *\r
+ * \warning The page buffer is not automatically reset after a page write.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ *\r
+ * \note A write operation can only clear bits.\r
+ */\r
+extern void flashc_write_user_page(void);\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the repeated \a src source byte.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Source byte.\r
+ * \param nbytes Number of bytes to set.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase);\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the repeated \a src big-endian source half-word.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Source half-word.\r
+ * \param nbytes Number of bytes to set.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase);\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the repeated \a src big-endian source word.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Source word.\r
+ * \param nbytes Number of bytes to set.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase);\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the repeated \a src big-endian source double-word.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Source double-word.\r
+ * \param nbytes Number of bytes to set.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase);\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the repeated \a src big-endian source pattern.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Source double-word.\r
+ * \param src_width \a src width in bits: 8, 16, 32 or 64.\r
+ * \param nbytes Number of bytes to set.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+#define flashc_memset(dst, src, src_width, nbytes, erase) \\r
+ TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase))\r
+\r
+/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst\r
+ * from the source pointed to by \a src.\r
+ *\r
+ * The destination areas that are not within the flash array or the User page\r
+ * are ignored.\r
+ *\r
+ * All pointer and size alignments are supported.\r
+ *\r
+ * \param dst Pointer to flash destination.\r
+ * \param src Pointer to source data.\r
+ * \param nbytes Number of bytes to copy.\r
+ * \param erase Whether to erase before writing: \c TRUE or \c FALSE.\r
+ *\r
+ * \return The value of \a dst.\r
+ *\r
+ * \warning If copying takes place between areas that overlap, the behavior is\r
+ * undefined.\r
+ *\r
+ * \warning A Lock Error is issued if the command is applied to pages belonging\r
+ * to a locked region or to the bootloader protected area.\r
+ *\r
+ * \note The FLASHC error status returned by \ref flashc_is_lock_error and\r
+ * \ref flashc_is_programming_error is updated.\r
+ */\r
+extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase);\r
+\r
+//! @}\r
\r
\r
-#endif /* #ifndef _FLASHC_H_*/\r
+#endif // _FLASHC_H_\r
* This file defines a useful set of functions for the GPIO.\r
*\r
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices with a PWM module can be used.\r
+ * - Supported devices: All AVR32 devices with a GPIO module can be used.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#ifndef _GPIO_H_\r
#define _GPIO_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
\r
/*! \name Return Values of the GPIO API\r
\r
/*! \brief Enables a specific module mode for a pin.\r
*\r
- * \param pin The pin number.\r
- * \param function The pin function.\r
+ * \param pin The pin number.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the part\r
+ * number; e.g. x = a0512) for module pins. E.g., to enable a PWM\r
+ * channel output, the pin number can be AVR32_PWM_PWM_3_PIN for PWM\r
+ * channel 3.\r
+ * \param function The pin function.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the\r
+ * part number; e.g. x = a0512) for module pin functions. E.g.,\r
+ * to enable a PWM channel output, the pin function can be\r
+ * AVR32_PWM_PWM_3_FUNCTION for PWM channel 3.\r
*\r
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.\r
*/\r
\r
/*! \brief Enables the GPIO mode of a pin.\r
*\r
- * \param pin The pin number.\r
+ * \param pin The pin number.\n\r
+ * Refer to the product header file `uc3x.h' (where x is the part\r
+ * number; e.g. x = a0512) for pin definitions. E.g., to enable the\r
+ * GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as\r
+ * AVR32_PWM_PWM_3_PIN for PWM channel 3 can also be used to release\r
+ * module pins for GPIO.\r
*/\r
extern void gpio_enable_gpio_pin(unsigned int pin);\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "preprocessor.h"\r
#include "intc.h"\r
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.\r
//! Each line handler table contains a set of pointers to interrupt handlers.\r
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \\r
-static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP];\r
+static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];\r
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);\r
#undef DECL_INT_LINE_HANDLER_TABLE\r
\r
\r
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev)\r
{\r
+ // Determine the group of the IRQ.\r
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;\r
\r
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief MACB driver for EVK1100 board.\r
+ *\r
+ * This file defines a useful set of functions for the MACB interface on\r
+ * AVR32 devices.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a MACB module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+#include <avr32/io.h>\r
+\r
+\r
+#ifdef FREERTOS_USED\r
+ #include "FreeRTOS.h" \r
+ #include "task.h"\r
+ #include "semphr.h"\r
+#endif\r
+#include "macb.h"\r
+#include "gpio.h"\r
+#include "conf_eth.h"\r
+#include "intc.h"\r
+\r
+\r
+/* Size of each receive buffer - DO NOT CHANGE. */\r
+#define RX_BUFFER_SIZE 128\r
+\r
+\r
+/* The buffer addresses written into the descriptors must be aligned so the\r
+last few bits are zero. These bits have special meaning for the MACB\r
+peripheral and cannot be used as part of the address. */\r
+#define ADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )\r
+\r
+/* Bit used within the address stored in the descriptor to mark the last\r
+descriptor in the array. */\r
+#define RX_WRAP_BIT ( ( unsigned long ) 0x02 )\r
+\r
+/* A short delay is used to wait for a buffer to become available, should\r
+one not be immediately available when trying to transmit a frame. */\r
+#define BUFFER_WAIT_DELAY ( 2 )\r
+\r
+#ifndef FREERTOS_USED\r
+#define portENTER_CRITICAL Disable_global_interrupt \r
+#define portEXIT_CRITICAL Enable_global_interrupt\r
+#define portENTER_SWITCHING_ISR() \r
+#define portEXIT_SWITCHING_ISR() \r
+#endif \r
+\r
+\r
+/* Buffer written to by the MACB DMA. Must be aligned as described by the\r
+comment above the ADDRESS_MASK definition. */\r
+#if __GNUC__\r
+static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+#elif __ICCAVR32__\r
+#pragma data_alignment=8\r
+static volatile char pcRxBuffer[ ETHERNET_CONF_NB_RX_BUFFERS * RX_BUFFER_SIZE ];\r
+#endif\r
+\r
+\r
+/* Buffer read by the MACB DMA. Must be aligned as described by the comment\r
+above the ADDRESS_MASK definition. */\r
+#if __GNUC__\r
+static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
+#elif __ICCAVR32__\r
+#pragma data_alignment=8\r
+static volatile char pcTxBuffer[ ETHERNET_CONF_NB_TX_BUFFERS * ETHERNET_CONF_TX_BUFFER_SIZE ];\r
+#endif\r
+\r
+/* Descriptors used to communicate between the program and the MACB peripheral.\r
+These descriptors hold the locations and state of the Rx and Tx buffers. */\r
+static volatile AVR32_TxTdDescriptor xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS ];\r
+static volatile AVR32_RxTdDescriptor xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS ];\r
+\r
+/* The IP and Ethernet addresses are read from the header files. */\r
+char cMACAddress[ 6 ] = { ETHERNET_CONF_ETHADDR0,ETHERNET_CONF_ETHADDR1,ETHERNET_CONF_ETHADDR2,ETHERNET_CONF_ETHADDR3,ETHERNET_CONF_ETHADDR4,ETHERNET_CONF_ETHADDR5 };\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the header file for descriptions of public functions. */\r
+\r
+/*\r
+ * Prototype for the MACB interrupt function - called by the asm wrapper.\r
+ */\r
+#ifdef FREERTOS_USED\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+#else\r
+#if __GNUC__\r
+__attribute__((__interrupt__))\r
+#elif __ICCAVR32__\r
+__interrupt\r
+#endif\r
+#endif\r
+void vMACB_ISR( void );\r
+static long prvMACB_ISR_NonNakedBehaviour( void );\r
+\r
+\r
+#if ETHERNET_CONF_USE_PHY_IT\r
+#ifdef FREERTOS_USED\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+#else\r
+#if __GNUC__\r
+__attribute__((__interrupt__))\r
+#elif __ICCAVR32__\r
+__interrupt\r
+#endif\r
+#endif\r
+void vPHY_ISR( void );\r
+static long prvPHY_ISR_NonNakedBehaviour( void );\r
+#endif\r
+\r
+\r
+/*\r
+ * Initialise both the Tx and Rx descriptors used by the MACB.\r
+ */\r
+static void prvSetupDescriptors(volatile avr32_macb_t * macb);\r
+\r
+/*\r
+ * Write our MAC address into the MACB. \r
+ */\r
+static void prvSetupMACAddress( volatile avr32_macb_t * macb );\r
+\r
+/*\r
+ * Configure the MACB for interrupts.\r
+ */\r
+static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb );\r
+\r
+/*\r
+ * Some initialisation functions.\r
+ */\r
+static Bool prvProbePHY( volatile avr32_macb_t * macb );\r
+static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress); \r
+static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue);\r
+\r
+\r
+#ifdef FREERTOS_USED\r
+/* The semaphore used by the MACB ISR to wake the MACB task. */\r
+static xSemaphoreHandle xSemaphore = NULL;\r
+#else\r
+static volatile Bool DataToRead = FALSE;\r
+#endif\r
+\r
+/* Holds the index to the next buffer from which data will be read. */\r
+volatile unsigned long ulNextRxBuffer = 0;\r
+\r
+\r
+long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame )\r
+{\r
+static unsigned long uxTxBufferIndex = 0;\r
+char *pcBuffer;\r
+unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;\r
+\r
+\r
+ /* If the length of data to be transmitted is greater than each individual\r
+ transmit buffer then the data will be split into more than one buffer.\r
+ Loop until the entire length has been buffered. */\r
+ while( ulDataBuffered < ulLength )\r
+ {\r
+ // Is a buffer available ?\r
+ while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )\r
+ {\r
+ // There is no room to write the Tx data to the Tx buffer. \r
+ // Wait a short while, then try again.\r
+#ifdef FREERTOS_USED\r
+ vTaskDelay( BUFFER_WAIT_DELAY );\r
+#else\r
+ __asm__ __volatile__ ("nop"); \r
+#endif\r
+ }\r
+ \r
+ portENTER_CRITICAL();\r
+ {\r
+ // Get the address of the buffer from the descriptor, \r
+ // then copy the data into the buffer.\r
+ pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;\r
+\r
+ // How much can we write to the buffer ?\r
+ ulDataRemainingToSend = ulLength - ulDataBuffered;\r
+ if( ulDataRemainingToSend <= ETHERNET_CONF_TX_BUFFER_SIZE )\r
+ {\r
+ // We can write all the remaining bytes.\r
+ ulLengthToSend = ulDataRemainingToSend;\r
+ }\r
+ else\r
+ {\r
+ // We can't write more than ETH_TX_BUFFER_SIZE in one go.\r
+ ulLengthToSend = ETHERNET_CONF_TX_BUFFER_SIZE;\r
+ }\r
+ // Copy the data into the buffer.\r
+ memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );\r
+ ulDataBuffered += ulLengthToSend;\r
+ // Is this the last data for the frame ? \r
+ if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )\r
+ {\r
+ // No more data remains for this frame so we can start the transmission.\r
+ ulLastBuffer = AVR32_LAST_BUFFER;\r
+ }\r
+ else\r
+ {\r
+ // More data to come for this frame.\r
+ ulLastBuffer = 0;\r
+ }\r
+ // Fill out the necessary in the descriptor to get the data sent,\r
+ // then move to the next descriptor, wrapping if necessary.\r
+ if( uxTxBufferIndex >= ( ETHERNET_CONF_NB_TX_BUFFERS - 1 ) )\r
+ {\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )\r
+ | ulLastBuffer\r
+ | AVR32_TRANSMIT_WRAP;\r
+ uxTxBufferIndex = 0;\r
+ }\r
+ else\r
+ {\r
+ xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AVR32_LENGTH_FRAME )\r
+ | ulLastBuffer;\r
+ uxTxBufferIndex++;\r
+ }\r
+ /* If this is the last buffer to be sent for this frame we can\r
+ start the transmission. */\r
+ if( ulLastBuffer )\r
+ {\r
+ macb->ncr |= AVR32_MACB_TSTART_MASK;\r
+ }\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+\r
+ return PASS;\r
+}\r
+\r
+\r
+unsigned long ulMACBInputLength( void )\r
+{\r
+register unsigned long ulIndex , ulLength = 0;\r
+unsigned int uiTemp;\r
+\r
+ // Skip any fragments. We are looking for the first buffer that contains\r
+ // data and has the SOF (start of frame) bit set.\r
+ while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )\r
+ {\r
+ // Ignoring this buffer. Mark it as free again.\r
+ uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;\r
+ xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );\r
+ ulNextRxBuffer++;\r
+ if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ }\r
+\r
+ // We are going to walk through the descriptors that make up this frame,\r
+ // but don't want to alter ulNextRxBuffer as this would prevent vMACBRead()\r
+ // from finding the data. Therefore use a copy of ulNextRxBuffer instead. \r
+ ulIndex = ulNextRxBuffer;\r
+\r
+ // Walk through the descriptors until we find the last buffer for this frame.\r
+ // The last buffer will give us the length of the entire frame.\r
+ while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength )\r
+ {\r
+ ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;\r
+ // Increment to the next buffer, wrapping if necessary.\r
+ ulIndex++;\r
+ if( ulIndex >= ETHERNET_CONF_NB_RX_BUFFERS )\r
+ {\r
+ ulIndex = 0;\r
+ }\r
+ }\r
+ return ulLength;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )\r
+{\r
+static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;\r
+static char *pcSource;\r
+register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;\r
+unsigned int uiTemp;\r
+\r
+ // Read ulSectionLength bytes from the Rx buffers. \r
+ // This is not necessarily any correspondence between the length of our Rx buffers, \r
+ // and the length of the data we are returning or the length of the data being requested.\r
+ // Therefore, between calls we have to remember not only which buffer we are currently\r
+ // processing, but our position within that buffer. \r
+ // This would be greatly simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater \r
+ // than the size of each Rx buffer, and that memory fragmentation did not occur.\r
+ \r
+ // This function should only be called after a call to ulMACBInputLength().\r
+ // This will ensure ulNextRxBuffer is set to the correct buffer. */\r
+\r
+ // vMACBRead is called with pcTo set to NULL to indicate that we are about\r
+ // to read a new frame. Any fragments remaining in the frame we were\r
+ // processing during the last call should be dropped.\r
+ if( pcTo == NULL )\r
+ {\r
+ // How many bytes are indicated as being in this buffer? \r
+ // If none then the buffer is completely full and the frame is contained within more\r
+ // than one buffer.\r
+ // Reset our state variables ready for the next read from this buffer.\r
+ pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );\r
+ ulFameBytesReadSoFar = ( unsigned long ) 0;\r
+ ulBufferPosition = ( unsigned long ) 0;\r
+ }\r
+ else\r
+ {\r
+ // Loop until we have obtained the required amount of data.\r
+ ulSectionBytesReadSoFar = 0;\r
+ while( ulSectionBytesReadSoFar < ulSectionLength )\r
+ {\r
+ // We may have already read some data from this buffer.\r
+ // How much data remains in the buffer?\r
+ ulBytesRemainingInBuffer = ( RX_BUFFER_SIZE - ulBufferPosition );\r
+\r
+ // How many more bytes do we need to read before we have the\r
+ // required amount of data?\r
+ ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;\r
+\r
+ // Do we want more data than remains in the buffer? \r
+ if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )\r
+ {\r
+ // We want more data than remains in the buffer so we can\r
+ // write the remains of the buffer to the destination, then move\r
+ // onto the next buffer to get the rest.\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );\r
+ ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;\r
+ ulFameBytesReadSoFar += ulBytesRemainingInBuffer;\r
+\r
+ // Mark the buffer as free again.\r
+ uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;\r
+ xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );\r
+ // Move onto the next buffer.\r
+ ulNextRxBuffer++;\r
+ \r
+ if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = ( unsigned long ) 0;\r
+ }\r
+ \r
+ // Reset the variables for the new buffer.\r
+ pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );\r
+ ulBufferPosition = ( unsigned long ) 0;\r
+ }\r
+ else\r
+ {\r
+ // We have enough data in this buffer to send back.\r
+ // Read out enough data and remember how far we read up to.\r
+ memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );\r
+\r
+ // There may be more data in this buffer yet.\r
+ // Increment our position in this buffer past the data we have just read.\r
+ ulBufferPosition += ulRemainingSectionBytes;\r
+ ulSectionBytesReadSoFar += ulRemainingSectionBytes;\r
+ ulFameBytesReadSoFar += ulRemainingSectionBytes;\r
+\r
+ // Have we now finished with this buffer?\r
+ if( ( ulBufferPosition >= RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )\r
+ {\r
+ // Mark the buffer as free again.\r
+ uiTemp = xRxDescriptors[ ulNextRxBuffer ].addr;\r
+ xRxDescriptors[ ulNextRxBuffer ].addr = uiTemp & ~( AVR32_OWNERSHIP_BIT );\r
+ // Move onto the next buffer.\r
+ ulNextRxBuffer++;\r
+ \r
+ if( ulNextRxBuffer >= ETHERNET_CONF_NB_RX_BUFFERS )\r
+ {\r
+ ulNextRxBuffer = 0;\r
+ }\r
+ \r
+ pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & ADDRESS_MASK );\r
+ ulBufferPosition = 0;\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+void vMACBSetMACAddress(const char * MACAddress)\r
+{\r
+ memcpy(cMACAddress, MACAddress, sizeof(cMACAddress));\r
+}\r
+\r
+Bool xMACBInit( volatile avr32_macb_t * macb )\r
+{\r
+volatile unsigned long status;\r
+\r
+ // set up registers\r
+ macb->ncr = 0;\r
+ macb->tsr = ~0UL;\r
+ macb->rsr = ~0UL;\r
+ macb->idr = ~0UL;\r
+ status = macb->isr;\r
+\r
+\r
+#if ETHERNET_CONF_USE_RMII_INTERFACE\r
+ // RMII used, set 0 to the USRIO Register\r
+ macb->usrio &= ~AVR32_MACB_RMII_MASK;\r
+#else\r
+ // RMII not used, set 1 to the USRIO Register\r
+ macb->usrio |= AVR32_MACB_RMII_MASK;\r
+#endif\r
+\r
+ // Load our MAC address into the MACB. \r
+ prvSetupMACAddress(macb);\r
+\r
+ // Setup the buffers and descriptors.\r
+ prvSetupDescriptors(macb);\r
+\r
+#if ETHERNET_CONF_SYSTEM_CLOCK <= 20000000\r
+ macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 40000000\r
+ macb->ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 80000000\r
+ macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
+#elif ETHERNET_CONF_SYSTEM_CLOCK <= 160000000\r
+ macb->ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
+#else\r
+# error System clock too fast\r
+#endif\r
+\r
+ // Are we connected?\r
+ if( prvProbePHY(macb) == TRUE )\r
+ {\r
+ // Enable the interrupt!\r
+ portENTER_CRITICAL();\r
+ {\r
+ prvSetupMACBInterrupt(macb);\r
+ }\r
+ portEXIT_CRITICAL();\r
+ // Enable Rx and Tx, plus the stats register.\r
+ macb->ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;\r
+ return (TRUE);\r
+ }\r
+ return (FALSE);\r
+}\r
+\r
+void vDisableMACBOperations(volatile avr32_macb_t * macb)\r
+{\r
+#if ETHERNET_CONF_USE_PHY_IT\r
+volatile avr32_gpio_t *gpio = &AVR32_GPIO;\r
+volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32];\r
+\r
+ gpio_port->ierc = 1 << (MACB_INTERRUPT_PIN%32);\r
+#endif\r
+\r
+ // write the MACB control register : disable Tx & Rx\r
+ macb->ncr &= ~((1 << AVR32_MACB_RE_OFFSET) | (1 << AVR32_MACB_TE_OFFSET));\r
+ // We no more want to interrupt on Rx and Tx events.\r
+ macb->idr = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;\r
+}\r
+\r
+\r
+void vClearMACBTxBuffer( void )\r
+{\r
+static unsigned long uxNextBufferToClear = 0;\r
+\r
+ // Called on Tx interrupt events to set the AVR32_TRANSMIT_OK bit in each\r
+ // Tx buffer within the frame just transmitted. This marks all the buffers\r
+ // as available again.\r
+\r
+ // The first buffer in the frame should have the bit set automatically. */\r
+ if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )\r
+ {\r
+ // Loop through the other buffers in the frame.\r
+ while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )\r
+ {\r
+ uxNextBufferToClear++;\r
+\r
+ if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+\r
+ xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;\r
+ }\r
+\r
+ // Start with the next buffer the next time a Tx interrupt is called.\r
+ uxNextBufferToClear++;\r
+\r
+ // Do we need to wrap back to the first buffer? \r
+ if( uxNextBufferToClear >= ETHERNET_CONF_NB_TX_BUFFERS )\r
+ {\r
+ uxNextBufferToClear = 0;\r
+ }\r
+ }\r
+}\r
+\r
+static void prvSetupDescriptors(volatile avr32_macb_t * macb)\r
+{\r
+unsigned long xIndex;\r
+unsigned long ulAddress;\r
+\r
+ // Initialise xRxDescriptors descriptor.\r
+ for( xIndex = 0; xIndex < ETHERNET_CONF_NB_RX_BUFFERS; ++xIndex )\r
+ {\r
+ // Calculate the address of the nth buffer within the array.\r
+ ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * RX_BUFFER_SIZE ) );\r
+\r
+ // Write the buffer address into the descriptor. \r
+ // The DMA will place the data at this address when this descriptor is being used.\r
+ // Mask off the bottom bits of the address as these have special meaning.\r
+ xRxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK;\r
+ }\r
+\r
+ // The last buffer has the wrap bit set so the MACB knows to wrap back\r
+ // to the first buffer.\r
+ xRxDescriptors[ ETHERNET_CONF_NB_RX_BUFFERS - 1 ].addr |= RX_WRAP_BIT;\r
+\r
+ // Initialise xTxDescriptors.\r
+ for( xIndex = 0; xIndex < ETHERNET_CONF_NB_TX_BUFFERS; ++xIndex )\r
+ {\r
+ // Calculate the address of the nth buffer within the array.\r
+ ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETHERNET_CONF_TX_BUFFER_SIZE ) );\r
+\r
+ // Write the buffer address into the descriptor. \r
+ // The DMA will read data from here when the descriptor is being used.\r
+ xTxDescriptors[ xIndex ].addr = ulAddress & ADDRESS_MASK;\r
+ xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;\r
+ }\r
+\r
+ // The last buffer has the wrap bit set so the MACB knows to wrap back\r
+ // to the first buffer.\r
+ xTxDescriptors[ ETHERNET_CONF_NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;\r
+\r
+ // Tell the MACB where to find the descriptors.\r
+ macb->rbqp = ( unsigned long )xRxDescriptors;\r
+ macb->tbqp = ( unsigned long )xTxDescriptors;\r
+\r
+ // Enable the copy of data into the buffers, ignore broadcasts,\r
+ // and don't copy FCS.\r
+ macb->ncfgr |= (AVR32_MACB_CAF_MASK | AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK);\r
+\r
+} \r
+\r
+static void prvSetupMACAddress( volatile avr32_macb_t * macb )\r
+{\r
+ // Must be written SA1L then SA1H.\r
+ macb->sa1b = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |\r
+ ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |\r
+ ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |\r
+ cMACAddress[ 0 ];\r
+\r
+ macb->sa1t = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |\r
+ cMACAddress[ 4 ];\r
+}\r
+\r
+static void prvSetupMACBInterrupt( volatile avr32_macb_t * macb )\r
+{\r
+#ifdef FREERTOS_USED\r
+ // Create the semaphore used to trigger the MACB task. \r
+ if (xSemaphore == NULL)\r
+ {\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ }\r
+#else \r
+ // Create the flag used to trigger the MACB polling task. \r
+ DataToRead = FALSE;\r
+#endif\r
+\r
+\r
+#ifdef FREERTOS_USED\r
+ if( xSemaphore != NULL)\r
+ {\r
+ // We start by 'taking' the semaphore so the ISR can 'give' it when the\r
+ // first interrupt occurs.\r
+ xSemaphoreTake( xSemaphore, 0 );\r
+#endif\r
+ // Setup the interrupt for MACB.\r
+ // Register the interrupt handler to the interrupt controller at interrupt level 2\r
+ INTC_register_interrupt((__int_handler)&vMACB_ISR, AVR32_MACB_IRQ, INT2);\r
+\r
+#if ETHERNET_CONF_USE_PHY_IT\r
+ /* GPIO enable interrupt upon rising edge */\r
+ gpio_enable_pin_interrupt(MACB_INTERRUPT_PIN, GPIO_FALLING_EDGE);\r
+ // Setup the interrupt for PHY.\r
+ // Register the interrupt handler to the interrupt controller at interrupt level 2\r
+ INTC_register_interrupt((__int_handler)&vPHY_ISR, (AVR32_GPIO_IRQ_0 + (MACB_INTERRUPT_PIN/8)), INT2);\r
+ /* enable interrupts on INT pin */\r
+ vWriteMDIO( macb, PHY_MICR , ( MICR_INTEN | MICR_INTOE ));\r
+ /* enable "link change" interrupt for Phy */\r
+ vWriteMDIO( macb, PHY_MISR , MISR_LINK_INT_EN );\r
+#endif\r
+\r
+ // We want to interrupt on Rx and Tx events\r
+ macb->ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;\r
+#ifdef FREERTOS_USED\r
+ }\r
+#endif\r
+}\r
+\r
+/*! Read a register on MDIO bus (access to the PHY)\r
+ * This function is looping until PHY gets ready\r
+ *\r
+ * \param macb Input. instance of the MACB to use\r
+ * \param usAddress Input. register to set.\r
+ *\r
+ * \return unsigned long data that has been read\r
+ */\r
+static unsigned long ulReadMDIO(volatile avr32_macb_t * macb, unsigned short usAddress)\r
+{\r
+unsigned long value, status;\r
+\r
+ // initiate transaction : enable management port\r
+ macb->ncr |= AVR32_MACB_NCR_MPE_MASK;\r
+ // Write the PHY configuration frame to the MAN register\r
+ macb->man = (AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
+ | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
+ | (2 << AVR32_MACB_RW_OFFSET) // Read operation\r
+ | ((ETHERNET_CONF_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
+ | (usAddress << AVR32_MACB_REGA_OFFSET); // Reg Add\r
+ // wait for PHY to be ready\r
+ do {\r
+ status = macb->nsr;\r
+ } while (!(status & AVR32_MACB_NSR_IDLE_MASK));\r
+ // read the register value in maintenance register\r
+ value = macb->man & 0x0000ffff;\r
+ // disable management port\r
+ macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
+ // return the read value\r
+ return (value);\r
+}\r
+\r
+/*! Write a given value to a register on MDIO bus (access to the PHY)\r
+ * This function is looping until PHY gets ready\r
+ *\r
+ * \param *macb Input. instance of the MACB to use\r
+ * \param usAddress Input. register to set.\r
+ * \param usValue Input. value to write.\r
+ *\r
+ */\r
+static void vWriteMDIO(volatile avr32_macb_t * macb, unsigned short usAddress, unsigned short usValue)\r
+{\r
+unsigned long status;\r
+\r
+ // initiate transaction : enable management port\r
+ macb->ncr |= AVR32_MACB_NCR_MPE_MASK;\r
+ // Write the PHY configuration frame to the MAN register\r
+ macb->man = (( AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
+ | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
+ | (1 << AVR32_MACB_RW_OFFSET) // Write operation\r
+ | ((ETHERNET_CONF_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
+ | (usAddress << AVR32_MACB_REGA_OFFSET)) // Reg Add\r
+ | (usValue & 0xffff); // Data\r
+ // wait for PHY to be ready\r
+ do {\r
+ status = macb->nsr;\r
+ } while (!(status & AVR32_MACB_NSR_IDLE_MASK));\r
+ // disable management port\r
+ macb->ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
+}\r
+\r
+static Bool prvProbePHY( volatile avr32_macb_t * macb )\r
+{\r
+volatile unsigned long mii_status, phy_ctrl;\r
+volatile unsigned long config;\r
+unsigned long upper, lower, mode, advertise, lpa;\r
+volatile unsigned long physID;\r
+\r
+ // Read Phy Identifier register 1 & 2\r
+ lower = ulReadMDIO(macb, PHY_PHYSID2);\r
+ upper = ulReadMDIO(macb, PHY_PHYSID1);\r
+ // get Phy ID, ignore Revision\r
+ physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);\r
+ // check if it match config\r
+ if (physID == ETHERNET_CONF_PHY_ID)\r
+ {\r
+ // read RBR\r
+ mode = ulReadMDIO(macb, PHY_RBR);\r
+ // set RMII mode if not done\r
+ if ((mode & RBR_RMII) != RBR_RMII)\r
+ {\r
+ // force RMII flag if strap options are wrong\r
+ mode |= RBR_RMII;\r
+ vWriteMDIO(macb, PHY_RBR, mode);\r
+ }\r
+\r
+ // set advertise register\r
+#if ETHERNET_CONF_AN_ENABLE == 1\r
+ advertise = ADVERTISE_CSMA | ADVERTISE_ALL;\r
+#else\r
+ advertise = ADVERTISE_CSMA;\r
+ #if ETHERNET_CONF_USE_100MB\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ advertise |= ADVERTISE_100FULL;\r
+ #else\r
+ advertise |= ADVERTISE_100HALF;\r
+ #endif\r
+ #else\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ advertise |= ADVERTISE_10FULL;\r
+ #else\r
+ advertise |= ADVERTISE_10HALF;\r
+ #endif\r
+ #endif\r
+#endif\r
+ // write advertise register\r
+ vWriteMDIO(macb, PHY_ADVERTISE, advertise);\r
+ // read Control register\r
+ config = ulReadMDIO(macb, PHY_BMCR);\r
+ // read Phy Control register\r
+ phy_ctrl = ulReadMDIO(macb, PHY_PHYCR);\r
+#if ETHERNET_CONF_AN_ENABLE\r
+ #if ETHERNET_CONF_AUTO_CROSS_ENABLE\r
+ // enable Auto MDIX\r
+ phy_ctrl |= PHYCR_MDIX_EN;\r
+ #else\r
+ // disable Auto MDIX\r
+ phy_ctrl &= ~PHYCR_MDIX_EN;\r
+ #if ETHERNET_CONF_CROSSED_LINK\r
+ // force direct link = Use crossed RJ45 cable\r
+ phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
+ #else\r
+ // force crossed link = Use direct RJ45 cable\r
+ phy_ctrl |= PHYCR_MDIX_FORCE;\r
+ #endif\r
+ #endif\r
+ // reset auto-negociation capability\r
+ config |= (BMCR_ANRESTART | BMCR_ANENABLE);\r
+#else\r
+ // disable Auto MDIX\r
+ phy_ctrl &= ~PHYCR_MDIX_EN;\r
+ #if ETHERNET_CONF_CROSSED_LINK\r
+ // force direct link = Use crossed RJ45 cable\r
+ phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
+ #else\r
+ // force crossed link = Use direct RJ45 cable\r
+ phy_ctrl |= PHYCR_MDIX_FORCE;\r
+ #endif\r
+ // clear AN bit\r
+ config &= ~BMCR_ANENABLE;\r
+\r
+ #if ETHERNET_CONF_USE_100MB\r
+ config |= BMCR_SPEED100;\r
+ #else\r
+ config &= ~BMCR_SPEED100;\r
+ #endif\r
+ #if ETHERNET_CONF_USE_FULL_DUPLEX\r
+ config |= BMCR_FULLDPLX;\r
+ #else\r
+ config &= ~BMCR_FULLDPLX;\r
+ #endif\r
+#endif\r
+ // update Phy ctrl register\r
+ vWriteMDIO(macb, PHY_PHYCR, phy_ctrl);\r
+\r
+ // update ctrl register\r
+ vWriteMDIO(macb, PHY_BMCR, config);\r
+\r
+ // loop while link status isn't OK\r
+ do {\r
+ mii_status = ulReadMDIO(macb, PHY_BMSR);\r
+ } while (!(mii_status & BMSR_LSTATUS));\r
+\r
+ // read the LPA configuration of the PHY\r
+ lpa = ulReadMDIO(macb, PHY_LPA);\r
+\r
+ // read the MACB config register\r
+ config = AVR32_MACB.ncfgr;\r
+\r
+ // if 100MB needed\r
+ if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL))\r
+ {\r
+ config |= AVR32_MACB_SPD_MASK;\r
+ }\r
+ else\r
+ {\r
+ config &= ~(AVR32_MACB_SPD_MASK);\r
+ }\r
+\r
+ // if FULL DUPLEX needed\r
+ if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL))\r
+ {\r
+ config |= AVR32_MACB_FD_MASK;\r
+ }\r
+ else\r
+ {\r
+ config &= ~(AVR32_MACB_FD_MASK);\r
+ }\r
+\r
+ // write the MACB config register\r
+ macb->ncfgr = config;\r
+\r
+ return TRUE;\r
+ }\r
+ return FALSE;\r
+}\r
+\r
+\r
+void vMACBWaitForInput( unsigned long ulTimeOut )\r
+{\r
+#ifdef FREERTOS_USED\r
+ // Just wait until we are signled from an ISR that data is available, or\r
+ // we simply time out.\r
+ xSemaphoreTake( xSemaphore, ulTimeOut );\r
+#else\r
+unsigned long i;\r
+ gpio_clr_gpio_pin(LED0_GPIO);\r
+ i = ulTimeOut * 1000; \r
+ // wait for an interrupt to occurs\r
+ do\r
+ {\r
+ if ( DataToRead == TRUE )\r
+ {\r
+ // IT occurs, reset interrupt flag\r
+ portENTER_CRITICAL();\r
+ DataToRead = FALSE; \r
+ portEXIT_CRITICAL();\r
+ break; \r
+ }\r
+ i--;\r
+ }\r
+ while(i != 0);\r
+ gpio_set_gpio_pin(LED0_GPIO); \r
+#endif\r
+}\r
+\r
+\r
+/*\r
+ * The MACB ISR. Handles both Tx and Rx complete interrupts.\r
+ */\r
+#ifdef FREERTOS_USED\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+#else\r
+#if __GNUC__\r
+__attribute__((__interrupt__))\r
+#elif __ICCAVR32__\r
+__interrupt\r
+#endif\r
+#endif\r
+void vMACB_ISR( void )\r
+{\r
+ // This ISR can cause a context switch, so the first statement must be a\r
+ // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ // variable declarations. \r
+ portENTER_SWITCHING_ISR();\r
+\r
+ // the return value is used by FreeRTOS to change the context if needed after rete instruction\r
+ // in standalone use, this value should be ignored \r
+ prvMACB_ISR_NonNakedBehaviour();\r
+\r
+ // Exit the ISR. If a task was woken by either a character being received\r
+ // or transmitted then a context switch will occur.\r
+ portEXIT_SWITCHING_ISR();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if __GNUC__\r
+__attribute__((__noinline__))\r
+#elif __ICCAVR32__\r
+#pragma optimize = no_inline\r
+#endif\r
+static long prvMACB_ISR_NonNakedBehaviour( void )\r
+{\r
+\r
+ // Variable definitions can be made now.\r
+ volatile unsigned long ulIntStatus, ulEventStatus;\r
+ long xSwitchRequired = FALSE;\r
+\r
+ // Find the cause of the interrupt.\r
+ ulIntStatus = AVR32_MACB.isr;\r
+ ulEventStatus = AVR32_MACB.rsr;\r
+\r
+ if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) )\r
+ {\r
+ // A frame has been received, signal the IP task so it can process\r
+ // the Rx descriptors.\r
+ portENTER_CRITICAL();\r
+#ifdef FREERTOS_USED\r
+ xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, FALSE );\r
+#else\r
+ DataToRead = TRUE; \r
+#endif \r
+ portEXIT_CRITICAL();\r
+ AVR32_MACB.rsr = AVR32_MACB_REC_MASK;\r
+ AVR32_MACB.rsr;\r
+ }\r
+\r
+ if( ulIntStatus & AVR32_MACB_TCOMP_MASK )\r
+ {\r
+ // A frame has been transmitted. Mark all the buffers used by the\r
+ // frame just transmitted as free again.\r
+ vClearMACBTxBuffer();\r
+ AVR32_MACB.tsr = AVR32_MACB_TSR_COMP_MASK;\r
+ AVR32_MACB.tsr;\r
+ }\r
+\r
+ return ( xSwitchRequired );\r
+}\r
+\r
+\r
+\r
+#if ETHERNET_CONF_USE_PHY_IT\r
+/*\r
+ * The PHY ISR. Handles Phy interrupts.\r
+ */\r
+#ifdef FREERTOS_USED\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+#else\r
+#if __GNUC__\r
+__attribute__((__interrupt__))\r
+#elif __ICCAVR32__\r
+__interrupt\r
+#endif\r
+#endif\r
+void vPHY_ISR( void )\r
+{\r
+ // This ISR can cause a context switch, so the first statement must be a\r
+ // call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ // variable declarations. \r
+ portENTER_SWITCHING_ISR();\r
+\r
+ // the return value is used by FreeRTOS to change the context if needed after rete instruction\r
+ // in standalone use, this value should be ignored \r
+ prvPHY_ISR_NonNakedBehaviour();\r
+\r
+ // Exit the ISR. If a task was woken by either a character being received\r
+ // or transmitted then a context switch will occur.\r
+ portEXIT_SWITCHING_ISR();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if __GNUC__\r
+__attribute__((__noinline__))\r
+#elif __ICCAVR32__\r
+#pragma optimize = no_inline\r
+#endif\r
+static long prvPHY_ISR_NonNakedBehaviour( void )\r
+{\r
+\r
+ // Variable definitions can be made now.\r
+ volatile unsigned long ulIntStatus, ulEventStatus;\r
+ long xSwitchRequired = FALSE;\r
+ volatile avr32_gpio_t *gpio = &AVR32_GPIO;\r
+ volatile avr32_gpio_port_t *gpio_port = &gpio->port[MACB_INTERRUPT_PIN/32];\r
+\r
+ // read Phy Interrupt register Status\r
+ ulIntStatus = ulReadMDIO(&AVR32_MACB, PHY_MISR);\r
+ \r
+ // read Phy status register\r
+ ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR);\r
+ // dummy read\r
+ ulEventStatus = ulReadMDIO(&AVR32_MACB, PHY_BMSR);\r
+\r
+ // clear interrupt flag on GPIO\r
+ gpio_port->ifrc = 1 << (MACB_INTERRUPT_PIN%32);\r
+ \r
+ return ( xSwitchRequired );\r
+}\r
+#endif\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief MACB example driver for EVK1100 board.\r
+ *\r
+ * This file defines a useful set of functions for the MACB interface on\r
+ * AVR32 devices.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a MACB module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef AVR32_MACB_H\r
+#define AVR32_MACB_H\r
+\r
+#include <avr32/io.h>\r
+\r
+#ifdef FREERTOS_USED\r
+#include <arch/sys_arch.h>\r
+#endif\r
+\r
+#include "conf_eth.h"\r
+\r
+/*! \name Rx Ring descriptor flags\r
+ */\r
+//! @{\r
+#define AVR32_MACB_RX_USED_OFFSET 0\r
+#define AVR32_MACB_RX_USED_SIZE 1\r
+#define AVR32_MACB_RX_WRAP_OFFSET 1\r
+#define AVR32_MACB_RX_WRAP_SIZE 1\r
+#define AVR32_MACB_RX_LEN_OFFSET 0\r
+#define AVR32_MACB_RX_LEN_SIZE 12\r
+#define AVR32_MACB_RX_OFFSET_OFFSET 12\r
+#define AVR32_MACB_RX_OFFSET_SIZE 2\r
+#define AVR32_MACB_RX_SOF_OFFSET 14\r
+#define AVR32_MACB_RX_SOF_SIZE 1\r
+#define AVR32_MACB_RX_EOF_OFFSET 15\r
+#define AVR32_MACB_RX_EOF_SIZE 1\r
+#define AVR32_MACB_RX_CFI_OFFSET 16\r
+#define AVR32_MACB_RX_CFI_SIZE 1\r
+//! @}\r
+\r
+/*! \name Tx Ring descriptor flags\r
+ */\r
+//! @{\r
+#define AVR32_MACB_TX_LEN_OFFSET 0\r
+#define AVR32_MACB_TX_LEN_SIZE 11\r
+#define AVR32_MACB_TX_EOF_OFFSET 15\r
+#define AVR32_MACB_TX_EOF_SIZE 1\r
+#define AVR32_MACB_TX_NOCRC_OFFSET 16\r
+#define AVR32_MACB_TX_NOCRC_SIZE 1\r
+#define AVR32_MACB_TX_EMF_OFFSET 27\r
+#define AVR32_MACB_TX_EMF_SIZE 1\r
+#define AVR32_MACB_TX_UNR_OFFSET 28\r
+#define AVR32_MACB_TX_UNR_SIZE 1\r
+#define AVR32_MACB_TX_MAXRETRY_OFFSET 29\r
+#define AVR32_MACB_TX_MAXRETRY_SIZE 1\r
+#define AVR32_MACB_TX_WRAP_OFFSET 30\r
+#define AVR32_MACB_TX_WRAP_SIZE 1\r
+#define AVR32_MACB_TX_USED_OFFSET 31\r
+#define AVR32_MACB_TX_USED_SIZE 1\r
+//! @}\r
+\r
+/*! \name Generic MII registers.\r
+ */\r
+//! @{\r
+#define PHY_BMCR 0x00 //!< Basic mode control register\r
+#define PHY_BMSR 0x01 //!< Basic mode status register\r
+#define PHY_PHYSID1 0x02 //!< PHYS ID 1\r
+#define PHY_PHYSID2 0x03 //!< PHYS ID 2\r
+#define PHY_ADVERTISE 0x04 //!< Advertisement control reg\r
+#define PHY_LPA 0x05 //!< Link partner ability reg\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+/*! \name Extended registers for DP83848\r
+ */\r
+//! @{\r
+#define PHY_RBR 0x17 //!< RMII Bypass reg\r
+#define PHY_MICR 0x11 //!< Interrupt Control reg\r
+#define PHY_MISR 0x12 //!< Interrupt Status reg\r
+#define PHY_PHYCR 0x19 //!< Phy CTRL reg\r
+//! @}\r
+#endif\r
+\r
+\r
+/*! \name Basic mode control register.\r
+ */\r
+//! @{\r
+#define BMCR_RESV 0x007f //!< Unused...\r
+#define BMCR_CTST 0x0080 //!< Collision test\r
+#define BMCR_FULLDPLX 0x0100 //!< Full duplex\r
+#define BMCR_ANRESTART 0x0200 //!< Auto negotiation restart\r
+#define BMCR_ISOLATE 0x0400 //!< Disconnect PHY from MII\r
+#define BMCR_PDOWN 0x0800 //!< Powerdown the PHY\r
+#define BMCR_ANENABLE 0x1000 //!< Enable auto negotiation\r
+#define BMCR_SPEED100 0x2000 //!< Select 100Mbps\r
+#define BMCR_LOOPBACK 0x4000 //!< TXD loopback bits\r
+#define BMCR_RESET 0x8000 //!< Reset the PHY\r
+//! @}\r
+\r
+/*! \name Basic mode status register.\r
+ */\r
+//! @{\r
+#define BMSR_ERCAP 0x0001 //!< Ext-reg capability\r
+#define BMSR_JCD 0x0002 //!< Jabber detected\r
+#define BMSR_LSTATUS 0x0004 //!< Link status\r
+#define BMSR_ANEGCAPABLE 0x0008 //!< Able to do auto-negotiation\r
+#define BMSR_RFAULT 0x0010 //!< Remote fault detected\r
+#define BMSR_ANEGCOMPLETE 0x0020 //!< Auto-negotiation complete\r
+#define BMSR_RESV 0x00c0 //!< Unused...\r
+#define BMSR_ESTATEN 0x0100 //!< Extended Status in R15\r
+#define BMSR_100FULL2 0x0200 //!< Can do 100BASE-T2 HDX\r
+#define BMSR_100HALF2 0x0400 //!< Can do 100BASE-T2 FDX\r
+#define BMSR_10HALF 0x0800 //!< Can do 10mbps, half-duplex\r
+#define BMSR_10FULL 0x1000 //!< Can do 10mbps, full-duplex\r
+#define BMSR_100HALF 0x2000 //!< Can do 100mbps, half-duplex\r
+#define BMSR_100FULL 0x4000 //!< Can do 100mbps, full-duplex\r
+#define BMSR_100BASE4 0x8000 //!< Can do 100mbps, 4k packets\r
+//! @}\r
+\r
+/*! \name Advertisement control register.\r
+ */\r
+//! @{\r
+#define ADVERTISE_SLCT 0x001f //!< Selector bits\r
+#define ADVERTISE_CSMA 0x0001 //!< Only selector supported\r
+#define ADVERTISE_10HALF 0x0020 //!< Try for 10mbps half-duplex\r
+#define ADVERTISE_1000XFULL 0x0020 //!< Try for 1000BASE-X full-duplex\r
+#define ADVERTISE_10FULL 0x0040 //!< Try for 10mbps full-duplex\r
+#define ADVERTISE_1000XHALF 0x0040 //!< Try for 1000BASE-X half-duplex\r
+#define ADVERTISE_100HALF 0x0080 //!< Try for 100mbps half-duplex\r
+#define ADVERTISE_1000XPAUSE 0x0080 //!< Try for 1000BASE-X pause\r
+#define ADVERTISE_100FULL 0x0100 //!< Try for 100mbps full-duplex\r
+#define ADVERTISE_1000XPSE_ASYM 0x0100 //!< Try for 1000BASE-X asym pause\r
+#define ADVERTISE_100BASE4 0x0200 //!< Try for 100mbps 4k packets\r
+#define ADVERTISE_PAUSE_CAP 0x0400 //!< Try for pause\r
+#define ADVERTISE_PAUSE_ASYM 0x0800 //!< Try for asymetric pause\r
+#define ADVERTISE_RESV 0x1000 //!< Unused...\r
+#define ADVERTISE_RFAULT 0x2000 //!< Say we can detect faults\r
+#define ADVERTISE_LPACK 0x4000 //!< Ack link partners response\r
+#define ADVERTISE_NPAGE 0x8000 //!< Next page bit\r
+//! @}\r
+\r
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)\r
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
+ ADVERTISE_100HALF | ADVERTISE_100FULL)\r
+\r
+/*! \name Link partner ability register.\r
+ */\r
+//! @{\r
+#define LPA_SLCT 0x001f //!< Same as advertise selector\r
+#define LPA_10HALF 0x0020 //!< Can do 10mbps half-duplex\r
+#define LPA_1000XFULL 0x0020 //!< Can do 1000BASE-X full-duplex\r
+#define LPA_10FULL 0x0040 //!< Can do 10mbps full-duplex\r
+#define LPA_1000XHALF 0x0040 //!< Can do 1000BASE-X half-duplex\r
+#define LPA_100HALF 0x0080 //!< Can do 100mbps half-duplex\r
+#define LPA_1000XPAUSE 0x0080 //!< Can do 1000BASE-X pause\r
+#define LPA_100FULL 0x0100 //!< Can do 100mbps full-duplex\r
+#define LPA_1000XPAUSE_ASYM 0x0100 //!< Can do 1000BASE-X pause asym\r
+#define LPA_100BASE4 0x0200 //!< Can do 100mbps 4k packets\r
+#define LPA_PAUSE_CAP 0x0400 //!< Can pause\r
+#define LPA_PAUSE_ASYM 0x0800 //!< Can pause asymetrically\r
+#define LPA_RESV 0x1000 //!< Unused...\r
+#define LPA_RFAULT 0x2000 //!< Link partner faulted\r
+#define LPA_LPACK 0x4000 //!< Link partner acked us\r
+#define LPA_NPAGE 0x8000 //!< Next page bit\r
+\r
+#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)\r
+#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)\r
+//! @}\r
+\r
+#if BOARD == EVK1100\r
+/*! RMII Bypass Register */\r
+#define RBR_RMII 0x0020 //!< RMII Mode\r
+/*! \name Interrupt Ctrl Register.\r
+ */\r
+//! @{\r
+#define MICR_INTEN 0x0002 //!< Enable interrupts\r
+#define MICR_INTOE 0x0001 //!< Enable INT output\r
+//! @}\r
+\r
+/*! \name Interrupt Status Register.\r
+ */\r
+//! @{\r
+#define MISR_ED_INT_EN 0x0040 //!< Energy Detect enabled\r
+#define MISR_LINK_INT_EN 0x0020 //!< Link status change enabled\r
+#define MISR_SPD_INT_EN 0x0010 //!< Speed change enabled\r
+#define MISR_DP_INT_EN 0x0008 //!< Duplex mode change enabled\r
+#define MISR_ANC_INT_EN 0x0004 //!< Auto-Neg complete enabled\r
+#define MISR_FHF_INT_EN 0x0002 //!< False Carrier enabled\r
+#define MISR_RHF_INT_EN 0x0001 //!< Receive Error enabled\r
+#define MISR_ED_INT 0x4000 //!< Energy Detect\r
+#define MISR_LINK_INT 0x2000 //!< Link status change\r
+#define MISR_SPD_INT 0x1000 //!< Speed change\r
+#define MISR_DP_INT 0x0800 //!< Duplex mode change\r
+#define MISR_ANC_INT 0x0400 //!< Auto-Neg complete\r
+#define MISR_FHF_INT 0x0200 //!< False Carrier\r
+#define MISR_RHF_INT 0x0100 //!< Receive Error\r
+//! @}\r
+\r
+/*! \name Phy Ctrl Register.\r
+ */\r
+//! @{\r
+#define PHYCR_MDIX_EN 0x8000 //!< Enable Auto MDIX\r
+#define PHYCR_MDIX_FORCE 0x4000 //!< Force MDIX crossed\r
+//! @}\r
+#endif\r
+\r
+/*! Packet structure.\r
+ */\r
+//! @{\r
+typedef struct\r
+{\r
+ char *data; \r
+ unsigned int len; \r
+} macb_packet_t;\r
+//! @}\r
+\r
+/*! Receive Transfer descriptor structure.\r
+ */\r
+//! @{\r
+typedef struct _AVR32_RxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int BroadCast:1;\r
+ unsigned int MultiCast:1;\r
+ unsigned int UniCast:1;\r
+ unsigned int ExternalAdd:1;\r
+ unsigned int Res1:1;\r
+ unsigned int Sa1Match:1;\r
+ unsigned int Sa2Match:1;\r
+ unsigned int Sa3Match:1;\r
+ unsigned int Sa4Match:1;\r
+ unsigned int TypeID:1;\r
+ unsigned int VlanTag:1;\r
+ unsigned int PriorityTag:1;\r
+ unsigned int VlanPriority:3;\r
+ unsigned int Cfi:1;\r
+ unsigned int EndOfFrame:1;\r
+ unsigned int StartOfFrame:1;\r
+ unsigned int Rxbuf_off:2;\r
+ unsigned int Res0:1;\r
+ unsigned int Length:11;\r
+ }S_Status;\r
+ }U_Status;\r
+}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor;\r
+//! @}\r
+\r
+/*! Transmit Transfer descriptor structure.\r
+ */\r
+//! @{\r
+typedef struct _AVR32_TxTdDescriptor {\r
+ unsigned int addr;\r
+ union\r
+ {\r
+ unsigned int status;\r
+ struct {\r
+ unsigned int BuffUsed:1;\r
+ unsigned int Wrap:1;\r
+ unsigned int TransmitError:1;\r
+ unsigned int TransmitUnderrun:1;\r
+ unsigned int BufExhausted:1;\r
+ unsigned int Res1:10;\r
+ unsigned int NoCrc:1;\r
+ unsigned int LastBuff:1;\r
+ unsigned int Res0:4;\r
+ unsigned int Length:11;\r
+ }S_Status;\r
+ }U_Status;\r
+}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor;\r
+//! @}\r
+\r
+/*! Mask for frame used. */\r
+#define AVR32_OWNERSHIP_BIT 0x00000001\r
+\r
+/*! Receive status defintion.\r
+ */\r
+//! @{\r
+#define AVR32_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected\r
+#define AVR32_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match\r
+#define AVR32_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match\r
+#define AVR32_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match\r
+#define AVR32_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match\r
+#define AVR32_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match\r
+#define AVR32_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match\r
+#define AVR32_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match\r
+#define AVR32_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match\r
+#define AVR32_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected\r
+#define AVR32_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected\r
+#define AVR32_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask\r
+#define AVR32_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator\r
+#define AVR32_EOF ((unsigned int) (1 << 15)) //* EOF\r
+#define AVR32_SOF ((unsigned int) (1 << 14)) //* SOF\r
+#define AVR32_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask\r
+#define AVR32_LENGTH_FRAME ((unsigned int) 0x0FFF) //* Length of frame\r
+//! @}\r
+\r
+/* Transmit Status definition */\r
+//! @{\r
+#define AVR32_TRANSMIT_OK ((unsigned int) (1 << 31)) //*\r
+#define AVR32_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor\r
+#define AVR32_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error\r
+#define AVR32_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun\r
+#define AVR32_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame\r
+#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame\r
+#define AVR32_LAST_BUFFER ((unsigned int) (1 << 15)) //*\r
+//! @}\r
+\r
+/**\r
+ * \brief Initialise the MACB driver. \r
+ * \r
+ * \param *macb Base address of the MACB\r
+ * \r
+ * \return TRUE if success, FALSE otherwise.\r
+ */\r
+Bool xMACBInit( volatile avr32_macb_t * macb );\r
+\r
+/**\r
+ * \brief Send ulLength bytes from pcFrom. This copies the buffer to one of the\r
+ * MACB Tx buffers, then indicates to the MACB that the buffer is ready.\r
+ * If lEndOfFrame is true then the data being copied is the end of the frame\r
+ * and the frame can be transmitted.\r
+ * \r
+ * \param *macb Base address of the MACB\r
+ * \param *pcFrom Address of the data buffer\r
+ * \param ulLength Length of the frame\r
+ * \param lEndOfFrame Flag for End Of Frame\r
+ * \r
+ * \return length sent.\r
+ */\r
+long lMACBSend(volatile avr32_macb_t * macb, char *pcFrom, unsigned long ulLength, long lEndOfFrame );\r
+\r
+\r
+/**\r
+ * \brief Frames can be read from the MACB in multiple sections.\r
+ * Read ulSectionLength bytes from the MACB receive buffers to pcTo.\r
+ * ulTotalFrameLength is the size of the entire frame. Generally vMACBRead\r
+ * will be repetedly called until the sum of all the ulSectionLenths totals\r
+ * the value of ulTotalFrameLength.\r
+ * \r
+ * \param *pcTo Address of the buffer\r
+ * \param ulSectionLength Length of the buffer\r
+ * \param ulTotalFrameLength Length of the frame\r
+ */ \r
+void vMACBRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength );\r
+\r
+/**\r
+ * \brief Called by the Tx interrupt, this function traverses the buffers used to\r
+ * hold the frame that has just completed transmission and marks each as\r
+ * free again.\r
+ */ \r
+void vClearMACBTxBuffer( void );\r
+\r
+/**\r
+ * \brief Suspend on a semaphore waiting either for the semaphore to be obtained\r
+ * or a timeout. The semaphore is used by the MACB ISR to indicate that\r
+ * data has been received and is ready for processing.\r
+ * \r
+ * \param ulTimeOut time to wait for an input\r
+ * \r
+ */\r
+void vMACBWaitForInput( unsigned long ulTimeOut );\r
+\r
+/**\r
+ * \brief Function to get length of the next frame in the receive buffers \r
+ * \r
+ * \return the length of the next frame in the receive buffers.\r
+ */\r
+unsigned long ulMACBInputLength( void );\r
+\r
+/**\r
+ * \brief Set the MACB Physical address (SA1B & SA1T registers).\r
+ * \r
+ * \param *MACAddress the MAC address to set.\r
+ */ \r
+void vMACBSetMACAddress(const char * MACAddress);\r
+\r
+/**\r
+ * \brief Disable MACB operations (Tx and Rx).\r
+ * \r
+ * \param *macb Base address of the MACB\r
+ */ \r
+void vDisableMACBOperations(volatile avr32_macb_t * macb);\r
+\r
+#endif\r
+\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#include "pm.h"\r
\r
\r
-void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
+/*! \name PM Writable Bit-Field Registers\r
+ */\r
+//! @{\r
+\r
+typedef union\r
{\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
- // Read\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
- // Modify\r
- oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK;\r
- // Write\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
-}\r
+ unsigned long mcctrl;\r
+ avr32_pm_mcctrl_t MCCTRL;\r
+} u_avr32_pm_mcctrl_t;\r
\r
+typedef union\r
+{\r
+ unsigned long cksel;\r
+ avr32_pm_cksel_t CKSEL;\r
+} u_avr32_pm_cksel_t;\r
\r
-void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+typedef union\r
+{\r
+ unsigned long pll;\r
+ avr32_pm_pll_t PLL;\r
+} u_avr32_pm_pll_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl0;\r
+ avr32_pm_oscctrl0_t OSCCTRL0;\r
+} u_avr32_pm_oscctrl0_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl1;\r
+ avr32_pm_oscctrl1_t OSCCTRL1;\r
+} u_avr32_pm_oscctrl1_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long oscctrl32;\r
+ avr32_pm_oscctrl32_t OSCCTRL32;\r
+} u_avr32_pm_oscctrl32_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long ier;\r
+ avr32_pm_ier_t IER;\r
+} u_avr32_pm_ier_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long idr;\r
+ avr32_pm_idr_t IDR;\r
+} u_avr32_pm_idr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long icr;\r
+ avr32_pm_icr_t ICR;\r
+} u_avr32_pm_icr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long gcctrl;\r
+ avr32_pm_gcctrl_t GCCTRL;\r
+} u_avr32_pm_gcctrl_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long rccr;\r
+ avr32_pm_rccr_t RCCR;\r
+} u_avr32_pm_rccr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long bgcr;\r
+ avr32_pm_bgcr_t BGCR;\r
+} u_avr32_pm_bgcr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long vregcr;\r
+ avr32_pm_vregcr_t VREGCR;\r
+} u_avr32_pm_vregcr_t;\r
+\r
+typedef union\r
+{\r
+ unsigned long bod;\r
+ avr32_pm_bod_t BOD;\r
+} u_avr32_pm_bod_t;\r
+\r
+//! @}\r
+\r
+\r
+/*! \brief Sets the mode of the oscillator 0.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).\r
+ */\r
+static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
// Read\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
// Modify\r
- oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
- AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3;\r
+ u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;\r
// Write\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
+ pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
}\r
\r
\r
-void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
+ pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);\r
+}\r
\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
- // Modify\r
- mcctrl.MCCTRL.osc0en = 1;\r
- oscctrl0.OSCCTRL0.startup = startup;\r
- // Write back\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
- pm->mcctrl = mcctrl.mcctrl;\r
\r
- while(!pm->ISR.osc0rdy); //For osc output valid\r
+void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)\r
+{\r
+ pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);\r
}\r
\r
\r
-void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
+ pm_enable_clk0_no_wait(pm, startup);\r
+ pm_wait_for_clk0_ready(pm);\r
+}\r
\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
\r
- // Modify\r
- mcctrl.MCCTRL.osc0en = 0;\r
-\r
- // Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
+void pm_disable_clk0(volatile avr32_pm_t *pm)\r
+{\r
+ pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;\r
}\r
\r
\r
void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl0;\r
- avr32_pm_oscctrl0_t OSCCTRL0;\r
- } oscctrl0 ;\r
-\r
// Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl0.oscctrl0 = pm->oscctrl0;\r
+ u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};\r
// Modify\r
- mcctrl.MCCTRL.osc0en = 1;\r
- oscctrl0.OSCCTRL0.startup=startup;\r
+ u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;\r
// Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
- pm->oscctrl0 = oscctrl0.oscctrl0;\r
+ pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;\r
+\r
+ pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;\r
}\r
\r
\r
void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.osc0rdy);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));\r
}\r
\r
\r
-void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
+/*! \brief Sets the mode of the oscillator 1.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).\r
+ */\r
+static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
// Read\r
- oscctrl1.oscctrl1= pm->oscctrl1;\r
+ u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
// Modify\r
- oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK;\r
+ u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;\r
// Write\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
}\r
\r
\r
-void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
+void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
- // Read\r
- oscctrl1.oscctrl1= pm->oscctrl1;\r
- // Modify\r
- oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
- AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3;\r
- // Write\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
+ pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);\r
}\r
\r
\r
-void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
-\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl1.oscctrl1 = pm->oscctrl1;\r
+ pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :\r
+ AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);\r
+}\r
\r
- mcctrl.MCCTRL.osc1en = 1;\r
- oscctrl1.OSCCTRL1.startup=startup;\r
- // Write back\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
- pm->mcctrl = mcctrl.mcctrl;\r
\r
- while(!pm->ISR.osc1rdy);\r
+void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
+ pm_enable_clk1_no_wait(pm, startup);\r
+ pm_wait_for_clk1_ready(pm);\r
}\r
\r
\r
void pm_disable_clk1(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
+ pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;\r
+}\r
\r
\r
+void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+{\r
// Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
-\r
+ u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};\r
// Modify\r
- mcctrl.MCCTRL.osc1en = 0;\r
-\r
+ u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;\r
// Write back\r
- pm->mcctrl = mcctrl.mcctrl;\r
+ pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;\r
+\r
+ pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;\r
}\r
\r
\r
-void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
+void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
- union {\r
- unsigned long oscctrl1;\r
- avr32_pm_oscctrl1_t OSCCTRL1;\r
- } oscctrl1 ;\r
-\r
- // Read register\r
- mcctrl.mcctrl = pm->mcctrl;\r
- oscctrl1.oscctrl1 = pm->oscctrl1;\r
-\r
- mcctrl.MCCTRL.osc1en = 1;\r
- oscctrl1.OSCCTRL1.startup=startup;\r
- // Write back\r
- pm->oscctrl1 = oscctrl1.oscctrl1;\r
- pm->mcctrl = mcctrl.mcctrl;\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));\r
}\r
\r
\r
-void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)\r
+/*! \brief Sets the mode of the 32-kHz oscillator.\r
+ *\r
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).\r
+ * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).\r
+ */\r
+static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)\r
{\r
- while(!pm->ISR.osc1rdy);\r
+ // Read\r
+ u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
+ // Modify\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;\r
+ // Write\r
+ pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
}\r
\r
\r
void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } u_ctrl;\r
- u_ctrl.oscctrl32 = pm->oscctrl32;\r
- u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK;\r
- pm->oscctrl32 = u_ctrl.oscctrl32;\r
+ pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);\r
}\r
\r
\r
void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } u_ctrl;\r
- u_ctrl.oscctrl32 = pm->oscctrl32;\r
- u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL;\r
- pm->oscctrl32 = u_ctrl.oscctrl32;\r
+ pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);\r
}\r
\r
\r
void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
- // Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
- // Modify\r
- oscctrl32.OSCCTRL32.osc32en = 1;\r
- oscctrl32.OSCCTRL32.startup=startup;\r
- // Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
-\r
- while(!pm->ISR.osc32rdy);\r
+ pm_enable_clk32_no_wait(pm, startup);\r
+ pm_wait_for_clk32_ready(pm);\r
}\r
\r
\r
void pm_disable_clk32(volatile avr32_pm_t *pm)\r
{\r
- // To get rid of a GCC bug\r
- // This makes C code longer, but not ASM\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
- // Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
- // Modify\r
- oscctrl32.OSCCTRL32.osc32en = 0;\r
- // Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
+ pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;\r
}\r
\r
\r
void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)\r
{\r
- union {\r
- unsigned long oscctrl32;\r
- avr32_pm_oscctrl32_t OSCCTRL32;\r
- } oscctrl32 ;\r
-\r
// Read register\r
- oscctrl32.oscctrl32 = pm->oscctrl32;\r
+ u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};\r
// Modify\r
- oscctrl32.OSCCTRL32.osc32en = 1;\r
- oscctrl32.OSCCTRL32.startup=startup;\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;\r
+ u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;\r
// Write back\r
- pm->oscctrl32 = oscctrl32.oscctrl32;\r
+ pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;\r
}\r
\r
\r
void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)\r
{\r
- // To get rid of a GCC bug\r
- // This makes C code longer, but not ASM\r
-\r
- while(!pm->ISR.osc32rdy);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));\r
}\r
\r
\r
unsigned int hsbdiv,\r
unsigned int hsbsel)\r
{\r
- // Force the compiler to generate only one 32 bits access\r
- union {\r
- avr32_pm_cksel_t selval ;\r
- unsigned long uword32;\r
- } cksel;\r
-\r
- cksel.uword32 = 0;\r
+ u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};\r
\r
- cksel.selval.cpudiv = hsbdiv;\r
- cksel.selval.cpusel = hsbsel;\r
- cksel.selval.hsbdiv = hsbdiv;\r
- cksel.selval.hsbsel = hsbsel;\r
- cksel.selval.pbbdiv = pbbdiv;\r
- cksel.selval.pbbsel = pbbsel;\r
- cksel.selval.pbadiv = pbadiv;\r
- cksel.selval.pbasel = pbasel;\r
+ u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;\r
+ u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;\r
+ u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;\r
+ u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;\r
+ u_avr32_pm_cksel.CKSEL.pbasel = pbasel;\r
+ u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;\r
+ u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;\r
+ u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;\r
\r
- pm->cksel = cksel.uword32;\r
+ pm->cksel = u_avr32_pm_cksel.cksel;\r
\r
// Wait for ckrdy bit and then clear it\r
- while(!(pm->ISR.ckrdy));\r
-\r
- return;\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));\r
}\r
\r
\r
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)\r
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1\r
unsigned int diven,\r
- unsigned int div) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
+ unsigned int div)\r
+{\r
+ u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};\r
\r
- u_gc.GCCTRL.oscsel = pll_osc;\r
- u_gc.GCCTRL.pllsel = osc_or_pll;\r
- u_gc.GCCTRL.diven = diven;\r
- u_gc.GCCTRL.div = div;\r
- u_gc.GCCTRL.cen = 0; // Disable GC first\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;\r
+ u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;\r
+ u_avr32_pm_gcctrl.GCCTRL.diven = diven;\r
+ u_avr32_pm_gcctrl.GCCTRL.div = div;\r
+\r
+ pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;\r
}\r
\r
\r
void pm_gc_enable(volatile avr32_pm_t *pm,\r
- unsigned int gc) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
- u_gc.gcctrl = pm->gcctrl[gc];\r
- u_gc.GCCTRL.cen = 1;\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ unsigned int gc)\r
+{\r
+ pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;\r
}\r
\r
\r
void pm_gc_disable(volatile avr32_pm_t *pm,\r
- unsigned int gc) {\r
- union {\r
- unsigned long gcctrl;\r
- avr32_pm_gcctrl_t GCCTRL;\r
- } u_gc;\r
- u_gc.gcctrl = pm->gcctrl[gc];\r
- u_gc.GCCTRL.cen = 0;\r
- pm->gcctrl[gc] = u_gc.gcctrl;\r
+ unsigned int gc)\r
+{\r
+ pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;\r
}\r
\r
\r
unsigned int mul,\r
unsigned int div,\r
unsigned int osc,\r
- unsigned int lockcount) {\r
-\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll=0;\r
-\r
- u_pll.PLL.pllmul = mul;\r
- u_pll.PLL.plldiv = div;\r
- u_pll.PLL.pllosc = osc;\r
- u_pll.PLL.pllcount = lockcount;\r
-\r
- u_pll.PLL.pllopt = 0;\r
+ unsigned int lockcount)\r
+{\r
+ u_avr32_pm_pll_t u_avr32_pm_pll = {0};\r
\r
- u_pll.PLL.plltest = 0;\r
+ u_avr32_pm_pll.PLL.pllosc = osc;\r
+ u_avr32_pm_pll.PLL.plldiv = div;\r
+ u_avr32_pm_pll.PLL.pllmul = mul;\r
+ u_avr32_pm_pll.PLL.pllcount = lockcount;\r
\r
- (pm->pll)[pll] = u_pll.pll;\r
+ pm->pll[pll] = u_avr32_pm_pll.pll;\r
}\r
\r
\r
unsigned int pll,\r
unsigned int pll_freq,\r
unsigned int pll_div2,\r
- unsigned int pll_wbwdisable) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2);\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll_wbwdisable)\r
+{\r
+ u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};\r
+ u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);\r
+ pm->pll[pll] = u_avr32_pm_pll.pll;\r
}\r
\r
\r
unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- return (pm->PLL)[pll].pllopt;\r
+ unsigned int pll)\r
+{\r
+ return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;\r
}\r
\r
\r
void pm_pll_enable(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllen = 1;\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll)\r
+{\r
+ pm->pll[pll] |= AVR32_PM_PLLEN_MASK;\r
}\r
\r
\r
void pm_pll_disable(volatile avr32_pm_t *pm,\r
- unsigned int pll) {\r
- union {\r
- unsigned long pll ;\r
- avr32_pm_pll_t PLL ;\r
- } u_pll;\r
-\r
- u_pll.pll = (pm->pll)[pll];\r
- u_pll.PLL.pllen = 0;\r
- (pm->pll)[pll] = u_pll.pll;\r
+ unsigned int pll)\r
+{\r
+ pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;\r
}\r
\r
\r
void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.lock0);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));\r
\r
// Bypass the lock signal of the PLL\r
pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;\r
\r
void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)\r
{\r
- while(!pm->ISR.lock1);\r
+ while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));\r
\r
// Bypass the lock signal of the PLL\r
pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;\r
\r
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)\r
{\r
- union {\r
- avr32_pm_mcctrl_t MCCTRL;\r
- unsigned long mcctrl;\r
- } mcctrl;\r
// Read\r
- mcctrl.mcctrl = pm->mcctrl;\r
+ u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};\r
// Modify\r
- mcctrl.MCCTRL.mcsel = clock;\r
- // Write Back\r
- pm->MCCTRL.mcsel = mcctrl.mcctrl;\r
+ u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;\r
+ // Write back\r
+ pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;\r
}\r
\r
\r
}\r
\r
\r
-void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long ier ;\r
- avr32_pm_ier_t IER ;\r
- } u_ier;\r
- u_ier.ier = 0;\r
- u_ier.IER.boddet = 1;\r
-\r
- pm->ier = u_ier.ier;\r
+void pm_bod_enable_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->ier = AVR32_PM_IER_BODDET_MASK;\r
}\r
\r
\r
-void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long idr ;\r
- avr32_pm_idr_t IDR ;\r
- } u_idr;\r
- u_idr.idr = 0;\r
- u_idr.IDR.boddet = 1;\r
-\r
- pm->idr = u_idr.idr;\r
+void pm_bod_disable_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->idr = AVR32_PM_IDR_BODDET_MASK;\r
}\r
\r
\r
-void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) {\r
-\r
- union {\r
- unsigned long icr ;\r
- avr32_pm_idr_t ICR ;\r
- } u_icr;\r
- u_icr.icr = 0;\r
- u_icr.ICR.boddet = 1;\r
-\r
- pm->icr = u_icr.icr;\r
+void pm_bod_clear_irq(volatile avr32_pm_t *pm)\r
+{\r
+ pm->icr = AVR32_PM_ICR_BODDET_MASK;\r
}\r
\r
\r
-unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) {\r
-\r
- return pm->ISR.boddet;\r
+unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)\r
+{\r
+ return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);\r
}\r
\r
\r
-unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) {\r
-\r
- return pm->IMR.boddet;\r
+unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)\r
+{\r
+ return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);\r
}\r
\r
\r
-unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) {\r
- union {\r
- unsigned long bod ;\r
- avr32_pm_bod_t BOD ;\r
- } u_bod;\r
-\r
- u_bod.bod = pm->bod;\r
-\r
- return (unsigned long) u_bod.BOD.level;\r
-\r
+unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)\r
+{\r
+ return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;\r
}\r
\r
\r
-void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) {\r
- (pm->gplp)[gplp] = value;\r
-\r
+void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value)\r
+{\r
+ pm->gplp[gplp] = value;\r
}\r
\r
\r
-unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) {\r
-\r
- return (pm->gplp)[gplp];\r
+unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp)\r
+{\r
+ return pm->gplp[gplp];\r
}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#ifndef _PM_H_\r
#define _PM_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-# include <avr32/uc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "preprocessor.h"\r
\r
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}\r
\r
\r
+/*! \brief Gets the MCU reset cause.\r
+ *\r
+ * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).\r
+ *\r
+ * \return The MCU reset cause which can be masked with the\r
+ * \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)\r
+{\r
+ return pm->rcause;\r
+}\r
+\r
+\r
/*!\r
* \brief This function will enable the external clock mode of the oscillator 0.\r
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "compiler.h"\r
#include "tc.h"\r
\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _TC_H_\r
#define _TC_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
\r
\r
//! TC driver functions return value in case of invalid argument(s).\r
-#define TC_INVALID_ARGUMENT -1\r
+#define TC_INVALID_ARGUMENT (-1)\r
\r
//! Number of timer/counter channels.\r
#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief USART driver for AVR32 UC3.\r
+ *\r
+ * This file contains basic functions for the AVR32 USART, with support for all\r
+ * modes, settings and clock speeds.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a USART module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "usart.h"\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Private Functions\r
+ */\r
+//! @{\r
+\r
+\r
+/*! \brief Checks if the USART is in multidrop mode.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if the USART is in multidrop mode, otherwise \c 0.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)\r
+{\r
+ return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;\r
+}\r
+\r
+\r
+/*! \brief Calculates a clock divider (\e CD) that gets the USART as close to a\r
+ * wanted baudrate as possible.\r
+ *\r
+ * \todo manage the FP fractal part to avoid big errors\r
+ *\r
+ * Baudrate calculation:\r
+ * \f$ baudrate = \frac{Selected Clock}{16 \times CD} \f$ with 16x oversampling or\r
+ * \f$ baudrate = \frac{Selected Clock}{8 \times CD} \f$ with 8x oversampling or\r
+ * \f$ baudrate = \frac{Selected Clock}{CD} \f$ with SYNC bit set to allow high speed.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param baudrate Wanted baudrate.\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Baudrate successfully initialized.\r
+ * \retval USART_INVALID_INPUT Wanted baudrate is impossible with given clock speed.\r
+ */\r
+\r
+static int usart_set_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, long pba_hz)\r
+{\r
+ // Clock divider.\r
+ int cd;\r
+\r
+ // Baudrate calculation.\r
+ if (baudrate < pba_hz / 16)\r
+ {\r
+ // Use 16x oversampling, clear SYNC bit.\r
+ usart->mr &=~ (AVR32_USART_MR_OVER_MASK | AVR32_USART_MR_SYNC_MASK);\r
+ cd = (pba_hz + 8 * baudrate) / (16 * baudrate); \r
+\r
+ if ((cd >65535)) return USART_INVALID_INPUT;\r
+ }\r
+ else if (baudrate < pba_hz / 8)\r
+ {\r
+ // Use 8x oversampling.\r
+ usart->mr |= AVR32_USART_MR_OVER_MASK;\r
+ // clear SYNC bit\r
+ usart->mr &=~ AVR32_USART_MR_SYNC_MASK;\r
+ \r
+ cd = (pba_hz + 4 * baudrate) / (8 * baudrate);\r
+\r
+ if ((cd < 1)||(cd >65535)) return USART_INVALID_INPUT;\r
+ }\r
+ else\r
+ {\r
+ // set SYNC to 1 \r
+ usart->mr |= AVR32_USART_MR_SYNC_MASK;\r
+ // use PBA/BaudRate\r
+ cd = (pba_hz / baudrate); \r
+ }\r
+ usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Initialization Functions\r
+ */\r
+//! @{\r
+\r
+\r
+void usart_reset(volatile avr32_usart_t *usart)\r
+{\r
+ // Disable all USART interrupts.\r
+ // Interrupts needed should be set explicitly on every reset.\r
+ usart->idr = 0xFFFFFFFF;\r
+\r
+ // Reset mode and other registers that could cause unpredictable behavior after reset.\r
+ usart->mr = 0;\r
+ usart->rtor = 0;\r
+ usart->ttgr = 0;\r
+\r
+ // Shutdown TX and RX (will be re-enabled when setup has successfully completed),\r
+ // reset status bits and turn off DTR and RTS.\r
+ usart->cr = AVR32_USART_CR_RSTRX_MASK |\r
+ AVR32_USART_CR_RSTTX_MASK |\r
+ AVR32_USART_CR_RSTSTA_MASK |\r
+ AVR32_USART_CR_RSTIT_MASK |\r
+ AVR32_USART_CR_RSTNACK_MASK |\r
+ AVR32_USART_CR_DTRDIS_MASK |\r
+ AVR32_USART_CR_RTSDIS_MASK;\r
+}\r
+\r
+\r
+int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+ // Reset the USART and shutdown TX and RX.\r
+ usart_reset(usart);\r
+\r
+ // Check input values.\r
+ if (!opt) // Null pointer.\r
+ return USART_INVALID_INPUT;\r
+ if (opt->charlength < 5 || opt->charlength > 9 ||\r
+ opt->paritytype > 7 ||\r
+ opt->stopbits > 2 + 255 ||\r
+ opt->channelmode > 3)\r
+ return USART_INVALID_INPUT;\r
+\r
+ if (usart_set_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ if (opt->charlength == 9)\r
+ {\r
+ // Character length set to 9 bits. MODE9 dominates CHRL.\r
+ usart->mr |= AVR32_USART_MR_MODE9_MASK;\r
+ }\r
+ else\r
+ {\r
+ // CHRL gives the character length (- 5) when MODE9 = 0.\r
+ usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;\r
+ }\r
+\r
+ usart->mr |= (opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET) |\r
+ (opt->paritytype << AVR32_USART_MR_PAR_OFFSET);\r
+\r
+ if (opt->stopbits > USART_2_STOPBITS)\r
+ {\r
+ // Set two stop bits\r
+ usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;\r
+ // and a timeguard period gives the rest.\r
+ usart->ttgr = opt->stopbits - USART_2_STOPBITS;\r
+ }\r
+ else\r
+ // Insert 1, 1.5 or 2 stop bits.\r
+ usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;\r
+\r
+ // Setup complete; enable communication.\r
+ // Enable input and output.\r
+ usart->cr |= AVR32_USART_CR_TXEN_MASK |\r
+ AVR32_USART_CR_RXEN_MASK;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+ // First: Setup standard RS232.\r
+ if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ // Clear previous mode.\r
+ usart->mr &= ~AVR32_USART_MR_MODE_MASK;\r
+ // Hardware handshaking.\r
+ usart->mr |= USART_MODE_HW_HSH << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,\r
+ long pba_hz, unsigned char irda_filter)\r
+{\r
+ // First: Setup standard RS232.\r
+ if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ // Set IrDA counter.\r
+ usart->ifr = irda_filter;\r
+\r
+ // Activate "low-pass filtering" of input.\r
+ usart->mr |= AVR32_USART_MR_FILTER_MASK;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+ // First: Setup standard RS232.\r
+ if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ // Clear previous mode.\r
+ usart->mr &= ~AVR32_USART_MR_MODE_MASK;\r
+ // Set modem mode.\r
+ usart->mr |= USART_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)\r
+{\r
+ // First: Setup standard RS232.\r
+ if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ // Clear previous mode.\r
+ usart->mr &= ~AVR32_USART_MR_MODE_MASK;\r
+ // Set RS485 mode.\r
+ usart->mr |= USART_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz)\r
+{\r
+ // Reset the USART and shutdown TX and RX.\r
+ usart_reset(usart);\r
+\r
+ // Check input values.\r
+ if (!opt) // Null pointer.\r
+ return USART_INVALID_INPUT;\r
+\r
+ if (t == 0)\r
+ {\r
+ // Set USART mode to ISO7816, T=0.\r
+ // The T=0 protocol always uses 2 stop bits.\r
+ usart->mr = (USART_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET) |\r
+ (AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET) |\r
+ (opt->bit_order << AVR32_USART_MR_MSBF_OFFSET); // Allow MSBF in T=0.\r
+ }\r
+ else if (t == 1)\r
+ {\r
+ // Only LSB first in the T=1 protocol.\r
+ // max_iterations field is only used in T=0 mode.\r
+ if (opt->bit_order != 0 ||\r
+ opt->max_iterations != 0)\r
+ return USART_INVALID_INPUT;\r
+ // Set USART mode to ISO7816, T=1.\r
+ // The T=1 protocol always uses 1 stop bit.\r
+ usart->mr = (USART_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET) |\r
+ (AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET);\r
+ }\r
+ else\r
+ return USART_INVALID_INPUT;\r
+\r
+ if (usart_set_baudrate(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT)\r
+ return USART_INVALID_INPUT;\r
+\r
+ // Set FIDI register: bit rate = selected clock/FI_DI_ratio/16.\r
+ usart->fidi = opt->fidi_ratio;\r
+ // Set ISO7816 spesific options in the MODE register.\r
+ usart->mr |= (opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET) |\r
+ (opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET) |\r
+ (opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET) |\r
+ AVR32_USART_MR_CLKO_MASK; // Enable clock output.\r
+\r
+ // Setup complete; enable input.\r
+ // Leave TX disabled for now.\r
+ usart->cr |= AVR32_USART_CR_RXEN_MASK;\r
+\r
+ return USART_SUCCESS;\r
+}\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Transmit/Receive Functions\r
+ */\r
+//! @{\r
+\r
+\r
+int usart_send_address(volatile avr32_usart_t *usart, int address)\r
+{\r
+ // Check if USART is in multidrop / RS485 mode.\r
+ if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT;\r
+\r
+ // Prepare to send an address.\r
+ usart->cr |= AVR32_USART_CR_SENDA_MASK;\r
+\r
+ // Write the address to TX.\r
+ usart_bw_write_char(usart, address);\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_write_char(volatile avr32_usart_t *usart, int c)\r
+{\r
+ if (usart->csr & AVR32_USART_CSR_TXRDY_MASK)\r
+ {\r
+ usart->thr = c;\r
+ return USART_SUCCESS;\r
+ }\r
+ else\r
+ return USART_TX_BUSY;\r
+}\r
+\r
+\r
+int usart_putchar(volatile avr32_usart_t *usart, int c)\r
+{\r
+ int timeout = USART_DEFAULT_TIMEOUT;\r
+\r
+ if (c == '\n')\r
+ {\r
+ do\r
+ {\r
+ if (!timeout--) return USART_FAILURE;\r
+ } while (usart_write_char(usart, '\r') != USART_SUCCESS);\r
+\r
+ timeout = USART_DEFAULT_TIMEOUT;\r
+ }\r
+\r
+ do\r
+ {\r
+ if (!timeout--) return USART_FAILURE;\r
+ } while (usart_write_char(usart, c) != USART_SUCCESS);\r
+\r
+ return USART_SUCCESS;\r
+}\r
+\r
+\r
+int usart_read_char(volatile avr32_usart_t *usart, int *c)\r
+{\r
+ // Check for errors: frame, parity and overrun. In RS485 mode, a parity error\r
+ // would mean that an address char has been received.\r
+ if (usart->csr & (AVR32_USART_CSR_OVRE_MASK |\r
+ AVR32_USART_CSR_FRAME_MASK |\r
+ AVR32_USART_CSR_PARE_MASK))\r
+ return USART_RX_ERROR;\r
+\r
+ // No error; if we really did receive a char, read it and return SUCCESS.\r
+ if (usart->csr & AVR32_USART_CSR_RXRDY_MASK)\r
+ {\r
+ *c = (unsigned short)usart->rhr;\r
+ return USART_SUCCESS;\r
+ }\r
+ else\r
+ return USART_RX_EMPTY;\r
+}\r
+\r
+\r
+int usart_getchar(volatile avr32_usart_t *usart)\r
+{\r
+ int c, ret;\r
+\r
+ while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY);\r
+\r
+ if (ret == USART_RX_ERROR)\r
+ return USART_FAILURE;\r
+\r
+ return c;\r
+}\r
+\r
+\r
+void usart_write_line(volatile avr32_usart_t *usart, const char *string)\r
+{\r
+ while (*string != '\0')\r
+ usart_putchar(usart, *string++);\r
+}\r
+\r
+\r
+int usart_get_echo_line(volatile avr32_usart_t *usart)\r
+{\r
+ int rx_char;\r
+ int retval = USART_SUCCESS;\r
+\r
+ while (1)\r
+ {\r
+ rx_char = usart_getchar(usart);\r
+ if (rx_char == USART_FAILURE)\r
+ {\r
+ usart_write_line(usart, "Error!!!\n");\r
+ break;\r
+ }\r
+ if (rx_char == '\x03')\r
+ {\r
+ retval = USART_FAILURE;\r
+ break;\r
+ }\r
+ usart_putchar(usart, rx_char);\r
+ if (rx_char == '\r')\r
+ {\r
+ usart_putchar(usart, '\n');\r
+ break;\r
+ }\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+//! @}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief USART driver for AVR32 UC3.\r
+ *\r
+ * This file contains basic functions for the AVR32 USART, with support for all\r
+ * modes, settings and clock speeds.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a USART module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _USART_H_\r
+#define _USART_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+\r
+/*! \name Return Values\r
+ */\r
+//! @{\r
+#define USART_SUCCESS 0 //!< Successful completion.\r
+#define USART_FAILURE -1 //!< Failure because of some unspecified reason.\r
+#define USART_INVALID_INPUT 1 //!< Input value out of range.\r
+#define USART_INVALID_ARGUMENT -1 //!< Argument value out of range.\r
+#define USART_TX_BUSY 2 //!< Transmitter was busy.\r
+#define USART_RX_EMPTY 3 //!< Nothing was received.\r
+#define USART_RX_ERROR 4 //!< Transmission error occurred.\r
+#define USART_MODE_FAULT 5 //!< USART not in the appropriate mode.\r
+//! @}\r
+\r
+//! Default time-out value (number of attempts).\r
+#define USART_DEFAULT_TIMEOUT 10000\r
+\r
+/*! \name Parity Settings\r
+ */\r
+//! @{\r
+#define USART_EVEN_PARITY AVR32_USART_MR_PAR_EVEN //!< Use even parity on character transmission.\r
+#define USART_ODD_PARITY AVR32_USART_MR_PAR_ODD //!< Use odd parity on character transmission.\r
+#define USART_SPACE_PARITY AVR32_USART_MR_PAR_SPACE //!< Use a space as parity bit.\r
+#define USART_MARK_PARITY AVR32_USART_MR_PAR_MARK //!< Use a mark as parity bit.\r
+#define USART_NO_PARITY AVR32_USART_MR_PAR_NONE //!< Don't use a parity bit.\r
+#define USART_MULTIDROP_PARITY AVR32_USART_MR_PAR_MULTI //!< Parity bit is used to flag address characters.\r
+//! @}\r
+\r
+/*! \name Operating Modes\r
+ */\r
+//! @{\r
+#define USART_MODE_NORMAL AVR32_USART_MR_MODE_NORMAL //!< Normal RS232 mode.\r
+#define USART_MODE_RS485 AVR32_USART_MR_MODE_RS485 //!< RS485 mode.\r
+#define USART_MODE_HW_HSH AVR32_USART_MR_MODE_HARDWARE //!< RS232 mode with hardware handshaking.\r
+#define USART_MODE_MODEM AVR32_USART_MR_MODE_MODEM //!< Modem mode.\r
+#define USART_MODE_ISO7816_T0 AVR32_USART_MR_MODE_ISO7816_T0 //!< ISO7816, T = 0 mode.\r
+#define USART_MODE_ISO7816_T1 AVR32_USART_MR_MODE_ISO7816_T1 //!< ISO7816, T = 1 mode.\r
+#define USART_MODE_IRDA AVR32_USART_MR_MODE_IRDA //!< IrDA mode.\r
+#define USART_MODE_SW_HSH AVR32_USART_MR_MODE_SOFTWARE //!< RS232 mode with software handshaking.\r
+//! @}\r
+\r
+\r
+/*! \name Channel Modes\r
+ */\r
+//! @{\r
+#define USART_NORMAL_CHMODE AVR32_USART_MR_CHMODE_NORMAL //!< Normal communication.\r
+#define USART_AUTO_ECHO AVR32_USART_MR_CHMODE_ECHO //!< Echo data.\r
+#define USART_LOCAL_LOOPBACK AVR32_USART_MR_CHMODE_LOCAL_LOOP //!< Local loopback.\r
+#define USART_REMOTE_LOOPBACK AVR32_USART_MR_CHMODE_REMOTE_LOOP //!< Remote loopback.\r
+//! @}\r
+\r
+/*! \name Stop Bits Settings\r
+ */\r
+//! @{\r
+#define USART_1_STOPBIT AVR32_USART_MR_NBSTOP_1 //!< Use 1 stop bit.\r
+#define USART_1_5_STOPBITS AVR32_USART_MR_NBSTOP_1_5 //!< Use 1.5 stop bits.\r
+#define USART_2_STOPBITS AVR32_USART_MR_NBSTOP_2 //!< Use 2 stop bits (for more, just give the number of bits).\r
+//! @}\r
+\r
+\r
+//! Input parameters when initializing RS232 and similar modes.\r
+typedef struct\r
+{\r
+ //! Set baudrate of the USART.\r
+ unsigned long baudrate;\r
+\r
+ //! Number of bits to transmit as a character (5 to 9).\r
+ unsigned char charlength;\r
+\r
+ //! How to calculate the parity bit: \ref USART_EVEN_PARITY, \ref USART_ODD_PARITY,\r
+ //! \ref USART_SPACE_PARITY, \ref USART_MARK_PARITY, \ref USART_NO_PARITY or\r
+ //! \ref USART_MULTIDROP_PARITY.\r
+ unsigned char paritytype;\r
+\r
+ //! Number of stop bits between two characters: \ref USART_1_STOPBIT,\r
+ //! \ref USART_1_5_STOPBITS, \ref USART_2_STOPBITS or any number from 3 to 257\r
+ //! which will result in a time guard period of that length between characters.\r
+ unsigned short stopbits;\r
+\r
+ //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,\r
+ //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.\r
+ unsigned char channelmode;\r
+} usart_options_t;\r
+\r
+//! Input parameters when initializing ISO7816 modes.\r
+typedef struct\r
+{\r
+ //! Set the frequency of the ISO7816 clock.\r
+ unsigned long iso7816_hz;\r
+\r
+ //! The number of ISO7816 clock ticks in every bit period (1 to 2047, 0 = disable clock).\r
+ //! Bit rate = \ref iso7816_hz / \ref fidi_ratio.\r
+ unsigned short fidi_ratio;\r
+\r
+ //! Inhibit Non Acknowledge:\n\r
+ //! - 0: the NACK is generated;\n\r
+ //! - 1: the NACK is not generated.\r
+ //!\r
+ //! \note This bit will be used only in ISO7816 mode, protocol T = 0 receiver.\r
+ int inhibit_nack;\r
+\r
+ //! Disable successive NACKs.\r
+ //! Successive parity errors are counted up to the value in the \ref max_iterations field.\r
+ //! These parity errors generate a NACK on the ISO line. As soon as this value is reached,\r
+ //! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted.\r
+ int dis_suc_nack;\r
+\r
+ //! Max number of repetitions (0 to 7).\r
+ unsigned char max_iterations;\r
+\r
+ //! Bit order in transmitted characters:\n\r
+ //! - 0: LSB first;\n\r
+ //! - 1: MSB first.\r
+ int bit_order;\r
+} iso7816_options_t;\r
+\r
+//! Input parameters when initializing ISO7816 modes.\r
+typedef struct\r
+{\r
+ //! Set the frequency of the SPI clock.\r
+ unsigned long baudrate;\r
+\r
+ //! Number of bits to transmit as a character (5 to 9).\r
+ unsigned char charlength;\r
+\r
+ //! Run the channel in testmode: \ref USART_NORMAL_CHMODE, \ref USART_AUTO_ECHO,\r
+ //! \ref USART_LOCAL_LOOPBACK or \ref USART_REMOTE_LOOPBACK.\r
+ unsigned char channelmode; \r
+ \r
+ //! Which SPI mode to use when transmitting.\r
+ unsigned char spimode;\r
+} usart_spi_options_t;\r
+ \r
+ \r
+\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Initialization Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Resets the USART and disables TX and RX.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ */\r
+extern void usart_reset(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Sets up the USART to use the standard RS232 protocol.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use hardware handshaking.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ *\r
+ * \note \ref usart_init_rs232 does not need to be invoked before this function.\r
+ */\r
+extern int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the IrDA protocol.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ * \param irda_filter Counter used to distinguish received ones from zeros.\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,\r
+ long pba_hz, unsigned char irda_filter);\r
+\r
+/*! \brief Sets up the USART to use the modem protocol, activating dedicated inputs/outputs.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the RS485 protocol.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up RS232 communication (see \ref usart_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the ISO7816 T=0 or T=1 smartcard protocols.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up ISO7816 communication (see \ref iso7816_options_t).\r
+ * \param t ISO7816 mode to use (T=0 or T=1).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_iso7816(volatile avr32_usart_t *usart, const iso7816_options_t *opt, int t, long pba_hz);\r
+\r
+/*! \brief Sets up the USART to use the SPI mode as master.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
+\r
+/*! \brief Sets up the USART to use the SPI mode as slave.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param opt Options needed to set up SPI mode (see \ref usart_spi_options_t).\r
+ * \param pba_hz USART module input clock frequency (PBA clock, Hz).\r
+ *\r
+ * \retval USART_SUCCESS Mode successfully initialized.\r
+ * \retval USART_INVALID_INPUT One or more of the arguments is out of valid range.\r
+ */\r
+extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz);\r
+\r
+//! @}\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \brief Selects slave chip.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return Status.\r
+ * \retval USART_SUCCESS Success.\r
+ */\r
+extern int usart_spi_selectChip(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Unselects slave chip.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return Status.\r
+ * \retval USART_SUCCESS Success.\r
+ * \retval USART_FAILURE Time out.\r
+ */\r
+extern int usart_spi_unselectChip(volatile avr32_usart_t *usart);\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Read and Reset Error Status Bits\r
+ */\r
+//! @{\r
+\r
+/*! \brief Resets the error status.\r
+ *\r
+ * This function resets the status bits indicating that a parity error,\r
+ * framing error or overrun has occurred. The RXBRK bit, indicating\r
+ * a start/end of break condition on the RX line, is also reset.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart)\r
+{\r
+ usart->cr |= AVR32_USART_CR_RSTSTA_MASK;\r
+}\r
+\r
+/*! \brief Checks if a parity error has occurred since last status reset.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a parity error has been detected, otherwise \c 0.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart)\r
+{\r
+ return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0;\r
+}\r
+\r
+/*! \brief Checks if a framing error has occurred since last status reset.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a framing error has been detected, otherwise \c 0.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart)\r
+{\r
+ return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0;\r
+}\r
+\r
+/*! \brief Checks if an overrun error has occurred since last status reset.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return \c 1 if a overrun error has been detected, otherwise \c 0.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart)\r
+{\r
+ return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0;\r
+}\r
+\r
+//! @}\r
+\r
+\r
+//------------------------------------------------------------------------------\r
+/*! \name Transmit/Receive Functions\r
+ */\r
+//! @{\r
+\r
+/*! \brief Addresses a receiver.\r
+ *\r
+ * While in RS485 mode, receivers only accept data addressed to them.\r
+ * A packet/char with the address tag set has to precede any data.\r
+ * This function is used to address a receiver. This receiver should read\r
+ * all the following data, until an address packet addresses another receiver.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param address Address of the target device.\r
+ *\r
+ * \retval USART_SUCCESS Address successfully sent (if current mode is RS485).\r
+ * \retval USART_MODE_FAULT Wrong operating mode.\r
+ */\r
+extern int usart_send_address(volatile avr32_usart_t *usart, int address);\r
+\r
+/*! \brief Writes the given character to the TX buffer if the transmitter is ready.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param c The character (up to 9 bits) to transmit.\r
+ *\r
+ * \retval USART_SUCCESS The transmitter was ready.\r
+ * \retval USART_TX_BUSY The transmitter was busy.\r
+ */\r
+extern int usart_write_char(volatile avr32_usart_t *usart, int c);\r
+\r
+/*! \brief An active wait writing a character to the USART.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param c The character (up to 9 bits) to transmit.\r
+ */\r
+#if __GNUC__\r
+__attribute__((__always_inline__))\r
+#endif\r
+extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c)\r
+{\r
+ while (usart_write_char(usart, c) != USART_SUCCESS);\r
+}\r
+\r
+/*! \brief Sends a character with the USART.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param c Character to write.\r
+ *\r
+ * \retval USART_SUCCESS The character was written.\r
+ * \retval USART_FAILURE The function timed out before the USART transmitter became ready to send.\r
+ */\r
+extern int usart_putchar(volatile avr32_usart_t *usart, int c);\r
+\r
+/*! \brief Checks the RX buffer for a received character, and stores it at the\r
+ * given memory location.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param c Pointer to the where the read character should be stored\r
+ * (must be at least short in order to accept 9-bit characters).\r
+ *\r
+ * \retval USART_SUCCESS The character was read successfully.\r
+ * \retval USART_RX_EMPTY The RX buffer was empty.\r
+ * \retval USART_RX_ERROR An error was deteceted.\r
+ */\r
+extern int usart_read_char(volatile avr32_usart_t *usart, int *c);\r
+\r
+/*! \brief Waits until a character is received, and returns it.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \return The received character, or \ref USART_FAILURE upon error.\r
+ */\r
+extern int usart_getchar(volatile avr32_usart_t *usart);\r
+\r
+/*! \brief Writes one character string to the USART.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ * \param string String to be written.\r
+ */\r
+extern void usart_write_line(volatile avr32_usart_t *usart, const char *string);\r
+\r
+/*! \brief Gets and echoes characters until end of line.\r
+ *\r
+ * \param usart Base address of the USART instance.\r
+ *\r
+ * \retval USART_SUCCESS Success.\r
+ * \retval USART_FAILURE ETX character received.\r
+ */\r
+extern int usart_get_echo_line(volatile avr32_usart_t *usart);\r
+\r
+//! @}\r
+\r
+\r
+#endif // _USART_H_\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* \brief FreeRTOS and lwIP example for AVR32 UC3.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
- *****************************************************************************/\r
+ ******************************************************************************/\r
\r
/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
*\r
\r
#include "board.h"\r
\r
+\r
/*-----------------------------------------------------------\r
* Application specific definitions.\r
*\r
/* Set the following definitions to 1 to include the API function, or zero\r
to exclude the API function. */\r
\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 0\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
\r
/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter\r
for the tick generation. Timer Counter will generate an accurate Tick;\r
- otherwise the CPU will generate a tick but with time drift\r
- configTICK_TC_CHANNEL is the TC channel.*/\r
+ otherwise the CPU will generate a tick but with time drift.\r
+ configTICK_TC_CHANNEL is the TC channel. */\r
#define configTICK_USE_TC 1\r
#define configTICK_TC_CHANNEL 2\r
\r
+/* configHEAP_INIT is a boolean indicating whether to initialize the heap with\r
+ 0xA5 in order to be able to determine the maximal heap consumption. */\r
+#define configHEAP_INIT 0\r
+\r
+\r
#endif /* FREERTOS_CONFIG_H */\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
- * \brief Basic SMTP Host for AVR32 UC3.\r
+ * \brief Basic SMTP Client for AVR32 UC3.\r
*\r
* - Compiler: GNU GCC for AVR32\r
* - Supported devices: All AVR32 devices can be used.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
*/\r
\r
-\r
/*\r
- Implements a simplistic SMTP client.\r
+ Implements a simplistic SMTP client. First time the task is started, connection is made and\r
+ email is sent. Mail flag is then reset. Each time you press the Push Button 0, a new mail will be sent.\r
*/\r
\r
#if (SMTP_USED == 1)\r
\r
#include <string.h>\r
\r
-/* Scheduler includes. */\r
+// Scheduler includes.\r
#include "FreeRTOS.h"\r
#include "task.h"\r
#include "BasicSMTP.h"\r
\r
\r
-/* Demo includes. */\r
-#include "AVR32_EMAC.h"\r
+// Demo includes.\r
#include "portmacro.h"\r
#include "partest.h"\r
+#include "intc.h"\r
+#include "gpio.h"\r
\r
-/* lwIP includes. */\r
+// lwIP includes.\r
#include "lwip/api.h"\r
#include "lwip/tcpip.h"\r
#include "lwip/memp.h"\r
#include "lwip/sockets.h"\r
#include "netif/loopif.h"\r
\r
-/*! SMTP default port */\r
+//! SMTP default port\r
#define SMTP_PORT 25\r
-/*! SMTP EHLO code answer */\r
+//! SMTP EHLO code answer\r
#define SMTP_EHLO_STRING "220"\r
-/*! SMTP end of transmission code answer */\r
+//! SMTP end of transmission code answer\r
#define SMTP_END_OF_TRANSMISSION_STRING "221"\r
-/*! SMTP OK code answer */\r
+//! SMTP OK code answer\r
#define SMTP_OK_STRING "250"\r
-/*! SMTP start of transmission code answer */\r
+//! SMTP start of transmission code answer\r
#define SMTP_START_OF_TRANSMISSION_STRING "354"\r
-/*! SMTP DATA<CRLF> */\r
+//! SMTP DATA<CRLF>\r
#define SMTP_DATA_STRING "DATA\r\n"\r
-/*! SMTP <CRLF>.<CRLF> */\r
+//! SMTP <CRLF>.<CRLF>\r
#define SMTP_MAIL_END_STRING "\r\n.\r\n"\r
-/*! SMTP QUIT<CRLFCRLF> */\r
-#define SMTP_QUIT_STRING "QUIT\r\n\r\n"\r
+//! SMTP QUIT<CRLFCRLF>\r
+#define SMTP_QUIT_STRING "QUIT\r\n"\r
\r
\r
-/*! Server address */\r
+//! Server address\r
+#error configure SMTP server address\r
portCHAR cServer[] = "192.168.0.1";\r
\r
-/*! Fill here the ehlo with your SMTP server name */\r
-#error configure SMTP server\r
-char ehlo[] = "EHLO smtp.domain.com\r\n";\r
+//! Fill here the mailfrom with your mail address\r
+#error configure SMTP mail sender\r
+char cMailfrom[] = "MAIL FROM: <sender@domain.com>\r\n";\r
\r
-/*! Fill here the mailfrom with your mail address */\r
-#error configure mail sender\r
-char mailfrom[] = "MAIL FROM: <sender@domain.com>\r\n";\r
+//! Fill here the mailto with your contact mail address\r
+#error configure SMTP mail recipient\r
+char cMailto[] = "RCPT TO: <recipient@domain.com>\r\n";\r
\r
-/*! Fill here the mailto with your contact mail address */\r
-#error configure mail receiver\r
-char mailto[] = "RCPT TO: <receiver@domain.com>\r\n";\r
+//! Fill here the mailcontent with the mail you want to send\r
+#error configure SMTP mail content\r
+char cMailcontent[] ="Subject: *** SPAM ***\r\nFROM: \"Your Name here\" <sender@domain.com>\r\nTO: \"Your Contact here\" <recipient@domain.com>\r\n\r\nSay what you want here.";\r
\r
-/*! Fill here the mailcontent with the mail you want to send */\r
-#error configure mail content\r
-char mailcontent[] ="Subject: *** SPAM ***\r\nFROM: \"Your Name here\" <sender@domain.com>\r\nTO: \"Your Contact here\" <receiver@domain.com>\r\n\r\nSay what you want here.";\r
+//! flag to send mail\r
+Bool bSendMail = pdFALSE;\r
\r
-Bool bSendMail = pdTRUE;\r
+//! buffer for SMTP response\r
portCHAR cTempBuffer[200];\r
\r
-/*! Basic SMTP Host task definition */\r
-portTASK_FUNCTION( vBasicSMTPHost, pvParameters )\r
+\r
+//_____ D E C L A R A T I O N S ____________________________________________\r
+//! interrupt handler.\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+void vpushb_ISR( void );\r
+\r
+//! soft interrupt handler. where treatment should be done\r
+#if __GNUC__\r
+__attribute__((__noinline__))\r
+#endif\r
+static portBASE_TYPE prvpushb_ISR_NonNakedBehaviour( void );\r
+\r
+\r
+\r
+//! Basic SMTP client task definition\r
+portTASK_FUNCTION( vBasicSMTPClient, pvParameters )\r
{\r
struct sockaddr_in stServeurSockAddr; \r
portLONG lRetval;\r
portLONG lSocket = -1;\r
\r
+ // configure push button 0 to produce IT on falling edge\r
+ gpio_enable_pin_interrupt(GPIO_PUSH_BUTTON_0 , GPIO_FALLING_EDGE);\r
+ // Disable all interrupts\r
+ vPortEnterCritical();\r
+ // register push button 0 handler on level 3\r
+ INTC_register_interrupt( (__int_handler)&vpushb_ISR, AVR32_GPIO_IRQ_0 + (GPIO_PUSH_BUTTON_0/8), INT3);\r
+ // Enable all interrupts\r
+ vPortExitCritical(); \r
\r
for (;;)\r
{\r
// wait for a signal to send a mail\r
while (bSendMail != pdTRUE) vTaskDelay(200);\r
\r
+ // Disable all interrupts\r
+ vPortEnterCritical();\r
+ // clear the flag \r
+ bSendMail = pdFALSE;\r
+ // Enable all interrupts\r
+ vPortExitCritical(); \r
+ // clear the LED\r
+ vParTestSetLED( 3 , pdFALSE );\r
// Set up port\r
memset(&stServeurSockAddr, 0, sizeof(stServeurSockAddr));\r
stServeurSockAddr.sin_len = sizeof(stServeurSockAddr);\r
stServeurSockAddr.sin_addr.s_addr = inet_addr(cServer);\r
stServeurSockAddr.sin_port = htons(SMTP_PORT);\r
stServeurSockAddr.sin_family = AF_INET;\r
-\r
- // clear the flag \r
- bSendMail = pdFALSE;\r
- \r
+ \r
// socket as a stream\r
if ( (lSocket = socket(AF_INET, SOCK_STREAM, 0)) < 0)\r
{\r
// socket failed, blink a LED and stay here\r
for (;;) {\r
- vParTestToggleLED( 0 );\r
+ vParTestToggleLED( 4 );\r
vTaskDelay( 200 );\r
}\r
}\r
{\r
// connect failed, blink a LED and stay here\r
for (;;) {\r
- vParTestToggleLED( 1 );\r
+ vParTestToggleLED( 6 );\r
vTaskDelay( 200 );\r
}\r
}\r
else\r
{\r
//Server: 220 SMTP Ready \r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer \r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
if (strncmp(cTempBuffer, SMTP_EHLO_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
//Client: EHLO smtp.domain.com\r
- /* send ehlo */\r
- send(lSocket, cEhlo, strlen(cEhlo), 0);\r
+ // send ehlo\r
+ send(lSocket, "HELO ", 5, 0);\r
+ send(lSocket, cServer, strlen(cServer), 0);\r
+ send(lSocket, "\r\n", 2, 0);\r
//Server: 250 \r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer\r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
}while (lRetval <= 0); \r
if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
-//Server: 250 HELP\r
- do\r
- {\r
- lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
- }while (lRetval <= 0); \r
//Client: MAIL FROM:<sender@domain.com>\r
- /* send MAIL FROM */\r
+ // send MAIL FROM\r
send(lSocket, cMailfrom, strlen(cMailfrom), 0); \r
//Server: 250 OK\r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer\r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
//Client: RCPT TO:<receiver@domain.com>\r
- /* send RCPT TO */\r
+ // send RCPT TO\r
send(lSocket, cMailto, strlen(cMailto), 0); \r
//Server: 250 OK\r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer\r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
//Client: DATA<CRLF>\r
- /* send DATA */\r
+ // send DATA\r
send(lSocket, SMTP_DATA_STRING, 6, 0); \r
//Server: 354 Start mail input; end with <CRLF>.<CRLF> \r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer\r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
}while (lRetval <= 0);\r
if (strncmp(cTempBuffer, SMTP_START_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
- /* send content */\r
+ // send content\r
send(lSocket, cMailcontent, strlen(cMailcontent), 0); \r
//Client: <CRLF>.<CRLF>\r
- /* send "<CRLF>.<CRLF>" */\r
+ // send "<CRLF>.<CRLF>"\r
send(lSocket, SMTP_MAIL_END_STRING, 5, 0);\r
//Server: 250 OK\r
- /* wait for SMTP Server answer */\r
+ // wait for SMTP Server answer\r
do\r
{\r
lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0);\r
if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0)\r
{\r
//Client: QUIT<CRLFCRLF>\r
- /* send QUIT */\r
+ // send QUIT \r
send(lSocket, SMTP_QUIT_STRING, 8, 0); \r
//Server: 221 smtp.domain.com closing transmission\r
do\r
} \r
}\r
} \r
- /* close socket */\r
+ // close socket\r
close(lSocket);\r
}\r
}\r
}\r
}\r
+\r
+/*! \brief push button naked interrupt handler.\r
+ *\r
+ */\r
+#if __GNUC__\r
+__attribute__((naked))\r
+#elif __ICCAVR32__\r
+#pragma shadow_registers = full // Naked.\r
+#endif\r
+void vpushb_ISR( void )\r
+{\r
+ /* This ISR can cause a context switch, so the first statement must be a\r
+ call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
+ variable declarations. */\r
+ portENTER_SWITCHING_ISR();\r
+\r
+ prvpushb_ISR_NonNakedBehaviour();\r
+\r
+ portEXIT_SWITCHING_ISR();\r
+}\r
+\r
+/*! \brief push button interrupt handler. Here, declarations should be done\r
+ *\r
+ */\r
+#if __GNUC__\r
+__attribute__((__noinline__))\r
+#elif __ICCAVR32__\r
+#pragma optimize = no_inline\r
+#endif\r
+static portBASE_TYPE prvpushb_ISR_NonNakedBehaviour( void )\r
+{\r
+ if (gpio_get_pin_interrupt_flag(GPIO_PUSH_BUTTON_0))\r
+ {\r
+ // set the flag \r
+ bSendMail = pdTRUE;\r
+ // allow new interrupt : clear the IFR flag\r
+ gpio_clear_pin_interrupt_flag(GPIO_PUSH_BUTTON_0);\r
+ }\r
+ // no context switch required, task is polling the flag\r
+ return( pdFALSE );\r
+}\r
+\r
+\r
+\r
+\r
+ \r
#endif\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
- * \brief Basic SMTP Host for AVR32 UC3.\r
+ * \brief Basic SMTP Client for AVR32 UC3.\r
*\r
* - Compiler: GNU GCC for AVR32\r
* - Supported devices: All AVR32 devices can be used.\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#include "portmacro.h"\r
\r
\r
-/* The function that implements the SMTP host task. */\r
-portTASK_FUNCTION_PROTO( vBasicSMTPHost, pvParameters );\r
+/* The function that implements the SMTP client task. */\r
+portTASK_FUNCTION_PROTO( vBasicSMTPClient, pvParameters );\r
\r
\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
\r
/* Demo includes. */\r
-#include "AVR32_EMAC.h"\r
#include "portmacro.h"\r
\r
/* lwIP includes. */\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#define ACK 04 /* acknowledgement */\r
#define ERROR 05 /* error code */\r
\r
+#if __ICCAVR32__\r
+#pragma pack(1)\r
+#endif\r
struct tftphdr {\r
short th_opcode; /* packet type */\r
union {\r
unsigned short tu_block; /* block # */\r
short tu_code; /* error code */\r
char tu_stuff[1]; /* request packet stuff */\r
- } __attribute__ ((packed)) th_u;\r
+ }\r
+#if __GNUC__\r
+ __attribute__ ((packed))\r
+#endif \r
+ th_u;\r
char th_data[1]; /* data or error string */\r
-} __attribute__ ((packed));\r
-\r
+}\r
+#if __GNUC__\r
+__attribute__ ((packed))\r
+#endif \r
+;\r
+#if __ICCAVR32__\r
+#pragma pack()\r
+#endif\r
\r
/* The function that implements the TFTP server task. */\r
portTASK_FUNCTION_PROTO( vBasicTFTPServer, pvParameters );\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
/*\r
Implements a simplistic WEB server. Every time a connection is made and\r
- data is received a dynamic page that shows the current FreeRTOS.org kernel \r
+ data is received a dynamic page that shows the current FreeRTOS.org kernel\r
statistics is generated and returned. The connection is then closed.\r
\r
This file was adapted from a FreeRTOS lwIP slip demo supplied by a third\r
/* Standard includes. */\r
#include <stdio.h>\r
#include <string.h>\r
-#include <fcntl.h>\r
\r
#include "conf_eth.h"\r
\r
\r
/* Demo includes. */\r
/* Demo app includes. */\r
-#include "AVR32_EMAC.h"\r
#include "portmacro.h"\r
\r
/* lwIP includes. */\r
-#include "lwip/api.h" \r
+#include "lwip/api.h"\r
#include "lwip/tcpip.h"\r
-#include "lwip/memp.h" \r
+#include "lwip/memp.h"\r
#include "lwip/stats.h"\r
#include "netif/loopif.h"\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
+++ /dev/null
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
-/*! \file *********************************************************************\r
- *\r
- * \brief EMAC abstraction layer for AVR32 UC3.\r
- *\r
- * - Compiler: GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices can be used.\r
- * - AppNote:\r
- *\r
- * \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
- *\r
- *****************************************************************************/\r
-\r
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- *\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- *\r
- * 3. The name of ATMEL may not be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-#ifndef AVR32_CONF_EMAC_H\r
-#define AVR32_CONF_EMAC_H\r
-\r
-#include "lwip/opt.h"\r
-\r
-/*! Number of receive buffers */\r
-#define NB_RX_BUFFERS 20\r
-\r
-/*! USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0\r
-to use an MII interface. */\r
-#define USE_RMII_INTERFACE 1\r
-\r
-/*! Number of Transmit buffers */\r
-#define NB_TX_BUFFERS ( MEMP_NUM_PBUF / 2 )\r
-\r
-/*! Size of each Transmit buffer. */\r
-#define ETH_TX_BUFFER_SIZE 1024 //( PBUF_POOL_BUFSIZE )\r
-\r
-#endif //* AVR32_CONF_EMAC_H\r
+++ /dev/null
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
-/*! \file *********************************************************************\r
- *\r
- * \brief EMAC abstraction layer for AVR32 UC3.\r
- *\r
- * - Compiler: GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices with a MACB can be used.\r
- * - AppNote:\r
- *\r
- * \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
- *\r
- *****************************************************************************/\r
-\r
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- *\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- *\r
- * 3. The name of ATMEL may not be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-\r
-/*\r
- * Interrupt driven driver for the EMAC peripheral. This driver is not\r
- * reentrant, re-entrancy is handled by a semaphore at the network interface\r
- * level. \r
- */\r
-\r
-\r
-/* Standard includes. */\r
-#include <stdio.h>\r
-#include <string.h>\r
-\r
-/* Scheduler includes. */\r
-#include "FreeRTOS.h"\r
-#include "semphr.h"\r
-#include "task.h"\r
-\r
-/* Demo app includes. */\r
-#include "AVR32_EMAC.h"\r
-#include "AVR32_CONF_EMAC.h"\r
-#include "DP83848.h"\r
-#include "intc.h"\r
-\r
-/* Hardware specific includes. */\r
-#include "gpio.h"\r
-\r
-/* Size of each receive buffer - DO NOT CHANGE. */\r
-#define ETH_RX_BUFFER_SIZE 128\r
-\r
-/* The buffer addresses written into the descriptors must be aligned so the\r
-last few bits are zero. These bits have special meaning for the EMAC\r
-peripheral and cannot be used as part of the address. */\r
-#define emacADDRESS_MASK ( ( unsigned portLONG ) 0xFFFFFFFC )\r
-\r
-/* Bit used within the address stored in the descriptor to mark the last\r
-descriptor in the array. */\r
-#define emacRX_WRAP_BIT ( ( unsigned portLONG ) 0x02 )\r
-\r
-\r
-/* A short delay is used to wait for a buffer to become available, should\r
-one not be immediately available when trying to transmit a frame. */\r
-#define emacBUFFER_WAIT_DELAY ( 2 )\r
-#define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )\r
-\r
-/* The time to block waiting for input. */\r
-#define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )\r
-\r
-/* Misc defines. */\r
-#define emacNO_DELAY ( 0 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* Buffer written to by the EMAC DMA. Must be aligned as described by the\r
-comment above the emacADDRESS_MASK definition. */\r
-static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
-\r
-/* Buffer read by the EMAC DMA. Must be aligned as described by the comment\r
-above the emacADDRESS_MASK definition. */\r
-static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));\r
-\r
-/* Descriptors used to communicate between the program and the EMAC peripheral.\r
-These descriptors hold the locations and state of the Rx and Tx buffers. */\r
-static volatile AVR32_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];\r
-static volatile AVR32_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];\r
-\r
-/* The IP and Ethernet addresses are read from the header files. */\r
-portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* See the header file for descriptions of public functions. */\r
-\r
-/*\r
- * Prototype for the EMAC interrupt function - called by the asm wrapper.\r
- */\r
-void vEMAC_ISR( void ) __attribute__ ((naked));\r
-\r
-/*\r
- * Initialise both the Tx and Rx descriptors used by the EMAC.\r
- */\r
-static void prvSetupDescriptors(void);\r
-\r
-/*\r
- * Write our MAC address into the EMAC. \r
- */\r
-static void prvSetupMACAddress( void );\r
-\r
-/*\r
- * Configure the EMAC and AIC for EMAC interrupts.\r
- */\r
-static void prvSetupEMACInterrupt( void );\r
-\r
-/*\r
- * Some initialisation functions taken from the Atmel EMAC sample code.\r
- */\r
-static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress );\r
-\r
-static void vWritePHY( unsigned portCHAR ucAddress, unsigned portLONG ulValue);\r
-\r
-static portBASE_TYPE prvProbePHY( void );\r
-\r
-/* The semaphore used by the EMAC ISR to wake the EMAC task. */\r
-static xSemaphoreHandle xSemaphore = NULL;\r
-\r
-/* Holds the index to the next buffer from which data will be read. */\r
-static volatile unsigned portLONG ulNextRxBuffer = 0;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* See the header file for descriptions of public functions. */\r
-portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )\r
-{\r
-static unsigned portBASE_TYPE uxTxBufferIndex = 0;\r
-//portBASE_TYPE xWaitCycles = 0;\r
-portLONG lReturn = pdPASS;\r
-portCHAR *pcBuffer;\r
-unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;\r
-\r
- /* If the length of data to be transmitted is greater than each individual\r
- transmit buffer then the data will be split into more than one buffer.\r
- Loop until the entire length has been buffered. */\r
- while( ulDataBuffered < ulLength )\r
- {\r
- /* Is a buffer available? */\r
- while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )\r
- {\r
- /* There is no room to write the Tx data to the Tx buffer. Wait a\r
- short while, then try again. */\r
- vTaskDelay( emacBUFFER_WAIT_DELAY );\r
- }\r
- \r
- /* lReturn will only be pdPASS if a buffer is available. */\r
- if( lReturn == pdPASS )\r
- {\r
- portENTER_CRITICAL();\r
- {\r
- /* Get the address of the buffer from the descriptor, then copy\r
- the data into the buffer. */\r
- pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;\r
-\r
- /* How much can we write to the buffer? */\r
- ulDataRemainingToSend = ulLength - ulDataBuffered;\r
- if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )\r
- {\r
- /* We can write all the remaining bytes. */\r
- ulLengthToSend = ulDataRemainingToSend;\r
- }\r
- else\r
- {\r
- /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */\r
- ulLengthToSend = ETH_TX_BUFFER_SIZE;\r
- }\r
-\r
- /* Copy the data into the buffer. */\r
- memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );\r
- ulDataBuffered += ulLengthToSend;\r
-\r
- /* Is this the last data for the frame? */\r
- if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )\r
- {\r
- /* No more data remains for this frame so we can start the\r
- transmission. */\r
- ulLastBuffer = AVR32_LAST_BUFFER;\r
- }\r
- else\r
- {\r
- /* More data to come for this frame. */\r
- ulLastBuffer = 0;\r
- }\r
- \r
- /* Fill out the necessary in the descriptor to get the data sent,\r
- then move to the next descriptor, wrapping if necessary. */\r
- if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )\r
- {\r
- xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )\r
- | ulLastBuffer\r
- | AVR32_TRANSMIT_WRAP;\r
- uxTxBufferIndex = 0;\r
- }\r
- else\r
- {\r
- xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )\r
- | ulLastBuffer;\r
- uxTxBufferIndex++;\r
- }\r
- \r
- /* If this is the last buffer to be sent for this frame we can\r
- start the transmission. */\r
- if( ulLastBuffer )\r
- {\r
- AVR32_MACB.ncr |= AVR32_MACB_TSTART_MASK;\r
- }\r
- }\r
- portEXIT_CRITICAL();\r
- }\r
- else\r
- {\r
- break;\r
- }\r
- }\r
-\r
- return lReturn;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* See the header file for descriptions of public functions. */\r
-unsigned portLONG ulEMACInputLength( void )\r
-{\r
-register unsigned portLONG ulIndex , ulLength = 0;\r
-\r
- /* Skip any fragments. We are looking for the first buffer that contains\r
- data and has the SOF (start of frame) bit set. */\r
- while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )\r
- {\r
- /* Ignoring this buffer. Mark it as free again. */\r
- xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
- ulNextRxBuffer++;\r
- if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
- {\r
- ulNextRxBuffer = 0;\r
- }\r
- }\r
-\r
- /* We are going to walk through the descriptors that make up this frame,\r
- but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()\r
- from finding the data. Therefore use a copy of ulNextRxBuffer instead. */\r
- ulIndex = ulNextRxBuffer;\r
- /* Walk through the descriptors until we find the last buffer for this\r
- frame. The last buffer will give us the length of the entire frame. */\r
- while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength )\r
- {\r
- ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;\r
- /* Increment to the next buffer, wrapping if necessary. */\r
- ulIndex++;\r
- if( ulIndex >= NB_RX_BUFFERS )\r
- {\r
- ulIndex = 0;\r
- }\r
- }\r
- return ulLength;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* See the header file for descriptions of public functions. */\r
-void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )\r
-{\r
-static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;\r
-static portCHAR *pcSource;\r
-register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;\r
-\r
- /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any\r
- correspondence between the length of our Rx buffers, and the length of the\r
- data we are returning or the length of the data being requested. Therefore,\r
- between calls we have to remember not only which buffer we are currently\r
- processing, but our position within that buffer. This would be greatly\r
- simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than\r
- the size of each Rx buffer, and that memory fragmentation did not occur.\r
- \r
- This function should only be called after a call to ulEMACInputLength().\r
- This will ensure ulNextRxBuffer is set to the correct buffer. */\r
-\r
-\r
- /* vEMACRead is called with pcTo set to NULL to indicate that we are about\r
- to read a new frame. Any fragments remaining in the frame we were\r
- processing during the last call should be dropped. */\r
- if( pcTo == NULL )\r
- {\r
- /* How many bytes are indicated as being in this buffer? If none then\r
- the buffer is completely full and the frame is contained within more\r
- than one buffer. */\r
- /* Reset our state variables ready for the next read from this buffer. */\r
- pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
- ulFameBytesReadSoFar = ( unsigned portLONG ) 0;\r
- ulBufferPosition = ( unsigned portLONG ) 0;\r
- }\r
- else\r
- {\r
- /* Loop until we have obtained the required amount of data. */\r
- ulSectionBytesReadSoFar = 0;\r
- while( ulSectionBytesReadSoFar < ulSectionLength )\r
- {\r
- /* We may have already read some data from this buffer. How much\r
- data remains in the buffer? */\r
- ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );\r
-\r
- /* How many more bytes do we need to read before we have the\r
- required amount of data? */\r
- ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;\r
-\r
- /* Do we want more data than remains in the buffer? */\r
- if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )\r
- {\r
- /* We want more data than remains in the buffer so we can\r
- write the remains of the buffer to the destination, then move\r
- onto the next buffer to get the rest. */\r
- memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );\r
- ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;\r
- ulFameBytesReadSoFar += ulBytesRemainingInBuffer;\r
-\r
- /* Mark the buffer as free again. */\r
- xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
- /* Move onto the next buffer. */\r
- ulNextRxBuffer++;\r
- if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
- {\r
- ulNextRxBuffer = ( unsigned portLONG ) 0;\r
- }\r
-\r
- /* Reset the variables for the new buffer. */\r
- pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
- ulBufferPosition = ( unsigned portLONG ) 0;\r
- }\r
- else\r
- {\r
- /* We have enough data in this buffer to send back. Read out\r
- enough data and remember how far we read up to. */\r
- memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );\r
-\r
- /* There may be more data in this buffer yet. Increment our\r
- position in this buffer past the data we have just read. */\r
- ulBufferPosition += ulRemainingSectionBytes;\r
- ulSectionBytesReadSoFar += ulRemainingSectionBytes;\r
- ulFameBytesReadSoFar += ulRemainingSectionBytes;\r
-\r
- /* Have we now finished with this buffer? */\r
- if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )\r
- {\r
- /* Mark the buffer as free again. */\r
- xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );\r
- /* Move onto the next buffer. */\r
- ulNextRxBuffer++;\r
- if( ulNextRxBuffer >= NB_RX_BUFFERS )\r
- {\r
- ulNextRxBuffer = 0;\r
- }\r
- pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );\r
- ulBufferPosition = 0;\r
- }\r
- }\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-void vEMACSetMACAddress(const portCHAR * EMACAddress)\r
-{\r
- memcpy(cMACAddress, EMACAddress, sizeof(cMACAddress));\r
-}\r
-\r
-/* See the header file for descriptions of public functions. */\r
-xSemaphoreHandle xEMACInit( void )\r
-{\r
-unsigned long status;\r
-\r
- /* enable GPIO's */\r
- gpio_enable_module_pin(AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION); //PB0\r
- gpio_enable_module_pin(AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION); //PB1\r
- gpio_enable_module_pin(AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION); //PB2\r
- gpio_enable_module_pin(AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION); //PB3\r
-\r
- gpio_enable_module_pin(AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION); //PB5\r
- gpio_enable_module_pin(AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION); //PB6\r
- gpio_enable_module_pin(AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION); //PB7\r
- gpio_enable_module_pin(AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION); //PB8\r
- gpio_enable_module_pin(AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION); //PB9\r
-\r
- gpio_enable_module_pin(AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION); //PB15\r
-\r
-\r
- /* set up registers */\r
- AVR32_MACB.ncr = 0;\r
- AVR32_MACB.tsr = ~0UL;\r
- AVR32_MACB.rsr = ~0UL;\r
- AVR32_MACB.idr = ~0UL;\r
- status = AVR32_MACB.isr;\r
-\r
-\r
-#ifndef USE_RMII_INTERFACE\r
- // RMII not used, set 1 to the USRIO Register\r
- AVR32_MACB.usrio |= AVR32_MACB_RMII_MASK;\r
-#else\r
- // RMII used, set 0 to the USRIO Register\r
- AVR32_MACB.usrio &= ~AVR32_MACB_RMII_MASK;\r
-#endif\r
-\r
- /* Load our MAC address into the EMAC. */\r
- prvSetupMACAddress();\r
-\r
- /* Setup the buffers and descriptors. */\r
- prvSetupDescriptors();\r
-\r
-#if configCPU_CLOCK_HZ <= 20000000\r
- AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
-#elif configCPU_CLOCK_HZ <= 40000000\r
- AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);\r
-#elif configCPU_CLOCK_HZ <= 80000000\r
- AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
-#elif configCPU_CLOCK_HZ <= 160000000\r
- AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;\r
-#else\r
-# error System clock too fast\r
-#endif\r
-\r
- /* Are we connected? */\r
- if( prvProbePHY() )\r
- {\r
- /* Enable the interrupt! */\r
- portENTER_CRITICAL();\r
- {\r
- prvSetupEMACInterrupt();\r
- vPassEMACSemaphore( xSemaphore );\r
- }\r
- portEXIT_CRITICAL();\r
- /* Enable Rx and Tx, plus the stats register. */\r
- AVR32_MACB.ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;\r
- }\r
- return xSemaphore;\r
-}\r
-\r
-/* See the header file for descriptions of public functions. */\r
-void vClearEMACTxBuffer( void )\r
-{\r
-static unsigned portBASE_TYPE uxNextBufferToClear = 0;\r
-\r
- /* Called on Tx interrupt events to set the AT91C_TRANSMIT_OK bit in each\r
- Tx buffer within the frame just transmitted. This marks all the buffers\r
- as available again.\r
-\r
- The first buffer in the frame should have the bit set automatically. */\r
- if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )\r
- {\r
- /* Loop through the other buffers in the frame. */\r
- while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )\r
- {\r
- uxNextBufferToClear++;\r
-\r
- if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
- {\r
- uxNextBufferToClear = 0;\r
- }\r
-\r
- xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;\r
- }\r
-\r
- /* Start with the next buffer the next time a Tx interrupt is called. */\r
- uxNextBufferToClear++;\r
-\r
- /* Do we need to wrap back to the first buffer? */\r
- if( uxNextBufferToClear >= NB_TX_BUFFERS )\r
- {\r
- uxNextBufferToClear = 0;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupDescriptors(void)\r
-{\r
-unsigned portBASE_TYPE xIndex;\r
-unsigned portLONG ulAddress;\r
-\r
- /* Initialise xRxDescriptors descriptor. */\r
- for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )\r
- {\r
- /* Calculate the address of the nth buffer within the array. */\r
- ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );\r
-\r
- /* Write the buffer address into the descriptor. The DMA will place\r
- the data at this address when this descriptor is being used. Mask off\r
- the bottom bits of the address as these have special meaning. */\r
- xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
- }\r
-\r
- /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
- to the first buffer. */\r
- xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;\r
-\r
- /* Initialise xTxDescriptors. */\r
- for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )\r
- {\r
- /* Calculate the address of the nth buffer within the array. */\r
- ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );\r
-\r
- /* Write the buffer address into the descriptor. The DMA will read\r
- data from here when the descriptor is being used. */\r
- xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;\r
- xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;\r
- }\r
-\r
- /* The last buffer has the wrap bit set so the EMAC knows to wrap back\r
- to the first buffer. */\r
- xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;\r
-\r
- /* Tell the EMAC where to find the descriptors. */\r
- AVR32_MACB.rbqp = ( unsigned portLONG )xRxDescriptors;\r
- AVR32_MACB.tbqp = ( unsigned portLONG )xTxDescriptors;\r
-\r
- /* Enable the copy of data into the buffers, ignore broadcasts,\r
- and don't copy FCS. */\r
- AVR32_MACB.ncfgr |= (AVR32_MACB_CAF_MASK | AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK);\r
-\r
-} \r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupMACAddress( void )\r
-{\r
- /* Must be written SA1L then SA1H. */\r
- AVR32_MACB.sa1b = ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |\r
- ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |\r
- ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8 ) |\r
- cMACAddress[ 0 ];\r
-\r
- AVR32_MACB.sa1t = ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |\r
- cMACAddress[ 4 ];\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupEMACInterrupt( void )\r
-{\r
- /* Create the semaphore used to trigger the EMAC task. */\r
- if (xSemaphore == NULL)\r
- {\r
- vSemaphoreCreateBinary( xSemaphore );\r
- }\r
-\r
- if( xSemaphore )\r
- {\r
- /* We start by 'taking' the semaphore so the ISR can 'give' it when the\r
- first interrupt occurs. */\r
- xSemaphoreTake( xSemaphore, emacNO_DELAY );\r
- portENTER_CRITICAL();\r
- {\r
- /* Setup the interrupt for USART0.\r
- Register the USART0 interrupt handler to the interrupt controller\r
- at interrupt level 2. */\r
- INTC_register_interrupt(&vEMAC_ISR, AVR32_MACB_IRQ, INT2);\r
-\r
- /* We want to interrupt on Rx and Tx events. */\r
- AVR32_MACB.ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;\r
- }\r
- portEXIT_CRITICAL();\r
- }\r
-}\r
-\r
-/*\r
- * The following functions are initialisation functions taken from the Atmel\r
- * EMAC sample code.\r
- */\r
-static portBASE_TYPE prvProbePHY( void )\r
-{\r
-unsigned long mii_status, advertise, lpa, phy_ctrl;\r
-unsigned long config;\r
-unsigned long upper, lower,mode;\r
-unsigned long physID;\r
-\r
- /* Read Phy Identifier register 1 & 2 */\r
- lower = vReadPHY(PHY_PHYSID2);\r
- upper = vReadPHY(PHY_PHYSID1);\r
- /* get Phy ID, ignore Revision */\r
- physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);\r
- /* check if it match config */\r
- if (physID == MII_DP83848_ID)\r
- {\r
- /* read RBR */\r
- mode = vReadPHY(PHY_RBR);\r
- /* set RMII mode if not done */\r
- if ((mode & RBR_RMII) != RBR_RMII)\r
- {\r
- /* force RMII flag if strap options are wrong */\r
- mode |= RBR_RMII;\r
- vWritePHY(PHY_RBR,mode);\r
- }\r
-\r
- /* set advertise register */\r
-#if ETHERNET_CONF_AN_ENABLE == 1\r
- advertise = ADVERTISE_CSMA | ADVERTISE_ALL;\r
-#else\r
- advertise = ADVERTISE_CSMA;\r
- #if ETHERNET_CONF_USE_100MB\r
- #if ETHERNET_CONF_USE_FULL_DUPLEX\r
- advertise |= ADVERTISE_100FULL;\r
- #else\r
- advertise |= ADVERTISE_100HALF;\r
- #endif\r
- #else\r
- #if ETHERNET_CONF_USE_FULL_DUPLEX\r
- advertise |= ADVERTISE_10FULL;\r
- #else\r
- advertise |= ADVERTISE_10HALF;\r
- #endif\r
- #endif\r
-#endif\r
- /* write advertise register */\r
- vWritePHY(PHY_ADVERTISE, advertise);\r
- /* read Control register */\r
- config = vReadPHY(PHY_BMCR);\r
- /* read Phy Control register */\r
- phy_ctrl = vReadPHY(PHY_PHYCR);\r
-#if ETHERNET_CONF_AN_ENABLE\r
- #if ETHERNET_CONF_AUTO_CROSS_ENABLE\r
- /* enable Auto MDIX */\r
- phy_ctrl |= PHYCR_MDIX_EN;\r
- #else\r
- /* disable Auto MDIX */\r
- phy_ctrl &= ~PHYCR_MDIX_EN;\r
- #if ETHERNET_CONF_CROSSED_LINK\r
- /* force direct link = Use crossed RJ45 cable */\r
- phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
- #else\r
- /* force crossed link = Use direct RJ45 cable */\r
- phy_ctrl |= PHYCR_MDIX_FORCE;\r
- #endif\r
- #endif\r
- /* reset auto-negociation capability */\r
- config |= (BMCR_ANRESTART | BMCR_ANENABLE);\r
-#else\r
- /* disable Auto MDIX */\r
- phy_ctrl &= ~PHYCR_MDIX_EN;\r
- #if ETHERNET_CONF_CROSSED_LINK\r
- /* force direct link = Use crossed RJ45 cable */\r
- phy_ctrl &= ~PHYCR_MDIX_FORCE;\r
- #else\r
- /* force crossed link = Use direct RJ45 cable */\r
- phy_ctrl |= PHYCR_MDIX_FORCE;\r
- #endif\r
- /* clear AN bit */\r
- config &= ~BMCR_ANENABLE;\r
-\r
- #if ETHERNET_CONF_USE_100MB\r
- config |= BMCR_SPEED100;\r
- #else\r
- config &= ~BMCR_SPEED100;\r
- #endif\r
- #if ETHERNET_CONF_USE_FULL_DUPLEX\r
- config |= BMCR_FULLDPLX;\r
- #else\r
- config &= ~BMCR_FULLDPLX;\r
- #endif\r
-#endif\r
- /* update Phy ctrl register */\r
- vWritePHY(PHY_PHYCR, phy_ctrl);\r
-\r
- /* update ctrl register */\r
- vWritePHY(PHY_BMCR, config);\r
-\r
- /* loop while link status isn't OK */\r
- do {\r
- mii_status = vReadPHY(PHY_BMSR);\r
- } while (!(mii_status & BMSR_LSTATUS));\r
-\r
- /* read the LPA configuration of the PHY */\r
- lpa = vReadPHY(PHY_LPA);\r
-\r
- /* read the MACB config register */\r
- config = AVR32_MACB.ncfgr;\r
-\r
- /* if 100MB needed */\r
- if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL))\r
- {\r
- config |= AVR32_MACB_SPD_MASK;\r
- }\r
- else\r
- {\r
- config &= ~(AVR32_MACB_SPD_MASK);\r
- }\r
-\r
- /* if FULL DUPLEX needed */\r
- if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL))\r
- {\r
- config |= AVR32_MACB_FD_MASK;\r
- }\r
- else\r
- {\r
- config &= ~(AVR32_MACB_FD_MASK);\r
- }\r
-\r
- /* write the MACB config register */\r
- AVR32_MACB.ncfgr = config;\r
-\r
- return pdPASS;\r
- }\r
- return pdFAIL;\r
-}\r
-\r
-static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress )\r
-{\r
- unsigned portLONG pulValue;\r
-\r
- /* Enable management port */\r
- AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;\r
-\r
- /* configure MDIO frame in MAN register */\r
- AVR32_MACB.man = (AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
- | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
- | (2 << AVR32_MACB_RW_OFFSET) // Read operation\r
- | ((DP83848_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
- | (ucAddress << AVR32_MACB_REGA_OFFSET); // Reg Add\r
-\r
- /* Wait until IDLE bit in Network Status register is cleared. */\r
- while( !( AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK ) )\r
- {\r
- __asm( "NOP" );\r
- }\r
-\r
- pulValue = (AVR32_MACB.man & 0x0000ffff );\r
-\r
- /* Disable management port */\r
- AVR32_MACB.ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
-\r
- return (pulValue);\r
-}\r
-\r
-\r
-static void vWritePHY( unsigned portCHAR ucAddress, unsigned portLONG ulValue )\r
-{\r
- /* Enable management port */\r
- AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;\r
-\r
- /* configure MDIO frame in MAN register */\r
- AVR32_MACB.man = (( AVR32_MACB_SOF_MASK & (0x01<<AVR32_MACB_SOF_OFFSET)) // SOF\r
- | (2 << AVR32_MACB_CODE_OFFSET) // Code\r
- | (1 << AVR32_MACB_RW_OFFSET) // Write operation\r
- | ((DP83848_PHY_ADDR & 0x1f) << AVR32_MACB_PHYA_OFFSET) // Phy Add\r
- | (ucAddress << AVR32_MACB_REGA_OFFSET)) // Reg Add\r
- | (ulValue & 0xffff); // Data\r
-\r
- /* Wait until IDLE bit in Network Status register is cleared */\r
- while( !( AVR32_MACB.nsr & AVR32_MACB_NSR_IDLE_MASK ) )\r
- {\r
- __asm( "NOP" );\r
- };\r
-\r
- /* Disable management port */\r
- AVR32_MACB.ncr &= ~AVR32_MACB_NCR_MPE_MASK;\r
-\r
-}\r
-\r
-void vEMACWaitForInput( void )\r
-{\r
- /* Just wait until we are signled from an ISR that data is available, or\r
- we simply time out. */\r
- xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );\r
-}\r
+++ /dev/null
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
-/*! \file *********************************************************************\r
- *\r
- * \brief EMAC abstraction layer for AVR32 UC3.\r
- *\r
- * - Compiler: GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices can be used.\r
- * - AppNote:\r
- *\r
- * \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
- *\r
- *****************************************************************************/\r
-\r
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- *\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- *\r
- * 3. The name of ATMEL may not be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-\r
-\r
-#ifndef AVR32_EMAC_H\r
-#define AVR32_EMAC_H\r
-\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
-#include <arch/sys_arch.h>\r
-\r
-#include "conf_eth.h"\r
-\r
-\r
-/* Receive Transfer descriptor structure */\r
-typedef struct _AVR32_RxTdDescriptor {\r
- unsigned int addr;\r
- union\r
- {\r
- unsigned int status;\r
- struct {\r
- unsigned int BroadCast:1;\r
- unsigned int MultiCast:1;\r
- unsigned int UniCast:1;\r
- unsigned int ExternalAdd:1;\r
- unsigned int Res1:1;\r
- unsigned int Sa1Match:1;\r
- unsigned int Sa2Match:1;\r
- unsigned int Sa3Match:1;\r
- unsigned int Sa4Match:1;\r
- unsigned int TypeID:1;\r
- unsigned int VlanTag:1;\r
- unsigned int PriorityTag:1;\r
- unsigned int VlanPriority:3;\r
- unsigned int Cfi:1;\r
- unsigned int EndOfFrame:1;\r
- unsigned int StartOfFrame:1;\r
- unsigned int Rxbuf_off:2;\r
- unsigned int Res0:1;\r
- unsigned int Length:11;\r
- }S_Status;\r
- }U_Status;\r
-}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor;\r
-\r
-\r
-/* Transmit Transfer descriptor structure */\r
-typedef struct _AVR32_TxTdDescriptor {\r
- unsigned int addr;\r
- union\r
- {\r
- unsigned int status;\r
- struct {\r
- unsigned int BuffUsed:1;\r
- unsigned int Wrap:1;\r
- unsigned int TransmitError:1;\r
- unsigned int TransmitUnderrun:1;\r
- unsigned int BufExhausted:1;\r
- unsigned int Res1:10;\r
- unsigned int NoCrc:1;\r
- unsigned int LastBuff:1;\r
- unsigned int Res0:4;\r
- unsigned int Length:11;\r
- }S_Status;\r
- }U_Status;\r
-}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor;\r
-\r
-#define AVR32_OWNERSHIP_BIT 0x00000001\r
-\r
-/* Receive status defintion */\r
-#define AVR32_BROADCAST_ADDR ((unsigned int) (1 << 31)) //* Broadcat address detected\r
-#define AVR32_MULTICAST_HASH ((unsigned int) (1 << 30)) //* MultiCast hash match\r
-#define AVR32_UNICAST_HASH ((unsigned int) (1 << 29)) //* UniCast hash match\r
-#define AVR32_EXTERNAL_ADDR ((unsigned int) (1 << 28)) //* External Address match\r
-#define AVR32_SA1_ADDR ((unsigned int) (1 << 26)) //* Specific address 1 match\r
-#define AVR32_SA2_ADDR ((unsigned int) (1 << 25)) //* Specific address 2 match\r
-#define AVR32_SA3_ADDR ((unsigned int) (1 << 24)) //* Specific address 3 match\r
-#define AVR32_SA4_ADDR ((unsigned int) (1 << 23)) //* Specific address 4 match\r
-#define AVR32_TYPE_ID ((unsigned int) (1 << 22)) //* Type ID match\r
-#define AVR32_VLAN_TAG ((unsigned int) (1 << 21)) //* VLAN tag detected\r
-#define AVR32_PRIORITY_TAG ((unsigned int) (1 << 20)) //* PRIORITY tag detected\r
-#define AVR32_VLAN_PRIORITY ((unsigned int) (7 << 17)) //* PRIORITY Mask\r
-#define AVR32_CFI_IND ((unsigned int) (1 << 16)) //* CFI indicator\r
-#define AVR32_EOF ((unsigned int) (1 << 15)) //* EOF\r
-#define AVR32_SOF ((unsigned int) (1 << 14)) //* SOF\r
-#define AVR32_RBF_OFFSET ((unsigned int) (3 << 12)) //* Receive Buffer Offset Mask\r
-#define AVR32_LENGTH_FRAME ((unsigned int) 0x0FFF) //* Length of frame\r
-\r
-/* Transmit Status definition */\r
-#define AVR32_TRANSMIT_OK ((unsigned int) (1 << 31)) //*\r
-#define AVR32_TRANSMIT_WRAP ((unsigned int) (1 << 30)) //* Wrap bit: mark the last descriptor\r
-#define AVR32_TRANSMIT_ERR ((unsigned int) (1 << 29)) //* RLE:transmit error\r
-#define AVR32_TRANSMIT_UND ((unsigned int) (1 << 28)) //* Transmit Underrun\r
-#define AVR32_BUF_EX ((unsigned int) (1 << 27)) //* Buffers exhausted in mid frame\r
-#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16)) //* No CRC will be appended to the current frame\r
-#define AVR32_LAST_BUFFER ((unsigned int) (1 << 15)) //*\r
-\r
-#define AVR32_EMAC_CLKEN 0x2\r
-\r
-/*\r
- * Initialise the EMAC driver. If successful a semaphore is returned that\r
- * is used by the EMAC ISR to indicate that Rx packets have been received.\r
- * If the initialisation fails then NULL is returned.\r
- */\r
-xSemaphoreHandle xEMACInit( void );\r
-\r
-/*\r
- * Send ulLength bytes from pcFrom. This copies the buffer to one of the\r
- * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.\r
- * If lEndOfFrame is true then the data being copied is the end of the frame\r
- * and the frame can be transmitted.\r
- */\r
-portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );\r
-\r
-/*\r
- * Frames can be read from the EMAC in multiple sections.\r
- * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.\r
- * ulTotalFrameLength is the size of the entire frame. Generally vEMACRead\r
- * will be repetedly called until the sum of all the ulSectionLenths totals\r
- * the value of ulTotalFrameLength.\r
- */\r
-void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );\r
-\r
-/*\r
- * The EMAC driver and interrupt service routines are defined in different\r
- * files as the driver is compiled to THUMB, and the ISR to ARM. This function\r
- * simply passes the semaphore used to communicate between the two.\r
- */\r
-void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );\r
-\r
-/*\r
- * Called by the Tx interrupt, this function traverses the buffers used to\r
- * hold the frame that has just completed transmission and marks each as\r
- * free again.\r
- */\r
-void vClearEMACTxBuffer( void );\r
-\r
-/*\r
- * Suspend on a semaphore waiting either for the semaphore to be obtained\r
- * or a timeout. The semaphore is used by the EMAC ISR to indicate that\r
- * data has been received and is ready for processing.\r
- */\r
-void vEMACWaitForInput( void );\r
-\r
-/*\r
- * Return the length of the next frame in the receive buffers.\r
- */\r
-unsigned portLONG ulEMACInputLength( void );\r
-\r
-/*\r
- * Set the MACB Physical address (SA1B & SA1T registers).\r
- */\r
-void vEMACSetMACAddress(const portCHAR * EMACAddress);\r
-\r
-/*\r
- * Get the MACB Physical address (SA1B & SA1T registers).\r
- */\r
-void vEMACGetMACAddress(portCHAR * EMACAddress);\r
-\r
-#endif\r
+++ /dev/null
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
-/*! \file *********************************************************************\r
- *\r
- * \brief EMAC abstraction layer for AVR32 UC3.\r
- *\r
- * - Compiler: GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices can be used.\r
- * - AppNote:\r
- *\r
- * \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
- *\r
- *****************************************************************************/\r
-\r
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- *\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- *\r
- * 3. The name of ATMEL may not be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-\r
-\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "semphr.h"\r
-\r
-#include "AVR32_EMAC.h"\r
-#include "AVR32_CONF_EMAC.h"\r
-\r
-#include "lwipopts.h"\r
-\r
-\r
-\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The semaphore used to signal the arrival of new data to the interface\r
-task. */\r
-static xSemaphoreHandle xSemaphore = NULL;\r
-\r
-static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void );\r
-\r
-\r
-/*\r
- * The EMAC ISR. Handles both Tx and Rx complete interrupts.\r
- */\r
-//__attribute__((naked,section (".handlers"))) void vEMAC_ISR( void )\r
-__attribute__((naked)) void vEMAC_ISR( void )\r
-{\r
- /* This ISR can cause a context switch, so the first statement must be a\r
- call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any\r
- variable declarations. */\r
- portENTER_SWITCHING_ISR();\r
-\r
- prvEMAC_ISR_NonNakedBehaviour();\r
- /* Exit the ISR. If a task was woken by either a character being received\r
- or transmitted then a context switch will occur. */\r
-\r
- portEXIT_SWITCHING_ISR();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void )\r
-{\r
-\r
- /* Variable definitions can be made now. */\r
- volatile unsigned portLONG ulIntStatus, ulEventStatus;\r
- portBASE_TYPE xSwitchRequired = pdFALSE;\r
- extern void vClearEMACTxBuffer( void );\r
-\r
- /* Find the cause of the interrupt. */\r
- ulIntStatus = AVR32_MACB.isr;\r
- ulEventStatus = AVR32_MACB.rsr;\r
-\r
- if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) )\r
- {\r
- /* A frame has been received, signal the lwIP task so it can process\r
- the Rx descriptors. */\r
- portENTER_CRITICAL();\r
- xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );\r
- portEXIT_CRITICAL();\r
- AVR32_MACB.rsr = AVR32_MACB_REC_MASK;\r
- AVR32_MACB.rsr;\r
- }\r
-\r
- if( ulIntStatus & AVR32_MACB_TCOMP_MASK )\r
- {\r
- /* A frame has been transmitted. Mark all the buffers used by the\r
- frame just transmitted as free again. */\r
- vClearEMACTxBuffer();\r
- AVR32_MACB.tsr = AVR32_MACB_TSR_COMP_MASK;\r
- AVR32_MACB.tsr;\r
- }\r
-\r
- return ( xSwitchRequired );\r
-}\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )\r
-{\r
- /* Simply store the semaphore that should be used by the ISR. */\r
- xSemaphore = xCreatedSemaphore;\r
-}\r
-\r
-\r
+++ /dev/null
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
-/*This file has been prepared for Doxygen automatic documentation generation.*/\r
-/*! \file *********************************************************************\r
- *\r
- * \brief PHY abstraction layer for AVR32 UC3 on EVK1100.\r
- *\r
- * - Compiler: GNU GCC for AVR32\r
- * - Supported devices: All AVR32 devices can be used.\r
- * - AppNote:\r
- *\r
- * \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
- *\r
- *****************************************************************************/\r
-\r
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- *\r
- * 1. Redistributions of source code must retain the above copyright notice,\r
- * this list of conditions and the following disclaimer.\r
- *\r
- * 2. Redistributions in binary form must reproduce the above copyright notice,\r
- * this list of conditions and the following disclaimer in the documentation\r
- * and/or other materials provided with the distribution.\r
- *\r
- * 3. The name of ATMEL may not be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-/* DP83848 registers. */\r
-/*! Generic MII registers. */\r
-#define PHY_BMCR 0x00 /* Basic mode control register */\r
-#define PHY_BMSR 0x01 /* Basic mode status register */\r
-#define PHY_PHYSID1 0x02 /* PHYS ID 1 */\r
-#define PHY_PHYSID2 0x03 /* PHYS ID 2 */\r
-#define PHY_ADVERTISE 0x04 /* Advertisement control reg */\r
-#define PHY_LPA 0x05 /* Link partner ability reg */\r
-\r
-#if BOARD == EVK1100\r
-/*! Extended registers for DP83848 */\r
-#define PHY_RBR 0x17 /* RMII Bypass reg */\r
-#define PHY_MICR 0x11 /* Interrupt Control reg */\r
-#define PHY_MISR 0x12 /* Interrupt Status reg */\r
-#define PHY_PHYCR 0x19 /* Phy CTRL reg */\r
-#endif\r
-\r
-\r
-/*! Basic mode control register. */\r
-#define BMCR_RESV 0x007f /* Unused... */\r
-#define BMCR_CTST 0x0080 /* Collision test */\r
-#define BMCR_FULLDPLX 0x0100 /* Full duplex */\r
-#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */\r
-#define BMCR_ISOLATE 0x0400 /* Disconnect PHY from MII */\r
-#define BMCR_PDOWN 0x0800 /* Powerdown the PHY */\r
-#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\r
-#define BMCR_SPEED100 0x2000 /* Select 100Mbps */\r
-#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */\r
-#define BMCR_RESET 0x8000 /* Reset the PHY */\r
-\r
-/*! Basic mode status register. */\r
-#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\r
-#define BMSR_JCD 0x0002 /* Jabber detected */\r
-#define BMSR_LSTATUS 0x0004 /* Link status */\r
-#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\r
-#define BMSR_RFAULT 0x0010 /* Remote fault detected */\r
-#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */\r
-#define BMSR_RESV 0x00c0 /* Unused... */\r
-#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */\r
-#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */\r
-#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */\r
-#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\r
-#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\r
-#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\r
-#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\r
-#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */\r
-\r
-/*! Advertisement control register. */\r
-#define ADVERTISE_SLCT 0x001f /* Selector bits */\r
-#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\r
-#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\r
-#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */\r
-#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\r
-#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */\r
-#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\r
-#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */\r
-#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\r
-#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */\r
-#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */\r
-#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */\r
-#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */\r
-#define ADVERTISE_RESV 0x1000 /* Unused... */\r
-#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */\r
-#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */\r
-#define ADVERTISE_NPAGE 0x8000 /* Next page bit */\r
-\r
-#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)\r
-#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\r
- ADVERTISE_100HALF | ADVERTISE_100FULL)\r
-\r
-/*! Link partner ability register. */\r
-#define LPA_SLCT 0x001f /* Same as advertise selector */\r
-#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */\r
-#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */\r
-#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */\r
-#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */\r
-#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */\r
-#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */\r
-#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */\r
-#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/\r
-#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */\r
-#define LPA_PAUSE_CAP 0x0400 /* Can pause */\r
-#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */\r
-#define LPA_RESV 0x1000 /* Unused... */\r
-#define LPA_RFAULT 0x2000 /* Link partner faulted */\r
-#define LPA_LPACK 0x4000 /* Link partner acked us */\r
-#define LPA_NPAGE 0x8000 /* Next page bit */\r
-\r
-#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)\r
-#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)\r
-\r
-#if BOARD == EVK1100\r
-/*! RMII Bypass Register */\r
-#define RBR_RMII 0x0020 /* RMII Mode */\r
-/*! Interrupt Ctrl Register */\r
-#define MICR_INTEN 0x0002 /* Enable interrupts */\r
-#define MICR_INTOE 0x0001 /* Enable INT output */\r
-/*! Interrupt Status Register */\r
-#define MISR_ED_INT_EN 0x0040 /* Energy Detect enabled */\r
-#define MISR_LINK_INT_EN 0x0020 /* Link status change enabled */\r
-#define MISR_SPD_INT_EN 0x0010 /* Speed change enabled */\r
-#define MISR_DP_INT_EN 0x0008 /* Duplex mode change enabled */\r
-#define MISR_ANC_INT_EN 0x0004 /* Auto-Neg complete enabled */\r
-#define MISR_FHF_INT_EN 0x0002 /* False Carrier enabled */\r
-#define MISR_RHF_INT_EN 0x0001 /* Receive Error enabled */\r
-#define MISR_ED_INT 0x4000 /* Energy Detect */\r
-#define MISR_LINK_INT 0x2000 /* Link status change */\r
-#define MISR_SPD_INT 0x1000 /* Speed change */\r
-#define MISR_DP_INT 0x0800 /* Duplex mode change */\r
-#define MISR_ANC_INT 0x0400 /* Auto-Neg complete */\r
-#define MISR_FHF_INT 0x0200 /* False Carrier */\r
-#define MISR_RHF_INT 0x0100 /* Receive Error */\r
-/*! Phy Ctrl Register */\r
-#define PHYCR_MDIX_EN 0x8000 /* Enable Auto MDIX */\r
-#define PHYCR_MDIX_FORCE 0x4000 /* Force MDIX crossed */\r
-#endif\r
-\r
-/*! PHY ID */\r
-#define MII_DP83848_ID 0x20005C90 /* 0x00225541 */\r
-\r
-/*! PHY Address */\r
-#define DP83848_PHY_ADDR 0x01\r
-\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
/* ethernet includes */\r
#include "ethernet.h"\r
-#include "AVR32_EMAC.h"\r
+#include "conf_eth.h"\r
+#include "macb.h"\r
+#include "gpio.h"\r
\r
#if (HTTP_USED == 1)\r
#include "BasicWEB.h"\r
//_____ D E F I N I T I O N S ______________________________________________\r
\r
/* global variable containing MAC Config (hw addr, IP, GW, ...) */\r
-struct netif EMAC_if;\r
+struct netif MACB_if;\r
\r
//_____ D E C L A R A T I O N S ____________________________________________\r
\r
*/\r
void vStartEthernetTask( unsigned portBASE_TYPE uxPriority )\r
{\r
+static const gpio_map_t MACB_GPIO_MAP =\r
+{\r
+ {AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION },\r
+ {AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION },\r
+ {AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION },\r
+ {AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION },\r
+ {AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION },\r
+ {AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION },\r
+ {AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION },\r
+ {AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION },\r
+ {AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION },\r
+ {AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION}\r
+};\r
+\r
+ // Assign GPIO to MACB\r
+ gpio_enable_module(MACB_GPIO_MAP, sizeof(MACB_GPIO_MAP) / sizeof(MACB_GPIO_MAP[0]));\r
+\r
/* Setup lwIP. */\r
prvlwIPInit();\r
\r
#endif\r
\r
#if (SMTP_USED == 1)\r
- /* Create the SMTP Host task. This uses the lwIP RTOS abstraction layer.*/\r
- sys_thread_new( vBasicSMTPHost, ( void * ) NULL, ethSMTPHOST_PRIORITY );\r
+ /* Create the SMTP Client task. This uses the lwIP RTOS abstraction layer.*/\r
+ sys_thread_new( vBasicSMTPClient, ( void * ) NULL, ethSMTPCLIENT_PRIORITY );\r
#endif\r
\r
}\r
portCHAR MacAddress[6];\r
\r
/* Default MAC addr. */\r
- MacAddress[0] = emacETHADDR0;\r
- MacAddress[1] = emacETHADDR1;\r
- MacAddress[2] = emacETHADDR2;\r
- MacAddress[3] = emacETHADDR3;\r
- MacAddress[4] = emacETHADDR4;\r
- MacAddress[5] = emacETHADDR5;\r
+ MacAddress[0] = ETHERNET_CONF_ETHADDR0;\r
+ MacAddress[1] = ETHERNET_CONF_ETHADDR1;\r
+ MacAddress[2] = ETHERNET_CONF_ETHADDR2;\r
+ MacAddress[3] = ETHERNET_CONF_ETHADDR3;\r
+ MacAddress[4] = ETHERNET_CONF_ETHADDR4;\r
+ MacAddress[5] = ETHERNET_CONF_ETHADDR5;\r
\r
- /* pass the EMAC address to AVR32_EMAC module */\r
- vEMACSetMACAddress( MacAddress );\r
+ /* pass the MAC address to MACB module */\r
+ vMACBSetMACAddress( MacAddress );\r
\r
/* set MAC hardware address length to be used by lwIP */\r
- EMAC_if.hwaddr_len = 6;\r
+ MACB_if.hwaddr_len = 6;\r
\r
/* set MAC hardware address to be used by lwIP */\r
- memcpy( EMAC_if.hwaddr, MacAddress, EMAC_if.hwaddr_len );\r
+ memcpy( MACB_if.hwaddr, MacAddress, MACB_if.hwaddr_len );\r
\r
/* Default ip addr. */\r
- IP4_ADDR( &xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3 );\r
+ IP4_ADDR( &xIpAddr,ETHERNET_CONF_IPADDR0,ETHERNET_CONF_IPADDR1,ETHERNET_CONF_IPADDR2,ETHERNET_CONF_IPADDR3 );\r
\r
/* Default Subnet mask. */\r
- IP4_ADDR( &xNetMask,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3 );\r
+ IP4_ADDR( &xNetMask,ETHERNET_CONF_NET_MASK0,ETHERNET_CONF_NET_MASK1,ETHERNET_CONF_NET_MASK2,ETHERNET_CONF_NET_MASK3 );\r
\r
/* Default Gw addr. */\r
- IP4_ADDR( &xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3 );\r
+ IP4_ADDR( &xGateway,ETHERNET_CONF_GATEWAY_ADDR0,ETHERNET_CONF_GATEWAY_ADDR1,ETHERNET_CONF_GATEWAY_ADDR2,ETHERNET_CONF_GATEWAY_ADDR3 );\r
\r
/* add data to netif */\r
- netif_add( &EMAC_if, &xIpAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input );\r
+ netif_add( &MACB_if, &xIpAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input );\r
\r
/* make it the default interface */\r
- netif_set_default( &EMAC_if );\r
+ netif_set_default( &MACB_if );\r
\r
/* bring it up */\r
- netif_set_up( &EMAC_if );\r
+ netif_set_up( &MACB_if );\r
}\r
\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
--- /dev/null
+/* errno.h standard header */\r
+#ifndef _ERRNO\r
+#define _ERRNO\r
+\r
+#ifndef _SYSTEM_BUILD\r
+ #pragma system_include\r
+#endif\r
+\r
+#ifndef _YVALS\r
+ #include <yvals.h>\r
+#endif\r
+_C_STD_BEGIN\r
+\r
+ /* ERROR CODES */\r
+#define EDOM _EDOM\r
+#define ERANGE _ERANGE\r
+#define EFPOS _EFPOS\r
+#define EILSEQ _EILSEQ\r
+\r
+ /* lwip error codes, from cygwin errno.h */\r
+#define EIO 5 /* I/O error */\r
+#define EWOULDBLOCK 11 /* Operation would block */\r
+#define ENOMEM 12 /* Not enough core */\r
+#define EFAULT 14 /* Bad address */\r
+#define EINVAL 22 /* Invalid argument */\r
+#define ENOSYS 88 /* Function not implemented */\r
+#define ECONNRESET 104 /* Connection reset by peer */\r
+#define ENOBUFS 105 /* No buffer space available */\r
+#define ENOPROTOOPT 109 /* Protocol not available */\r
+#define ESHUTDOWN 110 /* Can't send after socket shutdown */\r
+#define EADDRINUSE 112 /* Address already in use */\r
+#define ECONNABORTED 113 /* Connection aborted */\r
+#define EHOSTUNREACH 118 /* Host is unreachable */\r
+#define ENOTCONN 128 /* Socket is not connected */\r
+\r
+#define _NERR 129 /* one more than last code */\r
+\r
+ /* DECLARATIONS */\r
+_C_LIB_DECL\r
+#if !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE\r
+ extern int _TLS_QUAL errno;\r
+\r
+#else /* !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE */\r
+ __INTRINSIC int *_Geterrno(void);\r
+\r
+ #define errno (*_Geterrno())\r
+#endif /* !_MULTI_THREAD || _COMPILER_TLS && !_GLOBAL_LOCALE */\r
+_END_C_LIB_DECL\r
+_C_STD_END\r
+#endif /* _ERRNO */\r
+\r
+#ifdef _STD_USING\r
+ #ifndef errno\r
+ using _CSTD errno;\r
+ #endif\r
+#endif /* _STD_USING */\r
+/*\r
+ * Copyright (c) 1992-2002 by P.J. Plauger. ALL RIGHTS RESERVED.\r
+ * Consult your license regarding permissions and restrictions.\r
+V3.12:0576 */\r
+\r
+\r
+\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
#define LWIP_PLATFORM_ASSERT(x) \r
\r
/* */\r
+#if __GNUC__\r
#define PACK_STRUCT_BEGIN\r
+#elif __ICCAVR32__\r
+#define PACK_STRUCT_BEGIN _Pragma("pack(1)")\r
+#endif\r
+\r
+#if __GNUC__\r
#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))\r
+#elif __ICCAVR32__\r
+#define PACK_STRUCT_STRUCT\r
+#endif\r
+\r
+#if __GNUC__\r
#define PACK_STRUCT_END\r
+#elif __ICCAVR32__\r
+#define PACK_STRUCT_END _Pragma("pack()")\r
+#endif\r
+\r
#define PACK_STRUCT_FIELD(x) x\r
\r
#endif /* __CC_H__ */\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*\r
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
* All rights reserved. \r
\r
/* FreeRTOS includes. */\r
#include "FreeRTOS.h"\r
-#include "AVR32_EMAC.h"\r
-#include "AVR32_CONF_EMAC.h"\r
+#include "macb.h"\r
\r
#define netifMTU ( 1500 )\r
#define netifGUARD_BLOCK_TIME ( 250 )\r
/* Do whatever else is needed to initialize interface. */ \r
xNetIf = netif;\r
\r
- /* Initialise the EMAC. This routine contains code that polls status bits.\r
+ /* Initialise the MACB. This routine contains code that polls status bits.\r
If the Ethernet cable is not plugged in then this can take a considerable\r
time. To prevent this starving lower priority tasks of processing time we\r
lower our priority prior to the call, then raise it back again once the\r
initialisation is complete. */\r
uxPriority = uxTaskPriorityGet( NULL );\r
vTaskPrioritySet( NULL, tskIDLE_PRIORITY );\r
- while( xEMACInit() == NULL )\r
+ while( xMACBInit(&AVR32_MACB) == FALSE )\r
{\r
- __asm( "NOP" );\r
+ __asm__ __volatile__ ( "nop" );\r
}\r
vTaskPrioritySet( NULL, uxPriority );\r
\r
- /* Create the task that handles the EMAC. */\r
+ /* Create the task that handles the MACB. */\r
// xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );\r
sys_thread_new( ethernetif_input, NULL, netifINTERFACE_TASK_PRIORITY );\r
}\r
pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */\r
#endif\r
\r
- /* Access to the EMAC is guarded using a semaphore. */\r
+ /* Access to the MACB is guarded using a semaphore. */\r
if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )\r
{\r
for( q = p; q != NULL; q = q->next )\r
time. The size of the data in each pbuf is kept in the ->len\r
variable. if q->next == NULL then this is the last pbuf in the\r
chain. */\r
- if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )\r
+ if( !lMACBSend(&AVR32_MACB, q->payload, q->len, ( q->next == NULL ) ) )\r
{\r
xReturn = ~ERR_OK;\r
}\r
}\r
-\r
- xSemaphoreGive( xTxSemaphore );\r
+ xSemaphoreGive( xTxSemaphore );\r
}\r
\r
\r
if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )\r
{\r
/* Obtain the size of the packet. */\r
- len = ulEMACInputLength();\r
+ len = ulMACBInputLength();\r
\r
if( len )\r
{\r
#endif\r
\r
/* Let the driver know we are going to read a new packet. */\r
- vEMACRead( NULL, 0, len );\r
+ vMACBRead( NULL, 0, len );\r
\r
/* We iterate over the pbuf chain until we have read the entire\r
packet into the pbuf. */\r
{\r
/* Read enough bytes to fill this pbuf in the chain. The\r
available data in the pbuf is given by the q->len variable. */\r
- vEMACRead( q->payload, q->len, len );\r
+ vMACBRead( q->payload, q->len, len );\r
}\r
\r
#if ETH_PAD_SIZE\r
{\r
/* No packet could be read. Wait a for an interrupt to tell us\r
there is more data available. */\r
- vEMACWaitForInput();\r
+ vMACBWaitForInput(100);\r
}\r
\r
} while( p == NULL );\r
* actual setup of the hardware.\r
*\r
*/\r
-extern struct netif EMAC_if;\r
+extern struct netif MACB_if;\r
err_t\r
ethernetif_init(struct netif *netif)\r
{\r
netif->output = ethernetif_output;\r
netif->linkoutput = low_level_output;\r
\r
- for(i = 0; i < 6; i++) netif->hwaddr[i] = EMAC_if.hwaddr[i];\r
+ for(i = 0; i < 6; i++) netif->hwaddr[i] = MACB_if.hwaddr[i];\r
\r
low_level_init(netif);\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*\r
* Copyright (c) 2001-2004 Swedish Institute of Computer Science.\r
* All rights reserved. \r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
if( uxQueueMessagesWaiting( mbox ) )\r
{\r
/* Line for breakpoint. Should never break here! */\r
- __asm volatile ( "NOP" );\r
+ __asm__ __volatile__ ( "nop" );\r
}\r
\r
vQueueDelete( mbox );\r
}\r
#endif\r
#if (SMTP_USED == 1)\r
- else if (thread == vBasicSMTPHost)\r
+ else if (thread == vBasicSMTPClient)\r
{\r
- result = xTaskCreate( thread, ( signed portCHAR * ) "SMTP", lwipBASIC_SMTP_HOST_STACK_SIZE, arg, prio, &CreatedTask );\r
+ result = xTaskCreate( thread, ( signed portCHAR * ) "SMTP", lwipBASIC_SMTP_CLIENT_STACK_SIZE, arg, prio, &CreatedTask );\r
}\r
#endif\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
*/\r
\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
-\r
+#include <avr32/io.h>\r
#include "FreeRTOS.h"\r
#include "task.h"\r
#include "partest.h"\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
/* Demo application includes. */\r
#include "serial.h"\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-#else\r
-# error Unknown compiler\r
-#endif\r
+#include <avr32/io.h>\r
#include "board.h"\r
#include "gpio.h"\r
\r
#if __GNUC__\r
__attribute__((__naked__))\r
#elif __ICCAVR32__\r
-#pragma shadow_registers = full // All registers shadowed\r
-#pragma handler = AVR32_USART0_IRQ_GROUP, 0\r
-__interrupt\r
+#pragma shadow_registers = full // Naked.\r
#endif\r
static void vUSART0_ISR( void )\r
{\r
*/\r
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
{\r
+ static const gpio_map_t USART0_GPIO_MAP =\r
+ {\r
+ { AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION },\r
+ { AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION }\r
+ };\r
+\r
xComPortHandle xReturn = serHANDLE;\r
volatile avr32_usart_t *usart0 = &AVR32_USART0;\r
int cd; /* USART0 Clock Divider. */\r
** Configure USART0.\r
**/\r
/* Enable USART0 RXD & TXD pins. */\r
- gpio_enable_module_pin(AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION);\r
- gpio_enable_module_pin(AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION);\r
+ gpio_enable_module( USART0_GPIO_MAP, sizeof( USART0_GPIO_MAP ) / sizeof( USART0_GPIO_MAP[0] ) );\r
\r
/* Set the USART0 baudrate to be as close as possible to the wanted baudrate. */\r
/*\r
/* Write the Transmit Timeguard Register */\r
usart0->ttgr = 0;\r
\r
-#if __GNUC__\r
// Register the USART0 interrupt handler to the interrupt controller and\r
// enable the USART0 interrupt.\r
- INTC_register_interrupt(&vUSART0_ISR, AVR32_USART0_IRQ, INT1);\r
-#endif\r
+ INTC_register_interrupt((__int_handler)&vUSART0_ISR, AVR32_USART0_IRQ, INT1);\r
\r
/* Enable USART0 interrupt sources (but not Tx for now)... */\r
usart0->ier = AVR32_USART_IER_RXRDY_MASK;\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AVR32 UC3 ISP trampoline.\r
+ *\r
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII\r
+ * without having to take the general-purpose fuses into consideration, add this\r
+ * file to the project and change the program entry point to _trampoline.\r
+ *\r
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32UC devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "../conf_isp.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+ // This must be linked @ 0x80000000 if it is to be run upon reset.\r
+ .section .reset, "ax", @progbits\r
+\r
+\r
+ .global _trampoline\r
+ .type _trampoline, @function\r
+_trampoline:\r
+ // Jump to program start.\r
+ rjmp program_start\r
+\r
+ .org PROGRAM_START_OFFSET\r
+program_start:\r
+ // Jump to the C runtime startup routine.\r
+ lda.w pc, _stext\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief AVR32 UC3 ISP trampoline.\r
+ *\r
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII\r
+ * without having to take the general-purpose fuses into consideration, add this\r
+ * file to the project and change the program entry point to __trampoline.\r
+ *\r
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: All AVR32UC devices can be used.\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include "../conf_isp.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+ RSEG SSTACK:DATA:NOROOT(2)\r
+\r
+\r
+ // This must be linked @ 0x80000000 if it is to be run upon reset.\r
+ RSEG RESET:CODE:NOROOT(1)\r
+\r
+\r
+ PUBLIC __trampoline\r
+__trampoline:\r
+ // Jump to program start.\r
+ rjmp program_start\r
+\r
+ ORG PROGRAM_START_OFFSET\r
+program_start:\r
+ // Initialize the stack pointer.\r
+ lddpc sp, ??SPS\r
+ // Jump to the C runtime startup routine.\r
+ lddpc pc, ??cmain\r
+\r
+\r
+// Constant data area.\r
+\r
+ ALIGN 2\r
+\r
+??SPS:\r
+ DC32 SFE(SSTACK) & ~3\r
+\r
+ EXTERN ?main\r
+??cmain:\r
+ DC32 ?main\r
+\r
+\r
+ END\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
--- /dev/null
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file ******************************************************************\r
+ *\r
+ * \brief ISP configuration file.\r
+ *\r
+ * This file contains the possible external configuration of the ISP.\r
+ *\r
+ * - Compiler: IAR EWAVR32 and GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices with a USB module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ***************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#ifndef _CONF_ISP_H_\r
+#define _CONF_ISP_H_\r
+\r
+#include <avr32/io.h>\r
+#include "compiler.h"\r
+\r
+\r
+//_____ D E F I N I T I O N S ______________________________________________\r
+\r
+#define PRODUCT_MANUFACTURER_ID 0x58\r
+#define PRODUCT_FAMILY_ID 0x20\r
+\r
+#define ISP_VERSION 0x00\r
+#define ISP_ID0 0x00\r
+#define ISP_ID1 0x00\r
+\r
+#define ISP_GPFB_FORCE 31\r
+#define ISP_GPFB_FORCE_MASK 0x80000000\r
+#define ISP_GPFB_FORCE_OFFSET 31\r
+#define ISP_GPFB_FORCE_SIZE 1\r
+\r
+#define ISP_GPFB_IO_COND_EN 30\r
+#define ISP_GPFB_IO_COND_EN_MASK 0x40000000\r
+#define ISP_GPFB_IO_COND_EN_OFFSET 30\r
+#define ISP_GPFB_IO_COND_EN_SIZE 1\r
+\r
+#define ISP_GPFB_BOD_EN 29\r
+#define ISP_GPFB_BOD_EN_MASK 0x20000000\r
+#define ISP_GPFB_BOD_EN_OFFSET 29\r
+#define ISP_GPFB_BOD_EN_SIZE 1\r
+\r
+#define ISP_CFG (*(volatile U32 *)ISP_CFG_ADDRESS)\r
+#define ISP_CFG_ADDRESS (AVR32_FLASHC_USER_PAGE_ADDRESS + ISP_CFG_OFFSET)\r
+#define ISP_CFG_OFFSET 0x000001FC\r
+#define ISP_CFG_SIZE 4\r
+\r
+#define ISP_CFG_BOOT_KEY 17\r
+#define ISP_CFG_BOOT_KEY_MASK 0xFFFE0000\r
+#define ISP_CFG_BOOT_KEY_OFFSET 17\r
+#define ISP_CFG_BOOT_KEY_SIZE 15\r
+#define ISP_CFG_BOOT_KEY_VALUE 0x494F\r
+\r
+#define ISP_CFG_IO_COND_LEVEL 16\r
+#define ISP_CFG_IO_COND_LEVEL_MASK 0x00010000\r
+#define ISP_CFG_IO_COND_LEVEL_OFFSET 16\r
+#define ISP_CFG_IO_COND_LEVEL_SIZE 1\r
+\r
+#define ISP_CFG_IO_COND_PIN 8\r
+#define ISP_CFG_IO_COND_PIN_MASK 0x0000FF00\r
+#define ISP_CFG_IO_COND_PIN_OFFSET 8\r
+#define ISP_CFG_IO_COND_PIN_SIZE 8\r
+\r
+#define ISP_CFG_CRC8 0\r
+#define ISP_CFG_CRC8_MASK 0x000000FF\r
+#define ISP_CFG_CRC8_OFFSET 0\r
+#define ISP_CFG_CRC8_SIZE 8\r
+#define ISP_CFG_CRC8_POLYNOMIAL 0x107\r
+\r
+#define ISP_KEY (*(volatile U32 *)ISP_KEY_ADDRESS)\r
+#define ISP_KEY_ADDRESS (AVR32_SRAM_ADDRESS + ISP_KEY_OFFSET)\r
+#define ISP_KEY_OFFSET 0x00000000\r
+#define ISP_KEY_SIZE 4\r
+#define ISP_KEY_VALUE ('I' << 24 | 'S' << 16 | 'P' << 8 | 'K')\r
+\r
+#ifndef ISP_OSC\r
+ #define ISP_OSC 0\r
+#endif\r
+\r
+#define DFU_FRAME_LENGTH 2048\r
+\r
+#define PROGRAM_START_ADDRESS (AVR32_FLASH_ADDRESS + PROGRAM_START_OFFSET)\r
+#define PROGRAM_START_OFFSET 0x00002000\r
+\r
+\r
+#endif // _CONF_ISP_H_\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
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+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
+ .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH
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+ .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+ .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+ .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+ .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH
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+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
+ .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+ .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
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+ .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH
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+ .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH :FLASH
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+ .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .plt : { *(.plt) } >FLASH AT>FLASH :FLASH
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
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+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
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+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
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+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
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+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
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+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
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+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
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+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
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+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
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+ } >INTRAM AT>INTRAM :INTRAM
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+ /* Stabs debugging sections. */
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+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
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+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A0512 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A0512
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
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+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
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+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
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+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
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+ _end = .;
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+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A0512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A0512:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8007FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A0512\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
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+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
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+ /* Use a default stack size if stack size was not defined. */
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+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
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+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
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+}
+
+SECTIONS
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+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+ .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
+ .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH
+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
+ {
+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+ __heap_size__;
+ } >INTRAM AT>INTRAM :INTRAM
+ __heap_end__ = .;
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
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+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
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+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
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+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
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+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3A1512 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3A1512
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00080000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x0000FFFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
+ .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH
+ .dynstr : { *(.dynstr) } >FLASH AT>FLASH :FLASH
+ .gnu.version : { *(.gnu.version) } >FLASH AT>FLASH :FLASH
+ .gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH :FLASH
+ .gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH :FLASH
+ .rel.init : { *(.rel.init) } >FLASH AT>FLASH :FLASH
+ .rela.init : { *(.rela.init) } >FLASH AT>FLASH :FLASH
+ .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) } >FLASH AT>FLASH :FLASH
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+ .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
+ .rela.fini : { *(.rela.fini) } >FLASH AT>FLASH :FLASH
+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) } >FLASH AT>FLASH :FLASH
+ .rel.ctors : { *(.rel.ctors) } >FLASH AT>FLASH :FLASH
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+ .rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH :FLASH
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+ .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH
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+ .rela.plt : { *(.rela.plt) } >FLASH AT>FLASH :FLASH
+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .plt : { *(.plt) } >FLASH AT>FLASH :FLASH
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
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+ .eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH :FLASH
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
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+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
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+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
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+ is in. */
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+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
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+ {
+ *(.data .data.* .gnu.linkonce.d.*)
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+ /* SGI/MIPS DWARF 2 extensions */
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+ *(.stack)
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+ _estack = .;
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+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3A1512 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3A1512:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x0000FFFF SRAM RAM\r
+ * 0x80000000 0x8007FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3A1512\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8007FFFF\r
+-Z@(CODE)EV100=80004100-8007FFFF\r
+-P(CODE)EVSEG=80004000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8007FFFF\r
+-P(CONST)DATA32_C=80000000-8007FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8007FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8007FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8007FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8007FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-0000FFFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-0000FFFF\r
+-Z(DATA)TRACEBUFFER=00000004-0000FFFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-0000FFFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-0000FFFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B0128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B0128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .plt : { *(.plt) } >FLASH AT>FLASH :FLASH
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
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+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH :FLASH
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+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
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+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
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+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
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+ PROVIDE (edata = .);
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+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
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+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
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+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
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+ } >INTRAM AT>INTRAM :INTRAM
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+ /* Stabs debugging sections. */
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+ Symbols in the DWARF debugging sections are relative to the beginning
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
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+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B0128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B0128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B0128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B0256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B0256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
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+ .fini :
+ {
+ KEEP (*(.fini))
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+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
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+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B0256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B0256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B0256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
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+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B064 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B064
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
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+
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+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B064 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B064:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00003FFF SRAM RAM\r
+ * 0x80000000 0x8000FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B064\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8000FFFF\r
+-Z@(CODE)EV100=80004100-8000FFFF\r
+-P(CODE)EVSEG=80004000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8000FFFF\r
+-P(CONST)DATA32_C=80000000-8000FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00003FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B1128 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B1128
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00020000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
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+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
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+}
+
+SECTIONS
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+ } >INTRAM AT>FLASH :FLASH
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >INTRAM AT>FLASH :FLASH
+ .jcr : { KEEP (*(.jcr)) } >INTRAM AT>FLASH :FLASH
+ .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >INTRAM AT>FLASH :FLASH
+ .dynamic : { *(.dynamic) } >INTRAM AT>FLASH :FLASH
+ .got : { *(.got.plt) *(.got) } >INTRAM AT>FLASH :FLASH
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >INTRAM AT>FLASH :FLASH
+ .data1 : { *(.data1) } >INTRAM AT>FLASH :FLASH
+ .balign : { . = ALIGN(8); _edata = .; } >INTRAM AT>FLASH :FLASH
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
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+ . = ALIGN(8);
+ } >INTRAM AT>INTRAM :INTRAM
+ . = ALIGN(8);
+ _end = .;
+ PROVIDE (end = .);
+ __heap_start__ = ALIGN(8);
+ .heap :
+ {
+ *(.heap)
+ . = (__heap_size__ == __max_heap_size__) ?
+ ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ - ABSOLUTE(.) :
+ __heap_size__;
+ } >INTRAM AT>INTRAM :INTRAM
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+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
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+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
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+ /* DWARF 1.1 and DWARF 2 */
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+ /* DWARF 2 */
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+ /* SGI/MIPS DWARF 2 extensions */
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+ .stack ORIGIN(INTRAM) + LENGTH(INTRAM) - __stack_size__ :
+ {
+ _stack = .;
+ *(.stack)
+ . = __stack_size__;
+ _estack = .;
+ } >INTRAM AT>INTRAM :INTRAM
+ .userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE :USERPAGE
+ .factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE :FACTORYPAGE
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B1128 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B1128:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8001FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B1128\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8001FFFF\r
+-Z@(CODE)EV100=80004100-8001FFFF\r
+-P(CODE)EVSEG=80004000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8001FFFF\r
+-P(CONST)DATA32_C=80000000-8001FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8001FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8001FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8001FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8001FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B1256 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B1256
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00040000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
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+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
+ .hash : { *(.hash) } >FLASH AT>FLASH :FLASH
+ .dynsym : { *(.dynsym) } >FLASH AT>FLASH :FLASH
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+ .rel.got : { *(.rel.got) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
+ KEEP (*(.init))
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+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
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+ .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH :FLASH
+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
+ .dalign : { . = ALIGN(8); PROVIDE(_data = .); } >INTRAM AT>INTRAM :INTRAM
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >INTRAM AT>FLASH :FLASH
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >INTRAM AT>FLASH :FLASH
+ /* Ensure the __preinit_array_start label is properly aligned. We
+ could instead move the label definition inside the section, but
+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
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+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
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+ is in. */
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+ KEEP (*(.dtors))
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+ *(.data .data.* .gnu.linkonce.d.*)
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+ . = ALIGN(8);
+ _end = .;
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+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B1256 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B1256:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00007FFF SRAM RAM\r
+ * 0x80000000 0x8003FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B1256\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8003FFFF\r
+-Z@(CODE)EV100=80004100-8003FFFF\r
+-P(CODE)EVSEG=80004000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8003FFFF\r
+-P(CONST)DATA32_C=80000000-8003FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8003FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8003FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8003FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8003FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00007FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00007FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00007FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00007FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00007FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
--- /dev/null
+/******************************************************************************
+ * AVR32 AT32UC3B164 GNU LD script file.
+ *
+ * - Compiler: GNU GCC for AVR32
+ * - Supported devices: AVR32 AT32UC3B164
+ *
+ * - author Atmel Corporation: http://www.atmel.com \n
+ * Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+
+OUTPUT_ARCH(avr32:uc)
+
+ENTRY(_start)
+
+MEMORY
+{
+ FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 0x00010000
+ INTRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x00003FFC
+ USERPAGE : ORIGIN = 0x80800000, LENGTH = 0x00000200
+ FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 0x00000200
+}
+
+PHDRS
+{
+ FLASH PT_LOAD;
+ INTRAM PT_NULL;
+ USERPAGE PT_LOAD;
+ FACTORYPAGE PT_LOAD;
+}
+
+SECTIONS
+{
+ /* If this heap size is selected, all the INTRAM space from the end of the
+ data area to the beginning of the stack will be allocated for the heap. */
+ __max_heap_size__ = -1;
+
+ /* Use a default heap size if heap size was not defined. */
+ __heap_size__ = DEFINED(__heap_size__) ? __heap_size__ : __max_heap_size__;
+
+ /* Use a default stack size if stack size was not defined. */
+ __stack_size__ = DEFINED(__stack_size__) ? __stack_size__ : 4K;
+
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
+ .interp : { *(.interp) } >FLASH AT>FLASH :FLASH
+ .reset : { *(.reset) } >FLASH AT>FLASH :FLASH
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+ .rel.fini : { *(.rel.fini) } >FLASH AT>FLASH :FLASH
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+ .init :
+ {
+ KEEP (*(.init))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
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+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >FLASH AT>FLASH :FLASH =0xd703d703
+ PROVIDE (__etext = .);
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+ .lalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH :FLASH
+ . = ORIGIN(INTRAM);
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+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >INTRAM AT>FLASH :FLASH
+ .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >INTRAM AT>FLASH :FLASH
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+ /* Ensure the __preinit_array_start label is properly aligned. We
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+ the linker would then create the section even if it turns out to
+ be empty, which isn't pretty. */
+ PROVIDE (__preinit_array_start = ALIGN(32 / 8));
+ .preinit_array : { KEEP (*(.preinit_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__preinit_array_end = .);
+ PROVIDE (__init_array_start = .);
+ .init_array : { KEEP (*(.init_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__init_array_end = .);
+ PROVIDE (__fini_array_start = .);
+ .fini_array : { KEEP (*(.fini_array)) } >INTRAM AT>FLASH :FLASH
+ PROVIDE (__fini_array_end = .);
+ .ctors :
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+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
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+ /* We don't want to include the .ctor section from
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+ KEEP (*(.dtors))
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+ PROVIDE (end = .);
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+ . = (__heap_size__ == __max_heap_size__) ?
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+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/******************************************************************************\r
+ * AVR32 AT32UC3B164 XLINK command file for AVR32 IAR C/C++ Compiler.\r
+ *\r
+ * The assumed memory layout is the one of the AT32UC3B164:\r
+ *\r
+ * Start Stop Name Type\r
+ * ---------- ---------- ----- --------------\r
+ * 0x00000000 0x00003FFF SRAM RAM\r
+ * 0x80000000 0x8000FFFF FLASH FLASH\r
+ *\r
+ * Usage: xlink your_file(s) -f xcl-file libraries\r
+ *\r
+ * - Compiler: IAR EWAVR32\r
+ * - Supported devices: AVR32 AT32UC3B164\r
+ *\r
+ * - author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+/************************************************************************/\r
+/* The following segments are defined in this link file: */\r
+/* */\r
+/* Code segments */\r
+/* CODE32 -- Program code used by __code32 functions. */\r
+/* RESET -- Reset code. */\r
+/* EVSEG -- Exception vector handlers. */\r
+/* */\r
+/* Constant segments */\r
+/* INITTAB -- Segment initializer table. */\r
+/* DIFUNCT -- Dynamic initialization vector used by C++. */\r
+/* SWITCH -- Switch tables. */\r
+/* ACTAB -- Table of pointers to acall functions. */\r
+/* */\r
+/* DATA21_ID -- Initialization data for DATA21_I. */\r
+/* DATA32_ID -- Initialization data for DATA32_I. */\r
+/* DATA32_C -- Constant __data32 data. */\r
+/* */\r
+/* CHECKSUM -- Checksum segment. */\r
+/* */\r
+/* Data segments */\r
+/* DATA21_I -- Initialized __data21 data with non-zero */\r
+/* initial value. */\r
+/* DATA32_I -- Initialized __data32 data with non-zero */\r
+/* initial value. */\r
+/* DATA21_Z -- Initialized __data21 data with zero initial value. */\r
+/* DATA32_Z -- Initialized __data32 data with zero initial value. */\r
+/* DATA21_N -- Non-initialized __data21. */\r
+/* DATA32_N -- Non-initialized __data32. */\r
+/* SSTACK -- The system stack. */\r
+/* CSTACK -- The application stack. */\r
+/* HEAP -- The heap used by malloc and free. */\r
+/* */\r
+/************************************************************************/\r
+\r
+/************************************************************************/\r
+/* Define CPU */\r
+/************************************************************************/\r
+\r
+-cavr32\r
+\r
+// Declare the IPR0 memory location\r
+-DIPR0=FFFF0800\r
+\r
+/************************************************************************/\r
+/* Reset code is located at address 0x80000000 and up. */\r
+/************************************************************************/\r
+\r
+-Z(CODE)RESET=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* The exception handler code is located at address 0x80000000 */\r
+/* and up. Make sure that the exception table gets properly */\r
+/* allocated. By using the special -Z@ allocation primitive, the */\r
+/* placement is guaranteed to be at _EVBASE and onwards. */\r
+/************************************************************************/\r
+\r
+-Z@(CODE)EVTAB=80004000-8000FFFF\r
+-Z@(CODE)EV100=80004100-8000FFFF\r
+-P(CODE)EVSEG=80004000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate code and const segments. */\r
+/************************************************************************/\r
+\r
+-P(CODE)CODE32=80000000-8000FFFF\r
+-P(CONST)DATA32_C=80000000-8000FFFF\r
+\r
+// Initializers\r
+-Z(CONST)INITTAB,DIFUNCT=80000000-8000FFFF\r
+-Z(CONST)CHECKSUM,SWITCH=80000000-8000FFFF\r
+-Z(CONST)DATA21_ID,DATA32_ID=80000000-8000FFFF\r
+\r
+-Z(CONST)ACTAB,HTAB=80000000-8000FFFF\r
+\r
+/************************************************************************/\r
+/* Allocate the read/write segments that are mapped to RAM. */\r
+/************************************************************************/\r
+\r
+-Z(DATA)DATA21_I,DATA21_Z,DATA21_N=00000004-00003FFF\r
+-Z(DATA)DATA32_I,DATA32_Z,DATA32_N=00000004-00003FFF\r
+-Z(DATA)TRACEBUFFER=00000004-00003FFF\r
+\r
+-Z(DATA)SSTACK+_SSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)CSTACK+_CSTACK_SIZE#00000004-00003FFF\r
+-Z(DATA)HEAP+_HEAP_SIZE=00000004-00003FFF\r
+\r
+/************************************************************************/\r
+/* End of File */\r
+/************************************************************************/\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
/*! \brief Stringize.\r
*\r
- * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
*\r
- * May be used only within macros with the token passed as an argument if the token is #defined.\r
+ * May be used only within macros with the token passed as an argument if the token is \#defined.\r
*\r
- * For example, writing STRINGZ(PIN) within a macro #defined by PIN_NAME(PIN)\r
- * and invoked as PIN_NAME(PIN0) with PIN0 #defined as A0 is equivalent to\r
+ * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)\r
+ * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to\r
* writing "A0".\r
*/\r
#define STRINGZ(x) #x\r
\r
/*! \brief Absolute stringize.\r
*\r
- * Stringize a preprocessing token, this token being allowed to be #defined.\r
+ * Stringize a preprocessing token, this token being allowed to be \#defined.\r
*\r
- * No restriction of use if the token is #defined.\r
+ * No restriction of use if the token is \#defined.\r
*\r
- * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 #defined as A0 is\r
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is\r
* equivalent to writing "A0".\r
*/\r
#define ASTRINGZ(x) STRINGZ(x)\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - Supported devices: All AVR32 devices can be used.\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
/*! \name Token Paste\r
*\r
- * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
*\r
- * May be used only within macros with the tokens passed as arguments if the tokens are #defined.\r
+ * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.\r
*\r
- * For example, writing TPASTE2(U, WIDTH) within a macro #defined by\r
- * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH #defined as 32 is\r
+ * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by\r
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is\r
* equivalent to writing U32.\r
*/\r
//! @{\r
\r
/*! \name Absolute Token Paste\r
*\r
- * Paste N preprocessing tokens together, these tokens being allowed to be #defined.\r
+ * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.\r
*\r
- * No restriction of use if the tokens are #defined.\r
+ * No restriction of use if the tokens are \#defined.\r
*\r
- * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH #defined\r
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined\r
* as 32 is equivalent to writing U32.\r
*/\r
//! @{\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
#ifndef _COMPILER_H_\r
#define _COMPILER_H_\r
\r
-#if __GNUC__\r
-# include <avr32/io.h>\r
-#elif __ICCAVR32__ || __AAVR32__\r
-# include <avr32/iouc3a0512.h>\r
-# include <avr32/uc3a0512.h>\r
-# if __ICCAVR32__\r
-# include <intrinsics.h>\r
-# endif\r
-#else\r
-# error Unknown compiler\r
+#include <avr32/io.h>\r
+#if __ICCAVR32__\r
+# include <intrinsics.h>\r
#endif\r
-\r
#include "preprocessor.h"\r
\r
\r
#include <stddef.h>\r
#include <stdlib.h>\r
\r
+\r
+#if __ICCAVR32__\r
+\r
+/*! \name Compiler Keywords\r
+ *\r
+ * Port of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
+ */\r
+//! @{\r
+#define __asm__ asm\r
+#define __inline__ inline\r
+#define __volatile__\r
+//! @}\r
+\r
+#endif\r
+\r
+\r
/*! \name Usual Types\r
*/\r
//! @{\r
typedef double F64; //!< 64-bit floating-point number.\r
//! @}\r
\r
+\r
/*! \name Status Types\r
*/\r
//! @{\r
typedef U8 Status_t; //!< 8-bit-coded status.\r
//! @}\r
\r
-#if __ICCAVR32__\r
-\r
-/*! \name Compiler Keywords\r
- *\r
- * Translation of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.\r
- */\r
-//! @{\r
-#define __asm__ asm\r
-#define __inline__ inline\r
-#define __volatile__\r
-//! @}\r
-\r
-#endif\r
\r
/*! \name Aliasing Aggregate Types\r
*/\r
\r
#endif // __AVR32_ABI_COMPILER__\r
\r
+\r
//_____ M A C R O S ________________________________________________________\r
\r
/*! \name Usual Constants\r
#define SET 1\r
//! @}\r
\r
+\r
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
\r
-/*! \name Bit-Field Handling Macros\r
+/*! \name Bit-Field Handling\r
*/\r
//! @{\r
\r
\r
//! @}\r
\r
+\r
/*! \brief This macro is used to test fatal errors.\r
*\r
* The macro tests if the expression is FALSE. If it is, a fatal error is\r
#define Assert(expr)\r
#endif\r
\r
-/*! \name Zero-Bit Counting Macros\r
+\r
+/*! \name Zero-Bit Counting\r
*\r
* Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when\r
* applied to constant expressions (values known at compile time), so they are\r
\r
//! @}\r
\r
-/*! \name Alignment Macros\r
+\r
+/*! \name Alignment\r
*/\r
//! @{\r
\r
\r
//! @}\r
\r
-/*! \name Mathematics Macros\r
+\r
+/*! \name Mathematics\r
*\r
* The same considerations as for clz and ctz apply here but AVR32-GCC does not\r
* provide built-in functions to access the assembly instructions abs, min and\r
\r
//! @}\r
\r
+\r
/*! \brief Calls the routine at address \a addr.\r
*\r
* It generates a long call opcode.\r
(\\r
{\\r
__asm__ __volatile__ (\\r
- "lda.w r8, _start\n\t"\\r
- "lddpc r9, 1f\n\t"\\r
- "stm --sp, r8-r9\n\t"\\r
+ "lddpc r9, 3f\n\t"\\r
"mfsr r8, %[SR]\n\t"\\r
"bfextu r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\\r
"cp.w r8, 0b001\n\t"\\r
"breq 0f\n\t"\\r
+ "sub r8, pc, $ - 1f\n\t"\\r
+ "pushm r8-r9\n\t"\\r
"rete\n"\\r
"0:\n\t"\\r
- "rets\n\t"\\r
- ".balign 4\n"\\r
+ "mtsr %[SR], r9\n"\\r
"1:\n\t"\\r
+ "mov r0, 0\n\t"\\r
+ "mov r1, 0\n\t"\\r
+ "mov r2, 0\n\t"\\r
+ "mov r3, 0\n\t"\\r
+ "mov r4, 0\n\t"\\r
+ "mov r5, 0\n\t"\\r
+ "mov r6, 0\n\t"\\r
+ "mov r7, 0\n\t"\\r
+ "mov r8, 0\n\t"\\r
+ "mov r9, 0\n\t"\\r
+ "mov r10, 0\n\t"\\r
+ "mov r11, 0\n\t"\\r
+ "mov r12, 0\n\t"\\r
+ "mov sp, 0\n\t"\\r
+ "stdsp sp[0], sp\n\t"\\r
+ "ldmts sp, sp\n\t"\\r
+ "mov lr, 0\n\t"\\r
+ "lddpc pc, 2f\n\t"\\r
+ ".balign 4\n"\\r
+ "2:\n\t"\\r
+ ".word _start\n"\\r
+ "3:\n\t"\\r
".word %[RESET_SR]"\\r
:\\r
: [SR] "i" (AVR32_SR),\\r
{\\r
extern void *volatile __program_start;\\r
__asm__ __volatile__ (\\r
- "mov r8, LWRD(__program_start)\n\t"\\r
- "orh r8, HWRD(__program_start)\n\t"\\r
+ "mov r7, LWRD(__program_start)\n\t"\\r
+ "orh r7, HWRD(__program_start)\n\t"\\r
"mov r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
"orh r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\\r
- "stm --sp, r8-r9\n\t"\\r
"mfsr r8, "ASTRINGZ(AVR32_SR)"\n\t"\\r
"bfextu r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\\r
"cp.w r8, 001b\n\t"\\r
- "breq $ + 4\n\t"\\r
+ "breq $ + 10\n\t"\\r
+ "sub r8, pc, -12\n\t"\\r
+ "pushm r8-r9\n\t"\\r
"rete\n\t"\\r
- "rets"\\r
+ "mtsr "ASTRINGZ(AVR32_SR)", r9\n\t"\\r
+ "mov r0, 0\n\t"\\r
+ "mov r1, 0\n\t"\\r
+ "mov r2, 0\n\t"\\r
+ "mov r3, 0\n\t"\\r
+ "mov r4, 0\n\t"\\r
+ "mov r5, 0\n\t"\\r
+ "mov r6, 0\n\t"\\r
+ "st.w r0[4], r7\n\t"\\r
+ "mov r7, 0\n\t"\\r
+ "mov r8, 0\n\t"\\r
+ "mov r9, 0\n\t"\\r
+ "mov r10, 0\n\t"\\r
+ "mov r11, 0\n\t"\\r
+ "mov r12, 0\n\t"\\r
+ "mov sp, 0\n\t"\\r
+ "stdsp sp[0], sp\n\t"\\r
+ "ldmts sp, sp\n\t"\\r
+ "mov lr, 0\n\t"\\r
+ "ld.w pc, lr[4]"\\r
);\\r
__program_start;\\r
-}\r
+ }\r
#endif\r
\r
-/*! \name CPU Status Register Macros\r
+\r
+/*! \name System Register Access\r
*/\r
//! @{\r
\r
-/*! \brief Disables all exceptions.\r
+/*! \brief Gets the value of the \a sysreg system register.\r
+ *\r
+ * \param sysreg Address of the system register of which to get the value.\r
+ *\r
+ * \return Value of the \a sysreg system register.\r
+ */\r
+#if __GNUC__\r
+ #define Get_system_register(sysreg) __builtin_mfsr(sysreg)\r
+#elif __ICCAVR32__\r
+ #define Get_system_register(sysreg) __get_system_register(sysreg)\r
+#endif\r
+\r
+/*! \brief Sets the value of the \a sysreg system register to \a value.\r
+ *\r
+ * \param sysreg Address of the system register of which to set the value.\r
+ * \param value Value to set the \a sysreg system register to.\r
+ */\r
+#if __GNUC__\r
+ #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)\r
+#elif __ICCAVR32__\r
+ #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)\r
+#endif\r
+\r
+//! @}\r
+\r
+\r
+/*! \name CPU Status Register Access\r
+ */\r
+//! @{\r
+\r
+/*! \brief Tells whether exceptions are globally enabled.\r
+ *\r
+ * \return \c 1 if exceptions are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_exception_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_EM_MASK))\r
+\r
+/*! \brief Disables exceptions globally.\r
*/\r
#if __GNUC__\r
#define Disable_global_exception() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
#define Disable_global_exception() (__set_status_flag(AVR32_SR_EM_OFFSET))\r
#endif\r
\r
-/*! \brief Enables all exceptions.\r
+/*! \brief Enables exceptions globally.\r
*/\r
#if __GNUC__\r
#define Enable_global_exception() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_EM_OFFSET));})\r
#define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))\r
#endif\r
\r
-/*! \brief Disables all interrupts.\r
+/*! \brief Tells whether interrupts are globally enabled.\r
+ *\r
+ * \return \c 1 if interrupts are globally enabled, else \c 0.\r
+ */\r
+#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))\r
+\r
+/*! \brief Disables interrupts globally.\r
*/\r
#if __GNUC__\r
#define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" : : "i" (AVR32_SR_GM_OFFSET));})\r
#define Disable_global_interrupt() {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}\r
#endif\r
\r
-/*! \brief Enables all interrupts.\r
+/*! \brief Enables interrupts globally.\r
*/\r
#if __GNUC__\r
#define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})\r
#define Enable_global_interrupt() (__enable_interrupt())\r
#endif\r
\r
+/*! \brief Tells whether interrupt level \a int_lev is enabled.\r
+ *\r
+ * \param int_lev Interrupt level (0 to 3).\r
+ *\r
+ * \return \c 1 if interrupt level \a int_lev is enabled, else \c 0.\r
+ */\r
+#define Is_interrupt_level_enabled(int_lev) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_lev, M_MASK)))\r
+\r
/*! \brief Disables interrupt level \a int_lev.\r
*\r
* \param int_lev Interrupt level to disable (0 to 3).\r
\r
//! @}\r
\r
-/*! \name System Register Access Macros\r
- */\r
-//! @{\r
-\r
-/*! \brief Gets the value of the \a sysreg system register.\r
- *\r
- * \param sysreg Address of the system register of which to get the value.\r
- *\r
- * \return Value of the \a sysreg system register.\r
- */\r
-#if __GNUC__\r
- #define Get_system_register(sysreg) __builtin_mfsr(sysreg)\r
-#elif __ICCAVR32__\r
- #define Get_system_register(sysreg) __get_system_register(sysreg)\r
-#endif\r
-\r
-/*! \brief Sets the value of the \a sysreg system register to \a value.\r
- *\r
- * \param sysreg Address of the system register of which to set the value.\r
- * \param value Value to set the \a sysreg system register to.\r
- */\r
-#if __GNUC__\r
- #define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)\r
-#elif __ICCAVR32__\r
- #define Set_system_register(sysreg, value) __set_system_register(sysreg, value)\r
-#endif\r
-\r
-//! @}\r
-\r
#endif // __AVR32_ABI_COMPILER__\r
\r
+\r
//! Boolean evaluating MCU little endianism.\r
#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)\r
#define LITTLE_ENDIAN_MCU FALSE\r
//! Boolean evaluating MCU big endianism.\r
#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)\r
\r
+\r
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.\r
\r
-/*! \name U16/U32/U64 MCU Endianism Handling Macros\r
+/*! \name MCU Endianism Handling\r
*/\r
//! @{\r
+\r
#if LITTLE_ENDIAN_MCU\r
+\r
#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.\r
#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.\r
+\r
#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.\r
#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.\r
#define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.\r
#define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.\r
#define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.\r
#define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.\r
- #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
- #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
- #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
- #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+ #define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+ #define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+ #define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+ #define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.\r
#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.\r
#define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.\r
#define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.\r
#define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.\r
#define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.\r
- #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 1st rank of \a u64.\r
- #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 2nd rank of \a u64.\r
- #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 3rd rank of \a u64.\r
- #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64.\r
+ #define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64.\r
+ #define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64.\r
+ #define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64.\r
#define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.\r
#define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.\r
#define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.\r
#define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.\r
#define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.\r
#define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.\r
- #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 1st rank of \a u64.\r
- #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 2nd rank of \a u64.\r
- #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 3rd rank of \a u64.\r
- #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 4th rank of \a u64.\r
- #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 5th rank of \a u64.\r
- #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 6th rank of \a u64.\r
- #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 7th rank of \a u64.\r
- #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 8th rank of \a u64.\r
+ #define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64.\r
+ #define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64.\r
+ #define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64.\r
+ #define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64.\r
+ #define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64.\r
+ #define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64.\r
+ #define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64.\r
+ #define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64.\r
+\r
#else // BIG_ENDIAN_MCU\r
+\r
#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.\r
#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.\r
+\r
#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.\r
#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.\r
#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.\r
#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.\r
#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.\r
#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.\r
- #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
- #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
- #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
- #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+ #define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+ #define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+ #define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+ #define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+\r
#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.\r
#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.\r
#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.\r
#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.\r
#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.\r
#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.\r
- #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 1st rank of \a u64.\r
- #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
- #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
- #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.\r
+ #define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.\r
+ #define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.\r
+ #define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.\r
#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.\r
#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.\r
#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.\r
#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.\r
#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.\r
#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.\r
- #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 1st rank of \a u64.\r
- #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
- #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
- #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 4th rank of \a u64.\r
- #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 5th rank of \a u64.\r
- #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 6th rank of \a u64.\r
- #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 7th rank of \a u64.\r
- #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+ #define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.\r
+ #define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.\r
+ #define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.\r
+ #define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.\r
+ #define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.\r
+ #define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.\r
+ #define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.\r
+ #define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.\r
+\r
#endif\r
+\r
//! @}\r
\r
-/*! \name Endianism Conversion Macros\r
+\r
+/*! \name Endianism Conversion\r
*\r
* The same considerations as for clz and ctz apply here but AVR32-GCC's\r
* __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when\r
\r
//! @}\r
\r
+\r
+/*! \name Target Abstraction\r
+ */\r
+//! @{\r
+\r
+#define _GLOBEXT_ extern //!< extern storage-class specifier.\r
+#define _CONST_TYPE_ const //!< const type qualifier.\r
+#define _MEM_TYPE_SLOW_ //!< Slow memory type.\r
+#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.\r
+#define _MEM_TYPE_FAST_ //!< Fast memory type.\r
+\r
+typedef U8 Byte; //!< 8-bit unsigned integer.\r
+\r
+#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.\r
+#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.\r
+#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.\r
+#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.\r
+\r
+#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.\r
+#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.\r
+#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.\r
+#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.\r
+#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.\r
+#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.\r
+#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.\r
+#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.\r
+\r
+//! @}\r
+\r
#endif // __AVR32_ABI_COMPILER__\r
\r
\r
-/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file ******************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
***************************************************************************/\r
\r
/*! define stack size for TFTP server task */\r
#define lwipBASIC_TFTP_SERVER_STACK_SIZE 1024\r
\r
-/*! define stack size for SMTP host task */\r
-#define lwipBASIC_SMTP_HOST_STACK_SIZE 256\r
+/*! define stack size for SMTP Client task */\r
+#define lwipBASIC_SMTP_CLIENT_STACK_SIZE 256\r
\r
/*! define stack size for lwIP task */\r
#define lwipINTERFACE_STACK_SIZE 512\r
/*! define TFTP server priority */\r
#define ethTFTPSERVER_PRIORITY ( tskIDLE_PRIORITY + 3 )\r
\r
-/*! define SMTP host priority */\r
-#define ethSMTPHOST_PRIORITY ( tskIDLE_PRIORITY + 5 )\r
+/*! define SMTP Client priority */\r
+#define ethSMTPCLIENT_PRIORITY ( tskIDLE_PRIORITY + 5 )\r
\r
/*! define lwIP task priority */\r
#define lwipINTERFACE_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )\r
/*! LED used by the ethernet task, toggled on each activation */\r
#define webCONN_LED 7\r
\r
+/*! Phy Address (set through strap options) */\r
+#define ETHERNET_CONF_PHY_ADDR 0x01\r
+#define ETHERNET_CONF_PHY_ID 0x20005C90\r
+\r
+/*! Number of receive buffers */\r
+#define ETHERNET_CONF_NB_RX_BUFFERS 20\r
+\r
+/*! USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0\r
+to use an MII interface. */\r
+#define ETHERNET_CONF_USE_RMII_INTERFACE 1\r
+\r
+/*! Number of Transmit buffers */\r
+#define ETHERNET_CONF_NB_TX_BUFFERS 10\r
+\r
+/*! Size of each Transmit buffer. */\r
+#define ETHERNET_CONF_TX_BUFFER_SIZE 512\r
+\r
+/*! Clock definition */\r
+#define ETHERNET_CONF_SYSTEM_CLOCK 48000000\r
+\r
/*! Use Auto Negociation to get speed and duplex */\r
#define ETHERNET_CONF_AN_ENABLE 1\r
\r
\r
/* ethernet default parameters */\r
/*! MAC address definition. The MAC address must be unique on the network. */\r
-#define emacETHADDR0 0x00\r
-#define emacETHADDR1 0x04\r
-#define emacETHADDR2 0x25\r
-#define emacETHADDR3 0x40\r
-#define emacETHADDR4 0x40\r
-#define emacETHADDR5 0x40\r
-\r
-#if 0\r
-/*! The IP address being used. */\r
-#define emacIPADDR0 10\r
-#define emacIPADDR1 172\r
-#define emacIPADDR2 214\r
-#define emacIPADDR3 40\r
-\r
-/*! The gateway address being used. */\r
-#define emacGATEWAY_ADDR0 10\r
-#define emacGATEWAY_ADDR1 172\r
-#define emacGATEWAY_ADDR2 250\r
-#define emacGATEWAY_ADDR3 1\r
+#define ETHERNET_CONF_ETHADDR0 0x00\r
+#define ETHERNET_CONF_ETHADDR1 0x04\r
+#define ETHERNET_CONF_ETHADDR2 0x25\r
+#define ETHERNET_CONF_ETHADDR3 0x40\r
+#define ETHERNET_CONF_ETHADDR4 0x40\r
+#define ETHERNET_CONF_ETHADDR5 0x40\r
\r
-/*! The network mask being used. */\r
-#define emacNET_MASK0 255\r
-#define emacNET_MASK1 255\r
-#define emacNET_MASK2 0\r
-#define emacNET_MASK3 0\r
-\r
-#else\r
/*! The IP address being used. */\r
-#define emacIPADDR0 192\r
-#define emacIPADDR1 168\r
-#define emacIPADDR2 0\r
-#define emacIPADDR3 2\r
+#define ETHERNET_CONF_IPADDR0 192\r
+#define ETHERNET_CONF_IPADDR1 168\r
+#define ETHERNET_CONF_IPADDR2 0\r
+#define ETHERNET_CONF_IPADDR3 2\r
\r
/*! The gateway address being used. */\r
-#define emacGATEWAY_ADDR0 192\r
-#define emacGATEWAY_ADDR1 168\r
-#define emacGATEWAY_ADDR2 0\r
-#define emacGATEWAY_ADDR3 1\r
+#define ETHERNET_CONF_GATEWAY_ADDR0 192\r
+#define ETHERNET_CONF_GATEWAY_ADDR1 168\r
+#define ETHERNET_CONF_GATEWAY_ADDR2 0\r
+#define ETHERNET_CONF_GATEWAY_ADDR3 1\r
\r
/*! The network mask being used. */\r
-#define emacNET_MASK0 255\r
-#define emacNET_MASK1 255\r
-#define emacNET_MASK2 255\r
-#define emacNET_MASK3 0\r
-#endif\r
+#define ETHERNET_CONF_NET_MASK0 255\r
+#define ETHERNET_CONF_NET_MASK1 255\r
+#define ETHERNET_CONF_NET_MASK2 255\r
+#define ETHERNET_CONF_NET_MASK3 0\r
\r
#endif\r
--- /dev/null
+/*This file has been prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief lwIP configuration for AVR32 UC3.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32 devices can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ *****************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+\r
+#ifndef __LWIPOPTS_H__\r
+#define __LWIPOPTS_H__\r
+\r
+/* Include user defined options first */\r
+#include "conf_eth.h"\r
+// #include "lwip/debug.h"\r
+\r
+#define LWIP_PLATFORM_DIAG(x) \r
+#define LWIP_PLATFORM_ASSERT(x) \r
+\r
+/* Define default values for unconfigured parameters. */\r
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)\r
+\r
+/* These two control is reclaimer functions should be compiled\r
+ in. Should always be turned on (1). */\r
+#define MEM_RECLAIM 1\r
+#define MEMP_RECLAIM 1\r
+\r
+\r
+/* Platform specific locking */\r
+\r
+/*\r
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection\r
+ * for certain critical regions during buffer allocation, deallocation and memory\r
+ * allocation and deallocation.\r
+ */\r
+#define SYS_LIGHTWEIGHT_PROT 1\r
+\r
+/* ---------- Memory options ---------- */\r
+// #define MEM_LIBC_MALLOC 0\r
+\r
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which\r
+ lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2\r
+ byte alignment -> define MEM_ALIGNMENT to 2. */\r
+#define MEM_ALIGNMENT 4\r
+\r
+/* MEM_SIZE: the size of the heap memory. If the application will send\r
+a lot of data that needs to be copied, this should be set high. */\r
+#define MEM_SIZE 3 * 1024\r
+\r
+// #define MEMP_SANITY_CHECK 1\r
+\r
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application\r
+ sends a lot of data out of ROM (or other static memory), this\r
+ should be set high. */\r
+#define MEMP_NUM_PBUF 6\r
+\r
+/* Number of raw connection PCBs */\r
+#define MEMP_NUM_RAW_PCB 1\r
+\r
+#if (TFTP_USED == 1)\r
+ /* ---------- UDP options ---------- */\r
+ #define LWIP_UDP 1\r
+ #define UDP_TTL 255\r
+ /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+\r
+ #define MEMP_NUM_UDP_PCB 1\r
+#else\r
+ /* ---------- UDP options ---------- */\r
+ #define LWIP_UDP 0\r
+ #define UDP_TTL 0\r
+ /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One\r
+ per active UDP "connection". */\r
+\r
+ #define MEMP_NUM_UDP_PCB 0\r
+#endif\r
+\r
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB 14\r
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP\r
+ connections. */\r
+#define MEMP_NUM_TCP_PCB_LISTEN 2\r
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP\r
+ segments. */\r
+#define MEMP_NUM_TCP_SEG 6\r
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active\r
+ timeouts. */\r
+#define MEMP_NUM_SYS_TIMEOUT 6\r
+\r
+/* The following four are used only with the sequential API and can be\r
+ set to 0 if the application only will use the raw API. */\r
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */\r
+#define MEMP_NUM_NETBUF 3\r
+/* MEMP_NUM_NETCONN: the number of struct netconns. */\r
+#define MEMP_NUM_NETCONN 6\r
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for\r
+ communication between the TCP/IP stack and the sequential\r
+ programs. */\r
+#define MEMP_NUM_API_MSG 4\r
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used\r
+ for sequential API communication and incoming packets. Used in\r
+ src/api/tcpip.c. */\r
+#define MEMP_NUM_TCPIP_MSG 4\r
+\r
+\r
+/* ---------- Pbuf options ---------- */\r
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */\r
+\r
+#define PBUF_POOL_SIZE 6\r
+\r
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */\r
+\r
+#define PBUF_POOL_BUFSIZE 500\r
+\r
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a\r
+ link level header. */\r
+#define PBUF_LINK_HLEN 16\r
+\r
+/* ---------- TCP options ---------- */\r
+#define LWIP_TCP 1\r
+#define TCP_TTL 255\r
+/* TCP receive window. */\r
+#define TCP_WND 1500\r
+/* Controls if TCP should queue segments that arrive out of\r
+ order. Define to 0 if your device is low on memory. */\r
+#define TCP_QUEUE_OOSEQ 1\r
+\r
+/* TCP Maximum segment size. */\r
+#define TCP_MSS 1500\r
+\r
+/* TCP sender buffer space (bytes). */\r
+#define TCP_SND_BUF 2150\r
+\r
+/* TCP sender buffer space (pbufs). This must be at least = 2 *\r
+ TCP_SND_BUF/TCP_MSS for things to work. */\r
+#define TCP_SND_QUEUELEN 6 * TCP_SND_BUF/TCP_MSS\r
+\r
+\r
+\r
+/* Maximum number of retransmissions of data segments. */\r
+#define TCP_MAXRTX 12\r
+\r
+/* Maximum number of retransmissions of SYN segments. */\r
+#define TCP_SYNMAXRTX 4\r
+\r
+/* ---------- ARP options ---------- */\r
+#define ARP_TABLE_SIZE 10\r
+#define ARP_QUEUEING 0\r
+\r
+/* ---------- IP options ---------- */\r
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward\r
+ IP packets across network interfaces. If you are going to run lwIP\r
+ on a device with only one network interface, define this to 0. */\r
+#define IP_FORWARD 0\r
+\r
+/* If defined to 1, IP options are allowed (but not parsed). If\r
+ defined to 0, all packets with IP options are dropped. */\r
+#define IP_OPTIONS 1\r
+\r
+/* ---------- ICMP options ---------- */\r
+#define ICMP_TTL 255\r
+\r
+\r
+/* ---------- DHCP options ---------- */\r
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of\r
+ interfaces. DHCP is not implemented in lwIP 0.5.1, however, so\r
+ turning this on does currently not work. */\r
+#define LWIP_DHCP 0\r
+\r
+/* 1 if you want to do an ARP check on the offered address\r
+ (recommended). */\r
+#define DHCP_DOES_ARP_CHECK 1\r
+\r
+#define TCPIP_THREAD_PRIO lwipINTERFACE_TASK_PRIORITY\r
+\r
+/* ---------- Statistics options ---------- */\r
+#define LWIP_STATS 1\r
+\r
+#define LWIP_STATS_DISPLAY 1\r
+\r
+#if LWIP_STATS\r
+#define LINK_STATS 1\r
+#define IP_STATS 1\r
+#define ICMP_STATS 1\r
+#define UDP_STATS 1\r
+#define TCP_STATS 1\r
+#define MEM_STATS 1\r
+#define MEMP_STATS 1\r
+#define PBUF_STATS 1\r
+#define SYS_STATS 1\r
+#endif /* STATS */\r
+\r
+\r
+#endif /* __LWIPOPTS_H__ */\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file has been prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
<link rel="stylesheet" type="text/css" href="../../../../.docsrc/AVR32_ns.css">
</head>
<body>
-<p align="left" class="whs2"><a href="../../../AVR32_SERVICES_Readme.html"<font color="red"></font>Back to main page</a></p>
-<h1 align="center" class="whs1">AVR®32 AT32UC3 Series Software Library: Basic Web server and TFTP server example.<br>
+<p align="left" class="whs2"><a href="../../../AVR32_SERVICES_Readme.html"<font color="red"></font>Back to the SERVICES main page</a></p>
+<h1 align="center" class="whs1">AVR®32 AT32UC3 Series Software Framework: Basic Web server and TFTP server example.<br>
</h1>
<p align="center" class="whs2">Copyright © 2007 Atmel Corporation</p>
-<a><h2>Introduction</a></h2>
+<h2>Introduction</h2>
<p>This example implements a basic Web server and a basic TFTP server.
- It is running on top of the <a href="http://
www.sics.se/~adam/lwip"<font color="red"></font>lwIP TCP/IP stack</a> and the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port.</p>
- <p>This example thus contains a port of the <a href="http://
www.sics.se/~adam/lwip"<font color="red"></font>lwIP TCP/IP stack</a>. This port is using both the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port and the AVR32 UC3A MACB interface for the Ethernet access.</p>
+ It is running on top of the <a href="http://
savannah.nongnu.org/projects/lwip"<font color="red"></font>lwIP TCP/IP stack</a> and the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port.</p>
+ <p>This example thus contains a port of the <a href="http://
savannah.nongnu.org/projects/lwip"<font color="red"></font>lwIP TCP/IP stack</a>. This port is using both the AVR32 UC3 <a href="http://freertos.org"<font color="red"></font>freeRTOS.org</a> port and the AVR32 UC3A MACB interface for the Ethernet access.</p>
<p> </p>
-<a><h2>lwIP TCP/IP stack</a></h2>
+<h2>lwIP TCP/IP stack</h2>
<p>lwIP is an implementation of the TCP/IP protocol suite. The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP.</p>
<DT><B><u>lwIP features</u>:</B>
<DD><p class="whs3"><li>IP (Internet Protocol) including packet forwarding over multiple network interfaces</p></li>
<DD><p class="whs3"><li>DHCP (Dynamic Host Configuration Protocol)</p></li>
<DD><p class="whs3"><li>PPP (Point-to-Point Protocol)</p></li>
<DD><p class="whs3"><li>ARP (Address Resolution Protocol) for Ethernet</p></li>
-
+<p>lwIP is freely available (under a BSD-style license) in C source code format and can be downloaded from the <a href="http://savannah.nongnu.org/projects/lwip"<font color="red"></font>development homepage</a>.</p>
<p> </p>
-<a><h2>The Basic Web server</a></h2>
- <p>Implements a simplistic WEB server.</p>
+<h2>The Basic Web server</h2>
+ <p>Implements a simplistic WEB server. To use this demo part, define HTTP_USED to 1, else define to 0. (default is 1)</p>
<B><u>Demo description</u>:</B> Every time a connection is made and data is received, a dynamic page that shows the current FreeRTOS.org kernel statistics is generated and returned. The connection is then closed.</p>
<B><u>Note</u>:</B> The WEB server is reachable at the IP address 192.168.0.2.
<p> </p>
-<a><h2>The Basic TFTP server</a></h2>
- <p>Implements a simplistic TFTP server.</p>
+<h2>The Basic TFTP server</h2>
+ <p>Implements a simplistic TFTP server. To use this demo part, define TFTP_USED to 1, else define to 0. (default is 1)</p>
<DT><B><u>Demo description</u>:</B>
<DD><p class="whs3"><li>To put a file onto the TFTP server (Supported file size < 2048 bytes), on a PC command line type <i><b>tftp 192.168.0.2 PUT "a_file"</i></b>: this will copy <i>a_file</i> from your hard drive to a RAM buffer of the demo.</p></li>
<DD><p class="whs3"><li>To get a file from the TFTP server, on a PC command line type <i><b>tftp 192.168.0.2 GET "a_file"</i></b>: this will copy <i>a_file</i> from the RAM buffer of the application to the PC's hard drive.</p></li>
<p> </p>
-<a><h2>Device Info</a></h2>
- All AVR32 UC3A devices with a MACB module can be used. This example has been tested with the following setup(s):
- <DD><p class="whs3"><li type="disc">AT32UC3A0512 on the EVK1100 evaluation kit.</li></p>
-
-<p> </p>
-
-<a><h2>Contact Info</a></h2>
-For more info about Atmel AVR32 visit <a href="http://www.atmel.com/products/AVR32/">Atmel AVR32</a> <br>
- <a href="http://www.atmel.com/dyn/products/app_notes.asp?family_id=682">AVR32 Application Notes</a><br>
- Support mail: <a href="mailto:avr32@atmel.com">avr32@atmel.com</a>
-
-<p> </p>
-
-<a><h2>License</a></h2>
+<h2>The Basic SMTP client</h2>
+ <p>Implements a simplistic SMTP client. To use this demo part, define SMTP_USED to 1, else define to 0. (default is 0)</p>
+ <DT><B><u>Demo description</u>:</B>
+ <DD><p class="whs3"><li>Prior to compile and run the SMTP client, you will have to configure the connection settings :
+ <DD><DD><li>Server address : default is <i>192.168.0.1</i>.</li>
+ <DD><DD><li>Server name : used in the EHLO field, default is <i>smtp.domain.com</i>.</li>
+ <DD><DD><li>Mail sender : used in the mailfrom field, default is <i>sender@domain.com</i>.</li>
+ <DD><DD><li>Mail recipient : used in the mailto field, default is <i>receiver@domain.com</i>.</li>
+ <DD><DD><li>Mail content : default is <i>Subject: *** SPAM ***\r\nFROM: \"Your Name here\" <sender@domain.com>\r\nTO: \"Your Contact here\" <receiver@domain.com>\r\n\r\nSay what you want here</i>.</li>
+ </p></li>
+ <DD><p class="whs3"><li>Once all fields are configured, remove the <i>#error</i> lines to allow compilation.</p></li>
+ <DD><p class="whs3"><li>Run the software and press Push Button 0 to send an email.</p></li>
-Copyright (c) 2007, Atmel Corporation All rights reserved.
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-<ol>
-<li>Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-<li>Redistributions in binary form must reproduce the above copyright notice,
-this list of conditions and the following disclaimer in the documentation
-and/or other materials provided with the distribution.
-<li>The name of ATMEL may not be used to endorse or promote products derived
-from this software without specific prior written permission.
-</ol>
<p> </p>
-THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
-SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
+<h2>Device Info</h2>
+ All AVR32 UC3A devices with a MACB module can be used. This example has been tested with the following setup(s):
+ <DD><p class="whs3"><li type="disc">AT32UC3A0512 on the EVK1100 evaluation kit.</li></p>
+
<p> </p>
* \ingroup FreeRTOSIntro\r
*/\r
\r
+/*\r
+ Changes from V4.3.1\r
+\r
+ + Included local const within listGET_OWNER_OF_NEXT_ENTRY() to assist\r
+ compiler with optimisation. Thanks B.R.\r
+*/\r
\r
#ifndef LIST_H\r
#define LIST_H\r
* \ingroup LinkedList\r
*/\r
#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \\r
+{ \\r
+xList * const pxConstList = pxList; \\r
/* Increment the index to the next item and return the item, ensuring */ \\r
/* we don't return the marker used at the end of the list. */ \\r
- ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \\r
- if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
+ if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \\r
{ \\r
- ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
} \\r
- pxTCB = ( pxList )->pxIndex->pvOwner\r
+ pxTCB = ( pxConstList )->pxIndex->pvOwner; \\r
+}\r
\r
\r
/*\r
typedef void ( __interrupt __far *pxISR )();\r
#endif\r
\r
-#ifdef GCC_AVR32_PORT\r
- #include "portmacro.h"\r
-#endif\r
-\r
-#ifdef IAR_AVR32_PORT\r
- #include "portmacro.h"\r
+#ifdef __GNUC__\r
+ #ifdef __AVR32_AVR32A__\r
+ #include "portmacro.h"\r
+ #endif\r
+#endif\r
+\r
+#ifdef __ICCAVR32__\r
+ #ifdef __CORE__\r
+ #if __CORE__ == __AVR32A__\r
+ #include "portmacro.h"\r
+ #endif\r
+ #endif\r
#endif\r
\r
/*\r
-/******************************************************************************
- * Exception and interrupt vectors.
- *
- * This file has been built from the Newlib exception.S. It maps all events
- * supported by a UC3.
- *
- * - Compiler: GNU GCC for AVR32
- * - Supported devices: All AVR32A devices with an INTC module can be used.
- * - AppNote:
- *
- * - author Atmel Corporation: http://www.atmel.com \n
- * Support email: avr32@atmel.com
- *
- ******************************************************************************/
-
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include <avr32/io.h>
-#include "intc.h"
-
-
- .section .exception, "ax"
-
-
-// Start of Exception Vector Table.
-
- // EVBA must be aligned with a power of two strictly greater than the EVBA-
- // relative offset of the last vector.
- .balign 0x200
-
- // Export symbol.
- .global _evba
-_evba:
-
- .org 0x000
- // Unrecoverable Exception.
-_handle_Unrecoverable_Exception:
- rjmp $
-
- .org 0x004
- // TLB Multiple Hit: UNUSED IN AVR32A.
-_handle_TLB_Multiple_Hit:
- rjmp $
-
- .org 0x008
- // Bus Error Data Fetch.
-_handle_Bus_Error_Data_Fetch:
- rjmp $
-
- .org 0x00C
- // Bus Error Instruction Fetch.
-_handle_Bus_Error_Instruction_Fetch:
- rjmp $
-
- .org 0x010
- // NMI.
-_handle_NMI:
- rjmp $
-
- .org 0x014
- // Instruction Address.
-_handle_Instruction_Address:
- rjmp $
-
- .org 0x018
- // ITLB Protection.
-_handle_ITLB_Protection:
- rjmp $
-
- .org 0x01C
- // Breakpoint.
-_handle_Breakpoint:
- rjmp $
-
- .org 0x020
- // Illegal Opcode.
-_handle_Illegal_Opcode:
- rjmp $
-
- .org 0x024
- // Unimplemented Instruction.
-_handle_Unimplemented_Instruction:
- rjmp $
-
- .org 0x028
- // Privilege Violation.
-_handle_Privilege_Violation:
- rjmp $
-
- .org 0x02C
- // Floating-Point: UNUSED IN AVR32A.
-_handle_Floating_Point:
- rjmp $
-
- .org 0x030
- // Coprocessor Absent: UNUSED IN AVR32A.
-_handle_Coprocessor_Absent:
- rjmp $
-
- .org 0x034
- // Data Address (Read).
-_handle_Data_Address_Read:
- rjmp $
-
- .org 0x038
- // Data Address (Write).
-_handle_Data_Address_Write:
- rjmp $
-
- .org 0x03C
- // DTLB Protection (Read).
-_handle_DTLB_Protection_Read:
- rjmp $
-
- .org 0x040
- // DTLB Protection (Write).
-_handle_DTLB_Protection_Write:
- rjmp $
-
- .org 0x044
- // DTLB Modified: UNUSED IN AVR32A.
-_handle_DTLB_Modified:
- rjmp $
-
- .org 0x050
- // ITLB Miss: UNUSED IN AVR32A.
-_handle_ITLB_Miss:
- rjmp $
-
- .org 0x060
- // DTLB Miss (Read): UNUSED IN AVR32A.
-_handle_DTLB_Miss_Read:
- rjmp $
-
- .org 0x070
- // DTLB Miss (Write): UNUSED IN AVR32A.
-_handle_DTLB_Miss_Write:
- rjmp $
-
- .org 0x100
- // Supervisor Call.
-_handle_Supervisor_Call:
- lda.w pc, SCALLYield
-
-
-// Interrupt support.
-// The interrupt controller must provide the offset address relative to EVBA.
-// Important note:
-// All interrupts call a C function named _get_interrupt_handler.
-// This function will read group and interrupt line number to then return in
-// R12 a pointer to a user-provided interrupt handler.
-
- .balign 4
-
-_int0:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int0_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int0_normal:
-#endif
- mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int1:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int1_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int1_normal:
-#endif
- mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int2:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int2_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int2_normal:
-#endif
- mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int3:
- // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
- // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
- mfsr r12, AVR32_SR
- bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
- cp.w r12, 0b110
- brlo _int3_normal
- lddsp r12, sp[0 * 4]
- stdsp sp[6 * 4], r12
- lddsp r12, sp[1 * 4]
- stdsp sp[7 * 4], r12
- lddsp r12, sp[3 * 4]
- sub sp, -6 * 4
- rete
-_int3_normal:
-#endif
- mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
- call _get_interrupt_handler
- cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
- movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
- rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-// Constant data area.
-
- .balign 4
-
- // Values to store in the interrupt priority registers for the various interrupt priority levels.
- // The interrupt priority registers contain the interrupt priority level and
- // the EVBA-relative interrupt vector offset.
- .global ipr_val
-ipr_val:
- .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
- (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
- (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
- (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
+ *\r
+ * \brief Exception and interrupt vectors.\r
+ *\r
+ * This file maps all events supported by an AVR32UC.\r
+ *\r
+ * - Compiler: GNU GCC for AVR32\r
+ * - Supported devices: All AVR32UC devices with an INTC module can be used.\r
+ * - AppNote:\r
+ *\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
+ *\r
+ ******************************************************************************/\r
+\r
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions are met:\r
+ *\r
+ * 1. Redistributions of source code must retain the above copyright notice,\r
+ * this list of conditions and the following disclaimer.\r
+ *\r
+ * 2. Redistributions in binary form must reproduce the above copyright notice,\r
+ * this list of conditions and the following disclaimer in the documentation\r
+ * and/or other materials provided with the distribution.\r
+ *\r
+ * 3. The name of ATMEL may not be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED\r
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND\r
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,\r
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ */\r
+\r
+\r
+#include <avr32/io.h>\r
+#include "intc.h"\r
+\r
+\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
+ .section .exception, "ax", @progbits\r
+\r
+\r
+// Start of Exception Vector Table.\r
+\r
+ // EVBA must be aligned with a power of two strictly greater than the EVBA-\r
+ // relative offset of the last vector.\r
+ .balign 0x200\r
+\r
+ // Export symbol.\r
+ .global _evba\r
+ .type _evba, @function\r
+_evba:\r
+\r
+ .org 0x000\r
+ // Unrecoverable Exception.\r
+_handle_Unrecoverable_Exception:\r
+ rjmp $\r
+\r
+ .org 0x004\r
+ // TLB Multiple Hit: UNUSED IN AVR32UC.\r
+_handle_TLB_Multiple_Hit:\r
+ rjmp $\r
+\r
+ .org 0x008\r
+ // Bus Error Data Fetch.\r
+_handle_Bus_Error_Data_Fetch:\r
+ rjmp $\r
+\r
+ .org 0x00C\r
+ // Bus Error Instruction Fetch.\r
+_handle_Bus_Error_Instruction_Fetch:\r
+ rjmp $\r
+\r
+ .org 0x010\r
+ // NMI.\r
+_handle_NMI:\r
+ rjmp $\r
+\r
+ .org 0x014\r
+ // Instruction Address.\r
+_handle_Instruction_Address:\r
+ rjmp $\r
+\r
+ .org 0x018\r
+ // ITLB Protection.\r
+_handle_ITLB_Protection:\r
+ rjmp $\r
+\r
+ .org 0x01C\r
+ // Breakpoint.\r
+_handle_Breakpoint:\r
+ rjmp $\r
+\r
+ .org 0x020\r
+ // Illegal Opcode.\r
+_handle_Illegal_Opcode:\r
+ rjmp $\r
+\r
+ .org 0x024\r
+ // Unimplemented Instruction.\r
+_handle_Unimplemented_Instruction:\r
+ rjmp $\r
+\r
+ .org 0x028\r
+ // Privilege Violation.\r
+_handle_Privilege_Violation:\r
+ rjmp $\r
+\r
+ .org 0x02C\r
+ // Floating-Point: UNUSED IN AVR32UC.\r
+_handle_Floating_Point:\r
+ rjmp $\r
+\r
+ .org 0x030\r
+ // Coprocessor Absent: UNUSED IN AVR32UC.\r
+_handle_Coprocessor_Absent:\r
+ rjmp $\r
+\r
+ .org 0x034\r
+ // Data Address (Read).\r
+_handle_Data_Address_Read:\r
+ rjmp $\r
+\r
+ .org 0x038\r
+ // Data Address (Write).\r
+_handle_Data_Address_Write:\r
+ rjmp $\r
+\r
+ .org 0x03C\r
+ // DTLB Protection (Read).\r
+_handle_DTLB_Protection_Read:\r
+ rjmp $\r
+\r
+ .org 0x040\r
+ // DTLB Protection (Write).\r
+_handle_DTLB_Protection_Write:\r
+ rjmp $\r
+\r
+ .org 0x044\r
+ // DTLB Modified: UNUSED IN AVR32UC.\r
+_handle_DTLB_Modified:\r
+ rjmp $\r
+\r
+ .org 0x050\r
+ // ITLB Miss: UNUSED IN AVR32UC.\r
+_handle_ITLB_Miss:\r
+ rjmp $\r
+\r
+ .org 0x060\r
+ // DTLB Miss (Read): UNUSED IN AVR32UC.\r
+_handle_DTLB_Miss_Read:\r
+ rjmp $\r
+\r
+ .org 0x070\r
+ // DTLB Miss (Write): UNUSED IN AVR32UC.\r
+_handle_DTLB_Miss_Write:\r
+ rjmp $\r
+\r
+ .org 0x100\r
+ // Supervisor Call.\r
+_handle_Supervisor_Call:\r
+ lda.w pc, SCALLYield\r
+\r
+\r
+// Interrupt support.\r
+// The interrupt controller must provide the offset address relative to EVBA.\r
+// Important note:\r
+// All interrupts call a C function named _get_interrupt_handler.\r
+// This function will read group and interrupt line number to then return in\r
+// R12 a pointer to a user-provided interrupt handler.\r
+\r
+ .balign 4\r
+\r
+_int0:\r
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the\r
+ // CPU upon interrupt entry.\r
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.\r
+ mfsr r12, AVR32_SR\r
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE\r
+ cp.w r12, 0b110\r
+ brlo _int0_normal\r
+ lddsp r12, sp[0 * 4]\r
+ stdsp sp[6 * 4], r12\r
+ lddsp r12, sp[1 * 4]\r
+ stdsp sp[7 * 4], r12\r
+ lddsp r12, sp[3 * 4]\r
+ sub sp, -6 * 4\r
+ rete\r
+_int0_normal:\r
+#endif\r
+ mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.\r
+ call _get_interrupt_handler\r
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.\r
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.\r
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.\r
+\r
+_int1:\r
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the\r
+ // CPU upon interrupt entry.\r
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.\r
+ mfsr r12, AVR32_SR\r
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE\r
+ cp.w r12, 0b110\r
+ brlo _int1_normal\r
+ lddsp r12, sp[0 * 4]\r
+ stdsp sp[6 * 4], r12\r
+ lddsp r12, sp[1 * 4]\r
+ stdsp sp[7 * 4], r12\r
+ lddsp r12, sp[3 * 4]\r
+ sub sp, -6 * 4\r
+ rete\r
+_int1_normal:\r
+#endif\r
+ mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.\r
+ call _get_interrupt_handler\r
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.\r
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.\r
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.\r
+\r
+_int2:\r
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the\r
+ // CPU upon interrupt entry.\r
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.\r
+ mfsr r12, AVR32_SR\r
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE\r
+ cp.w r12, 0b110\r
+ brlo _int2_normal\r
+ lddsp r12, sp[0 * 4]\r
+ stdsp sp[6 * 4], r12\r
+ lddsp r12, sp[1 * 4]\r
+ stdsp sp[7 * 4], r12\r
+ lddsp r12, sp[3 * 4]\r
+ sub sp, -6 * 4\r
+ rete\r
+_int2_normal:\r
+#endif\r
+ mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.\r
+ call _get_interrupt_handler\r
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.\r
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.\r
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.\r
+\r
+_int3:\r
+ // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the\r
+ // CPU upon interrupt entry.\r
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.\r
+ mfsr r12, AVR32_SR\r
+ bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE\r
+ cp.w r12, 0b110\r
+ brlo _int3_normal\r
+ lddsp r12, sp[0 * 4]\r
+ stdsp sp[6 * 4], r12\r
+ lddsp r12, sp[1 * 4]\r
+ stdsp sp[7 * 4], r12\r
+ lddsp r12, sp[3 * 4]\r
+ sub sp, -6 * 4\r
+ rete\r
+_int3_normal:\r
+#endif\r
+ mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.\r
+ call _get_interrupt_handler\r
+ cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.\r
+ movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.\r
+ rete // If this was a spurious interrupt (R12 == NULL), return from event handler.\r
+\r
+\r
+// Constant data area.\r
+\r
+ .balign 4\r
+\r
+ // Values to store in the interrupt priority registers for the various interrupt priority levels.\r
+ // The interrupt priority registers contain the interrupt priority level and\r
+ // the EVBA-relative interrupt vector offset.\r
+ .global ipr_val\r
+ .type ipr_val, @object\r
+ipr_val:\r
+ .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\\r
+ (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\\r
+ (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\\r
+ (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
/*-----------------------------------------------------------*/\r
\r
/*\r
- * Low-level initialization routine called during Newlib's startup.\r
+ * Low-level initialization routine called during startup, before the main\r
+ * function.\r
* This version comes in replacement to the default one provided by Newlib.\r
* Newlib's _init_startup only calls init_exceptions, but Newlib's exception\r
* vectors are not compatible with the SCALL management in the current FreeRTOS\r
\r
/* Code section present if and only if the debug trace is activated. */\r
#if configDBG\r
+ {\r
+ static const gpio_map_t DBG_USART_GPIO_MAP =\r
+ {\r
+ { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },\r
+ { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }\r
+ };\r
\r
/* Initialize the USART used for the debug trace with the configured parameters. */\r
set_usart_base( ( void * ) configDBG_USART );\r
- gpio_enable_module_pin( configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION );\r
- gpio_enable_module_pin( configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION );\r
+ gpio_enable_module( DBG_USART_GPIO_MAP,\r
+ sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );\r
usart_init( configDBG_USART_BAUDRATE );\r
-\r
+ }\r
#endif\r
}\r
/*-----------------------------------------------------------*/\r
/* Save the context of the interrupted task. */\r
portSAVE_CONTEXT_OS_INT();\r
\r
- /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
- clock cycles from now. */\r
#if( configTICK_USE_TC==1 )\r
/* Clear the interrupt flag. */\r
AVR32_TC.channel[configTICK_TC_CHANNEL].sr;\r
#else\r
+ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
+ clock cycles from now. */\r
prvScheduleNextTick();\r
#endif\r
- \r
+\r
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
calls in a critical section . */\r
portENTER_CRITICAL();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-\r
/*\r
* Initialise the stack of a task to look exactly as if a call to\r
* portSAVE_CONTEXT had been called.\r
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
clock cycles from now. */\r
#if( configTICK_USE_TC==0 )\r
+ static void prvScheduleFirstTick(void)\r
+ {\r
+ unsigned long lCycles;\r
+\r
+ lCycles = Get_system_register(AVR32_COUNT);\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
+ // generation feature does not get disabled.\r
+ if(0 == lCycles)\r
+ {\r
+ lCycles++;\r
+ }\r
+ Set_system_register(AVR32_COMPARE, lCycles);\r
+ }\r
+ \r
static void prvScheduleNextTick(void)\r
{\r
- unsigned long lCountVal, lCompareVal;\r
+ unsigned long lCycles, lCount;\r
\r
- lCountVal = Get_system_register(AVR32_COUNT);\r
- lCompareVal = lCountVal + (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
- Set_system_register(AVR32_COMPARE, lCompareVal);\r
+ lCycles = Get_system_register(AVR32_COMPARE);\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
+ // generation feature does not get disabled.\r
+ if(0 == lCycles)\r
+ {\r
+ lCycles++;\r
+ }\r
+ lCount = Get_system_register(AVR32_COUNT);\r
+ if( lCycles < lCount )\r
+ { // We missed a tick, recover for the next.\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ }\r
+ Set_system_register(AVR32_COMPARE, lCycles);\r
}\r
#endif\r
/*-----------------------------------------------------------*/\r
INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);\r
\r
/* Initialize the timer/counter. */\r
- tc_init_waveform(tc, &waveform_opt); \r
+ tc_init_waveform(tc, &waveform_opt);\r
\r
/* Set the compare triggers.\r
Remember TC counter is 16-bits, so counting second is not possible!\r
That's why we configure it to count ms. */\r
- tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ/ 4) / 1000 );\r
+ tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );\r
\r
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );\r
\r
#else\r
{\r
INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);\r
- prvScheduleNextTick();\r
+ prvScheduleFirstTick();\r
}\r
#endif\r
}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
* The current source file name and line number are output with a colon before\r
* the formatted string.\r
* A carriage return and a linefeed are appended to the output.\r
- * stdout is redirected by Newlib to the USART configured by configDBG_USART.\r
+ * stdout is redirected to the USART configured by configDBG_USART.\r
* The parameters are the same as for the standard printf function.\r
* There is no return value.\r
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,\r
-/******************************************************************************\r
- * Exception and interrupt vectors.\r
+/*This file is prepared for Doxygen automatic documentation generation.*/\r
+/*! \file *********************************************************************\r
*\r
- * This file has been built from the Newlib exception.S. It maps all events\r
- * supported by a UC3.\r
+ * \brief Exception and interrupt vectors.\r
+ *\r
+ * This file maps all events supported by an AVR32UC.\r
*\r
* - Compiler: IAR EWAVR32\r
- * - Supported devices: All AVR32A devices with an INTC module can be used.\r
+ * - Supported devices: All AVR32UC devices with an INTC module can be used.\r
* - AppNote:\r
*\r
- * - author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * \author Atmel Corporation: http://www.atmel.com \n\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
*/\r
\r
\r
-#include <avr32/iouc3a0512.h>\r
-#include <avr32/uc3a0512.h>\r
+#include <avr32/io.h>\r
#include "intc.h"\r
\r
\r
+//! @{\r
+//! \verbatim\r
+\r
+\r
// Start of Exception Vector Table.\r
\r
// EVBA must be aligned with a power of two strictly greater than the EVBA-\r
ORG 0x000\r
// Unrecoverable Exception.\r
_handle_Unrecoverable_Exception:\r
- rjmp $\r
+ rjmp _handle_Unrecoverable_Exception\r
\r
ORG 0x004\r
- // TLB Multiple Hit: UNUSED IN AVR32A.\r
+ // TLB Multiple Hit: UNUSED IN AVR32UC.\r
_handle_TLB_Multiple_Hit:\r
- rjmp $\r
+ rjmp _handle_TLB_Multiple_Hit\r
\r
ORG 0x008\r
// Bus Error Data Fetch.\r
_handle_Bus_Error_Data_Fetch:\r
- rjmp $\r
+ rjmp _handle_Bus_Error_Data_Fetch\r
\r
ORG 0x00C\r
// Bus Error Instruction Fetch.\r
_handle_Bus_Error_Instruction_Fetch:\r
- rjmp $\r
+ rjmp _handle_Bus_Error_Instruction_Fetch\r
\r
ORG 0x010\r
// NMI.\r
_handle_NMI:\r
- rjmp $\r
+ rjmp _handle_NMI\r
\r
ORG 0x014\r
// Instruction Address.\r
_handle_Instruction_Address:\r
- rjmp $\r
+ rjmp _handle_Instruction_Address\r
\r
ORG 0x018\r
// ITLB Protection.\r
_handle_ITLB_Protection:\r
- rjmp $\r
+ rjmp _handle_ITLB_Protection\r
\r
ORG 0x01C\r
// Breakpoint.\r
_handle_Breakpoint:\r
- rjmp $\r
+ rjmp _handle_Breakpoint\r
\r
ORG 0x020\r
// Illegal Opcode.\r
_handle_Illegal_Opcode:\r
- rjmp $\r
+ rjmp _handle_Illegal_Opcode\r
\r
ORG 0x024\r
// Unimplemented Instruction.\r
_handle_Unimplemented_Instruction:\r
- rjmp $\r
+ rjmp _handle_Unimplemented_Instruction\r
\r
ORG 0x028\r
// Privilege Violation.\r
_handle_Privilege_Violation:\r
- rjmp $\r
+ rjmp _handle_Privilege_Violation\r
\r
ORG 0x02C\r
- // Floating-Point: UNUSED IN AVR32A.\r
+ // Floating-Point: UNUSED IN AVR32UC.\r
_handle_Floating_Point:\r
- rjmp $\r
+ rjmp _handle_Floating_Point\r
\r
ORG 0x030\r
- // Coprocessor Absent: UNUSED IN AVR32A.\r
+ // Coprocessor Absent: UNUSED IN AVR32UC.\r
_handle_Coprocessor_Absent:\r
- rjmp $\r
+ rjmp _handle_Coprocessor_Absent\r
\r
ORG 0x034\r
// Data Address (Read).\r
_handle_Data_Address_Read:\r
- rjmp $\r
+ rjmp _handle_Data_Address_Read\r
\r
ORG 0x038\r
// Data Address (Write).\r
_handle_Data_Address_Write:\r
- rjmp $\r
+ rjmp _handle_Data_Address_Write\r
\r
ORG 0x03C\r
// DTLB Protection (Read).\r
_handle_DTLB_Protection_Read:\r
- rjmp $\r
+ rjmp _handle_DTLB_Protection_Read\r
\r
ORG 0x040\r
// DTLB Protection (Write).\r
_handle_DTLB_Protection_Write:\r
- rjmp $\r
+ rjmp _handle_DTLB_Protection_Write\r
\r
ORG 0x044\r
- // DTLB Modified: UNUSED IN AVR32A.\r
+ // DTLB Modified: UNUSED IN AVR32UC.\r
_handle_DTLB_Modified:\r
- rjmp $\r
+ rjmp _handle_DTLB_Modified\r
\r
ORG 0x050\r
- // ITLB Miss: UNUSED IN AVR32A.\r
+ // ITLB Miss: UNUSED IN AVR32UC.\r
_handle_ITLB_Miss:\r
- rjmp $\r
+ rjmp _handle_ITLB_Miss\r
\r
ORG 0x060\r
- // DTLB Miss (Read): UNUSED IN AVR32A.\r
+ // DTLB Miss (Read): UNUSED IN AVR32UC.\r
_handle_DTLB_Miss_Read:\r
- rjmp $\r
+ rjmp _handle_DTLB_Miss_Read\r
\r
ORG 0x070\r
- // DTLB Miss (Write): UNUSED IN AVR32A.\r
+ // DTLB Miss (Write): UNUSED IN AVR32UC.\r
_handle_DTLB_Miss_Write:\r
- rjmp $\r
+ rjmp _handle_DTLB_Miss_Write\r
\r
ORG 0x100\r
// Supervisor Call.\r
\r
\r
END\r
+\r
+\r
+//! \endverbatim\r
+//! @}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
\r
/* Scheduler includes. */\r
#include "FreeRTOS.h"\r
-\r
-/* Get rid of inline in task.h. */\r
#include "task.h"\r
\r
/* AVR32 UC3 includes. */\r
-#include <avr32/iouc3a0512.h>\r
+#include <avr32/io.h>\r
#include <intrinsics.h>\r
#include "gpio.h"\r
\r
#if( configTICK_USE_TC==0 )\r
static void prvScheduleNextTick( void );\r
#endif\r
+\r
+/* Setup the timer to generate the tick interrupts. */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
/*-----------------------------------------------------------*/\r
\r
/*\r
/* Code section present if and only if the debug trace is activated. */\r
#if configDBG\r
{\r
- static const usart_options_t usart_opt =\r
+ static const gpio_map_t DBG_USART_GPIO_MAP =\r
+ {\r
+ { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },\r
+ { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }\r
+ };\r
+\r
+ static const usart_options_t DBG_USART_OPTIONS =\r
{\r
- .baudrate = configDBG_USART_BAUDRATE,\r
- .charlength = 8,\r
- .paritytype = USART_NO_PARITY,\r
- .stopbits = USART_1_STOPBIT,\r
- .channelmode = USART_MODE_NORMAL\r
+ .baudrate = configDBG_USART_BAUDRATE,\r
+ .charlength = 8,\r
+ .paritytype = USART_NO_PARITY,\r
+ .stopbits = USART_1_STOPBIT,\r
+ .channelmode = USART_NORMAL_CHMODE\r
};\r
\r
/* Initialize the USART used for the debug trace with the configured parameters. */\r
extern volatile avr32_usart_t *volatile stdio_usart_base;\r
stdio_usart_base = configDBG_USART;\r
- gpio_enable_module_pin(configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION);\r
- gpio_enable_module_pin(configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION);\r
- usart_init_rs232(configDBG_USART, &usart_opt, configCPU_CLOCK_HZ);\r
+ gpio_enable_module( DBG_USART_GPIO_MAP,\r
+ sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );\r
+ usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);\r
}\r
#endif\r
\r
/* Save the context of the interrupted task. */\r
portSAVE_CONTEXT_OS_INT();\r
\r
- /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
- clock cycles from now. */\r
#if( configTICK_USE_TC==1 )\r
/* Clear the interrupt flag. */\r
AVR32_TC.channel[configTICK_TC_CHANNEL].sr;\r
#else\r
+ /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
+ clock cycles from now. */\r
prvScheduleNextTick();\r
#endif\r
- \r
+\r
/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
calls in a critical section . */\r
portENTER_CRITICAL();\r
}\r
/*-----------------------------------------------------------*/\r
\r
-/* Setup the timer to generate the tick interrupts. */\r
-static void prvSetupTimerInterrupt( void );\r
-/*-----------------------------------------------------------*/\r
-\r
/*\r
* Initialise the stack of a task to look exactly as if a call to\r
* portSAVE_CONTEXT had been called.\r
/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
clock cycles from now. */\r
#if( configTICK_USE_TC==0 )\r
+ static void prvScheduleFirstTick(void)\r
+ {\r
+ unsigned long lCycles;\r
+\r
+ lCycles = Get_system_register(AVR32_COUNT);\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
+ // generation feature does not get disabled.\r
+ if(0 == lCycles)\r
+ {\r
+ lCycles++;\r
+ }\r
+ Set_system_register(AVR32_COMPARE, lCycles);\r
+ }\r
+ \r
static void prvScheduleNextTick(void)\r
{\r
- unsigned long lCountVal, lCompareVal;\r
+ unsigned long lCycles, lCount;\r
\r
- lCountVal = Get_system_register(AVR32_COUNT);\r
- lCompareVal = lCountVal + (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
- Set_system_register(AVR32_COMPARE, lCompareVal);\r
+ lCycles = Get_system_register(AVR32_COMPARE);\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
+ // generation feature does not get disabled.\r
+ if(0 == lCycles)\r
+ {\r
+ lCycles++;\r
+ }\r
+ lCount = Get_system_register(AVR32_COUNT);\r
+ if( lCycles < lCount )\r
+ { // We missed a tick, recover for the next.\r
+ lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
+ }\r
+ Set_system_register(AVR32_COMPARE, lCycles);\r
}\r
#endif\r
/*-----------------------------------------------------------*/\r
/* Set the compare triggers.\r
Remember TC counter is 16-bits, so counting second is not possible!\r
That's why we configure it to count ms. */\r
- tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / 1000 );\r
+ tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );\r
\r
tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );\r
\r
#else\r
{\r
INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);\r
- prvScheduleNextTick();\r
+ prvScheduleFirstTick();\r
}\r
#endif\r
}\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
*****************************************************************************/\r
\r
* These settings should not be altered.\r
*-----------------------------------------------------------\r
*/\r
-#include <avr32/iouc3a0512.h>\r
+#include <avr32/io.h>\r
#include "intc.h"\r
#include "compiler.h"\r
\r
* The current source file name and line number are output with a colon before\r
* the formatted string.\r
* A carriage return and a linefeed are appended to the output.\r
- * stdout is redirected by Newlib to the USART configured by configDBG_USART.\r
+ * stdout is redirected to the USART configured by configDBG_USART.\r
* The parameters are the same as for the standard printf function.\r
* There is no return value.\r
* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,\r
\\r
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \\r
/* there is also no context save. */ \\r
-} \r
- \r
-/* \r
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1 \r
- */ \r
+}\r
+\r
+/*\r
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1\r
+ */\r
#define portEXIT_SWITCHING_ISR() \\r
{ \\r
__asm__ __volatile__ ( \\r
/* there is also no context restore. */ \\r
"rete" \\r
); \\r
-} \r
- \r
-#else \r
- \r
-/* \r
- * ISR entry and exit macros. These are only required if a task switch \r
- * is required from the ISR. \r
- */ \r
+}\r
+\r
+#else\r
+\r
+/*\r
+ * ISR entry and exit macros. These are only required if a task switch\r
+ * is required from the ISR.\r
+ */\r
#define portENTER_SWITCHING_ISR() \\r
{ \\r
extern volatile unsigned portLONG ulCriticalNesting; \\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
\r
#include <yfuns.h>\r
-#include <avr32/iouc3a0512.h>\r
+#include <avr32/io.h>\r
#include "usart.h"\r
\r
\r
-/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */\r
-\r
/*This file is prepared for Doxygen automatic documentation generation.*/\r
/*! \file *********************************************************************\r
*\r
* - AppNote:\r
*\r
* \author Atmel Corporation: http://www.atmel.com \n\r
- * Support email: avr32@atmel.com\r
+ * Support and FAQ: http://support.atmel.no/\r
*\r
******************************************************************************/\r
\r
\r
\r
#include <yfuns.h>\r
-#include <avr32/iouc3a0512.h>\r
+#include <avr32/io.h>\r
#include "usart.h"\r
\r
\r
projects / freertos / commitdiff