]> git.sur5r.net Git - freertos/commitdiff
Initial IAR LPC1768 demo. Work in progress at this point.
authorrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 9 Aug 2009 12:19:17 +0000 (12:19 +0000)
committerrichardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 9 Aug 2009 12:19:17 +0000 (12:19 +0000)
git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@841 1d2547de-c912-0410-9cb9-b8ca96c0e9e2

57 files changed:
Demo/CORTEX_LPC1768_IAR/Flash.mac [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/FreeRTOSConfig.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LED.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPC1768_Flash.icf [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPC17xx.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/USB_CDC.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/type.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbapi.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbcontrol.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbdebug.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c.bak [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbinit.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstdreq.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstruct.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/ParTest.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewd [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewp [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/RTOSDemo.eww [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/core_cm3.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/cstartup_M.s [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/main.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/printf-stdarg.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.cspy.bat [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dbgdt [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dni [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.wsdt [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo_Debug.jlink [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/system_LPC17xx.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/EthDev.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/EthDev_LPC17xx.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/clock-arch.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/emac.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/http-strings [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/http-strings.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/http-strings.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/404.html [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.html [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/io.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/runtime.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/stats.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/tcp.shtml [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/httpd.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/makefsdata [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/makestrings [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/uIP_Task.c [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/uip-conf.h [new file with mode: 0644]
Demo/CORTEX_LPC1768_IAR/webserver/webserver.h [new file with mode: 0644]

diff --git a/Demo/CORTEX_LPC1768_IAR/Flash.mac b/Demo/CORTEX_LPC1768_IAR/Flash.mac
new file mode 100644 (file)
index 0000000..95eeeaa
--- /dev/null
@@ -0,0 +1,13 @@
+execUserReset()\r
+{\r
+  __writeMemory32(0x00000000, 0xE000ED08, "Memory"); //Vector table remap at 0x00000000\r
+}\r
+\r
+execUserPreload()\r
+{\r
+  // If the MAM values was wrong, a dummy read is necessary to get the flash memory in sync.\r
+  __writeMemory32(0x00000001, 0x400FC040, "Memory"); // MEMMAP = 1\r
+  __readMemory32(0x00000000, "Memory");\r
+  __writeMemory32(0x00000000, 0xE000ED08, "Memory"); //Vector table remap at 0x00000000\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LPC1768_IAR/FreeRTOSConfig.h
new file mode 100644 (file)
index 0000000..44dbc5d
--- /dev/null
@@ -0,0 +1,154 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under\r
+       the terms of the GNU General Public License (version 2) as published by the\r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the\r
+       source code for proprietary components outside of the FreeRTOS kernel.\r
+       Alternative commercial license and support terms are also available upon\r
+       request.  See the licensing section of http://www.FreeRTOS.org for full\r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION           1\r
+#define configUSE_IDLE_HOOK                    0\r
+#define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configUSE_TICK_HOOK                    1\r
+#define configCPU_CLOCK_HZ                     ( ( unsigned portLONG ) 99000000 )\r
+#define configTICK_RATE_HZ                     ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE       ( ( unsigned portSHORT ) 80 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) ( 19 * 1024 ) )\r
+#define configMAX_TASK_NAME_LEN                ( 12 )\r
+#define configUSE_TRACE_FACILITY       1\r
+#define configUSE_16_BIT_TICKS         0\r
+#define configIDLE_SHOULD_YIELD                0\r
+#define configUSE_CO_ROUTINES          0\r
+#define configUSE_MUTEXES                      1\r
+\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+#define configUSE_COUNTING_SEMAPHORES  0\r
+#define configUSE_ALTERNATIVE_API              0\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES            1\r
+#define configQUEUE_REGISTRY_SIZE              10\r
+#define configGENERATE_RUN_TIME_STATS  1\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet                       1\r
+#define INCLUDE_uxTaskPriorityGet                      1\r
+#define INCLUDE_vTaskDelete                                    1\r
+#define INCLUDE_vTaskCleanUpResources          0\r
+#define INCLUDE_vTaskSuspend                           1\r
+#define INCLUDE_vTaskDelayUntil                                1\r
+#define INCLUDE_vTaskDelay                                     1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark    1\r
+\r
+/*-----------------------------------------------------------\r
+ * Ethernet configuration.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* MAC address configuration. */\r
+#define configMAC_ADDR0        0x00\r
+#define configMAC_ADDR1        0x12\r
+#define configMAC_ADDR2        0x13\r
+#define configMAC_ADDR3        0x10\r
+#define configMAC_ADDR4        0x15\r
+#define configMAC_ADDR5        0x11\r
+\r
+/* IP address configuration. */\r
+#define configIP_ADDR0         192\r
+#define configIP_ADDR1         168\r
+#define configIP_ADDR2         0\r
+#define configIP_ADDR3         201\r
+\r
+/* Netmask configuration. */\r
+#define configNET_MASK0                255\r
+#define configNET_MASK1                255\r
+#define configNET_MASK2                255\r
+#define configNET_MASK3                0\r
+\r
+/* Use the system definition, if there is one */\r
+#ifdef __NVIC_PRIO_BITS\r
+       #define configPRIO_BITS       __NVIC_PRIO_BITS\r
+#else\r
+       #define configPRIO_BITS       5        /* 32 priority levels */\r
+#endif\r
+\r
+/* The lowest priority. */\r
+#define configKERNEL_INTERRUPT_PRIORITY        ( 31 << (8 - configPRIO_BITS) )\r
+/* Priority 5, or 160 as only the top three bits are implemented. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY   ( 5 << (8 - configPRIO_BITS) )\r
+\r
+/* Priorities passed to NVIC_SetPriority() do not require shifting as the\r
+function does the shifting itself.  Note these priorities need to be equal to\r
+or lower than configMAX_SYSCALL_INTERRUPT_PRIORITY - therefore the numeric\r
+value needs to be equal to or greater than 5 (on the Cortex M3 the lower the\r
+numeric value the higher the interrupt priority). */\r
+#define configEMAC_INTERRUPT_PRIORITY          5\r
+#define configUSB_INTERRUPT_PRIORITY           6\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Macros required to setup the timer for the run time stats.\r
+ *-----------------------------------------------------------*/\r
+#ifdef __ICCARM__\r
+       #include "LPC17xx.h"\r
+       extern void vConfigureTimerForRunTimeStats( void );\r
+       #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()\r
+       #define portGET_RUN_TIME_COUNTER_VALUE() TIM0->TC\r
+#endif\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LED.h b/Demo/CORTEX_LPC1768_IAR/LED.h
new file mode 100644 (file)
index 0000000..2aae6cb
--- /dev/null
@@ -0,0 +1,55 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under \r
+       the terms of the GNU General Public License (version 2) as published by the \r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the \r
+       source code for proprietary components outside of the FreeRTOS kernel.  \r
+       Alternative commercial license and support terms are also available upon \r
+       request.  See the licensing section of http://www.FreeRTOS.org for full \r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+#ifndef LED_HH\r
+#define LED_HH\r
+\r
+void vToggleLED( unsigned long ulLED );\r
+void vSetLEDState( unsigned long ulLED, long lState );\r
+long lGetLEDState( unsigned long ulLED );\r
+\r
+#endif\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPC1768_Flash.icf b/Demo/CORTEX_LPC1768_IAR/LPC1768_Flash.icf
new file mode 100644 (file)
index 0000000..1f03595
--- /dev/null
@@ -0,0 +1,37 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000100;\r
+define symbol __ICFEDIT_region_ROM_end__     = 0x0007FFFF;\r
+define symbol __ICFEDIT_region_RAM_start__   = 0x10000000;\r
+define symbol __ICFEDIT_region_RAM_end__     = 0x10007FFF;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__   = 0x800;\r
+define symbol __ICFEDIT_size_heap__     = 0x400;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];\r
+\r
+define symbol _AHB_RAM_start__  = 0x2007C000;\r
+define symbol _AHB_RAM_end__    = 0x20083FFF;\r
+define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];\r
+\r
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };\r
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };\r
+\r
+initialize by copy { readwrite };\r
+do not initialize  { section .noinit };\r
+do not initialize  { section USB_DMA_RAM };\r
+\r
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };\r
+place in ROM_region   { readonly };\r
+place in RAM_region   { readwrite,\r
+                        block CSTACK, block HEAP };\r
+place in AHB_RAM_region\r
+                      { readwrite data section AHB_RAM_MEMORY, section USB_DMA_RAM,  section EMAC_DMA_RAM};\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPC17xx.h b/Demo/CORTEX_LPC1768_IAR/LPC17xx.h
new file mode 100644 (file)
index 0000000..f2480b1
--- /dev/null
@@ -0,0 +1,1081 @@
+#ifndef __LPC17xx_H\r
+#define __LPC17xx_H\r
+\r
+/* System Control Block (SCB) includes:\r
+   Flash Accelerator Module, Clocking and Power Control, External Interrupts,\r
+   Reset, System Control and Status\r
+*/\r
+#define SCB_BASE_ADDR   0x400FC000\r
+\r
+#define PCONP_PCTIM0    0x00000002\r
+#define PCONP_PCTIM1    0x00000004\r
+#define PCONP_PCUART0   0x00000008\r
+#define PCONP_PCUART1   0x00000010\r
+#define PCONP_PCPWM1    0x00000040\r
+#define PCONP_PCI2C0    0x00000080\r
+#define PCONP_PCSPI     0x00000100\r
+#define PCONP_PCRTC     0x00000200\r
+#define PCONP_PCSSP1    0x00000400\r
+#define PCONP_PCAD      0x00001000\r
+#define PCONP_PCCAN1    0x00002000\r
+#define PCONP_PCCAN2    0x00004000\r
+#define PCONP_PCGPIO    0x00008000\r
+#define PCONP_PCRIT     0x00010000\r
+#define PCONP_PCMCPWM   0x00020000\r
+#define PCONP_PCQEI     0x00040000\r
+#define PCONP_PCI2C1    0x00080000\r
+#define PCONP_PCSSP0    0x00200000\r
+#define PCONP_PCTIM2    0x00400000\r
+#define PCONP_PCTIM3    0x00800000\r
+#define PCONP_PCUART2   0x01000000\r
+#define PCONP_PCUART3   0x02000000\r
+#define PCONP_PCI2C2    0x04000000\r
+#define PCONP_PCI2S     0x08000000\r
+#define PCONP_PCGPDMA   0x20000000\r
+#define PCONP_PCENET    0x40000000\r
+#define PCONP_PCUSB     0x80000000\r
+\r
+#define PLLCON_PLLE     0x00000001\r
+#define PLLCON_PLLC     0x00000002\r
+#define PLLCON_MASK     0x00000003\r
+\r
+#define PLLCFG_MUL1     0x00000000\r
+#define PLLCFG_MUL2     0x00000001\r
+#define PLLCFG_MUL3     0x00000002\r
+#define PLLCFG_MUL4     0x00000003\r
+#define PLLCFG_MUL5     0x00000004\r
+#define PLLCFG_MUL6     0x00000005\r
+#define PLLCFG_MUL7     0x00000006\r
+#define PLLCFG_MUL8     0x00000007\r
+#define PLLCFG_MUL9     0x00000008\r
+#define PLLCFG_MUL10    0x00000009\r
+#define PLLCFG_MUL11    0x0000000A\r
+#define PLLCFG_MUL12    0x0000000B\r
+#define PLLCFG_MUL13    0x0000000C\r
+#define PLLCFG_MUL14    0x0000000D\r
+#define PLLCFG_MUL15    0x0000000E\r
+#define PLLCFG_MUL16    0x0000000F\r
+#define PLLCFG_MUL17    0x00000010\r
+#define PLLCFG_MUL18    0x00000011\r
+#define PLLCFG_MUL19    0x00000012\r
+#define PLLCFG_MUL20    0x00000013\r
+#define PLLCFG_MUL21    0x00000014\r
+#define PLLCFG_MUL22    0x00000015\r
+#define PLLCFG_MUL23    0x00000016\r
+#define PLLCFG_MUL24    0x00000017\r
+#define PLLCFG_MUL25    0x00000018\r
+#define PLLCFG_MUL26    0x00000019\r
+#define PLLCFG_MUL27    0x0000001A\r
+#define PLLCFG_MUL28    0x0000001B\r
+#define PLLCFG_MUL29    0x0000001C\r
+#define PLLCFG_MUL30    0x0000001D\r
+#define PLLCFG_MUL31    0x0000001E\r
+#define PLLCFG_MUL32    0x0000001F\r
+#define PLLCFG_MUL33    0x00000020\r
+#define PLLCFG_MUL34    0x00000021\r
+#define PLLCFG_MUL35    0x00000022\r
+#define PLLCFG_MUL36    0x00000023\r
+\r
+#define PLLCFG_DIV1     0x00000000\r
+#define PLLCFG_DIV2     0x00010000\r
+#define PLLCFG_DIV3     0x00020000\r
+#define PLLCFG_DIV4     0x00030000\r
+#define PLLCFG_DIV5     0x00040000\r
+#define PLLCFG_DIV6     0x00050000\r
+#define PLLCFG_DIV7     0x00060000\r
+#define PLLCFG_DIV8     0x00070000\r
+#define PLLCFG_DIV9     0x00080000\r
+#define PLLCFG_DIV10    0x00090000\r
+#define PLLCFG_MASK            0x00FF7FFF\r
+\r
+#define PLLSTAT_MSEL_MASK      0x00007FFF\r
+#define PLLSTAT_NSEL_MASK      0x00FF0000\r
+\r
+#define PLLSTAT_PLLE   (1 << 24)\r
+#define PLLSTAT_PLLC   (1 << 25)\r
+#define PLLSTAT_PLOCK  (1 << 26)\r
+\r
+#define PLLFEED_FEED1   0x000000AA\r
+#define PLLFEED_FEED2   0x00000055\r
+\r
+#define NVIC_IRQ_WDT         0u         // IRQ0,  exception number 16\r
+#define NVIC_IRQ_TIMER0      1u         // IRQ1,  exception number 17\r
+#define NVIC_IRQ_TIMER1      2u         // IRQ2,  exception number 18\r
+#define NVIC_IRQ_TIMER2      3u         // IRQ3,  exception number 19\r
+#define NVIC_IRQ_TIMER3      4u         // IRQ4,  exception number 20\r
+#define NVIC_IRQ_UART0       5u         // IRQ5,  exception number 21\r
+#define NVIC_IRQ_UART1       6u         // IRQ6,  exception number 22\r
+#define NVIC_IRQ_UART2       7u         // IRQ7,  exception number 23\r
+#define NVIC_IRQ_UART3       8u         // IRQ8,  exception number 24\r
+#define NVIC_IRQ_PWM1        9u         // IRQ9,  exception number 25\r
+#define NVIC_IRQ_I2C0        10u        // IRQ10, exception number 26\r
+#define NVIC_IRQ_I2C1        11u        // IRQ11, exception number 27\r
+#define NVIC_IRQ_I2C2        12u        // IRQ12, exception number 28\r
+#define NVIC_IRQ_SPI         13u        // IRQ13, exception number 29\r
+#define NVIC_IRQ_SSP0        14u        // IRQ14, exception number 30\r
+#define NVIC_IRQ_SSP1        15u        // IRQ15, exception number 31\r
+#define NVIC_IRQ_PLL0        16u        // IRQ16, exception number 32\r
+#define NVIC_IRQ_RTC         17u        // IRQ17, exception number 33\r
+#define NVIC_IRQ_EINT0       18u        // IRQ18, exception number 34\r
+#define NVIC_IRQ_EINT1       19u        // IRQ19, exception number 35\r
+#define NVIC_IRQ_EINT2       20u        // IRQ20, exception number 36\r
+#define NVIC_IRQ_EINT3       21u        // IRQ21, exception number 37\r
+#define NVIC_IRQ_ADC         22u        // IRQ22, exception number 38\r
+#define NVIC_IRQ_BOD         23u        // IRQ23, exception number 39\r
+#define NVIC_IRQ_USB         24u        // IRQ24, exception number 40\r
+#define NVIC_IRQ_CAN         25u        // IRQ25, exception number 41\r
+#define NVIC_IRQ_GPDMA       26u        // IRQ26, exception number 42\r
+#define NVIC_IRQ_I2S         27u        // IRQ27, exception number 43\r
+#define NVIC_IRQ_ETHERNET    28u        // IRQ28, exception number 44\r
+#define NVIC_IRQ_RIT         29u        // IRQ29, exception number 45\r
+#define NVIC_IRQ_MCPWM       30u        // IRQ30, exception number 46\r
+#define NVIC_IRQ_QE          31u        // IRQ31, exception number 47\r
+#define NVIC_IRQ_PLL1        32u        // IRQ32, exception number 48\r
+#define NVIC_IRQ_USB_ACT     33u        // IRQ33, exception number 49\r
+#define NVIC_IRQ_CAN_ACT     34u        // IRQ34, exception number 50\r
+\r
+\r
+#endif  // __LPC17xx_H\r
+\r
+\r
+#ifndef CMSIS_17xx_H\r
+#define CMSIS_17xx_H\r
+\r
+/******************************************************************************\r
+ * @file:    LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for\r
+ *           NXP LPC17xx Device Series\r
+ * @version: V1.1\r
+ * @date:    14th May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
+ * processor based microcontrollers.  This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __LPC17xx_H__\r
+#define __LPC17xx_H__\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ---------- Interrupt Number Definition -----------------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */\r
+  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */\r
+  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */\r
+  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */\r
+  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */\r
+  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */\r
+  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */\r
+  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */\r
+\r
+/******  LPC17xx Specific Interrupt Numbers *******************************************************/\r
+  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */\r
+  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */\r
+  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */\r
+  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */\r
+  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */\r
+  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */\r
+  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */\r
+  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */\r
+  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */\r
+  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */\r
+  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */\r
+  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */\r
+  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */\r
+  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */\r
+  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */\r
+  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */\r
+  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */\r
+  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */\r
+  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */\r
+  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */\r
+  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */\r
+  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */\r
+  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */\r
+  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */\r
+  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */\r
+  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */\r
+  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */\r
+  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */\r
+  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */\r
+  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */\r
+  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */\r
+  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */\r
+  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */\r
+} IRQn_Type;\r
+\r
+\r
+/*\r
+ * ==========================================================================\r
+ * ----------- Processor and Core Peripheral Section ------------------------\r
+ * ==========================================================================\r
+ */\r
+\r
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */\r
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */\r
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */\r
+\r
+\r
+//#include "..\core_cm3.h"                    /* Cortex-M3 processor and core peripherals           */\r
+#include "core_cm3.h"\r
+#include "system_LPC17xx.h"                 /* System Header                                      */\r
+\r
+\r
+\r
+/**\r
+ * Initialize the system clock\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+\r
+\r
+/******************************************************************************/\r
+/*                Device Specific Peripheral registers structures             */\r
+/******************************************************************************/\r
+\r
+/*------------- System Control (SC) ------------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */\r
+       uint32_t RESERVED0[31];\r
+  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */\r
+  __IO uint32_t PLL0CFG;\r
+  __I  uint32_t PLL0STAT;\r
+  __O  uint32_t PLL0FEED;\r
+       uint32_t RESERVED1[4];\r
+  __IO uint32_t PLL1CON;\r
+  __IO uint32_t PLL1CFG;\r
+  __I  uint32_t PLL1STAT;\r
+  __O  uint32_t PLL1FEED;\r
+       uint32_t RESERVED2[4];\r
+  __IO uint32_t PCON;\r
+  __IO uint32_t PCONP;\r
+       uint32_t RESERVED3[15];\r
+  __IO uint32_t CCLKCFG;\r
+  __IO uint32_t USBCLKCFG;\r
+  __IO uint32_t CLKSRCSEL;\r
+       uint32_t RESERVED4[12];\r
+  __IO uint32_t EXTINT;                 /* External Interrupts                */\r
+       uint32_t RESERVED5;\r
+  __IO uint32_t EXTMODE;\r
+  __IO uint32_t EXTPOLAR;\r
+       uint32_t RESERVED6[12];\r
+  __IO uint32_t RSID;                   /* Reset                              */\r
+       uint32_t RESERVED7[7];\r
+  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */\r
+  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */\r
+  __IO uint32_t PCLKSEL0;\r
+  __IO uint32_t PCLKSEL1;\r
+       uint32_t RESERVED8[4];\r
+  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */\r
+       uint32_t RESERVED9;\r
+  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */\r
+ } SC_TypeDef;\r
+\r
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t PINSEL0;\r
+  __IO uint32_t PINSEL1;\r
+  __IO uint32_t PINSEL2;\r
+  __IO uint32_t PINSEL3;\r
+  __IO uint32_t PINSEL4;\r
+  __IO uint32_t PINSEL5;\r
+  __IO uint32_t PINSEL6;\r
+  __IO uint32_t PINSEL7;\r
+  __IO uint32_t PINSEL8;\r
+  __IO uint32_t PINSEL9;\r
+  __IO uint32_t PINSEL10;\r
+       uint32_t RESERVED0[5];\r
+  __IO uint32_t PINMODE0;\r
+  __IO uint32_t PINMODE1;\r
+  __IO uint32_t PINMODE2;\r
+  __IO uint32_t PINMODE3;\r
+  __IO uint32_t PINMODE4;\r
+  __IO uint32_t PINMODE5;\r
+  __IO uint32_t PINMODE6;\r
+  __IO uint32_t PINMODE7;\r
+  __IO uint32_t PINMODE8;\r
+  __IO uint32_t PINMODE9;\r
+  __IO uint32_t PINMODE_OD0;\r
+  __IO uint32_t PINMODE_OD1;\r
+  __IO uint32_t PINMODE_OD2;\r
+  __IO uint32_t PINMODE_OD3;\r
+  __IO uint32_t PINMODE_OD4;\r
+} PINCON_TypeDef;\r
+\r
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t FIODIR;\r
+       uint32_t RESERVED0[3];\r
+  __IO uint32_t FIOMASK;\r
+  __IO uint32_t FIOPIN;\r
+  __IO uint32_t FIOSET;\r
+  __O  uint32_t FIOCLR;\r
+} GPIO_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __I  uint32_t IntStatus;\r
+  __I  uint32_t IO0IntStatR;\r
+  __I  uint32_t IO0IntStatF;\r
+  __O  uint32_t IO0IntClr;\r
+  __IO uint32_t IO0IntEnR;\r
+  __IO uint32_t IO0IntEnF;\r
+       uint32_t RESERVED0[3];\r
+  __I  uint32_t IO2IntStatR;\r
+  __I  uint32_t IO2IntStatF;\r
+  __O  uint32_t IO2IntClr;\r
+  __IO uint32_t IO2IntEnR;\r
+  __IO uint32_t IO2IntEnF;\r
+} GPIOINT_TypeDef;\r
+\r
+/*------------- Timer (TIM) --------------------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t IR;\r
+  __IO uint32_t TCR;\r
+  __IO uint32_t TC;\r
+  __IO uint32_t PR;\r
+  __IO uint32_t PC;\r
+  __IO uint32_t MCR;\r
+  __IO uint32_t MR0;\r
+  __IO uint32_t MR1;\r
+  __IO uint32_t MR2;\r
+  __IO uint32_t MR3;\r
+  __IO uint32_t CCR;\r
+  __I  uint32_t CR0;\r
+  __I  uint32_t CR1;\r
+       uint32_t RESERVED0[2];\r
+  __IO uint32_t EMR;\r
+       uint32_t RESERVED1[24];\r
+  __IO uint32_t CTCR;\r
+} TIM_TypeDef;\r
+\r
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t IR;\r
+  __IO uint32_t TCR;\r
+  __IO uint32_t TC;\r
+  __IO uint32_t PR;\r
+  __IO uint32_t PC;\r
+  __IO uint32_t MCR;\r
+  __IO uint32_t MR0;\r
+  __IO uint32_t MR1;\r
+  __IO uint32_t MR2;\r
+  __IO uint32_t MR3;\r
+  __IO uint32_t CCR;\r
+  __I  uint32_t CR0;\r
+  __I  uint32_t CR1;\r
+  __I  uint32_t CR2;\r
+  __I  uint32_t CR3;\r
+  __IO uint32_t MR4;\r
+  __IO uint32_t MR5;\r
+  __IO uint32_t MR6;\r
+  __IO uint32_t PCR;\r
+  __IO uint32_t LER;\r
+       uint32_t RESERVED0[7];\r
+  __IO uint32_t CTCR;\r
+} PWM_TypeDef;\r
+\r
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
+typedef struct\r
+{\r
+  union {\r
+  __I  uint8_t  RBR;\r
+  __O  uint8_t  THR;\r
+  __IO uint8_t  DLL;\r
+       uint32_t RESERVED0;\r
+  };\r
+  union {\r
+  __IO uint8_t  DLM;\r
+  __IO uint32_t IER;\r
+  };\r
+  union {\r
+  __I  uint32_t IIR;\r
+  __O  uint8_t  FCR;\r
+  };\r
+  __IO uint8_t  LCR;\r
+       uint8_t  RESERVED1[7];\r
+  __IO uint8_t  LSR;\r
+       uint8_t  RESERVED2[7];\r
+  __IO uint8_t  SCR;\r
+       uint8_t  RESERVED3[3];\r
+  __IO uint32_t ACR;\r
+  __IO uint8_t  ICR;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  FDR;\r
+       uint8_t  RESERVED5[7];\r
+  __IO uint8_t  TER;\r
+       uint8_t  RESERVED6[27];\r
+  __IO uint8_t  RS485CTRL;\r
+       uint8_t  RESERVED7[3];\r
+  __IO uint8_t  ADRMATCH;\r
+} UART_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  union {\r
+  __I  uint8_t  RBR;\r
+  __O  uint8_t  THR;\r
+  __IO uint8_t  DLL;\r
+       uint32_t RESERVED0;\r
+  };\r
+  union {\r
+  __IO uint8_t  DLM;\r
+  __IO uint32_t IER;\r
+  };\r
+  union {\r
+  __I  uint32_t IIR;\r
+  __O  uint8_t  FCR;\r
+  };\r
+  __IO uint8_t  LCR;\r
+       uint8_t  RESERVED1[3];\r
+  __IO uint8_t  MCR;\r
+       uint8_t  RESERVED2[3];\r
+  __IO uint8_t  LSR;\r
+       uint8_t  RESERVED3[3];\r
+  __IO uint8_t  MSR;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  SCR;\r
+       uint8_t  RESERVED5[3];\r
+  __IO uint32_t ACR;\r
+       uint32_t RESERVED6;\r
+  __IO uint32_t FDR;\r
+       uint32_t RESERVED7;\r
+  __IO uint8_t  TER;\r
+       uint8_t  RESERVED8[27];\r
+  __IO uint8_t  RS485CTRL;\r
+       uint8_t  RESERVED9[3];\r
+  __IO uint8_t  ADRMATCH;\r
+       uint8_t  RESERVED10[3];\r
+  __IO uint8_t  RS485DLY;\r
+} UART1_TypeDef;\r
+\r
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t SPCR;\r
+  __I  uint32_t SPSR;\r
+  __IO uint32_t SPDR;\r
+  __IO uint32_t SPCCR;\r
+       uint32_t RESERVED0[3];\r
+  __IO uint32_t SPINT;\r
+} SPI_TypeDef;\r
+\r
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t CR0;\r
+  __IO uint32_t CR1;\r
+  __IO uint32_t DR;\r
+  __I  uint32_t SR;\r
+  __IO uint32_t CPSR;\r
+  __IO uint32_t IMSC;\r
+  __IO uint32_t RIS;\r
+  __IO uint32_t MIS;\r
+  __IO uint32_t ICR;\r
+  __IO uint32_t DMACR;\r
+} SSP_TypeDef;\r
+\r
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t I2CONSET;\r
+  __I  uint32_t I2STAT;\r
+  __IO uint32_t I2DAT;\r
+  __IO uint32_t I2ADR0;\r
+  __IO uint32_t I2SCLH;\r
+  __IO uint32_t I2SCLL;\r
+  __O  uint32_t I2CONCLR;\r
+  __IO uint32_t MMCTRL;\r
+  __IO uint32_t I2ADR1;\r
+  __IO uint32_t I2ADR2;\r
+  __IO uint32_t I2ADR3;\r
+  __I  uint32_t I2DATA_BUFFER;\r
+  __IO uint32_t I2MASK0;\r
+  __IO uint32_t I2MASK1;\r
+  __IO uint32_t I2MASK2;\r
+  __IO uint32_t I2MASK3;\r
+} I2C_TypeDef;\r
+\r
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t I2SDAO;\r
+  __IO  uint32_t I2SDAI;\r
+  __O  uint32_t I2STXFIFO;\r
+  __I  uint32_t I2SRXFIFO;\r
+  __I  uint32_t I2SSTATE;\r
+  __IO uint32_t I2SDMA1;\r
+  __IO uint32_t I2SDMA2;\r
+  __IO uint32_t I2SIRQ;\r
+  __IO uint32_t I2STXRATE;\r
+  __IO uint32_t I2SRXRATE;\r
+  __IO uint32_t I2STXBITRATE;\r
+  __IO uint32_t I2SRXBITRATE;\r
+  __IO uint32_t I2STXMODE;\r
+  __IO uint32_t I2SRXMODE;\r
+} I2S_TypeDef;\r
+\r
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t RICOMPVAL;\r
+  __IO uint32_t RIMASK;\r
+  __IO uint8_t  RICTRL;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint32_t RICOUNTER;\r
+} RIT_TypeDef;\r
+\r
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint8_t  ILR;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint8_t  CCR;\r
+       uint8_t  RESERVED1[3];\r
+  __IO uint8_t  CIIR;\r
+       uint8_t  RESERVED2[3];\r
+  __IO uint8_t  AMR;\r
+       uint8_t  RESERVED3[3];\r
+  __I  uint32_t CTIME0;\r
+  __I  uint32_t CTIME1;\r
+  __I  uint32_t CTIME2;\r
+  __IO uint8_t  SEC;\r
+       uint8_t  RESERVED4[3];\r
+  __IO uint8_t  MIN;\r
+       uint8_t  RESERVED5[3];\r
+  __IO uint8_t  HOUR;\r
+       uint8_t  RESERVED6[3];\r
+  __IO uint8_t  DOM;\r
+       uint8_t  RESERVED7[3];\r
+  __IO uint8_t  DOW;\r
+       uint8_t  RESERVED8[3];\r
+  __IO uint16_t DOY;\r
+       uint16_t RESERVED9;\r
+  __IO uint8_t  MONTH;\r
+       uint8_t  RESERVED10[3];\r
+  __IO uint16_t YEAR;\r
+       uint16_t RESERVED11;\r
+  __IO uint32_t CALIBRATION;\r
+  __IO uint32_t GPREG0;\r
+  __IO uint32_t GPREG1;\r
+  __IO uint32_t GPREG2;\r
+  __IO uint32_t GPREG3;\r
+  __IO uint32_t GPREG4;\r
+  __IO uint8_t  WAKEUPDIS;\r
+       uint8_t  RESERVED12[3];\r
+  __IO uint8_t  PWRCTRL;\r
+       uint8_t  RESERVED13[3];\r
+  __IO uint8_t  ALSEC;\r
+       uint8_t  RESERVED14[3];\r
+  __IO uint8_t  ALMIN;\r
+       uint8_t  RESERVED15[3];\r
+  __IO uint8_t  ALHOUR;\r
+       uint8_t  RESERVED16[3];\r
+  __IO uint8_t  ALDOM;\r
+       uint8_t  RESERVED17[3];\r
+  __IO uint8_t  ALDOW;\r
+       uint8_t  RESERVED18[3];\r
+  __IO uint16_t ALDOY;\r
+       uint16_t RESERVED19;\r
+  __IO uint8_t  ALMON;\r
+       uint8_t  RESERVED20[3];\r
+  __IO uint16_t ALYEAR;\r
+       uint16_t RESERVED21;\r
+} RTC_TypeDef;\r
+\r
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint8_t  WDMOD;\r
+       uint8_t  RESERVED0[3];\r
+  __IO uint32_t WDTC;\r
+  __O  uint8_t  WDFEED;\r
+       uint8_t  RESERVED1[3];\r
+  __I  uint32_t WDTV;\r
+  __IO uint32_t WDCLKSEL;\r
+} WDT_TypeDef;\r
+\r
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t ADCR;\r
+  __IO uint32_t ADGDR;\r
+       uint32_t RESERVED0;\r
+  __IO uint32_t ADINTEN;\r
+  __I  uint32_t ADDR0;\r
+  __I  uint32_t ADDR1;\r
+  __I  uint32_t ADDR2;\r
+  __I  uint32_t ADDR3;\r
+  __I  uint32_t ADDR4;\r
+  __I  uint32_t ADDR5;\r
+  __I  uint32_t ADDR6;\r
+  __I  uint32_t ADDR7;\r
+  __I  uint32_t ADSTAT;\r
+  __IO uint32_t ADTRM;\r
+} ADC_TypeDef;\r
+\r
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t DACR;\r
+  __IO uint32_t DACCTRL;\r
+  __IO uint16_t DACCNTVAL;\r
+} DAC_TypeDef;\r
+\r
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
+typedef struct\r
+{\r
+  __I  uint32_t MCCON;\r
+  __O  uint32_t MCCON_SET;\r
+  __O  uint32_t MCCON_CLR;\r
+  __I  uint32_t MCCAPCON;\r
+  __O  uint32_t MCCAPCON_SET;\r
+  __O  uint32_t MCCAPCON_CLR;\r
+  __IO uint32_t MCTIM0;\r
+  __IO uint32_t MCTIM1;\r
+  __IO uint32_t MCTIM2;\r
+  __IO uint32_t MCPER0;\r
+  __IO uint32_t MCPER1;\r
+  __IO uint32_t MCPER2;\r
+  __IO uint32_t MCPW0;\r
+  __IO uint32_t MCPW1;\r
+  __IO uint32_t MCPW2;\r
+  __IO uint32_t MCDEADTIME;\r
+  __IO uint32_t MCCCP;\r
+  __IO uint32_t MCCR0;\r
+  __IO uint32_t MCCR1;\r
+  __IO uint32_t MCCR2;\r
+  __I  uint32_t MCINTEN;\r
+  __O  uint32_t MCINTEN_SET;\r
+  __O  uint32_t MCINTEN_CLR;\r
+  __I  uint32_t MCCNTCON;\r
+  __O  uint32_t MCCNTCON_SET;\r
+  __O  uint32_t MCCNTCON_CLR;\r
+  __I  uint32_t MCINTFLAG;\r
+  __O  uint32_t MCINTFLAG_SET;\r
+  __O  uint32_t MCINTFLAG_CLR;\r
+  __O  uint32_t MCCAP_CLR;\r
+} MCPWM_TypeDef;\r
+\r
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
+typedef struct\r
+{\r
+  __O  uint32_t QEICON;\r
+  __I  uint32_t QEISTAT;\r
+  __IO uint32_t QEICONF;\r
+  __I  uint32_t QEIPOS;\r
+  __IO uint32_t QEIMAXPOS;\r
+  __IO uint32_t CMPOS0;\r
+  __IO uint32_t CMPOS1;\r
+  __IO uint32_t CMPOS2;\r
+  __I  uint32_t INXCNT;\r
+  __IO uint32_t INXCMP;\r
+  __IO uint32_t QEILOAD;\r
+  __I  uint32_t QEITIME;\r
+  __I  uint32_t QEIVEL;\r
+  __I  uint32_t QEICAP;\r
+  __IO uint32_t VELCOMP;\r
+  __IO uint32_t FILTER;\r
+       uint32_t RESERVED0[998];\r
+  __O  uint32_t QEIIEC;\r
+  __O  uint32_t QEIIES;\r
+  __I  uint32_t QEIINTSTAT;\r
+  __I  uint32_t QEIIE;\r
+  __O  uint32_t QEICLR;\r
+  __O  uint32_t QEISET;\r
+} QEI_TypeDef;\r
+\r
+/*------------- Controller Area Network (CAN) --------------------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t mask[512];              /* ID Masks                           */\r
+} CANAF_RAM_TypeDef;\r
+\r
+typedef struct                          /* Acceptance Filter Registers        */\r
+{\r
+  __IO uint32_t AFMR;\r
+  __IO uint32_t SFF_sa;\r
+  __IO uint32_t SFF_GRP_sa;\r
+  __IO uint32_t EFF_sa;\r
+  __IO uint32_t EFF_GRP_sa;\r
+  __IO uint32_t ENDofTable;\r
+  __I  uint32_t LUTerrAd;\r
+  __I  uint32_t LUTerr;\r
+} CANAF_TypeDef;\r
+\r
+typedef struct                          /* Central Registers                  */\r
+{\r
+  __I  uint32_t CANTxSR;\r
+  __I  uint32_t CANRxSR;\r
+  __I  uint32_t CANMSR;\r
+} CANCR_TypeDef;\r
+\r
+typedef struct                          /* Controller Registers               */\r
+{\r
+  __IO uint32_t MOD;\r
+  __O  uint32_t CMR;\r
+  __IO uint32_t GSR;\r
+  __I  uint32_t ICR;\r
+  __IO uint32_t IER;\r
+  __IO uint32_t BTR;\r
+  __IO uint32_t EWL;\r
+  __I  uint32_t SR;\r
+  __IO uint32_t RFS;\r
+  __IO uint32_t RID;\r
+  __IO uint32_t RDA;\r
+  __IO uint32_t RDB;\r
+  __IO uint32_t TFI1;\r
+  __IO uint32_t TID1;\r
+  __IO uint32_t TDA1;\r
+  __IO uint32_t TDB1;\r
+  __IO uint32_t TFI2;\r
+  __IO uint32_t TID2;\r
+  __IO uint32_t TDA2;\r
+  __IO uint32_t TDB2;\r
+  __IO uint32_t TFI3;\r
+  __IO uint32_t TID3;\r
+  __IO uint32_t TDA3;\r
+  __IO uint32_t TDB3;\r
+} CAN_TypeDef;\r
+\r
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
+typedef struct                          /* Common Registers                   */\r
+{\r
+  __I  uint32_t DMACIntStat;\r
+  __I  uint32_t DMACIntTCStat;\r
+  __O  uint32_t DMACIntTCClear;\r
+  __I  uint32_t DMACIntErrStat;\r
+  __O  uint32_t DMACIntErrClr;\r
+  __I  uint32_t DMACRawIntTCStat;\r
+  __I  uint32_t DMACRawIntErrStat;\r
+  __I  uint32_t DMACEnbldChns;\r
+  __IO uint32_t DMACSoftBReq;\r
+  __IO uint32_t DMACSoftSReq;\r
+  __IO uint32_t DMACSoftLBReq;\r
+  __IO uint32_t DMACSoftLSReq;\r
+  __IO uint32_t DMACConfig;\r
+  __IO uint32_t DMACSync;\r
+} GPDMA_TypeDef;\r
+\r
+typedef struct                          /* Channel Registers                  */\r
+{\r
+  __IO uint32_t DMACCSrcAddr;\r
+  __IO uint32_t DMACCDestAddr;\r
+  __IO uint32_t DMACCLLI;\r
+  __IO uint32_t DMACCControl;\r
+  __IO uint32_t DMACCConfig;\r
+} GPDMACH_TypeDef;\r
+\r
+/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
+typedef struct\r
+{\r
+  __I  uint32_t HcRevision;             /* USB Host Registers                 */\r
+  __IO uint32_t HcControl;\r
+  __IO uint32_t HcCommandStatus;\r
+  __IO uint32_t HcInterruptStatus;\r
+  __IO uint32_t HcInterruptEnable;\r
+  __IO uint32_t HcInterruptDisable;\r
+  __IO uint32_t HcHCCA;\r
+  __I  uint32_t HcPeriodCurrentED;\r
+  __IO uint32_t HcControlHeadED;\r
+  __IO uint32_t HcControlCurrentED;\r
+  __IO uint32_t HcBulkHeadED;\r
+  __IO uint32_t HcBulkCurrentED;\r
+  __I  uint32_t HcDoneHead;\r
+  __IO uint32_t HcFmInterval;\r
+  __I  uint32_t HcFmRemaining;\r
+  __I  uint32_t HcFmNumber;\r
+  __IO uint32_t HcPeriodicStart;\r
+  __IO uint32_t HcLSTreshold;\r
+  __IO uint32_t HcRhDescriptorA;\r
+  __IO uint32_t HcRhDescriptorB;\r
+  __IO uint32_t HcRhStatus;\r
+  __IO uint32_t HcRhPortStatus1;\r
+  __IO uint32_t HcRhPortStatus2;\r
+       uint32_t RESERVED0[40];\r
+  __I  uint32_t Module_ID;\r
+\r
+  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */\r
+  __IO uint32_t OTGIntEn;\r
+  __O  uint32_t OTGIntSet;\r
+  __O  uint32_t OTGIntClr;\r
+  __IO uint32_t OTGStCtrl;\r
+  __IO uint32_t OTGTmr;\r
+       uint32_t RESERVED1[58];\r
+\r
+  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */\r
+  __IO uint32_t USBDevIntEn;\r
+  __O  uint32_t USBDevIntClr;\r
+  __O  uint32_t USBDevIntSet;\r
+\r
+  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */\r
+  __I  uint32_t USBCmdData;\r
+\r
+  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */\r
+  __O  uint32_t USBTxData;\r
+  __I  uint32_t USBRxPLen;\r
+  __O  uint32_t USBTxPLen;\r
+  __IO uint32_t USBCtrl;\r
+  __O  uint32_t USBDevIntPri;\r
+\r
+  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */\r
+  __IO uint32_t USBEpIntEn;\r
+  __O  uint32_t USBEpIntClr;\r
+  __O  uint32_t USBEpIntSet;\r
+  __O  uint32_t USBEpIntPri;\r
+\r
+  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/\r
+  __O  uint32_t USBEpInd;\r
+  __IO uint32_t USBMaxPSize;\r
+\r
+  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */\r
+  __O  uint32_t USBDMARClr;\r
+  __O  uint32_t USBDMARSet;\r
+       uint32_t RESERVED2[9];\r
+  __IO uint32_t USBUDCAH;\r
+  __I  uint32_t USBEpDMASt;\r
+  __O  uint32_t USBEpDMAEn;\r
+  __O  uint32_t USBEpDMADis;\r
+  __I  uint32_t USBDMAIntSt;\r
+  __IO uint32_t USBDMAIntEn;\r
+       uint32_t RESERVED3[2];\r
+  __I  uint32_t USBEoTIntSt;\r
+  __O  uint32_t USBEoTIntClr;\r
+  __O  uint32_t USBEoTIntSet;\r
+  __I  uint32_t USBNDDRIntSt;\r
+  __O  uint32_t USBNDDRIntClr;\r
+  __O  uint32_t USBNDDRIntSet;\r
+  __I  uint32_t USBSysErrIntSt;\r
+  __O  uint32_t USBSysErrIntClr;\r
+  __O  uint32_t USBSysErrIntSet;\r
+       uint32_t RESERVED4[15];\r
+\r
+  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */\r
+  __O  uint32_t I2C_WO;\r
+  __I  uint32_t I2C_STS;\r
+  __IO uint32_t I2C_CTL;\r
+  __IO uint32_t I2C_CLKHI;\r
+  __O  uint32_t I2C_CLKLO;\r
+       uint32_t RESERVED5[823];\r
+\r
+  union {\r
+  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */\r
+  __IO uint32_t OTGClkCtrl;\r
+  } ;\r
+  union {\r
+  __I  uint32_t USBClkSt;\r
+  __I  uint32_t OTGClkSt;\r
+  };\r
+} USB_TypeDef;\r
+\r
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
+typedef struct\r
+{\r
+  __IO uint32_t MAC1;                   /* MAC Registers                      */\r
+  __IO uint32_t MAC2;\r
+  __IO uint32_t IPGT;\r
+  __IO uint32_t IPGR;\r
+  __IO uint32_t CLRT;\r
+  __IO uint32_t MAXF;\r
+  __IO uint32_t SUPP;\r
+  __IO uint32_t TEST;\r
+  __IO uint32_t MCFG;\r
+  __IO uint32_t MCMD;\r
+  __IO uint32_t MADR;\r
+  __O  uint32_t MWTD;\r
+  __I  uint32_t MRDD;\r
+  __I  uint32_t MIND;\r
+       uint32_t RESERVED0[2];\r
+  __IO uint32_t SA0;\r
+  __IO uint32_t SA1;\r
+  __IO uint32_t SA2;\r
+       uint32_t RESERVED1[45];\r
+  __IO uint32_t Command;                /* Control Registers                  */\r
+  __I  uint32_t Status;\r
+  __IO uint32_t RxDescriptor;\r
+  __IO uint32_t RxStatus;\r
+  __IO uint32_t RxDescriptorNumber;\r
+  __I  uint32_t RxProduceIndex;\r
+  __IO uint32_t RxConsumeIndex;\r
+  __IO uint32_t TxDescriptor;\r
+  __IO uint32_t TxStatus;\r
+  __IO uint32_t TxDescriptorNumber;\r
+  __IO uint32_t TxProduceIndex;\r
+  __I  uint32_t TxConsumeIndex;\r
+       uint32_t RESERVED2[10];\r
+  __I  uint32_t TSV0;\r
+  __I  uint32_t TSV1;\r
+  __I  uint32_t RSV;\r
+       uint32_t RESERVED3[3];\r
+  __IO uint32_t FlowControlCounter;\r
+  __I  uint32_t FlowControlStatus;\r
+       uint32_t RESERVED4[34];\r
+  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */\r
+  __IO uint32_t RxFilterWoLStatus;\r
+  __IO uint32_t RxFilterWoLClear;\r
+       uint32_t RESERVED5;\r
+  __IO uint32_t HashFilterL;\r
+  __IO uint32_t HashFilterH;\r
+       uint32_t RESERVED6[882];\r
+  __I  uint32_t IntStatus;              /* Module Control Registers           */\r
+  __IO uint32_t IntEnable;\r
+  __O  uint32_t IntClear;\r
+  __O  uint32_t IntSet;\r
+       uint32_t RESERVED7;\r
+  __IO uint32_t PowerDown;\r
+       uint32_t RESERVED8;\r
+  __IO uint32_t Module_ID;\r
+} EMAC_TypeDef;\r
+\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral memory map                              */\r
+/******************************************************************************/\r
+/* Base addresses                                                             */\r
+#define FLASH_BASE            (0x00000000UL)\r
+#define RAM_BASE              (0x10000000UL)\r
+#define GPIO_BASE             (0x2009C000UL)\r
+#define APB0_BASE             (0x40000000UL)\r
+#define APB1_BASE             (0x40080000UL)\r
+#define AHB_BASE              (0x50000000UL)\r
+#define CM3_BASE              (0xE0000000UL)\r
+\r
+/* APB0 peripherals                                                           */\r
+#define WDT_BASE              (APB0_BASE + 0x00000)\r
+#define TIM0_BASE             (APB0_BASE + 0x04000)\r
+#define TIM1_BASE             (APB0_BASE + 0x08000)\r
+#define UART0_BASE            (APB0_BASE + 0x0C000)\r
+#define UART1_BASE            (APB0_BASE + 0x10000)\r
+#define PWM1_BASE             (APB0_BASE + 0x18000)\r
+#define I2C0_BASE             (APB0_BASE + 0x1C000)\r
+#define SPI_BASE              (APB0_BASE + 0x20000)\r
+#define RTC_BASE              (APB0_BASE + 0x24000)\r
+#define GPIOINT_BASE          (APB0_BASE + 0x28080)\r
+#define PINCON_BASE           (APB0_BASE + 0x2C000)\r
+#define SSP1_BASE             (APB0_BASE + 0x30000)\r
+#define ADC_BASE              (APB0_BASE + 0x34000)\r
+#define CANAF_RAM_BASE        (APB0_BASE + 0x38000)\r
+#define CANAF_BASE            (APB0_BASE + 0x3C000)\r
+#define CANCR_BASE            (APB0_BASE + 0x40000)\r
+#define CAN1_BASE             (APB0_BASE + 0x44000)\r
+#define CAN2_BASE             (APB0_BASE + 0x48000)\r
+#define I2C1_BASE             (APB0_BASE + 0x5C000)\r
+\r
+/* APB1 peripherals                                                           */\r
+#define SSP0_BASE             (APB1_BASE + 0x08000)\r
+#define DAC_BASE              (APB1_BASE + 0x0C000)\r
+#define TIM2_BASE             (APB1_BASE + 0x10000)\r
+#define TIM3_BASE             (APB1_BASE + 0x14000)\r
+#define UART2_BASE            (APB1_BASE + 0x18000)\r
+#define UART3_BASE            (APB1_BASE + 0x1C000)\r
+#define I2C2_BASE             (APB1_BASE + 0x20000)\r
+#define I2S_BASE              (APB1_BASE + 0x28000)\r
+#define RIT_BASE              (APB1_BASE + 0x30000)\r
+#define MCPWM_BASE            (APB1_BASE + 0x38000)\r
+#define QEI_BASE              (APB1_BASE + 0x3C000)\r
+#define SC_BASE               (APB1_BASE + 0x7C000)\r
+\r
+/* AHB peripherals                                                            */\r
+#define EMAC_BASE             (AHB_BASE  + 0x00000)\r
+#define GPDMA_BASE            (AHB_BASE  + 0x04000)\r
+#define GPDMACH0_BASE         (AHB_BASE  + 0x04100)\r
+#define GPDMACH1_BASE         (AHB_BASE  + 0x04120)\r
+#define GPDMACH2_BASE         (AHB_BASE  + 0x04140)\r
+#define GPDMACH3_BASE         (AHB_BASE  + 0x04160)\r
+#define GPDMACH4_BASE         (AHB_BASE  + 0x04180)\r
+#define GPDMACH5_BASE         (AHB_BASE  + 0x041A0)\r
+#define GPDMACH6_BASE         (AHB_BASE  + 0x041C0)\r
+#define GPDMACH7_BASE         (AHB_BASE  + 0x041E0)\r
+#define USB_BASE              (AHB_BASE  + 0x0C000)\r
+\r
+/* GPIOs                                                                      */\r
+#define GPIO0_BASE            (GPIO_BASE + 0x00000)\r
+#define GPIO1_BASE            (GPIO_BASE + 0x00020)\r
+#define GPIO2_BASE            (GPIO_BASE + 0x00040)\r
+#define GPIO3_BASE            (GPIO_BASE + 0x00060)\r
+#define GPIO4_BASE            (GPIO_BASE + 0x00080)\r
+\r
+\r
+/******************************************************************************/\r
+/*                         Peripheral declaration                             */\r
+/******************************************************************************/\r
+#define SC                    ((       SC_TypeDef *)        SC_BASE)\r
+#define GPIO0                 ((     GPIO_TypeDef *)     GPIO0_BASE)\r
+#define GPIO1                 ((     GPIO_TypeDef *)     GPIO1_BASE)\r
+#define GPIO2                 ((     GPIO_TypeDef *)     GPIO2_BASE)\r
+#define GPIO3                 ((     GPIO_TypeDef *)     GPIO3_BASE)\r
+#define GPIO4                 ((     GPIO_TypeDef *)     GPIO4_BASE)\r
+#define WDT                   ((      WDT_TypeDef *)       WDT_BASE)\r
+#define TIM0                  ((      TIM_TypeDef *)      TIM0_BASE)\r
+#define TIM1                  ((      TIM_TypeDef *)      TIM1_BASE)\r
+#define TIM2                  ((      TIM_TypeDef *)      TIM2_BASE)\r
+#define TIM3                  ((      TIM_TypeDef *)      TIM3_BASE)\r
+#define RIT                   ((      RIT_TypeDef *)       RIT_BASE)\r
+#define UART0                 ((     UART_TypeDef *)     UART0_BASE)\r
+#define UART1                 ((    UART1_TypeDef *)     UART1_BASE)\r
+#define UART2                 ((     UART_TypeDef *)     UART2_BASE)\r
+#define UART3                 ((     UART_TypeDef *)     UART3_BASE)\r
+#define PWM1                  ((      PWM_TypeDef *)      PWM1_BASE)\r
+#define I2C0                  ((      I2C_TypeDef *)      I2C0_BASE)\r
+#define I2C1                  ((      I2C_TypeDef *)      I2C1_BASE)\r
+#define I2C2                  ((      I2C_TypeDef *)      I2C2_BASE)\r
+#define I2S                   ((      I2S_TypeDef *)       I2S_BASE)\r
+#define SPI                   ((      SPI_TypeDef *)       SPI_BASE)\r
+#define RTC                   ((      RTC_TypeDef *)       RTC_BASE)\r
+#define GPIOINT               ((  GPIOINT_TypeDef *)   GPIOINT_BASE)\r
+#define PINCON                ((   PINCON_TypeDef *)    PINCON_BASE)\r
+#define SSP0                  ((      SSP_TypeDef *)      SSP0_BASE)\r
+#define SSP1                  ((      SSP_TypeDef *)      SSP1_BASE)\r
+#define ADC                   ((      ADC_TypeDef *)       ADC_BASE)\r
+#define DAC                   ((      DAC_TypeDef *)       DAC_BASE)\r
+#define CANAF_RAM             ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)\r
+#define CANAF                 ((    CANAF_TypeDef *)     CANAF_BASE)\r
+#define CANCR                 ((    CANCR_TypeDef *)     CANCR_BASE)\r
+#define CAN1                  ((      CAN_TypeDef *)      CAN1_BASE)\r
+#define CAN2                  ((      CAN_TypeDef *)      CAN2_BASE)\r
+#define MCPWM                 ((    MCPWM_TypeDef *)     MCPWM_BASE)\r
+#define QEI                   ((      QEI_TypeDef *)       QEI_BASE)\r
+#define EMAC                  ((     EMAC_TypeDef *)      EMAC_BASE)\r
+#define GPDMA                 ((    GPDMA_TypeDef *)     GPDMA_BASE)\r
+#define GPDMACH0              ((  GPDMACH_TypeDef *)  GPDMACH0_BASE)\r
+#define GPDMACH1              ((  GPDMACH_TypeDef *)  GPDMACH1_BASE)\r
+#define GPDMACH2              ((  GPDMACH_TypeDef *)  GPDMACH2_BASE)\r
+#define GPDMACH3              ((  GPDMACH_TypeDef *)  GPDMACH3_BASE)\r
+#define GPDMACH4              ((  GPDMACH_TypeDef *)  GPDMACH4_BASE)\r
+#define GPDMACH5              ((  GPDMACH_TypeDef *)  GPDMACH5_BASE)\r
+#define GPDMACH6              ((  GPDMACH_TypeDef *)  GPDMACH6_BASE)\r
+#define GPDMACH7              ((  GPDMACH_TypeDef *)  GPDMACH7_BASE)\r
+#define USB                   ((      USB_TypeDef *)       USB_BASE)\r
+\r
+#endif  // __LPC17xx_H__\r
+\r
+\r
+#endif\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/USB_CDC.c b/Demo/CORTEX_LPC1768_IAR/LPCUSB/USB_CDC.c
new file mode 100644 (file)
index 0000000..f27542d
--- /dev/null
@@ -0,0 +1,437 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+/*\r
+       Minimal implementation of a USB serial port, using the CDC class.\r
+       This example application simply echoes everything it receives right back\r
+       to the host.\r
+\r
+       Windows:\r
+       Extract the usbser.sys file from .cab file in C:\WINDOWS\Driver Cache\i386\r
+       and store it somewhere (C:\temp is a good place) along with the usbser.inf\r
+       file. Then plug in the LPC176x and direct windows to the usbser driver.\r
+       Windows then creates an extra COMx port that you can open in a terminal\r
+       program, like hyperterminal. [Note for FreeRTOS users - the required .inf\r
+       file is included in the project directory.]\r
+\r
+       Linux:\r
+       The device should be recognised automatically by the cdc_acm driver,\r
+       which creates a /dev/ttyACMx device file that acts just like a regular\r
+       serial port.\r
+\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+#include "usbapi.h"\r
+#include "usbdebug.h"\r
+#include "usbstruct.h"\r
+\r
+#include "LPC17xx.h"\r
+\r
+#define usbMAX_SEND_BLOCK              ( 20 / portTICK_RATE_MS )\r
+#define usbBUFFER_LEN                  ( 20 )\r
+\r
+#define INCREMENT_ECHO_BY 1\r
+#define BAUD_RATE      115200\r
+\r
+#define INT_IN_EP              0x81\r
+#define BULK_OUT_EP            0x05\r
+#define BULK_IN_EP             0x82\r
+\r
+#define MAX_PACKET_SIZE        64\r
+\r
+#define LE_WORD(x)             ((x)&0xFF),((x)>>8)\r
+\r
+// CDC definitions\r
+#define CS_INTERFACE                   0x24\r
+#define CS_ENDPOINT                            0x25\r
+\r
+#define        SET_LINE_CODING                 0x20\r
+#define        GET_LINE_CODING                 0x21\r
+#define        SET_CONTROL_LINE_STATE  0x22\r
+\r
+// data structure for GET_LINE_CODING / SET_LINE_CODING class requests\r
+typedef struct {\r
+       unsigned long           dwDTERate;\r
+       unsigned char           bCharFormat;\r
+       unsigned char           bParityType;\r
+       unsigned char           bDataBits;\r
+} TLineCoding;\r
+\r
+static TLineCoding LineCoding = {115200, 0, 0, 8};\r
+static unsigned char abBulkBuf[64];\r
+static unsigned char abClassReqData[8];\r
+\r
+static xQueueHandle xRxedChars = NULL, xCharsForTx = NULL;\r
+\r
+// forward declaration of interrupt handler\r
+void USBIntHandler(void);\r
+\r
+static const unsigned char abDescriptors[] = {\r
+\r
+// device descriptor\r
+       0x12,\r
+       DESC_DEVICE,\r
+       LE_WORD(0x0101),                        // bcdUSB\r
+       0x02,                                           // bDeviceClass\r
+       0x00,                                           // bDeviceSubClass\r
+       0x00,                                           // bDeviceProtocol\r
+       MAX_PACKET_SIZE0,                       // bMaxPacketSize\r
+       LE_WORD(0xFFFF),                        // idVendor\r
+       LE_WORD(0x0005),                        // idProduct\r
+       LE_WORD(0x0100),                        // bcdDevice\r
+       0x01,                                           // iManufacturer\r
+       0x02,                                           // iProduct\r
+       0x03,                                           // iSerialNumber\r
+       0x01,                                           // bNumConfigurations\r
+\r
+// configuration descriptor\r
+       0x09,\r
+       DESC_CONFIGURATION,\r
+       LE_WORD(67),                            // wTotalLength\r
+       0x02,                                           // bNumInterfaces\r
+       0x01,                                           // bConfigurationValue\r
+       0x00,                                           // iConfiguration\r
+       0xC0,                                           // bmAttributes\r
+       0x32,                                           // bMaxPower\r
+// control class interface\r
+       0x09,\r
+       DESC_INTERFACE,\r
+       0x00,                                           // bInterfaceNumber\r
+       0x00,                                           // bAlternateSetting\r
+       0x01,                                           // bNumEndPoints\r
+       0x02,                                           // bInterfaceClass\r
+       0x02,                                           // bInterfaceSubClass\r
+       0x01,                                           // bInterfaceProtocol, linux requires value of 1 for the cdc_acm module\r
+       0x00,                                           // iInterface\r
+// header functional descriptor\r
+       0x05,\r
+       CS_INTERFACE,\r
+       0x00,\r
+       LE_WORD(0x0110),\r
+// call management functional descriptor\r
+       0x05,\r
+       CS_INTERFACE,\r
+       0x01,\r
+       0x01,                                           // bmCapabilities = device handles call management\r
+       0x01,                                           // bDataInterface\r
+// ACM functional descriptor\r
+       0x04,\r
+       CS_INTERFACE,\r
+       0x02,\r
+       0x02,                                           // bmCapabilities\r
+// union functional descriptor\r
+       0x05,\r
+       CS_INTERFACE,\r
+       0x06,\r
+       0x00,                                           // bMasterInterface\r
+       0x01,                                           // bSlaveInterface0\r
+// notification EP\r
+       0x07,\r
+       DESC_ENDPOINT,\r
+       INT_IN_EP,                                      // bEndpointAddress\r
+       0x03,                                           // bmAttributes = intr\r
+       LE_WORD(8),                                     // wMaxPacketSize\r
+       0x0A,                                           // bInterval\r
+// data class interface descriptor\r
+       0x09,\r
+       DESC_INTERFACE,\r
+       0x01,                                           // bInterfaceNumber\r
+       0x00,                                           // bAlternateSetting\r
+       0x02,                                           // bNumEndPoints\r
+       0x0A,                                           // bInterfaceClass = data\r
+       0x00,                                           // bInterfaceSubClass\r
+       0x00,                                           // bInterfaceProtocol\r
+       0x00,                                           // iInterface\r
+// data EP OUT\r
+       0x07,\r
+       DESC_ENDPOINT,\r
+       BULK_OUT_EP,                            // bEndpointAddress\r
+       0x02,                                           // bmAttributes = bulk\r
+       LE_WORD(MAX_PACKET_SIZE),       // wMaxPacketSize\r
+       0x00,                                           // bInterval\r
+// data EP in\r
+       0x07,\r
+       DESC_ENDPOINT,\r
+       BULK_IN_EP,                                     // bEndpointAddress\r
+       0x02,                                           // bmAttributes = bulk\r
+       LE_WORD(MAX_PACKET_SIZE),       // wMaxPacketSize\r
+       0x00,                                           // bInterval\r
+       \r
+       // string descriptors\r
+       0x04,\r
+       DESC_STRING,\r
+       LE_WORD(0x0409),\r
+\r
+       0x0E,\r
+       DESC_STRING,\r
+       'L', 0, 'P', 0, 'C', 0, 'U', 0, 'S', 0, 'B', 0,\r
+\r
+       0x14,\r
+       DESC_STRING,\r
+       'U', 0, 'S', 0, 'B', 0, 'S', 0, 'e', 0, 'r', 0, 'i', 0, 'a', 0, 'l', 0,\r
+\r
+       0x12,\r
+       DESC_STRING,\r
+       'D', 0, 'E', 0, 'A', 0, 'D', 0, 'C', 0, '0', 0, 'D', 0, 'E', 0,\r
+\r
+// terminating zero\r
+       0\r
+};\r
+\r
+\r
+/**\r
+       Local function to handle incoming bulk data\r
+               \r
+       @param [in] bEP\r
+       @param [in] bEPStatus\r
+ */\r
+static void BulkOut(unsigned char bEP, unsigned char bEPStatus)\r
+{\r
+       int i, iLen;\r
+       long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       ( void ) bEPStatus;\r
+       \r
+       // get data from USB into intermediate buffer\r
+       iLen = USBHwEPRead(bEP, abBulkBuf, sizeof(abBulkBuf));\r
+       for (i = 0; i < iLen; i++) {\r
+               // put into queue\r
+               xQueueSendFromISR( xRxedChars, &( abBulkBuf[ i ] ), &lHigherPriorityTaskWoken );\r
+       }\r
+       \r
+       portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+/**\r
+       Local function to handle outgoing bulk data\r
+               \r
+       @param [in] bEP\r
+       @param [in] bEPStatus\r
+ */\r
+static void BulkIn(unsigned char bEP, unsigned char bEPStatus)\r
+{\r
+       int i, iLen;\r
+       long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       ( void ) bEPStatus;\r
+       \r
+       if (uxQueueMessagesWaitingFromISR( xCharsForTx ) == 0) {\r
+               // no more data, disable further NAK interrupts until next USB frame\r
+               USBHwNakIntEnable(0);\r
+               return;\r
+       }\r
+\r
+       // get bytes from transmit FIFO into intermediate buffer\r
+       for (i = 0; i < MAX_PACKET_SIZE; i++) {\r
+               if( xQueueReceiveFromISR( xCharsForTx, ( &abBulkBuf[i] ), &lHigherPriorityTaskWoken ) != pdPASS )\r
+               {\r
+                       break;\r
+               }\r
+       }\r
+       iLen = i;\r
+       \r
+       // send over USB\r
+       if (iLen > 0) {\r
+               USBHwEPWrite(bEP, abBulkBuf, iLen);\r
+       }\r
+       \r
+       portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+\r
+/**\r
+       Local function to handle the USB-CDC class requests\r
+               \r
+       @param [in] pSetup\r
+       @param [out] piLen\r
+       @param [out] ppbData\r
+ */\r
+static BOOL HandleClassRequest(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       switch (pSetup->bRequest) {\r
+\r
+       // set line coding\r
+       case SET_LINE_CODING:\r
+DBG("SET_LINE_CODING\n");\r
+               memcpy((unsigned char *)&LineCoding, *ppbData, 7);\r
+               *piLen = 7;\r
+DBG("dwDTERate=%u, bCharFormat=%u, bParityType=%u, bDataBits=%u\n",\r
+       LineCoding.dwDTERate,\r
+       LineCoding.bCharFormat,\r
+       LineCoding.bParityType,\r
+       LineCoding.bDataBits);\r
+               break;\r
+\r
+       // get line coding\r
+       case GET_LINE_CODING:\r
+DBG("GET_LINE_CODING\n");\r
+               *ppbData = (unsigned char *)&LineCoding;\r
+               *piLen = 7;\r
+               break;\r
+\r
+       // set control line state\r
+       case SET_CONTROL_LINE_STATE:\r
+               // bit0 = DTR, bit = RTS\r
+DBG("SET_CONTROL_LINE_STATE %X\n", pSetup->wValue);\r
+               break;\r
+\r
+       default:\r
+               return FALSE;\r
+       }\r
+       return TRUE;\r
+}\r
+\r
+\r
+/**\r
+       Writes one character to VCOM port\r
+       \r
+       @param [in] c character to write\r
+       @returns character written, or EOF if character could not be written\r
+ */\r
+int VCOM_putchar(int c)\r
+{\r
+char cc = ( char ) c;\r
+\r
+       if( xQueueSend( xCharsForTx, &cc, usbMAX_SEND_BLOCK ) == pdPASS )\r
+       {\r
+               return c;\r
+       }\r
+       else\r
+       {\r
+               return EOF;\r
+       }\r
+}\r
+\r
+\r
+/**\r
+       Reads one character from VCOM port\r
+       \r
+       @returns character read, or EOF if character could not be read\r
+ */\r
+int VCOM_getchar(void)\r
+{\r
+       unsigned char c;\r
+       \r
+       /* Block the task until a character is available. */\r
+       xQueueReceive( xRxedChars, &c, portMAX_DELAY );\r
+       return c;\r
+}\r
+\r
+\r
+/**\r
+       Interrupt handler\r
+       \r
+       Simply calls the USB ISR\r
+ */\r
+//void USBIntHandler(void)\r
+void USB_IRQHandler(void)\r
+{\r
+       USBHwISR();\r
+}\r
+\r
+\r
+static void USBFrameHandler(unsigned short wFrame)\r
+{\r
+       ( void ) wFrame;\r
+       \r
+       if( uxQueueMessagesWaitingFromISR( xCharsForTx ) > 0 )\r
+       {\r
+               // data available, enable NAK interrupt on bulk in\r
+               USBHwNakIntEnable(INACK_BI);\r
+       }\r
+}\r
+\r
+void vUSBTask( void *pvParameters )\r
+{\r
+       int c;\r
+       \r
+       /* Just to prevent compiler warnings about the unused parameter. */\r
+       ( void ) pvParameters;\r
+       DBG("Initialising USB stack\n");\r
+\r
+       xRxedChars = xQueueCreate( usbBUFFER_LEN, sizeof( char ) );\r
+       xCharsForTx = xQueueCreate( usbBUFFER_LEN, sizeof( char ) );\r
+\r
+       if( ( xRxedChars == NULL ) || ( xCharsForTx == NULL ) )\r
+       {\r
+               /* Not enough heap available to create the buffer queues, can't do\r
+               anything so just delete ourselves. */\r
+               vTaskDelete( NULL );\r
+       }\r
+       \r
+       \r
+       // initialise stack\r
+       USBInit();\r
+\r
+       // register descriptors\r
+       USBRegisterDescriptors(abDescriptors);\r
+\r
+       // register class request handler\r
+       USBRegisterRequestHandler(REQTYPE_TYPE_CLASS, HandleClassRequest, abClassReqData);\r
+\r
+       // register endpoint handlers\r
+       USBHwRegisterEPIntHandler(INT_IN_EP, NULL);\r
+       USBHwRegisterEPIntHandler(BULK_IN_EP, BulkIn);\r
+       USBHwRegisterEPIntHandler(BULK_OUT_EP, BulkOut);\r
+       \r
+       // register frame handler\r
+       USBHwRegisterFrameHandler(USBFrameHandler);\r
+\r
+       // enable bulk-in interrupts on NAKs\r
+       USBHwNakIntEnable(INACK_BI);\r
+\r
+       DBG("Starting USB communication\n");\r
+\r
+       NVIC_SetPriority( USB_IRQn, configUSB_INTERRUPT_PRIORITY );\r
+       NVIC_EnableIRQ( USB_IRQn );\r
+               \r
+       // connect to bus\r
+               \r
+       DBG("Connecting to USB bus\n");\r
+       USBHwConnect(TRUE);\r
+\r
+       // echo any character received (do USB stuff in interrupt)\r
+       for( ;; )\r
+       {\r
+               c = VCOM_getchar();\r
+               if (c != EOF)\r
+               {\r
+                       // Echo character back with INCREMENT_ECHO_BY offset, so for example if\r
+                       // INCREMENT_ECHO_BY is 1 and 'A' is received, 'B' will be echoed back.\r
+                       VCOM_putchar(c + INCREMENT_ECHO_BY );\r
+               }\r
+       }\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/type.h b/Demo/CORTEX_LPC1768_IAR/LPCUSB/type.h
new file mode 100644 (file)
index 0000000..89d3685
--- /dev/null
@@ -0,0 +1,38 @@
+/*****************************************************************************\r
+ *   type.h:  Type definition Header file for NXP LPC17xx Family \r
+ *   Microprocessors\r
+ *\r
+ *   Copyright(C) 2008, NXP Semiconductor\r
+ *   All rights reserved.\r
+ *\r
+ *   History\r
+ *   2008.08.21  ver 1.00    Prelimnary version, first Release\r
+ *\r
+******************************************************************************/\r
+#ifndef __TYPE_H__\r
+#define __TYPE_H__\r
+\r
+#ifndef NULL\r
+#define NULL    ((void *)0)\r
+#endif\r
+\r
+#ifndef FALSE\r
+#define FALSE   (0)\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE    (1)\r
+#endif\r
+\r
+typedef unsigned char  BYTE;\r
+typedef unsigned short WORD;\r
+typedef unsigned long  DWORD;\r
+typedef unsigned int   BOOL;\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+\r
+/* Pointer to Function returning Void (any number of parameters) */\r
+typedef void (*PFV)();\r
+\r
+#endif  /* __TYPE_H__ */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbapi.h b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbapi.h
new file mode 100644 (file)
index 0000000..050f0d9
--- /dev/null
@@ -0,0 +1,118 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, \r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+/**\r
+       @file\r
+*/\r
+\r
+#include "usbstruct.h"         // for TSetupPacket\r
+\r
+/*************************************************************************\r
+       USB configuration\r
+**************************************************************************/\r
+\r
+#define MAX_PACKET_SIZE0       64              /**< maximum packet size for EP 0 */\r
+\r
+/*************************************************************************\r
+       USB hardware interface\r
+**************************************************************************/\r
+\r
+// endpoint status sent through callback\r
+#define EP_STATUS_DATA         (1<<0)          /**< EP has data */\r
+#define EP_STATUS_STALLED      (1<<1)          /**< EP is stalled */\r
+#define EP_STATUS_SETUP                (1<<2)          /**< EP received setup packet */\r
+#define EP_STATUS_ERROR                (1<<3)          /**< EP data was overwritten by setup packet */\r
+#define EP_STATUS_NACKED       (1<<4)          /**< EP sent NAK */\r
+\r
+// device status sent through callback\r
+#define DEV_STATUS_CONNECT             (1<<0)  /**< device just got connected */\r
+#define DEV_STATUS_SUSPEND             (1<<2)  /**< device entered suspend state */\r
+#define DEV_STATUS_RESET               (1<<4)  /**< device just got reset */\r
+\r
+// interrupt bits for NACK events in USBHwNakIntEnable\r
+// (these bits conveniently coincide with the LPC176x USB controller bit)\r
+#define INACK_CI               (1<<1)                  /**< interrupt on NACK for control in */\r
+#define INACK_CO               (1<<2)                  /**< interrupt on NACK for control out */\r
+#define INACK_II               (1<<3)                  /**< interrupt on NACK for interrupt in */\r
+#define INACK_IO               (1<<4)                  /**< interrupt on NACK for interrupt out */\r
+#define INACK_BI               (1<<5)                  /**< interrupt on NACK for bulk in */\r
+#define INACK_BO               (1<<6)                  /**< interrupt on NACK for bulk out */\r
+\r
+BOOL USBHwInit                 (void);\r
+void USBHwISR                  (void);\r
+\r
+void USBHwNakIntEnable (unsigned char bIntBits);\r
+\r
+void USBHwConnect              (BOOL fConnect);\r
+\r
+void USBHwSetAddress   (unsigned char bAddr);\r
+void USBHwConfigDevice (BOOL fConfigured);\r
+\r
+// endpoint operations\r
+void USBHwEPConfig             (unsigned char bEP, unsigned short wMaxPacketSize);\r
+int  USBHwEPRead               (unsigned char bEP, unsigned char *pbBuf, int iMaxLen);\r
+int     USBHwEPWrite           (unsigned char bEP, unsigned char *pbBuf, int iLen);\r
+void USBHwEPStall              (unsigned char bEP, BOOL fStall);\r
+unsigned char   USBHwEPGetStatus       (unsigned char bEP);\r
+\r
+/** Endpoint interrupt handler callback */\r
+typedef void (TFnEPIntHandler) (unsigned char bEP, unsigned char bEPStatus);\r
+void USBHwRegisterEPIntHandler (unsigned char bEP, TFnEPIntHandler *pfnHandler);\r
+\r
+/** Device status handler callback */\r
+typedef void (TFnDevIntHandler)        (unsigned char bDevStatus);\r
+void USBHwRegisterDevIntHandler        (TFnDevIntHandler *pfnHandler);\r
+\r
+/** Frame event handler callback */\r
+typedef void (TFnFrameHandler)(unsigned short wFrame);\r
+void USBHwRegisterFrameHandler(TFnFrameHandler *pfnHandler);\r
+\r
+\r
+/*************************************************************************\r
+       USB application interface\r
+**************************************************************************/\r
+\r
+// initialise the complete stack, including HW\r
+BOOL USBInit(void);\r
+\r
+/** Request handler callback (standard, vendor, class) */\r
+typedef BOOL (TFnHandleRequest)(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData);\r
+void USBRegisterRequestHandler(int iType, TFnHandleRequest *pfnHandler, unsigned char *pbDataStore);\r
+void USBRegisterCustomReqHandler(TFnHandleRequest *pfnHandler);\r
+\r
+/** Descriptor handler callback */\r
+typedef BOOL (TFnGetDescriptor)(unsigned short wTypeIndex, unsigned short wLangID, int *piLen, unsigned char **ppbData);\r
+\r
+/** Default standard request handler */\r
+BOOL USBHandleStandardRequest(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData);\r
+\r
+/** Default EP0 handler */\r
+void USBHandleControlTransfer(unsigned char bEP, unsigned char bEPStat);\r
+\r
+/** Descriptor handling */\r
+void USBRegisterDescriptors(const unsigned char *pabDescriptors);\r
+BOOL USBGetDescriptor(unsigned short wTypeIndex, unsigned short wLangID, int *piLen, unsigned char **ppbData);\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbcontrol.c b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbcontrol.c
new file mode 100644 (file)
index 0000000..d78e553
--- /dev/null
@@ -0,0 +1,246 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/** @file\r
+       Control transfer handler.\r
+       \r
+       This module handles control transfers and is normally installed on the\r
+       endpoint 0 callback.\r
+       \r
+       Control transfers can be of the following type:\r
+       0 Standard;\r
+       1 Class;\r
+       2 Vendor;\r
+       3 Reserved.\r
+\r
+       A callback can be installed for each of these control transfers using\r
+       USBRegisterRequestHandler.\r
+       When an OUT request arrives, data is collected in the data store provided\r
+       with the USBRegisterRequestHandler call. When the transfer is done, the\r
+       callback is called.\r
+       When an IN request arrives, the callback is called immediately to either\r
+       put the control transfer data in the data store, or to get a pointer to\r
+       control transfer data. The data is then packetised and sent to the host.\r
+*/\r
+\r
+#include "usbdebug.h"\r
+\r
+#include "usbstruct.h"\r
+#include "usbapi.h"\r
+\r
+\r
+\r
+#define        MAX_CONTROL_SIZE        128     /**< maximum total size of control transfer data */\r
+#define        MAX_REQ_HANDLERS        4       /**< standard, class, vendor, reserved */\r
+\r
+static TSetupPacket            Setup;  /**< setup packet */\r
+\r
+static unsigned char                           *pbData;        /**< pointer to data buffer */\r
+static int                             iResidue;       /**< remaining bytes in buffer */\r
+static int                             iLen;           /**< total length of control transfer */\r
+\r
+/** Array of installed request handler callbacks */\r
+static TFnHandleRequest *apfnReqHandlers[4] = {NULL, NULL, NULL, NULL};\r
+/** Array of installed request data pointers */\r
+static unsigned char                           *apbDataStore[4] = {NULL, NULL, NULL, NULL};\r
+\r
+/**\r
+       Local function to handle a request by calling one of the installed\r
+       request handlers.\r
+               \r
+       In case of data going from host to device, the data is at *ppbData.\r
+       In case of data going from device to host, the handler can either\r
+       choose to write its data at *ppbData or update the data pointer.\r
+               \r
+       @param [in]             pSetup          The setup packet\r
+       @param [in,out] *piLen          Pointer to data length\r
+       @param [in,out] ppbData         Data buffer.\r
+\r
+       @return TRUE if the request was handles successfully\r
+ */\r
+static BOOL _HandleRequest(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       TFnHandleRequest *pfnHandler;\r
+       int iType;\r
+       \r
+       iType = REQTYPE_GET_TYPE(pSetup->bmRequestType);\r
+       pfnHandler = apfnReqHandlers[iType];\r
+       if (pfnHandler == NULL) {\r
+               DBG("No handler for reqtype %d\n", iType);\r
+               return FALSE;\r
+       }\r
+\r
+       return pfnHandler(pSetup, piLen, ppbData);\r
+}\r
+\r
+\r
+/**\r
+       Local function to stall the control endpoint\r
+       \r
+       @param [in]     bEPStat Endpoint status\r
+ */\r
+static void StallControlPipe(unsigned char bEPStat)\r
+{\r
+       unsigned char   *pb;\r
+       int     i;\r
+\r
+       USBHwEPStall(0x80, TRUE);\r
+\r
+// dump setup packet\r
+       DBG("STALL on [");\r
+       pb = (unsigned char *)&Setup;\r
+       for (i = 0; i < 8; i++) {\r
+               DBG(" %02x", *pb++);\r
+       }\r
+       DBG("] stat=%x\n", bEPStat);\r
+}\r
+\r
+\r
+/**\r
+       Sends next chunk of data (possibly 0 bytes) to host\r
+ */\r
+static void DataIn(void)\r
+{\r
+       int iChunk;\r
+\r
+       if( MAX_PACKET_SIZE0 < iResidue )\r
+       {\r
+               iChunk = MAX_PACKET_SIZE0;\r
+       }\r
+       else\r
+       {\r
+               iChunk = iResidue;\r
+       }\r
+\r
+       USBHwEPWrite(0x80, pbData, iChunk);\r
+       pbData += iChunk;\r
+       iResidue -= iChunk;\r
+}\r
+\r
+\r
+/**\r
+ *     Handles IN/OUT transfers on EP0\r
+ *\r
+ *     @param [in]     bEP             Endpoint address\r
+ *     @param [in]     bEPStat Endpoint status\r
+ */\r
+void USBHandleControlTransfer(unsigned char bEP, unsigned char bEPStat)\r
+{\r
+       int iChunk, iType;\r
+\r
+       if (bEP == 0x00) {\r
+               // OUT transfer\r
+               if (bEPStat & EP_STATUS_SETUP) {\r
+                       // setup packet, reset request message state machine\r
+                       USBHwEPRead(0x00, (unsigned char *)&Setup, sizeof(Setup));\r
+                       DBG("S%x", Setup.bRequest);\r
+\r
+                       // defaults for data pointer and residue\r
+                       iType = REQTYPE_GET_TYPE(Setup.bmRequestType);\r
+                       pbData = apbDataStore[iType];\r
+                       iResidue = Setup.wLength;\r
+                       iLen = Setup.wLength;\r
+\r
+                       if ((Setup.wLength == 0) ||\r
+                               (REQTYPE_GET_DIR(Setup.bmRequestType) == REQTYPE_DIR_TO_HOST)) {\r
+                               // ask installed handler to process request\r
+                               if (!_HandleRequest(&Setup, &iLen, &pbData)) {\r
+                                       DBG("_HandleRequest1 failed\n");\r
+                                       StallControlPipe(bEPStat);\r
+                                       return;\r
+                               }\r
+                               // send smallest of requested and offered length\r
+                               if( iLen < Setup.wLength )\r
+                               {\r
+                                       iResidue = iLen;\r
+                               }\r
+                               else\r
+                               {\r
+                                       iResidue = Setup.wLength;\r
+                               }\r
+\r
+                               // send first part (possibly a zero-length status message)\r
+                               DataIn();\r
+                       }\r
+               }\r
+               else {          \r
+                       if (iResidue > 0) {\r
+                               // store data\r
+                               iChunk = USBHwEPRead(0x00, pbData, iResidue);\r
+                               if (iChunk < 0) {\r
+                                       StallControlPipe(bEPStat);\r
+                                       return;\r
+                               }\r
+                               pbData += iChunk;\r
+                               iResidue -= iChunk;\r
+                               if (iResidue == 0) {\r
+                                       // received all, send data to handler\r
+                                       iType = REQTYPE_GET_TYPE(Setup.bmRequestType);\r
+                                       pbData = apbDataStore[iType];\r
+                                       if (!_HandleRequest(&Setup, &iLen, &pbData)) {\r
+                                               DBG("_HandleRequest2 failed\n");\r
+                                               StallControlPipe(bEPStat);\r
+                                               return;\r
+                                       }\r
+                                       // send status to host\r
+                                       DataIn();\r
+                               }\r
+                       }\r
+                       else {\r
+                               // absorb zero-length status message\r
+                               iChunk = USBHwEPRead(0x00, NULL, 0);\r
+                               DBG(iChunk > 0 ? "?" : "");\r
+                       }\r
+               }\r
+       }\r
+       else if (bEP == 0x80) {\r
+               // IN transfer\r
+               // send more data if available (possibly a 0-length packet)\r
+               DataIn();\r
+       }\r
+       else {\r
+               ASSERT(FALSE);\r
+       }\r
+}\r
+\r
+\r
+/**\r
+       Registers a callback for handling requests\r
+               \r
+       @param [in]     iType                   Type of request, e.g. REQTYPE_TYPE_STANDARD\r
+       @param [in]     *pfnHandler             Callback function pointer\r
+       @param [in]     *pbDataStore    Data storage area for this type of request\r
+ */\r
+void USBRegisterRequestHandler(int iType, TFnHandleRequest *pfnHandler, unsigned char *pbDataStore)\r
+{\r
+       ASSERT(iType >= 0);\r
+       ASSERT(iType < 4);\r
+       apfnReqHandlers[iType] = pfnHandler;\r
+       apbDataStore[iType] = pbDataStore;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbdebug.h b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbdebug.h
new file mode 100644 (file)
index 0000000..490f0a7
--- /dev/null
@@ -0,0 +1,41 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+// CodeRed - comment out this printf, as will use real one from stdio.h\r
+// to implement output via semihosting\r
+\r
+//int printf(const char *format, ...);\r
+# include <stdio.h>\r
+\r
+#ifdef _DEBUG\r
+#define DBG    printf\r
+#define ASSERT(x)      if(!(x)){DBG("\nAssertion '%s' failed in %s:%s#%d!\n",#x,__FILE__,__FUNCTION__,__LINE__);while(1);}\r
+#else\r
+#define DBG(...)\r
+#define ASSERT(x)\r
+#endif\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c
new file mode 100644 (file)
index 0000000..3105685
--- /dev/null
@@ -0,0 +1,521 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers\r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/** @file\r
+       USB hardware layer\r
+ */\r
+\r
+\r
+#include "usbdebug.h"\r
+#include "usbhw_lpc.h"\r
+#include "usbapi.h"\r
+\r
+/** Installed device interrupt handler */\r
+static TFnDevIntHandler *_pfnDevIntHandler = NULL;\r
+/** Installed endpoint interrupt handlers */\r
+static TFnEPIntHandler *_apfnEPIntHandlers[16];\r
+/** Installed frame interrupt handlers */\r
+static TFnFrameHandler *_pfnFrameHandler = NULL;\r
+\r
+/** convert from endpoint address to endpoint index */\r
+#define EP2IDX(bEP)    ((((bEP)&0xF)<<1)|(((bEP)&0x80)>>7))\r
+/** convert from endpoint index to endpoint address */\r
+#define IDX2EP(idx)    ((((idx)<<7)&0x80)|(((idx)>>1)&0xF))\r
+\r
+\r
+\r
+/**\r
+       Local function to wait for a device interrupt (and clear it)\r
+\r
+       @param [in]     dwIntr          Bitmask of interrupts to wait for\r
+ */\r
+static void Wait4DevInt(unsigned long dwIntr)\r
+{\r
+       // wait for specific interrupt\r
+       while ((USB->USBDevIntSt & dwIntr) != dwIntr);\r
+       // clear the interrupt bits\r
+       USB->USBDevIntClr = dwIntr;\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command to the USB protocol engine\r
+\r
+       @param [in]     bCmd            Command to send\r
+ */\r
+static void USBHwCmd(unsigned char bCmd)\r
+{\r
+       // clear CDFULL/CCEMTY\r
+       USB->USBDevIntClr = CDFULL | CCEMTY;\r
+       // write command code\r
+       USB->USBCmdCode = 0x00000500 | (bCmd << 16);\r
+       Wait4DevInt(CCEMTY);\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command + data to the USB protocol engine\r
+\r
+       @param [in]     bCmd            Command to send\r
+       @param [in]     bData           Data to send\r
+ */\r
+static void USBHwCmdWrite(unsigned char bCmd, unsigned short bData)\r
+{\r
+       // write command code\r
+       USBHwCmd(bCmd);\r
+\r
+       // write command data\r
+       USB->USBCmdCode = 0x00000100 | (bData << 16);\r
+       Wait4DevInt(CCEMTY);\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command to the USB protocol engine and read data\r
+\r
+       @param [in]     bCmd            Command to send\r
+\r
+       @return the data\r
+ */\r
+static unsigned char USBHwCmdRead(unsigned char bCmd)\r
+{\r
+       // write command code\r
+       USBHwCmd(bCmd);\r
+\r
+       // get data\r
+       USB->USBCmdCode = 0x00000200 | (bCmd << 16);\r
+       Wait4DevInt(CDFULL);\r
+       return USB->USBCmdData;\r
+}\r
+\r
+\r
+/**\r
+       'Realizes' an endpoint, meaning that buffer space is reserved for\r
+       it. An endpoint needs to be realised before it can be used.\r
+\r
+       From experiments, it appears that a USB reset causes USBReEP to\r
+       re-initialise to 3 (= just the control endpoints).\r
+       However, a USB bus reset does not disturb the USBMaxPSize settings.\r
+\r
+       @param [in]     idx                     Endpoint index\r
+       @param [in] wMaxPSize   Maximum packet size for this endpoint\r
+ */\r
+static void USBHwEPRealize(int idx, unsigned short wMaxPSize)\r
+{\r
+       USB->USBReEP |= (1 << idx);\r
+       USB->USBEpInd = idx;\r
+       USB->USBMaxPSize = wMaxPSize;\r
+       Wait4DevInt(EP_RLZED);\r
+}\r
+\r
+\r
+/**\r
+       Enables or disables an endpoint\r
+\r
+       @param [in]     idx             Endpoint index\r
+       @param [in]     fEnable TRUE to enable, FALSE to disable\r
+ */\r
+static void USBHwEPEnable(int idx, BOOL fEnable)\r
+{\r
+       USBHwCmdWrite(CMD_EP_SET_STATUS | idx, fEnable ? 0 : EP_DA);\r
+}\r
+\r
+\r
+/**\r
+       Configures an endpoint and enables it\r
+\r
+       @param [in]     bEP                             Endpoint number\r
+       @param [in]     wMaxPacketSize  Maximum packet size for this EP\r
+ */\r
+void USBHwEPConfig(unsigned char bEP, unsigned short wMaxPacketSize)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // realise EP\r
+       USBHwEPRealize(idx, wMaxPacketSize);\r
+\r
+       // enable EP\r
+       USBHwEPEnable(idx, TRUE);\r
+}\r
+\r
+\r
+/**\r
+       Registers an endpoint event callback\r
+\r
+       @param [in]     bEP                             Endpoint number\r
+       @param [in]     pfnHandler              Callback function\r
+ */\r
+void USBHwRegisterEPIntHandler(unsigned char bEP, TFnEPIntHandler *pfnHandler)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       ASSERT(idx<32);\r
+\r
+       /* add handler to list of EP handlers */\r
+       _apfnEPIntHandlers[idx / 2] = pfnHandler;\r
+\r
+       /* enable EP interrupt */\r
+       USB->USBEpIntEn |= (1 << idx);\r
+       USB->USBDevIntEn |= EP_SLOW;\r
+\r
+       DBG("Registered handler for EP 0x%x\n", bEP);\r
+}\r
+\r
+\r
+/**\r
+       Registers an device status callback\r
+\r
+       @param [in]     pfnHandler      Callback function\r
+ */\r
+void USBHwRegisterDevIntHandler(TFnDevIntHandler *pfnHandler)\r
+{\r
+       _pfnDevIntHandler = pfnHandler;\r
+\r
+       // enable device interrupt\r
+       USB->USBDevIntEn |= DEV_STAT;\r
+\r
+       DBG("Registered handler for device status\n");\r
+}\r
+\r
+\r
+/**\r
+       Registers the frame callback\r
+\r
+       @param [in]     pfnHandler      Callback function\r
+ */\r
+void USBHwRegisterFrameHandler(TFnFrameHandler *pfnHandler)\r
+{\r
+       _pfnFrameHandler = pfnHandler;\r
+\r
+       // enable device interrupt\r
+       USB->USBDevIntEn |= FRAME;\r
+\r
+       DBG("Registered handler for frame\n");\r
+}\r
+\r
+\r
+/**\r
+       Sets the USB address.\r
+\r
+       @param [in]     bAddr           Device address to set\r
+ */\r
+void USBHwSetAddress(unsigned char bAddr)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_SET_ADDRESS, DEV_EN | bAddr);\r
+}\r
+\r
+\r
+/**\r
+       Connects or disconnects from the USB bus\r
+\r
+       @param [in]     fConnect        If TRUE, connect, otherwise disconnect\r
+ */\r
+void USBHwConnect(BOOL fConnect)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_STATUS, fConnect ? CON : 0);\r
+}\r
+\r
+\r
+/**\r
+       Enables interrupt on NAK condition\r
+\r
+       For IN endpoints a NAK is generated when the host wants to read data\r
+       from the device, but none is available in the endpoint buffer.\r
+       For OUT endpoints a NAK is generated when the host wants to write data\r
+       to the device, but the endpoint buffer is still full.\r
+\r
+       The endpoint interrupt handlers can distinguish regular (ACK) interrupts\r
+       from NAK interrupt by checking the bits in their bEPStatus argument.\r
+\r
+       @param [in]     bIntBits        Bitmap indicating which NAK interrupts to enable\r
+ */\r
+void USBHwNakIntEnable(unsigned char bIntBits)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_SET_MODE, bIntBits);\r
+}\r
+\r
+\r
+/**\r
+       Gets the status from a specific endpoint.\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @return Endpoint status byte (containing EP_STATUS_xxx bits)\r
+ */\r
+unsigned char  USBHwEPGetStatus(unsigned char bEP)\r
+{\r
+       int idx = EP2IDX(bEP);\r
+\r
+       return USBHwCmdRead(CMD_EP_SELECT | idx);\r
+}\r
+\r
+\r
+/**\r
+       Sets the stalled property of an endpoint\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     fStall  TRUE to stall, FALSE to unstall\r
+ */\r
+void USBHwEPStall(unsigned char bEP, BOOL fStall)\r
+{\r
+       int idx = EP2IDX(bEP);\r
+\r
+       USBHwCmdWrite(CMD_EP_SET_STATUS | idx, fStall ? EP_ST : 0);\r
+}\r
+\r
+\r
+/**\r
+       Writes data to an endpoint buffer\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     pbBuf   Endpoint data\r
+       @param [in]     iLen    Number of bytes to write\r
+\r
+       @return TRUE if the data was successfully written or <0 in case of error.\r
+*/\r
+int USBHwEPWrite(unsigned char bEP, unsigned char *pbBuf, int iLen)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // set write enable for specific endpoint\r
+       USB->USBCtrl = WR_EN | ((bEP & 0xF) << 2);\r
+\r
+       // set packet length\r
+       USB->USBTxPLen = iLen;\r
+\r
+       // write data\r
+       while (USB->USBCtrl & WR_EN) {\r
+               USB->USBTxData = (pbBuf[3] << 24) | (pbBuf[2] << 16) | (pbBuf[1] << 8) | pbBuf[0];\r
+               pbBuf += 4;\r
+       }\r
+\r
+       // select endpoint and validate buffer\r
+       USBHwCmd(CMD_EP_SELECT | idx);\r
+       USBHwCmd(CMD_EP_VALIDATE_BUFFER);\r
+\r
+       return iLen;\r
+}\r
+\r
+\r
+/**\r
+       Reads data from an endpoint buffer\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     pbBuf   Endpoint data\r
+       @param [in]     iMaxLen Maximum number of bytes to read\r
+\r
+       @return the number of bytes available in the EP (possibly more than iMaxLen),\r
+       or <0 in case of error.\r
+ */\r
+int USBHwEPRead(unsigned char bEP, unsigned char *pbBuf, int iMaxLen)\r
+{\r
+       unsigned int i, idx;\r
+       unsigned long   dwData, dwLen;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // set read enable bit for specific endpoint\r
+       USB->USBCtrl = RD_EN | ((bEP & 0xF) << 2);\r
+\r
+       // wait for PKT_RDY\r
+       do {\r
+               dwLen = USB->USBRxPLen;\r
+       } while ((dwLen & PKT_RDY) == 0);\r
+\r
+       // packet valid?\r
+       if ((dwLen & DV) == 0) {\r
+               return -1;\r
+       }\r
+\r
+       // get length\r
+       dwLen &= PKT_LNGTH_MASK;\r
+\r
+       // get data\r
+       dwData = 0;\r
+       for (i = 0; i < dwLen; i++) {\r
+               if ((i % 4) == 0) {\r
+                       dwData = USB->USBRxData;\r
+               }\r
+               if ((pbBuf != NULL) && ((int)i < iMaxLen)) {\r
+                       pbBuf[i] = dwData & 0xFF;\r
+               }\r
+               dwData >>= 8;\r
+       }\r
+\r
+       // make sure RD_EN is clear\r
+       USB->USBCtrl = 0;\r
+\r
+       // select endpoint and clear buffer\r
+       USBHwCmd(CMD_EP_SELECT | idx);\r
+       USBHwCmd(CMD_EP_CLEAR_BUFFER);\r
+\r
+       return dwLen;\r
+}\r
+\r
+\r
+/**\r
+       Sets the 'configured' state.\r
+\r
+       All registered endpoints are 'realised' and enabled, and the\r
+       'configured' bit is set in the device status register.\r
+\r
+       @param [in]     fConfigured     If TRUE, configure device, else unconfigure\r
+ */\r
+void USBHwConfigDevice(BOOL fConfigured)\r
+{\r
+       // set configured bit\r
+       USBHwCmdWrite(CMD_DEV_CONFIG, fConfigured ? CONF_DEVICE : 0);\r
+}\r
+\r
+\r
+/**\r
+       USB interrupt handler\r
+\r
+       @todo Get all 11 bits of frame number instead of just 8\r
+\r
+       Endpoint interrupts are mapped to the slow interrupt\r
+ */\r
+void USBHwISR(void)\r
+{\r
+       unsigned long   dwStatus;\r
+       unsigned long dwIntBit;\r
+       unsigned char   bEPStat, bDevStat, bStat;\r
+       int i;\r
+       unsigned short  wFrame;\r
+\r
+       // handle device interrupts\r
+       dwStatus = USB->USBDevIntSt;\r
+\r
+       // frame interrupt\r
+       if (dwStatus & FRAME) {\r
+               // clear int\r
+               USB->USBDevIntClr = FRAME;\r
+               // call handler\r
+               if (_pfnFrameHandler != NULL) {\r
+                       wFrame = USBHwCmdRead(CMD_DEV_READ_CUR_FRAME_NR);\r
+                       _pfnFrameHandler(wFrame);\r
+               }\r
+       }\r
+\r
+       // device status interrupt\r
+       if (dwStatus & DEV_STAT) {\r
+               /*      Clear DEV_STAT interrupt before reading DEV_STAT register.\r
+                       This prevents corrupted device status reads, see\r
+                       LPC2148 User manual revision 2, 25 july 2006.\r
+               */\r
+               USB->USBDevIntClr = DEV_STAT;\r
+               bDevStat = USBHwCmdRead(CMD_DEV_STATUS);\r
+               if (bDevStat & (CON_CH | SUS_CH | RST)) {\r
+                       // convert device status into something HW independent\r
+                       bStat = ((bDevStat & CON) ? DEV_STATUS_CONNECT : 0) |\r
+                                       ((bDevStat & SUS) ? DEV_STATUS_SUSPEND : 0) |\r
+                                       ((bDevStat & RST) ? DEV_STATUS_RESET : 0);\r
+                       // call handler\r
+                       if (_pfnDevIntHandler != NULL) {\r
+                               _pfnDevIntHandler(bStat);\r
+                       }\r
+               }\r
+       }\r
+\r
+       // endpoint interrupt\r
+       if (dwStatus & EP_SLOW) {\r
+               // clear EP_SLOW\r
+               USB->USBDevIntClr = EP_SLOW;\r
+               // check all endpoints\r
+               for (i = 0; i < 32; i++) {\r
+                       dwIntBit = (1 << i);\r
+                       if (USB->USBEpIntSt & dwIntBit) {\r
+                               // clear int (and retrieve status)\r
+                               USB->USBEpIntClr = dwIntBit;\r
+                               Wait4DevInt(CDFULL);\r
+                               bEPStat = USB->USBCmdData;\r
+                               // convert EP pipe stat into something HW independent\r
+                               bStat = ((bEPStat & EPSTAT_FE) ? EP_STATUS_DATA : 0) |\r
+                                               ((bEPStat & EPSTAT_ST) ? EP_STATUS_STALLED : 0) |\r
+                                               ((bEPStat & EPSTAT_STP) ? EP_STATUS_SETUP : 0) |\r
+                                               ((bEPStat & EPSTAT_EPN) ? EP_STATUS_NACKED : 0) |\r
+                                               ((bEPStat & EPSTAT_PO) ? EP_STATUS_ERROR : 0);\r
+                               // call handler\r
+                               if (_apfnEPIntHandlers[i / 2] != NULL) {\r
+                                       _apfnEPIntHandlers[i / 2](IDX2EP(i), bStat);\r
+                               }\r
+                       }\r
+               }\r
+       }\r
+}\r
+\r
+\r
+\r
+/**\r
+       Initialises the USB hardware\r
+\r
+\r
+       @return TRUE if the hardware was successfully initialised\r
+ */\r
+BOOL USBHwInit(void)\r
+{\r
+       // P2.9 -> USB_CONNECT\r
+       PINCON->PINSEL4 &= ~0x000C0000;\r
+       PINCON->PINSEL4 |= 0x00040000;\r
+\r
+       // P1.18 -> USB_UP_LED\r
+       // P1.30 -> VBUS\r
+       PINCON->PINSEL3 &= ~0x30000030;\r
+       PINCON->PINSEL3 |= 0x20000010;\r
+\r
+       // P0.29 -> USB_D+\r
+       // P0.30 -> USB_D-\r
+       PINCON->PINSEL1 &= ~0x3C000000;\r
+       PINCON->PINSEL1 |= 0x14000000;\r
+\r
+       // enable PUSB\r
+       SC->PCONP |= (1UL << 31UL);\r
+\r
+       USB->OTGClkCtrl = 0x12;                   /* Dev clock, AHB clock enable  */\r
+       while ((USB->OTGClkSt & 0x12) != 0x12);\r
+\r
+       // disable/clear all interrupts for now\r
+       USB->USBDevIntEn = 0;\r
+       USB->USBDevIntClr = 0xFFFFFFFF;\r
+       USB->USBDevIntPri = 0;\r
+\r
+       USB->USBEpIntEn = 0;\r
+       USB->USBEpIntClr = 0xFFFFFFFF;\r
+       USB->USBEpIntPri = 0;\r
+\r
+       // by default, only ACKs generate interrupts\r
+       USBHwNakIntEnable(0);\r
+\r
+       return TRUE;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c.bak b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.c.bak
new file mode 100644 (file)
index 0000000..29de3de
--- /dev/null
@@ -0,0 +1,521 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers\r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/** @file\r
+       USB hardware layer\r
+ */\r
+\r
+\r
+#include "usbdebug.h"\r
+#include "usbhw_lpc.h"\r
+#include "usbapi.h"\r
+\r
+/** Installed device interrupt handler */\r
+static TFnDevIntHandler *_pfnDevIntHandler = NULL;\r
+/** Installed endpoint interrupt handlers */\r
+static TFnEPIntHandler *_apfnEPIntHandlers[16];\r
+/** Installed frame interrupt handlers */\r
+static TFnFrameHandler *_pfnFrameHandler = NULL;\r
+\r
+/** convert from endpoint address to endpoint index */\r
+#define EP2IDX(bEP)    ((((bEP)&0xF)<<1)|(((bEP)&0x80)>>7))\r
+/** convert from endpoint index to endpoint address */\r
+#define IDX2EP(idx)    ((((idx)<<7)&0x80)|(((idx)>>1)&0xF))\r
+\r
+\r
+\r
+/**\r
+       Local function to wait for a device interrupt (and clear it)\r
+\r
+       @param [in]     dwIntr          Bitmask of interrupts to wait for\r
+ */\r
+static void Wait4DevInt(unsigned long dwIntr)\r
+{\r
+       // wait for specific interrupt\r
+       while ((USB->USBDevIntSt & dwIntr) != dwIntr);\r
+       // clear the interrupt bits\r
+       USB->USBDevIntClr = dwIntr;\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command to the USB protocol engine\r
+\r
+       @param [in]     bCmd            Command to send\r
+ */\r
+static void USBHwCmd(unsigned char bCmd)\r
+{\r
+       // clear CDFULL/CCEMTY\r
+       USB->USBDevIntClr = CDFULL | CCEMTY;\r
+       // write command code\r
+       USB->USBCmdCode = 0x00000500 | (bCmd << 16);\r
+       Wait4DevInt(CCEMTY);\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command + data to the USB protocol engine\r
+\r
+       @param [in]     bCmd            Command to send\r
+       @param [in]     bData           Data to send\r
+ */\r
+static void USBHwCmdWrite(unsigned char bCmd, unsigned short bData)\r
+{\r
+       // write command code\r
+       USBHwCmd(bCmd);\r
+\r
+       // write command data\r
+       USB->USBCmdCode = 0x00000100 | (bData << 16);\r
+       Wait4DevInt(CCEMTY);\r
+}\r
+\r
+\r
+/**\r
+       Local function to send a command to the USB protocol engine and read data\r
+\r
+       @param [in]     bCmd            Command to send\r
+\r
+       @return the data\r
+ */\r
+static unsigned char USBHwCmdRead(unsigned char bCmd)\r
+{\r
+       // write command code\r
+       USBHwCmd(bCmd);\r
+\r
+       // get data\r
+       USB->USBCmdCode = 0x00000200 | (bCmd << 16);\r
+       Wait4DevInt(CDFULL);\r
+       return USB->USBCmdData;\r
+}\r
+\r
+\r
+/**\r
+       'Realizes' an endpoint, meaning that buffer space is reserved for\r
+       it. An endpoint needs to be realised before it can be used.\r
+\r
+       From experiments, it appears that a USB reset causes USBReEP to\r
+       re-initialise to 3 (= just the control endpoints).\r
+       However, a USB bus reset does not disturb the USBMaxPSize settings.\r
+\r
+       @param [in]     idx                     Endpoint index\r
+       @param [in] wMaxPSize   Maximum packet size for this endpoint\r
+ */\r
+static void USBHwEPRealize(int idx, unsigned short wMaxPSize)\r
+{\r
+       USB->USBReEP |= (1 << idx);\r
+       USB->USBEpInd = idx;\r
+       USB->USBMaxPSize = wMaxPSize;\r
+       Wait4DevInt(EP_RLZED);\r
+}\r
+\r
+\r
+/**\r
+       Enables or disables an endpoint\r
+\r
+       @param [in]     idx             Endpoint index\r
+       @param [in]     fEnable TRUE to enable, FALSE to disable\r
+ */\r
+static void USBHwEPEnable(int idx, BOOL fEnable)\r
+{\r
+       USBHwCmdWrite(CMD_EP_SET_STATUS | idx, fEnable ? 0 : EP_DA);\r
+}\r
+\r
+\r
+/**\r
+       Configures an endpoint and enables it\r
+\r
+       @param [in]     bEP                             Endpoint number\r
+       @param [in]     wMaxPacketSize  Maximum packet size for this EP\r
+ */\r
+void USBHwEPConfig(unsigned char bEP, unsigned short wMaxPacketSize)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // realise EP\r
+       USBHwEPRealize(idx, wMaxPacketSize);\r
+\r
+       // enable EP\r
+       USBHwEPEnable(idx, TRUE);\r
+}\r
+\r
+\r
+/**\r
+       Registers an endpoint event callback\r
+\r
+       @param [in]     bEP                             Endpoint number\r
+       @param [in]     pfnHandler              Callback function\r
+ */\r
+void USBHwRegisterEPIntHandler(unsigned char bEP, TFnEPIntHandler *pfnHandler)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       ASSERT(idx<32);\r
+\r
+       /* add handler to list of EP handlers */\r
+       _apfnEPIntHandlers[idx / 2] = pfnHandler;\r
+\r
+       /* enable EP interrupt */\r
+       USB->USBEpIntEn |= (1 << idx);\r
+       USB->USBDevIntEn |= EP_SLOW;\r
+\r
+       DBG("Registered handler for EP 0x%x\n", bEP);\r
+}\r
+\r
+\r
+/**\r
+       Registers an device status callback\r
+\r
+       @param [in]     pfnHandler      Callback function\r
+ */\r
+void USBHwRegisterDevIntHandler(TFnDevIntHandler *pfnHandler)\r
+{\r
+       _pfnDevIntHandler = pfnHandler;\r
+\r
+       // enable device interrupt\r
+       USB->USBDevIntEn |= DEV_STAT;\r
+\r
+       DBG("Registered handler for device status\n");\r
+}\r
+\r
+\r
+/**\r
+       Registers the frame callback\r
+\r
+       @param [in]     pfnHandler      Callback function\r
+ */\r
+void USBHwRegisterFrameHandler(TFnFrameHandler *pfnHandler)\r
+{\r
+       _pfnFrameHandler = pfnHandler;\r
+\r
+       // enable device interrupt\r
+       USB->USBDevIntEn |= FRAME;\r
+\r
+       DBG("Registered handler for frame\n");\r
+}\r
+\r
+\r
+/**\r
+       Sets the USB address.\r
+\r
+       @param [in]     bAddr           Device address to set\r
+ */\r
+void USBHwSetAddress(unsigned char bAddr)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_SET_ADDRESS, DEV_EN | bAddr);\r
+}\r
+\r
+\r
+/**\r
+       Connects or disconnects from the USB bus\r
+\r
+       @param [in]     fConnect        If TRUE, connect, otherwise disconnect\r
+ */\r
+void USBHwConnect(BOOL fConnect)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_STATUS, fConnect ? CON : 0);\r
+}\r
+\r
+\r
+/**\r
+       Enables interrupt on NAK condition\r
+\r
+       For IN endpoints a NAK is generated when the host wants to read data\r
+       from the device, but none is available in the endpoint buffer.\r
+       For OUT endpoints a NAK is generated when the host wants to write data\r
+       to the device, but the endpoint buffer is still full.\r
+\r
+       The endpoint interrupt handlers can distinguish regular (ACK) interrupts\r
+       from NAK interrupt by checking the bits in their bEPStatus argument.\r
+\r
+       @param [in]     bIntBits        Bitmap indicating which NAK interrupts to enable\r
+ */\r
+void USBHwNakIntEnable(unsigned char bIntBits)\r
+{\r
+       USBHwCmdWrite(CMD_DEV_SET_MODE, bIntBits);\r
+}\r
+\r
+\r
+/**\r
+       Gets the status from a specific endpoint.\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @return Endpoint status byte (containing EP_STATUS_xxx bits)\r
+ */\r
+unsigned char  USBHwEPGetStatus(unsigned char bEP)\r
+{\r
+       int idx = EP2IDX(bEP);\r
+\r
+       return USBHwCmdRead(CMD_EP_SELECT | idx);\r
+}\r
+\r
+\r
+/**\r
+       Sets the stalled property of an endpoint\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     fStall  TRUE to stall, FALSE to unstall\r
+ */\r
+void USBHwEPStall(unsigned char bEP, BOOL fStall)\r
+{\r
+       int idx = EP2IDX(bEP);\r
+\r
+       USBHwCmdWrite(CMD_EP_SET_STATUS | idx, fStall ? EP_ST : 0);\r
+}\r
+\r
+\r
+/**\r
+       Writes data to an endpoint buffer\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     pbBuf   Endpoint data\r
+       @param [in]     iLen    Number of bytes to write\r
+\r
+       @return TRUE if the data was successfully written or <0 in case of error.\r
+*/\r
+int USBHwEPWrite(unsigned char bEP, unsigned char *pbBuf, int iLen)\r
+{\r
+       int idx;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // set write enable for specific endpoint\r
+       USB->USBCtrl = WR_EN | ((bEP & 0xF) << 2);\r
+\r
+       // set packet length\r
+       USB->USBTxPLen = iLen;\r
+\r
+       // write data\r
+       while (USB->USBCtrl & WR_EN) {\r
+               USB->USBTxData = (pbBuf[3] << 24) | (pbBuf[2] << 16) | (pbBuf[1] << 8) | pbBuf[0];\r
+               pbBuf += 4;\r
+       }\r
+\r
+       // select endpoint and validate buffer\r
+       USBHwCmd(CMD_EP_SELECT | idx);\r
+       USBHwCmd(CMD_EP_VALIDATE_BUFFER);\r
+\r
+       return iLen;\r
+}\r
+\r
+\r
+/**\r
+       Reads data from an endpoint buffer\r
+\r
+       @param [in]     bEP             Endpoint number\r
+       @param [in]     pbBuf   Endpoint data\r
+       @param [in]     iMaxLen Maximum number of bytes to read\r
+\r
+       @return the number of bytes available in the EP (possibly more than iMaxLen),\r
+       or <0 in case of error.\r
+ */\r
+int USBHwEPRead(unsigned char bEP, unsigned char *pbBuf, int iMaxLen)\r
+{\r
+       unsigned int i, idx;\r
+       unsigned long   dwData, dwLen;\r
+\r
+       idx = EP2IDX(bEP);\r
+\r
+       // set read enable bit for specific endpoint\r
+       USB->USBCtrl = RD_EN | ((bEP & 0xF) << 2);\r
+\r
+       // wait for PKT_RDY\r
+       do {\r
+               dwLen = USB->USBRxPLen;\r
+       } while ((dwLen & PKT_RDY) == 0);\r
+\r
+       // packet valid?\r
+       if ((dwLen & DV) == 0) {\r
+               return -1;\r
+       }\r
+\r
+       // get length\r
+       dwLen &= PKT_LNGTH_MASK;\r
+\r
+       // get data\r
+       dwData = 0;\r
+       for (i = 0; i < dwLen; i++) {\r
+               if ((i % 4) == 0) {\r
+                       dwData = USB->USBRxData;\r
+               }\r
+               if ((pbBuf != NULL) && (i < iMaxLen)) {\r
+                       pbBuf[i] = dwData & 0xFF;\r
+               }\r
+               dwData >>= 8;\r
+       }\r
+\r
+       // make sure RD_EN is clear\r
+       USB->USBCtrl = 0;\r
+\r
+       // select endpoint and clear buffer\r
+       USBHwCmd(CMD_EP_SELECT | idx);\r
+       USBHwCmd(CMD_EP_CLEAR_BUFFER);\r
+\r
+       return dwLen;\r
+}\r
+\r
+\r
+/**\r
+       Sets the 'configured' state.\r
+\r
+       All registered endpoints are 'realised' and enabled, and the\r
+       'configured' bit is set in the device status register.\r
+\r
+       @param [in]     fConfigured     If TRUE, configure device, else unconfigure\r
+ */\r
+void USBHwConfigDevice(BOOL fConfigured)\r
+{\r
+       // set configured bit\r
+       USBHwCmdWrite(CMD_DEV_CONFIG, fConfigured ? CONF_DEVICE : 0);\r
+}\r
+\r
+\r
+/**\r
+       USB interrupt handler\r
+\r
+       @todo Get all 11 bits of frame number instead of just 8\r
+\r
+       Endpoint interrupts are mapped to the slow interrupt\r
+ */\r
+void USBHwISR(void)\r
+{\r
+       unsigned long   dwStatus;\r
+       unsigned long dwIntBit;\r
+       unsigned char   bEPStat, bDevStat, bStat;\r
+       int i;\r
+       unsigned short  wFrame;\r
+\r
+       // handle device interrupts\r
+       dwStatus = USB->USBDevIntSt;\r
+\r
+       // frame interrupt\r
+       if (dwStatus & FRAME) {\r
+               // clear int\r
+               USB->USBDevIntClr = FRAME;\r
+               // call handler\r
+               if (_pfnFrameHandler != NULL) {\r
+                       wFrame = USBHwCmdRead(CMD_DEV_READ_CUR_FRAME_NR);\r
+                       _pfnFrameHandler(wFrame);\r
+               }\r
+       }\r
+\r
+       // device status interrupt\r
+       if (dwStatus & DEV_STAT) {\r
+               /*      Clear DEV_STAT interrupt before reading DEV_STAT register.\r
+                       This prevents corrupted device status reads, see\r
+                       LPC2148 User manual revision 2, 25 july 2006.\r
+               */\r
+               USB->USBDevIntClr = DEV_STAT;\r
+               bDevStat = USBHwCmdRead(CMD_DEV_STATUS);\r
+               if (bDevStat & (CON_CH | SUS_CH | RST)) {\r
+                       // convert device status into something HW independent\r
+                       bStat = ((bDevStat & CON) ? DEV_STATUS_CONNECT : 0) |\r
+                                       ((bDevStat & SUS) ? DEV_STATUS_SUSPEND : 0) |\r
+                                       ((bDevStat & RST) ? DEV_STATUS_RESET : 0);\r
+                       // call handler\r
+                       if (_pfnDevIntHandler != NULL) {\r
+                               _pfnDevIntHandler(bStat);\r
+                       }\r
+               }\r
+       }\r
+\r
+       // endpoint interrupt\r
+       if (dwStatus & EP_SLOW) {\r
+               // clear EP_SLOW\r
+               USB->USBDevIntClr = EP_SLOW;\r
+               // check all endpoints\r
+               for (i = 0; i < 32; i++) {\r
+                       dwIntBit = (1 << i);\r
+                       if (USB->USBEpIntSt & dwIntBit) {\r
+                               // clear int (and retrieve status)\r
+                               USB->USBEpIntClr = dwIntBit;\r
+                               Wait4DevInt(CDFULL);\r
+                               bEPStat = USB->USBCmdData;\r
+                               // convert EP pipe stat into something HW independent\r
+                               bStat = ((bEPStat & EPSTAT_FE) ? EP_STATUS_DATA : 0) |\r
+                                               ((bEPStat & EPSTAT_ST) ? EP_STATUS_STALLED : 0) |\r
+                                               ((bEPStat & EPSTAT_STP) ? EP_STATUS_SETUP : 0) |\r
+                                               ((bEPStat & EPSTAT_EPN) ? EP_STATUS_NACKED : 0) |\r
+                                               ((bEPStat & EPSTAT_PO) ? EP_STATUS_ERROR : 0);\r
+                               // call handler\r
+                               if (_apfnEPIntHandlers[i / 2] != NULL) {\r
+                                       _apfnEPIntHandlers[i / 2](IDX2EP(i), bStat);\r
+                               }\r
+                       }\r
+               }\r
+       }\r
+}\r
+\r
+\r
+\r
+/**\r
+       Initialises the USB hardware\r
+\r
+\r
+       @return TRUE if the hardware was successfully initialised\r
+ */\r
+BOOL USBHwInit(void)\r
+{\r
+       // P2.9 -> USB_CONNECT\r
+       PINCON->PINSEL4 &= ~0x000C0000;\r
+       PINCON->PINSEL4 |= 0x00040000;\r
+\r
+       // P1.18 -> USB_UP_LED\r
+       // P1.30 -> VBUS\r
+       PINCON->PINSEL3 &= ~0x30000030;\r
+       PINCON->PINSEL3 |= 0x20000010;\r
+\r
+       // P0.29 -> USB_D+\r
+       // P0.30 -> USB_D-\r
+       PINCON->PINSEL1 &= ~0x3C000000;\r
+       PINCON->PINSEL1 |= 0x14000000;\r
+\r
+       // enable PUSB\r
+       SC->PCONP |= (1 << 31);\r
+\r
+       USB->OTGClkCtrl = 0x12;                   /* Dev clock, AHB clock enable  */\r
+       while ((USB->OTGClkSt & 0x12) != 0x12);\r
+\r
+       // disable/clear all interrupts for now\r
+       USB->USBDevIntEn = 0;\r
+       USB->USBDevIntClr = 0xFFFFFFFF;\r
+       USB->USBDevIntPri = 0;\r
+\r
+       USB->USBEpIntEn = 0;\r
+       USB->USBEpIntClr = 0xFFFFFFFF;\r
+       USB->USBEpIntPri = 0;\r
+\r
+       // by default, only ACKs generate interrupts\r
+       USBHwNakIntEnable(0);\r
+\r
+       return TRUE;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.h b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbhw_lpc.h
new file mode 100644 (file)
index 0000000..8578177
--- /dev/null
@@ -0,0 +1,149 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/**\r
+       Hardware definitions for the LPC176x USB controller\r
+\r
+       These are private to the usbhw module\r
+*/\r
+\r
+// CodeRed - pull in defines from NXP header file\r
+//#include "NXP\LPC17xx\LPC17xx.h"\r
+#include "LPC17xx.h"\r
+\r
+\r
+// CodeRed - these registers have been renamed on LPC176x\r
+#define USBReEP USBReEp\r
+#define OTG_CLK_CTRL USBClkCtrl\r
+#define OTG_CLK_STAT USBClkSt\r
+\r
+/* USBIntSt bits */\r
+#define USB_INT_REQ_LP                         (1<<0)\r
+#define USB_INT_REQ_HP                         (1<<1)\r
+#define USB_INT_REQ_DMA                                (1<<2)\r
+#define USB_need_clock                         (1<<8)\r
+#define EN_USB_BITS                                    (1<<31)\r
+\r
+/* USBDevInt... bits */\r
+#define FRAME                                          (1<<0)\r
+#define EP_FAST                                                (1<<1)\r
+#define EP_SLOW                                                (1<<2)\r
+#define DEV_STAT                                       (1<<3)\r
+#define CCEMTY                                         (1<<4)\r
+#define CDFULL                                         (1<<5)\r
+#define RxENDPKT                                       (1<<6)\r
+#define TxENDPKT                                       (1<<7)\r
+#define EP_RLZED                                       (1<<8)\r
+#define ERR_INT                                                (1<<9)\r
+\r
+/* USBRxPLen bits */\r
+#define PKT_LNGTH                                      (1<<0)\r
+#define PKT_LNGTH_MASK                         0x3FF\r
+#define DV                                                     (1<<10)\r
+#define PKT_RDY                                                (1<<11)\r
+\r
+/* USBCtrl bits */\r
+#define RD_EN                                          (1<<0)\r
+#define WR_EN                                          (1<<1)\r
+#define LOG_ENDPOINT                           (1<<2)\r
+\r
+/* protocol engine command codes */\r
+       /* device commands */\r
+#define CMD_DEV_SET_ADDRESS                    0xD0\r
+#define CMD_DEV_CONFIG                         0xD8\r
+#define CMD_DEV_SET_MODE                       0xF3\r
+#define CMD_DEV_READ_CUR_FRAME_NR      0xF5\r
+#define CMD_DEV_READ_TEST_REG          0xFD\r
+#define CMD_DEV_STATUS                         0xFE            /* read/write */\r
+#define CMD_DEV_GET_ERROR_CODE         0xFF\r
+#define CMD_DEV_READ_ERROR_STATUS      0xFB\r
+       /* endpoint commands */\r
+#define CMD_EP_SELECT                          0x00\r
+#define CMD_EP_SELECT_CLEAR                    0x40\r
+#define CMD_EP_SET_STATUS                      0x40\r
+#define CMD_EP_CLEAR_BUFFER                    0xF2\r
+#define CMD_EP_VALIDATE_BUFFER         0xFA\r
+\r
+/* set address command */\r
+#define DEV_ADDR                                       (1<<0)\r
+#define DEV_EN                                         (1<<7)\r
+\r
+/* configure device command */\r
+#define CONF_DEVICE                                    (1<<0)\r
+\r
+/* set mode command */\r
+#define AP_CLK                                         (1<<0)\r
+#define INAK_CI                                                (1<<1)\r
+#define INAK_CO                                                (1<<2)\r
+#define INAK_II                                                (1<<3)\r
+#define INAK_IO                                                (1<<4)\r
+#define INAK_BI                                                (1<<5)\r
+#define INAK_BO                                                (1<<6)\r
+\r
+/* set get device status command */\r
+#define CON                                                    (1<<0)\r
+#define CON_CH                                         (1<<1)\r
+#define SUS                                                    (1<<2)\r
+#define SUS_CH                                         (1<<3)\r
+#define RST                                                    (1<<4)\r
+\r
+/* get error code command */\r
+// ...\r
+\r
+/* Select Endpoint command read bits */\r
+#define EPSTAT_FE                                      (1<<0)\r
+#define EPSTAT_ST                                      (1<<1)\r
+#define EPSTAT_STP                                     (1<<2)\r
+#define EPSTAT_PO                                      (1<<3)\r
+#define EPSTAT_EPN                                     (1<<4)\r
+#define EPSTAT_B1FULL                          (1<<5)\r
+#define EPSTAT_B2FULL                          (1<<6)\r
+\r
+/* CMD_EP_SET_STATUS command */\r
+#define EP_ST                                          (1<<0)\r
+#define EP_DA                                          (1<<5)\r
+#define EP_RF_MO                                       (1<<6)\r
+#define EP_CND_ST                                      (1<<7)\r
+\r
+/* read error status command */\r
+#define PID_ERR                                                (1<<0)\r
+#define UEPKT                                          (1<<1)\r
+#define DCRC                                           (1<<2)\r
+#define TIMEOUT                                                (1<<3)\r
+#define EOP                                                    (1<<4)\r
+#define B_OVRN                                         (1<<5)\r
+#define BTSTF                                          (1<<6)\r
+#define TGL_ERR                                                (1<<7)\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbinit.c b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbinit.c
new file mode 100644 (file)
index 0000000..f1784c2
--- /dev/null
@@ -0,0 +1,82 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/** @file\r
+       USB stack initialisation\r
+ */\r
+\r
+\r
+#include "usbdebug.h"\r
+#include "usbapi.h"\r
+\r
+\r
+/** data storage area for standard requests */\r
+static unsigned char   abStdReqData[8];\r
+\r
+\r
+/**\r
+       USB reset handler\r
+       \r
+       @param [in] bDevStatus  Device status\r
+ */\r
+static void HandleUsbReset(unsigned char bDevStatus)\r
+{\r
+       if (bDevStatus & DEV_STATUS_RESET) {\r
+               DBG("\n!");\r
+       }\r
+}\r
+\r
+\r
+/**\r
+       Initialises the USB hardware and sets up the USB stack by\r
+       installing default callbacks.\r
+       \r
+       @return TRUE if initialisation was successful\r
+ */\r
+BOOL USBInit(void)\r
+{\r
+       // init hardware\r
+       USBHwInit();\r
+       \r
+       // register bus reset handler\r
+       USBHwRegisterDevIntHandler(HandleUsbReset);\r
+       \r
+       // register control transfer handler on EP0\r
+       USBHwRegisterEPIntHandler(0x00, USBHandleControlTransfer);\r
+       USBHwRegisterEPIntHandler(0x80, USBHandleControlTransfer);\r
+       \r
+       // setup control endpoints\r
+       USBHwEPConfig(0x00, MAX_PACKET_SIZE0);\r
+       USBHwEPConfig(0x80, MAX_PACKET_SIZE0);\r
+       \r
+       // register standard request handler\r
+       USBRegisterRequestHandler(REQTYPE_TYPE_STANDARD, USBHandleStandardRequest, abStdReqData);\r
+\r
+       return TRUE;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstdreq.c b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstdreq.c
new file mode 100644 (file)
index 0000000..05e58b4
--- /dev/null
@@ -0,0 +1,430 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, \r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/** @file\r
+       Standard request handler.\r
+       \r
+       This modules handles the 'chapter 9' processing, specifically the\r
+       standard device requests in table 9-3 from the universal serial bus\r
+       specification revision 2.0\r
+       \r
+       Specific types of devices may specify additional requests (for example\r
+       HID devices add a GET_DESCRIPTOR request for interfaces), but they\r
+       will not be part of this module.\r
+\r
+       @todo some requests have to return a request error if device not configured:\r
+       @todo GET_INTERFACE, GET_STATUS, SET_INTERFACE, SYNCH_FRAME\r
+       @todo this applies to the following if endpoint != 0:\r
+       @todo SET_FEATURE, GET_FEATURE \r
+*/\r
+\r
+#include "usbdebug.h"\r
+#include "usbstruct.h"\r
+#include "usbapi.h"\r
+\r
+#define MAX_DESC_HANDLERS      4               /**< device, interface, endpoint, other */\r
+\r
+\r
+/* general descriptor field offsets */\r
+#define DESC_bLength                                   0       /**< length offset */\r
+#define DESC_bDescriptorType                   1       /**< descriptor type offset */  \r
+\r
+/* config descriptor field offsets */\r
+#define CONF_DESC_wTotalLength                 2       /**< total length offset */\r
+#define CONF_DESC_bConfigurationValue  5       /**< configuration value offset */      \r
+#define CONF_DESC_bmAttributes                 7       /**< configuration characteristics */\r
+\r
+/* interface descriptor field offsets */\r
+#define INTF_DESC_bAlternateSetting            3       /**< alternate setting offset */\r
+\r
+/* endpoint descriptor field offsets */\r
+#define ENDP_DESC_bEndpointAddress             2       /**< endpoint address offset */\r
+#define ENDP_DESC_wMaxPacketSize               4       /**< maximum packet size offset */\r
+\r
+\r
+/** Currently selected configuration */\r
+static unsigned char                           bConfiguration = 0;\r
+/** Installed custom request handler */\r
+static TFnHandleRequest        *pfnHandleCustomReq = NULL;\r
+/** Pointer to registered descriptors */\r
+static const unsigned char                     *pabDescrip = NULL;\r
+\r
+\r
+/**\r
+       Registers a pointer to a descriptor block containing all descriptors\r
+       for the device.\r
+\r
+       @param [in]     pabDescriptors  The descriptor byte array\r
+ */\r
+void USBRegisterDescriptors(const unsigned char *pabDescriptors)\r
+{\r
+       pabDescrip = pabDescriptors;\r
+}\r
+\r
+\r
+/**\r
+       Parses the list of installed USB descriptors and attempts to find\r
+       the specified USB descriptor.\r
+               \r
+       @param [in]             wTypeIndex      Type and index of the descriptor\r
+       @param [in]             wLangID         Language ID of the descriptor (currently unused)\r
+       @param [out]    *piLen          Descriptor length\r
+       @param [out]    *ppbData        Descriptor data\r
+       \r
+       @return TRUE if the descriptor was found, FALSE otherwise\r
+ */\r
+BOOL USBGetDescriptor(unsigned short wTypeIndex, unsigned short wLangID, int *piLen, unsigned char **ppbData)\r
+{\r
+       unsigned char   bType, bIndex;\r
+       unsigned char   *pab;\r
+       int iCurIndex;\r
+       \r
+       ASSERT(pabDescrip != NULL);\r
+\r
+       bType = GET_DESC_TYPE(wTypeIndex);\r
+       bIndex = GET_DESC_INDEX(wTypeIndex);\r
+       \r
+       pab = (unsigned char *)pabDescrip;\r
+       iCurIndex = 0;\r
+       \r
+       while (pab[DESC_bLength] != 0) {\r
+               if (pab[DESC_bDescriptorType] == bType) {\r
+                       if (iCurIndex == bIndex) {\r
+                               // set data pointer\r
+                               *ppbData = pab;\r
+                               // get length from structure\r
+                               if (bType == DESC_CONFIGURATION) {\r
+                                       // configuration descriptor is an exception, length is at offset 2 and 3\r
+                                       *piLen =        (pab[CONF_DESC_wTotalLength]) |\r
+                                                               (pab[CONF_DESC_wTotalLength + 1] << 8);\r
+                               }\r
+                               else {\r
+                                       // normally length is at offset 0\r
+                                       *piLen = pab[DESC_bLength];\r
+                               }\r
+                               return TRUE;\r
+                       }\r
+                       iCurIndex++;\r
+               }\r
+               // skip to next descriptor\r
+               pab += pab[DESC_bLength];\r
+       }\r
+       // nothing found\r
+       DBG("Desc %x not found!\n", wTypeIndex);\r
+       return FALSE;\r
+}\r
+\r
+\r
+/**\r
+       Configures the device according to the specified configuration index and\r
+       alternate setting by parsing the installed USB descriptor list.\r
+       A configuration index of 0 unconfigures the device.\r
+               \r
+       @param [in]             bConfigIndex    Configuration index\r
+       @param [in]             bAltSetting             Alternate setting number\r
+       \r
+       @todo function always returns TRUE, add stricter checking?\r
+       \r
+       @return TRUE if successfully configured, FALSE otherwise\r
+ */\r
+static BOOL USBSetConfiguration(unsigned char bConfigIndex, unsigned char bAltSetting)\r
+{\r
+       unsigned char   *pab;\r
+       unsigned char   bCurConfig, bCurAltSetting;\r
+       unsigned char   bEP;\r
+       unsigned short  wMaxPktSize;\r
+       \r
+       ASSERT(pabDescrip != NULL);\r
+\r
+       if (bConfigIndex == 0) {\r
+               // unconfigure device\r
+               USBHwConfigDevice(FALSE);\r
+       }\r
+       else {\r
+               // configure endpoints for this configuration/altsetting\r
+               pab = (unsigned char *)pabDescrip;\r
+               bCurConfig = 0xFF;\r
+               bCurAltSetting = 0xFF;\r
+\r
+               while (pab[DESC_bLength] != 0) {\r
+\r
+                       switch (pab[DESC_bDescriptorType]) {\r
+\r
+                       case DESC_CONFIGURATION:\r
+                               // remember current configuration index\r
+                               bCurConfig = pab[CONF_DESC_bConfigurationValue];\r
+                               break;\r
+\r
+                       case DESC_INTERFACE:\r
+                               // remember current alternate setting\r
+                               bCurAltSetting = pab[INTF_DESC_bAlternateSetting];\r
+                               break;\r
+\r
+                       case DESC_ENDPOINT:\r
+                               if ((bCurConfig == bConfigIndex) &&\r
+                                       (bCurAltSetting == bAltSetting)) {\r
+                                       // endpoint found for desired config and alternate setting\r
+                                       bEP = pab[ENDP_DESC_bEndpointAddress];\r
+                                       wMaxPktSize =   (pab[ENDP_DESC_wMaxPacketSize]) |\r
+                                                                       (pab[ENDP_DESC_wMaxPacketSize + 1] << 8);\r
+                                       // configure endpoint\r
+                                       USBHwEPConfig(bEP, wMaxPktSize);\r
+                               }\r
+                               break;\r
+\r
+                       default:\r
+                               break;\r
+                       }\r
+                       // skip to next descriptor\r
+                       pab += pab[DESC_bLength];\r
+               }\r
+               \r
+               // configure device\r
+               USBHwConfigDevice(TRUE);\r
+       }\r
+\r
+       return TRUE;\r
+}\r
+\r
+\r
+/**\r
+       Local function to handle a standard device request\r
+               \r
+       @param [in]             pSetup          The setup packet\r
+       @param [in,out] *piLen          Pointer to data length\r
+       @param [in,out] ppbData         Data buffer.\r
+\r
+       @return TRUE if the request was handled successfully\r
+ */\r
+static BOOL HandleStdDeviceReq(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       unsigned char   *pbData = *ppbData;\r
+\r
+       switch (pSetup->bRequest) {\r
+       \r
+       case REQ_GET_STATUS:\r
+               // bit 0: self-powered\r
+               // bit 1: remote wakeup = not supported\r
+               pbData[0] = 0;\r
+               pbData[1] = 0;\r
+               *piLen = 2;\r
+               break;\r
+               \r
+       case REQ_SET_ADDRESS:\r
+               USBHwSetAddress(pSetup->wValue);\r
+               break;\r
+\r
+       case REQ_GET_DESCRIPTOR:\r
+               DBG("D%x", pSetup->wValue);\r
+               return USBGetDescriptor(pSetup->wValue, pSetup->wIndex, piLen, ppbData);\r
+\r
+       case REQ_GET_CONFIGURATION:\r
+               // indicate if we are configured\r
+               pbData[0] = bConfiguration;\r
+               *piLen = 1;\r
+               break;\r
+\r
+       case REQ_SET_CONFIGURATION:\r
+               if (!USBSetConfiguration(pSetup->wValue & 0xFF, 0)) {\r
+                       DBG("USBSetConfiguration failed!\n");\r
+                       return FALSE;\r
+               }\r
+               // configuration successful, update current configuration\r
+               bConfiguration = pSetup->wValue & 0xFF; \r
+               break;\r
+\r
+       case REQ_CLEAR_FEATURE:\r
+       case REQ_SET_FEATURE:\r
+               if (pSetup->wValue == FEA_REMOTE_WAKEUP) {\r
+                       // put DEVICE_REMOTE_WAKEUP code here\r
+               }\r
+               if (pSetup->wValue == FEA_TEST_MODE) {\r
+                       // put TEST_MODE code here\r
+               }\r
+               return FALSE;\r
+\r
+       case REQ_SET_DESCRIPTOR:\r
+               DBG("Device req %d not implemented\n", pSetup->bRequest);\r
+               return FALSE;\r
+\r
+       default:\r
+               DBG("Illegal device req %d\n", pSetup->bRequest);\r
+               return FALSE;\r
+       }\r
+       \r
+       return TRUE;\r
+}\r
+\r
+\r
+/**\r
+       Local function to handle a standard interface request\r
+               \r
+       @param [in]             pSetup          The setup packet\r
+       @param [in,out] *piLen          Pointer to data length\r
+       @param [in]             ppbData         Data buffer.\r
+\r
+       @return TRUE if the request was handled successfully\r
+ */\r
+static BOOL HandleStdInterfaceReq(TSetupPacket *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       unsigned char   *pbData = *ppbData;\r
+\r
+       switch (pSetup->bRequest) {\r
+\r
+       case REQ_GET_STATUS:\r
+               // no bits specified\r
+               pbData[0] = 0;\r
+               pbData[1] = 0;\r
+               *piLen = 2;\r
+               break;\r
+\r
+       case REQ_CLEAR_FEATURE:\r
+       case REQ_SET_FEATURE:\r
+               // not defined for interface\r
+               return FALSE;\r
+       \r
+       case REQ_GET_INTERFACE: // TODO use bNumInterfaces\r
+        // there is only one interface, return n-1 (= 0)\r
+               pbData[0] = 0;\r
+               *piLen = 1;\r
+               break;\r
+       \r
+       case REQ_SET_INTERFACE: // TODO use bNumInterfaces\r
+               // there is only one interface (= 0)\r
+               if (pSetup->wValue != 0) {\r
+                       return FALSE;\r
+               }\r
+               *piLen = 0;\r
+               break;\r
+\r
+       default:\r
+               DBG("Illegal interface req %d\n", pSetup->bRequest);\r
+               return FALSE;\r
+       }\r
+\r
+       return TRUE;\r
+}\r
+\r
+\r
+/**\r
+       Local function to handle a standard endpoint request\r
+               \r
+       @param [in]             pSetup          The setup packet\r
+       @param [in,out] *piLen          Pointer to data length\r
+       @param [in]             ppbData         Data buffer.\r
+\r
+       @return TRUE if the request was handled successfully\r
+ */\r
+static BOOL HandleStdEndPointReq(TSetupPacket  *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       unsigned char   *pbData = *ppbData;\r
+\r
+       switch (pSetup->bRequest) {\r
+       case REQ_GET_STATUS:\r
+               // bit 0 = endpointed halted or not\r
+               pbData[0] = (USBHwEPGetStatus(pSetup->wIndex) & EP_STATUS_STALLED) ? 1 : 0;\r
+               pbData[1] = 0;\r
+               *piLen = 2;\r
+               break;\r
+               \r
+       case REQ_CLEAR_FEATURE:\r
+               if (pSetup->wValue == FEA_ENDPOINT_HALT) {\r
+                       // clear HALT by unstalling\r
+                       USBHwEPStall(pSetup->wIndex, FALSE);\r
+                       break;\r
+               }\r
+               // only ENDPOINT_HALT defined for endpoints\r
+               return FALSE;\r
+       \r
+       case REQ_SET_FEATURE:\r
+               if (pSetup->wValue == FEA_ENDPOINT_HALT) {\r
+                       // set HALT by stalling\r
+                       USBHwEPStall(pSetup->wIndex, TRUE);\r
+                       break;\r
+               }\r
+               // only ENDPOINT_HALT defined for endpoints\r
+               return FALSE;\r
+\r
+       case REQ_SYNCH_FRAME:\r
+               DBG("EP req %d not implemented\n", pSetup->bRequest);\r
+               return FALSE;\r
+\r
+       default:\r
+               DBG("Illegal EP req %d\n", pSetup->bRequest);\r
+               return FALSE;\r
+       }\r
+       \r
+       return TRUE;\r
+}\r
+\r
+\r
+/**\r
+       Default handler for standard ('chapter 9') requests\r
+       \r
+       If a custom request handler was installed, this handler is called first.\r
+               \r
+       @param [in]             pSetup          The setup packet\r
+       @param [in,out] *piLen          Pointer to data length\r
+       @param [in]             ppbData         Data buffer.\r
+\r
+       @return TRUE if the request was handled successfully\r
+ */\r
+BOOL USBHandleStandardRequest(TSetupPacket     *pSetup, int *piLen, unsigned char **ppbData)\r
+{\r
+       // try the custom request handler first\r
+       if ((pfnHandleCustomReq != NULL) && pfnHandleCustomReq(pSetup, piLen, ppbData)) {\r
+               return TRUE;\r
+       }\r
+       \r
+       switch (REQTYPE_GET_RECIP(pSetup->bmRequestType)) {\r
+       case REQTYPE_RECIP_DEVICE:              return HandleStdDeviceReq(pSetup, piLen, ppbData);\r
+       case REQTYPE_RECIP_INTERFACE:   return HandleStdInterfaceReq(pSetup, piLen, ppbData);\r
+       case REQTYPE_RECIP_ENDPOINT:    return HandleStdEndPointReq(pSetup, piLen, ppbData);\r
+       default:                                                return FALSE;\r
+       }\r
+}\r
+\r
+\r
+/**\r
+       Registers a callback for custom device requests\r
+       \r
+       In USBHandleStandardRequest, the custom request handler gets a first\r
+       chance at handling the request before it is handed over to the 'chapter 9'\r
+       request handler.\r
+       \r
+       This can be used for example in HID devices, where a REQ_GET_DESCRIPTOR\r
+       request is sent to an interface, which is not covered by the 'chapter 9'\r
+       specification.\r
+               \r
+       @param [in]     pfnHandler      Callback function pointer\r
+ */\r
+void USBRegisterCustomReqHandler(TFnHandleRequest *pfnHandler)\r
+{\r
+       pfnHandleCustomReq = pfnHandler;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstruct.h b/Demo/CORTEX_LPC1768_IAR/LPCUSB/usbstruct.h
new file mode 100644 (file)
index 0000000..a4b5fa7
--- /dev/null
@@ -0,0 +1,119 @@
+/*\r
+       LPCUSB, an USB device driver for LPC microcontrollers   \r
+       Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl)\r
+\r
+       Redistribution and use in source and binary forms, with or without\r
+       modification, are permitted provided that the following conditions are met:\r
+\r
+       1. Redistributions of source code must retain the above copyright\r
+          notice, this list of conditions and the following disclaimer.\r
+       2. Redistributions in binary form must reproduce the above copyright\r
+          notice, this list of conditions and the following disclaimer in the\r
+          documentation and/or other materials provided with the distribution.\r
+       3. The name of the author may not be used to endorse or promote products\r
+          derived from this software without specific prior written permission.\r
+\r
+       THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\r
+       IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
+       OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
+       IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+       NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+       DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+       THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
+       THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+*/\r
+\r
+\r
+/**\r
+       Definitions of structures of standard USB packets\r
+*/\r
+\r
+#ifndef _USBSTRUCT_H_\r
+#define _USBSTRUCT_H_\r
+\r
+// CodeRed - include the LPCUSB type.h file rather than NXP one directly\r
+#include "type.h"\r
+\r
+/** setup packet definitions */\r
+typedef struct {\r
+       unsigned char   bmRequestType;                  /**< characteristics of the specific request */\r
+       unsigned char   bRequest;                               /**< specific request */\r
+       unsigned short  wValue;                                 /**< request specific parameter */\r
+       unsigned short  wIndex;                                 /**< request specific parameter */\r
+       unsigned short  wLength;                                /**< length of data transfered in data phase */\r
+} TSetupPacket;\r
+\r
+\r
+#define REQTYPE_GET_DIR(x)             (((x)>>7)&0x01)\r
+#define REQTYPE_GET_TYPE(x)            (((x)>>5)&0x03)\r
+#define REQTYPE_GET_RECIP(x)   ((x)&0x1F)\r
+\r
+#define REQTYPE_DIR_TO_DEVICE  0\r
+#define REQTYPE_DIR_TO_HOST            1\r
+\r
+#define REQTYPE_TYPE_STANDARD  0\r
+#define REQTYPE_TYPE_CLASS             1\r
+#define REQTYPE_TYPE_VENDOR            2\r
+#define REQTYPE_TYPE_RESERVED  3\r
+\r
+#define REQTYPE_RECIP_DEVICE   0\r
+#define REQTYPE_RECIP_INTERFACE        1\r
+#define REQTYPE_RECIP_ENDPOINT 2\r
+#define REQTYPE_RECIP_OTHER            3\r
+\r
+/* standard requests */\r
+#define        REQ_GET_STATUS                  0x00\r
+#define REQ_CLEAR_FEATURE              0x01\r
+#define REQ_SET_FEATURE                        0x03\r
+#define REQ_SET_ADDRESS                        0x05\r
+#define REQ_GET_DESCRIPTOR             0x06\r
+#define REQ_SET_DESCRIPTOR             0x07\r
+#define REQ_GET_CONFIGURATION  0x08\r
+#define REQ_SET_CONFIGURATION  0x09\r
+#define REQ_GET_INTERFACE              0x0A\r
+#define REQ_SET_INTERFACE              0x0B\r
+#define REQ_SYNCH_FRAME                        0x0C\r
+\r
+/* class requests HID */\r
+#define HID_GET_REPORT                 0x01\r
+#define HID_GET_IDLE                   0x02\r
+#define HID_GET_PROTOCOL               0x03\r
+#define HID_SET_REPORT                 0x09\r
+#define HID_SET_IDLE                   0x0A\r
+#define HID_SET_PROTOCOL               0x0B\r
+\r
+/* feature selectors */\r
+#define FEA_ENDPOINT_HALT              0x00\r
+#define FEA_REMOTE_WAKEUP              0x01\r
+#define FEA_TEST_MODE                  0x02\r
+\r
+/*\r
+       USB descriptors\r
+*/\r
+\r
+/** USB descriptor header */\r
+typedef struct {\r
+       unsigned char   bLength;                        /**< descriptor length */\r
+       unsigned char   bDescriptorType;        /**< descriptor type */\r
+} TUSBDescHeader;\r
+\r
+#define DESC_DEVICE                            1\r
+#define DESC_CONFIGURATION             2\r
+#define DESC_STRING                            3\r
+#define DESC_INTERFACE                 4\r
+#define DESC_ENDPOINT                  5\r
+#define DESC_DEVICE_QUALIFIER  6\r
+#define DESC_OTHER_SPEED               7\r
+#define DESC_INTERFACE_POWER   8\r
+\r
+#define DESC_HID_HID                   0x21\r
+#define DESC_HID_REPORT                        0x22\r
+#define DESC_HID_PHYSICAL              0x23\r
+\r
+#define GET_DESC_TYPE(x)               (((x)>>8)&0xFF)\r
+#define GET_DESC_INDEX(x)              ((x)&0xFF)\r
+\r
+#endif /* _USBSTRUCT_H_ */\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/ParTest.c b/Demo/CORTEX_LPC1768_IAR/ParTest.c
new file mode 100644 (file)
index 0000000..e642437
--- /dev/null
@@ -0,0 +1,138 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under\r
+       the terms of the GNU General Public License (version 2) as published by the\r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the\r
+       source code for proprietary components outside of the FreeRTOS kernel.\r
+       Alternative commercial license and support terms are also available upon\r
+       request.  See the licensing section of http://www.FreeRTOS.org for full\r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/* FreeRTOS.org includes. */\r
+#include "FreeRTOS.h"\r
+\r
+/* Demo application includes. */\r
+#include "partest.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+#define partstNUM_LEDS                 ( 1 )\r
+#define partstLED_OUTPUT               ( 1 << 25 )\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       /* Only one LED on P1.25. */\r
+    GPIO1->FIODIR  = partstLED_OUTPUT;\r
+\r
+       /* Start with LED off. */\r
+    GPIO1->FIOSET = partstLED_OUTPUT;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLEDIn, signed long xValue )\r
+{\r
+       /* Used to set and clear LEDs on FIO2. */\r
+\r
+       if( ulLEDIn < partstNUM_LEDS )\r
+       {\r
+               /* Set of clear the output. */\r
+               if( xValue )\r
+               {\r
+                       GPIO1->FIOCLR = partstLED_OUTPUT;\r
+               }\r
+               else\r
+               {\r
+                       GPIO1->FIOSET = partstLED_OUTPUT;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLEDIn )\r
+{\r
+unsigned long ulCurrentState;\r
+\r
+       /* Used to toggle LEDs on FIO2. */\r
+\r
+       if( ulLEDIn < partstNUM_LEDS )\r
+       {\r
+               /* If this bit is already set, clear it, and visa versa. */\r
+               ulCurrentState = GPIO1->FIOPIN;\r
+               if( ulCurrentState & partstLED_OUTPUT )\r
+               {\r
+                       GPIO1->FIOCLR = partstLED_OUTPUT;\r
+               }\r
+               else\r
+               {\r
+                       GPIO1->FIOSET = partstLED_OUTPUT;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+long lParTestGetLEDState( void )\r
+{\r
+       if( ( GPIO1->FIOPIN & partstLED_OUTPUT ) != 0 )\r
+       {\r
+               return pdFALSE;\r
+       }\r
+       else\r
+       {\r
+               return pdTRUE;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLEDState( long lState )\r
+{\r
+       /* Used to set and clear the LEDs on FIO1. */\r
+       if( lState != pdFALSE )\r
+       {\r
+               GPIO1->FIOSET = partstLED_OUTPUT;\r
+       }\r
+       else\r
+       {\r
+               GPIO1->FIOCLR = partstLED_OUTPUT;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewd b/Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewd
new file mode 100644 (file)
index 0000000..da9d540
--- /dev/null
@@ -0,0 +1,1387 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state>$PROJ_DIR$\Flash.mac</state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\debugger\NXP\iolpc1768.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.40.0.51529</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>5.40.0.51529</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashNXPLPC512K_Cortex.board</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommunication</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>10</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>5.40.0.51529</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>ARMSIM_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CLowLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CDevice</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoadersV3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck1</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesSuppressCheck3</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCImagesPath3</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OverrideDefFlashBoard</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimEnablePSP</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspOverrideConfig</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCSimPspConfigFile</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>GDBSERVER_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommunication</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>10</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCJLinkAttachSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetList</name>\r
+          <version>0</version>\r
+          <state>5</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>LMIFTDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>2</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>LmiftdiSpeed</name>\r
+          <state>500</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiftdiLogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLmiFtdiInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>3</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJTagUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorInterfaceCmdLine</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>STLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>###Uninitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$PROJ_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\FreeRTOS\FreeRTOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewp b/Demo/CORTEX_LPC1768_IAR/RTOSDemo.ewp
new file mode 100644 (file)
index 0000000..44825cf
--- /dev/null
@@ -0,0 +1,1700 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>17</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Debug\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Debug\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Debug\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>11</version>\r
+          <state>35</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath</name>\r
+          <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>5.40.0.51529</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>LPC1768       NXP LPC1768</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>PACK_STRUCT_END=</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state>Pe550, Pa082, Pa039</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>0000000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state>$PROJ_DIR$\..\common\include</state>\r
+          <state>$PROJ_DIR$\..\..\source\include</state>\r
+          <state>$PROJ_DIR$\..\..\source\portable\iar\arm_cm3</state>\r
+          <state>$PROJ_DIR$</state>\r
+          <state>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip</state>\r
+          <state>$PROJ_DIR$\lpcusb</state>\r
+          <state>$PROJ_DIR$\webserver</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncludePath</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>7</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AStdIncludes</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state>$PROJ_DIR$</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>c.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>RTOSDemo.out</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$PROJ_DIR$\LPC1768_Flash.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state>__iar_program_start</state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <configuration>\r
+    <name>Release</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>0</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <version>17</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>Release\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>Release\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>Release\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>11</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>Full formatting.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath</name>\r
+          <state>$TOOLKIT_DIR$\INC\DLib_Config_Normal.h</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>5.10.0.159</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>default       None</state>\r
+        </option>\r
+        <option>\r
+          <name>GenLowLevelInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianModeBE</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGBufferedTerminalOutput</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GenStdoutInterface</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>21</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>NDEBUG</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssSource</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagSuppress</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagRemark</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarning</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagError</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCAllowList</name>\r
+          <version>1</version>\r
+          <state>1111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDebugInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IEndianMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangConformance</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCSignedPlainChar</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRequirePrototypes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDiagWarnAreErr</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCompilerRuntimeInfo</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLangSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCLibConfigHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>PreInclude</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCIncludePath2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCStdIncludePath</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>CCCodeSection</name>\r
+          <state>.text</state>\r
+        </option>\r
+        <option>\r
+          <name>IInterwork2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IProcessorMode2</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevel</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptStrategy</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCOptLevelSlave</name>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules98</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>CompilerMisraRules04</name>\r
+          <version>0</version>\r
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>AARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>7</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>AObjPrefix</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ACaseSensitivity</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacroChars</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnWhat</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnOne</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange1</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AWarnRange2</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>ADebug</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AltRegisterNames</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ADefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AList</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AListHeader</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AListing</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>Includes</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacDefs</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExps</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>MacExec</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OnlyAssed</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MultiLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLengthCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>PageLength</name>\r
+          <state>80</state>\r
+        </option>\r
+        <option>\r
+          <name>TabSpacing</name>\r
+          <state>8</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDefines</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefInternal</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AXRefDual</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>AOutputFile</name>\r
+          <state>$FILE_BNAME$.o</state>\r
+        </option>\r
+        <option>\r
+          <name>AMultibyteSupport</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ALimitErrorsEdit</name>\r
+          <state>100</state>\r
+        </option>\r
+        <option>\r
+          <name>AIgnoreStdInclude</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AStdIncludes</name>\r
+          <state>$TOOLKIT_DIR$\INC\</state>\r
+        </option>\r
+        <option>\r
+          <name>AUserIncludes</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsCheckV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AExtraOptionsV2</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>OBJCOPY</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>OOCOutputFormat</name>\r
+          <version>2</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCOutputOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCOutputFile</name>\r
+          <state>c.srec</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCCommandLineProducer</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OOCObjCopyEnable</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>CUSTOM</name>\r
+      <archiveVersion>3</archiveVersion>\r
+      <data>\r
+        <extensions></extensions>\r
+        <cmdline></cmdline>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BICOMP</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+    <settings>\r
+      <name>BUILDACTION</name>\r
+      <archiveVersion>1</archiveVersion>\r
+      <data>\r
+        <prebuild></prebuild>\r
+        <postbuild></postbuild>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>8</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>IlinkOutputFile</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLibIOConfig</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>XLinkMisraHandler</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkInputFileSlave</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDebugInfoEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkKeepSymbols</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySymbol</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinarySegment</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkRawBinaryAlign</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkConfigDefines</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkMapFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogInitialization</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogModule</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogSection</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLogVeneer</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\generic.icf</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIcfFileSlave</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkEnableRemarks</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkSuppressDiags</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsRem</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsWarn</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkTreatAsErr</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkWarningsAreErrors</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkUseExtraOptions</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkLowLevelInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAutoLibEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkAdditionalLibs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkOverrideProgramEntryLabel</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabelSelect</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkProgramEntryLabel</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>DoFill</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerByte</name>\r
+          <state>0xFF</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerStart</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>FillerEnd</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcSize</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlign</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcAlgo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcPoly</name>\r
+          <state>0x11021</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcCompl</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcBitOrder</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcInitialValue</name>\r
+          <state>0x0</state>\r
+        </option>\r
+        <option>\r
+          <name>DoCrc</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBE8Slave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkBufferedTerminalOutput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkStdoutInterfaceSlave</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CrcFullSize</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IlinkIElfToolPostProcess</name>\r
+          <state>0</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARCHIVE</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>0</debug>\r
+        <option>\r
+          <name>IarchiveInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>IarchiveOutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>Common Demo Tasks</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\BlockQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\blocktim.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\flash.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\GenQTest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\integer.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\PollQ.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\QPeek.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\recmutex.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\semtest.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>FreeRTOS</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>LPCUSB</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\LPCUSB\USB_CDC.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\LPCUSB\usbcontrol.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\LPCUSB\usbhw_lpc.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\LPCUSB\usbinit.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\LPCUSB\usbstdreq.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>WEB Server</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\emac.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\http-strings.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\httpd-cgi.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\httpd-fs.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\httpd.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\webserver\uIP_Task.c</name>\r
+    </file>\r
+  </group>\r
+  <file>\r
+    <name>$PROJ_DIR$\cstartup_M.s</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\main.c</name>\r
+  </file>\r
+  <file>\r
+    <name>$PROJ_DIR$\ParTest.c</name>\r
+  </file>\r
+</project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/RTOSDemo.eww b/Demo/CORTEX_LPC1768_IAR/RTOSDemo.eww
new file mode 100644 (file)
index 0000000..239a938
--- /dev/null
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/core_cm3.h b/Demo/CORTEX_LPC1768_IAR/core_cm3.h
new file mode 100644 (file)
index 0000000..b6f9696
--- /dev/null
@@ -0,0 +1,1367 @@
+/******************************************************************************\r
+ * @file:    core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.20\r
+ * @date:    22. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */\r
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */\r
+\r
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */\r
+\r
+/**\r
+ *  Lint configuration \n\r
+ *  ----------------------- \n\r
+ *\r
+ *  The following Lint messages will be suppressed and not shown: \n\r
+ *  \n\r
+ *    --- Error 10: --- \n\r
+ *    register uint32_t __regBasePri         __asm("basepri"); \n\r
+ *    Error 10: Expecting ';' \n\r
+ *     \n\r
+ *    --- Error 530: --- \n\r
+ *    return(__regBasePri); \n\r
+ *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ *     \n\r
+ *    --- Error 550: --- \n\r
+ *      __regBasePri = (basePri & 0x1ff); \n\r
+ *    } \n\r
+ *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ *     \n\r
+ *    --- Error 754: --- \n\r
+ *    uint32_t RESERVED0[24]; \n\r
+ *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 750: --- \n\r
+ *    #define __CM3_CORE_H__ \n\r
+ *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 528: --- \n\r
+ *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ *     \n\r
+ *    --- Error 751: --- \n\r
+ *    } InterruptType_Type; \n\r
+ *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ *    Note:  To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10  */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h>                           /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+  #include <intrinsics.h>                     /* IAR Intrinsics   */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#define     __I     volatile                  /*!< defines 'read only' permissions      */\r
+#else\r
+#define     __I     volatile const            /*!< defines 'read only' permissions      */\r
+#endif\r
+#define     __O     volatile                  /*!< defines 'write only' permissions     */\r
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                 Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */\r
+#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */\r
+#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */\r
+#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */\r
+#define ITM_TCR_ITMENA              1         /*!< ITM enable                   */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+  __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */\r
+       uint32_t RESERVED0[24];\r
+  __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */\r
+       uint32_t RSERVED1[24];\r
+  __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */\r
+       uint32_t RESERVED2[24];\r
+  __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */\r
+       uint32_t RESERVED3[24];\r
+  __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */\r
+       uint32_t RESERVED4[56];\r
+  __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */\r
+       uint32_t RESERVED5[644];\r
+  __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */\r
+}  NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */\r
+  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */\r
+  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */\r
+  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */\r
+  __IO uint32_t SCR;                          /*!< System Control Register                                  */\r
+  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */\r
+  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */\r
+  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */\r
+  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */\r
+  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */\r
+  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */\r
+  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */\r
+  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */\r
+  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */\r
+  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */\r
+  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */\r
+  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */\r
+  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */\r
+  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */\r
+  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */\r
+  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */\r
+  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+  __O  union  \r
+  {\r
+    __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */\r
+    __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */\r
+    __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */\r
+  }  PORT [32];                               /*!< ITM Stimulus Port Registers           */\r
+       uint32_t RESERVED0[864];\r
+  __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */\r
+       uint32_t RESERVED1[15];\r
+  __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */\r
+       uint32_t RESERVED2[15];\r
+  __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */\r
+       uint32_t RESERVED3[29];\r
+  __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */\r
+  __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */\r
+  __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */\r
+       uint32_t RESERVED4[43];\r
+  __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */\r
+  __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */\r
+       uint32_t RESERVED5[6];\r
+  __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */\r
+  __I  uint32_t PID5;\r
+  __I  uint32_t PID6;\r
+  __I  uint32_t PID7;\r
+  __I  uint32_t PID0;\r
+  __I  uint32_t PID1;\r
+  __I  uint32_t PID2;\r
+  __I  uint32_t PID3;\r
+  __I  uint32_t CID0;\r
+  __I  uint32_t CID1;\r
+  __I  uint32_t CID2;\r
+  __I  uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+       uint32_t RESERVED0;\r
+  __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+  __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */\r
+#else\r
+       uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+  __I  uint32_t TYPE;                         /*!< MPU Type Register                               */\r
+  __IO uint32_t CTRL;                         /*!< MPU Control Register                            */\r
+  __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */\r
+  __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */\r
+  __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */\r
+  __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */\r
+  __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */\r
+  __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */\r
+  __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */\r
+  __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */\r
+  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */\r
+  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */\r
+  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */\r
+#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */\r
+#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */\r
+#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */\r
+#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */\r
+#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */\r
+\r
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */\r
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */\r
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */\r
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */\r
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */\r
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */\r
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */\r
+#endif\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ *                Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM   )\r
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */\r
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */\r
+\r
+#elif defined ( __ICCARM__ )\r
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */\r
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined   (  __GNUC__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\r
+\r
+#elif defined   (  __TASKING__  )\r
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */\r
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */\r
+\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+\r
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq                __enable_fiq\r
+#define __disable_fault_irq               __disable_fiq\r
+\r
+#define __NOP                             __nop\r
+#define __WFI                             __wfi\r
+#define __WFE                             __wfe\r
+#define __SEV                             __sev\r
+#define __ISB()                           __isb(0)\r
+#define __DSB()                           __dsb(0)\r
+#define __DMB()                           __dmb(0)\r
+#define __REV                             __rev\r
+#define __RBIT                            __rbit\r
+#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))\r
+#define __STREXB(value, ptr)              __strex(value, ptr)\r
+#define __STREXH(value, ptr)              __strex(value, ptr)\r
+#define __STREXW(value, ptr)              __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq();     */\r
+/* intrinsic void __disable_irq();    */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else  /* (__ARMCC_VERSION >= 400000)  */\r
+\r
+\r
+/**\r
+ * @brief  Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX                           __clrex\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t  __get_BASEPRI(void)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+  register uint32_t __regBasePri         __ASM("basepri");\r
+  __regBasePri = (basePri & 0x1ff);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  register uint32_t __regPriMask         __ASM("primask");\r
+  __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  register uint32_t __regFaultMask       __ASM("faultmask");\r
+  __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+ * \r
+ * @param  none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  register uint32_t __regControl         __ASM("control");\r
+  __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION  */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */\r
+#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }\r
+\r
+#define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE  void __WFI()                     { __ASM ("wfi"); }\r
+static __INLINE  void __WFE()                     { __ASM ("wfe"); }\r
+static __INLINE  void __SEV()                     { __ASM ("sev"); }\r
+static __INLINE  void __CLREX()                   { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void)                                     */\r
+/* intrinsic void __DSB(void)                                     */\r
+/* intrinsic void __DMB(void)                                     */\r
+/* intrinsic void __set_PRIMASK();                                */\r
+/* intrinsic void __get_PRIMASK();                                */\r
+/* intrinsic void __set_FAULTMASK();                              */\r
+/* intrinsic void __get_FAULTMASK();                              */\r
+/* intrinsic uint32_t __REV(uint32_t value);                      */\r
+/* intrinsic uint32_t __REVSH(uint32_t value);                    */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *);              */\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP()                      { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV()                      { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB()                      { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief  Return the Process Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief  Set the Process Stack Pointer\r
+ *\r
+ * @param  uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief  Return the Main Stack Pointer\r
+ *\r
+ * @param  none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief  Set the Main Stack Pointer\r
+ *\r
+ * @param  uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief  Return the Base Priority value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief  Set the Base Priority value\r
+ *\r
+ * @param  uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief  Return the Priority Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t  __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Priority Mask value\r
+ *\r
+ * @param  uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief  Return the Fault Mask value\r
+ *\r
+ * @param  none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief  Set the Fault Mask value\r
+ *\r
+ * @param  uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief  Return the Control Register value\r
+* \r
+*  @param  none\r
+*  @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief  Set the Control Register value\r
+ *\r
+ * @param  uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief  Reverse byte order in integer value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief  Reverse byte order in unsigned short value\r
+ *\r
+ * @param  uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param  int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * @brief  Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief  Reverse bit order of value\r
+ *\r
+ * @param  uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief  LDR Exclusive\r
+ *\r
+ * @param  uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint8_t *address\r
+ * @param  uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint16_t *address\r
+ * @param  uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief  STR Exclusive\r
+ *\r
+ * @param  uint32_t *address\r
+ * @param  uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ##########################   NVIC functions  #################################### */\r
+\r
+\r
+/**\r
+ * @brief  Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param  uint32_t priority_grouping is priority grouping field\r
+ * @return none \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+  uint32_t reg_value;\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  \r
+  reg_value  = SCB->AIRCR;                                                    /* read old register configuration    */\r
+  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                              /* clear bits to change               */\r
+  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8)));  /* Insert write key and priorty group */\r
+  SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief  Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @param  none\r
+ * @return uint32_t   priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+  return ((SCB->AIRCR >> 8) & 0x07);                                          /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief  Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param  IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param  IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param  IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return uint32_t 1 if pending interrupt else 0\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the pending bit for an external interrupt\r
+ * \r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief  Clear the pending bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief  Read the active bit for an external interrupt\r
+ *\r
+ * @param  IRQn_Type  IRQn is the Number of the interrupt\r
+ * @return uint32_t   1 if active else 0\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief  Set the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @param  priority is the priority for the interrupt\r
+ * @return none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+  if(IRQn < 0) {\r
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+  else {\r
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts      */\r
+}\r
+\r
+/**\r
+ * @brief  Read the priority for an interrupt\r
+ *\r
+ * @param  IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t  priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+  if(IRQn < 0) {\r
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */\r
+  else {\r
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Encode the priority for an interrupt\r
+ *\r
+ * @param  uint32_t PriorityGroup   is the used priority group\r
+ * @param  uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
+ * @param  uint32_t SubPriority     is the sub priority value (starting from 0)\r
+ * @return uint32_t                    the priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
\r
+  return (\r
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))\r
+         );\r
+}\r
+\r
+\r
+/**\r
+ * @brief  Decode the priority of an interrupt\r
+ *\r
+ * @param  uint32_t   Priority       the priority for the interrupt\r
+ * @param  uint32_t   PrioGroup   is the used priority group\r
+ * @param  uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
+ * @param  uint32_t* pSubPrio     is the sub priority value (starting from 0)\r
+ * @return none\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */\r
+  uint32_t PreemptPriorityBits;\r
+  uint32_t SubPriorityBits;\r
+\r
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+  \r
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ##################################    SysTick function  ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */\r
+#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */\r
+#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */\r
+#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */\r
+\r
+/**\r
+ * @brief  Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param  uint32_t ticks is the number of ticks between two interrupts\r
+ * @return  none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                             /* Reload value impossible */\r
+\r
+  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                      /* set reload register */\r
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                            /* set Priority for Cortex-M0 System Interrupts */\r
+  SysTick->VAL   =  (0x00);                                                              /* Load the SysTick Counter Value */\r
+  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
+  return (0);                                                                            /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ##################################    Reset function  ############################################ */\r
+\r
+/**\r
+ * @brief  Initiate a system reset request.\r
+ *\r
+ * @param   none\r
+ * @return  none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
+  __DSB();                                                                             /* Ensure completion of memory access */              \r
+  while(1);                                                                            /* wait until reset */\r
+}\r
+\r
+\r
+/* ##################################    Debug Output  function  ############################################ */\r
+\r
+\r
+/**\r
+ * @brief  Outputs a character via the ITM channel 0\r
+ *\r
+ * @param   uint32_t character to output\r
+ * @return  uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output.  \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+  if (ch == '\n') ITM_SendChar('\r');\r
+  \r
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&\r
+      (ITM->TCR & ITM_TCR_ITMENA)                  &&\r
+      (ITM->TER & (1UL << 0))  ) \r
+  {\r
+    while (ITM->PORT[0].u32 == 0);\r
+    ITM->PORT[0].u8 = (uint8_t) ch;\r
+  }  \r
+  return (ch);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/cstartup_M.s b/Demo/CORTEX_LPC1768_IAR/cstartup_M.s
new file mode 100644 (file)
index 0000000..e8be5f6
--- /dev/null
@@ -0,0 +1,271 @@
+/**************************************************\r
+ *\r
+ * Part one of the system initialization code, contains low-level\r
+ * initialization, plain thumb variant.\r
+ *\r
+ * Copyright 2009 IAR Systems. All rights reserved.\r
+ *\r
+ * $Revision: 28532 $\r
+ *\r
+ **************************************************/\r
+\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; The vector table is normally located at address 0.\r
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\r
+; The name "__vector_table" has special meaning for C-SPY:\r
+; it is where the SP start value is found, and the NVIC vector\r
+; table register (VTOR) is initialized to this address if != 0.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+        MODULE  ?cstartup\r
+\r
+        ;; Forward declaration of sections.\r
+        SECTION CSTACK:DATA:NOROOT(3)\r
+\r
+        SECTION .intvec:CODE:NOROOT(2)\r
+\r
+        EXTERN  __iar_program_start\r
+               EXTERN xPortPendSVHandler\r
+               EXTERN xPortSysTickHandler\r
+               EXTERN vPortSVCHandler\r
+               EXTERN vEMAC_ISR\r
+        PUBLIC  __vector_table\r
+        PUBLIC  __vector_table_0x1c\r
+\r
+        DATA\r
+__vector_table\r
+        DCD     sfe(CSTACK)                 ; Top of Stack\r
+        DCD     __iar_program_start         ; Reset Handler\r
+        DCD     NMI_Handler                 ; NMI Handler\r
+        DCD     HardFault_Handler           ; Hard Fault Handler\r
+        DCD     MemManage_Handler           ; MPU Fault Handler\r
+        DCD     BusFault_Handler            ; Bus Fault Handler\r
+        DCD     UsageFault_Handler          ; Usage Fault Handler\r
+__vector_table_0x1c\r
+        DCD     0                           ; Reserved\r
+        DCD     0                           ; Reserved\r
+        DCD     0                           ; Reserved\r
+        DCD     0                           ; Reserved\r
+        DCD     vPortSVCHandler             ; SVCall Handler\r
+        DCD     DebugMon_Handler            ; Debug Monitor Handler\r
+        DCD     0                           ; Reserved\r
+        DCD     xPortPendSVHandler          ; PendSV Handler\r
+        DCD     xPortSysTickHandler         ; SysTick Handler\r
+        DCD     WDT_IRQHandler              ; Watchdog Handler\r
+        DCD     TMR0_IRQHandler             ; TIMER0 Handler\r
+        DCD     TMR1_IRQHandler             ; TIMER1 Handler\r
+        DCD     TMR2_IRQHandler             ; TIMER2 Handler\r
+        DCD     TMR3_IRQHandler             ; TIMER3 Handler\r
+        DCD     UART0_IRQHandler            ; UART0 Handler\r
+        DCD     UART1_IRQHandler            ; UART1 Handler\r
+        DCD     UART2_IRQHandler            ; UART2 Handler\r
+        DCD     UART3_IRQHandler            ; UART3 Handler\r
+        DCD     PWM1_IRQHandler             ; PWM1 Handler\r
+        DCD     I2C0_IRQHandler             ; I2C0 Handler\r
+        DCD     I2C1_IRQHandler             ; I2C1 Handler\r
+        DCD     I2C2_IRQHandler             ; I2C2 Handler\r
+        DCD     SPI_IRQHandler              ; SPI Handler\r
+        DCD     SSP0_IRQHandler             ; SSP0 Handler\r
+        DCD     SSP1_IRQHandler             ; SSP1 Handler\r
+        DCD     PLL0_IRQHandler             ; PLL0 Handler\r
+        DCD     RTC_IRQHandler              ; RTC Handler\r
+        DCD     EINT0_IRQHandler            ; EXT Interupt 0 Handler\r
+        DCD     EINT1_IRQHandler            ; EXT Interupt 1 Handler\r
+        DCD     EINT2_IRQHandler            ; EXT Interupt 2 Handler\r
+        DCD     EINT3_IRQHandler            ; EXT Interupt 3 Handler\r
+        DCD     ADC_IRQHandler              ; ADC Handler\r
+        DCD     BOD_IRQHandler              ; BOD Handler\r
+        DCD     USB_IRQHandler              ; USB Handler\r
+        DCD     CAN_IRQHandler              ; CAN Handler\r
+        DCD     GPDMA_IRQHandler            ; General Purpose DMA Handler\r
+        DCD     I2S_IRQHandler              ; I2S Handler\r
+        DCD     vEMAC_ISR                              ; Ethernet Handler\r
+        DCD     RIT_IRQHandler              ; Repetitive Interrupt Timer Handler\r
+        DCD     MotorControlPWM_IRQHandler  ; Motor Control PWM Handler\r
+        DCD     QE_IRQHandler               ; Quadrature Encoder Handler\r
+        DCD     PLL1_IRQHandler             ; PLL1 Handler\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+        THUMB\r
+\r
+        PUBWEAK NMI_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+NMI_Handler\r
+        B NMI_Handler\r
+        PUBWEAK HardFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+HardFault_Handler\r
+        B HardFault_Handler\r
+        PUBWEAK MemManage_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+MemManage_Handler\r
+        B MemManage_Handler\r
+        PUBWEAK BusFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+BusFault_Handler\r
+        B BusFault_Handler\r
+        PUBWEAK UsageFault_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+UsageFault_Handler\r
+        B UsageFault_Handler\r
+        PUBWEAK SVC_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SVC_Handler\r
+        B SVC_Handler\r
+        PUBWEAK DebugMon_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+DebugMon_Handler\r
+        B DebugMon_Handler\r
+        PUBWEAK PendSV_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+PendSV_Handler\r
+        B PendSV_Handler\r
+        PUBWEAK SysTick_Handler\r
+        SECTION .text:CODE:REORDER(1)\r
+SysTick_Handler\r
+        B SysTick_Handler\r
+        PUBWEAK WDT_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+WDT_IRQHandler\r
+        B WDT_IRQHandler\r
+        PUBWEAK TMR0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TMR0_IRQHandler\r
+        B TMR0_IRQHandler\r
+        PUBWEAK TMR1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TMR1_IRQHandler\r
+        B TMR1_IRQHandler\r
+        PUBWEAK TMR2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TMR2_IRQHandler\r
+        B TMR2_IRQHandler\r
+        PUBWEAK TMR3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+TMR3_IRQHandler\r
+        B TMR3_IRQHandler\r
+        PUBWEAK UART0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+UART0_IRQHandler\r
+        B UART0_IRQHandler\r
+        PUBWEAK UART1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+UART1_IRQHandler\r
+        B UART1_IRQHandler\r
+        PUBWEAK UART2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+UART2_IRQHandler\r
+        B UART2_IRQHandler\r
+        PUBWEAK UART3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+UART3_IRQHandler\r
+        B UART3_IRQHandler\r
+        PUBWEAK PWM1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PWM1_IRQHandler\r
+        B PWM1_IRQHandler\r
+        PUBWEAK I2C0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C0_IRQHandler\r
+        B I2C0_IRQHandler\r
+        PUBWEAK I2C1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C1_IRQHandler\r
+        B I2C1_IRQHandler\r
+        PUBWEAK I2C2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2C2_IRQHandler\r
+        B I2C2_IRQHandler\r
+        PUBWEAK SPI_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SPI_IRQHandler\r
+        B SPI_IRQHandler\r
+        PUBWEAK SSP0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SSP0_IRQHandler\r
+        B SSP0_IRQHandler\r
+        PUBWEAK SSP1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+SSP1_IRQHandler\r
+        B SSP1_IRQHandler\r
+        PUBWEAK PLL0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PLL0_IRQHandler\r
+        B PLL0_IRQHandler\r
+        PUBWEAK RTC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RTC_IRQHandler\r
+        B RTC_IRQHandler\r
+        PUBWEAK EINT0_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EINT0_IRQHandler\r
+        B EINT0_IRQHandler\r
+        PUBWEAK EINT1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EINT1_IRQHandler\r
+        B EINT1_IRQHandler\r
+        PUBWEAK EINT2_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EINT2_IRQHandler\r
+        B EINT2_IRQHandler\r
+        PUBWEAK EINT3_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+EINT3_IRQHandler\r
+        B EINT3_IRQHandler\r
+        PUBWEAK ADC_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+ADC_IRQHandler\r
+        B ADC_IRQHandler\r
+        PUBWEAK BOD_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+BOD_IRQHandler\r
+        B BOD_IRQHandler\r
+        PUBWEAK USB_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+USB_IRQHandler\r
+        B USB_IRQHandler\r
+        PUBWEAK CAN_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+CAN_IRQHandler\r
+        B CAN_IRQHandler\r
+        PUBWEAK GPDMA_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+GPDMA_IRQHandler\r
+        B GPDMA_IRQHandler\r
+        PUBWEAK I2S_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+I2S_IRQHandler\r
+        B I2S_IRQHandler\r
+        PUBWEAK Ethernet_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+Ethernet_IRQHandler\r
+        B Ethernet_IRQHandler\r
+        PUBWEAK RIT_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+RIT_IRQHandler\r
+        B RIT_IRQHandler\r
+        PUBWEAK MotorControlPWM_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+MotorControlPWM_IRQHandler\r
+        B MotorControlPWM_IRQHandler\r
+        PUBWEAK QE_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+QE_IRQHandler\r
+        B QE_IRQHandler\r
+        PUBWEAK PLL1_IRQHandler\r
+        SECTION .text:CODE:REORDER(1)\r
+PLL1_IRQHandler\r
+        B PLL1_IRQHandler\r
+\r
+        END\r
diff --git a/Demo/CORTEX_LPC1768_IAR/main.c b/Demo/CORTEX_LPC1768_IAR/main.c
new file mode 100644 (file)
index 0000000..6074eda
--- /dev/null
@@ -0,0 +1,369 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under\r
+       the terms of the GNU General Public License (version 2) as published by the\r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the\r
+       source code for proprietary components outside of the FreeRTOS kernel.\r
+       Alternative commercial license and support terms are also available upon\r
+       request.  See the licensing section of http://www.FreeRTOS.org for full\r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * Creates all the demo application tasks, then starts the scheduler.  The WEB\r
+ * documentation provides more details of the standard demo application tasks\r
+ * (which just exist to test the kernel port and provide an example of how to use\r
+ * each FreeRTOS API function).\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and tests are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Check" hook -  This only executes fully every five seconds from the tick\r
+ * hook.  Its main function is to check that all the standard demo tasks are\r
+ * still operational.  The status can be viewed using on the Task Stats page\r
+ * served by the WEB server.\r
+ *\r
+ * "uIP" task -  This is the task that handles the uIP stack.  All TCP/IP\r
+ * processing is performed in this task.\r
+ *\r
+ * "USB" task - Enumerates the USB device as a CDC class, then echoes back all\r
+ * received characters with a configurable offset (for example, if the offset\r
+ * is 1 and 'A' is received then 'B' will be sent back).  A dumb terminal such\r
+ * as Hyperterminal can be used to talk to the USB task.\r
+ */\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo app includes. */\r
+#include "BlockQ.h"\r
+#include "integer.h"\r
+#include "blocktim.h"\r
+#include "flash.h"\r
+#include "partest.h"\r
+#include "semtest.h"\r
+#include "PollQ.h"\r
+#include "GenQTest.h"\r
+#include "QPeek.h"\r
+#include "recmutex.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The time between cycles of the 'check' functionality (defined within the\r
+tick hook). */\r
+#define mainCHECK_DELAY                                                ( ( portTickType ) 5000 / portTICK_RATE_MS )\r
+\r
+/* Task priorities. */\r
+#define mainQUEUE_POLL_PRIORITY                                ( tskIDLE_PRIORITY + 2 )\r
+#define mainSEM_TEST_PRIORITY                          ( tskIDLE_PRIORITY + 1 )\r
+#define mainBLOCK_Q_PRIORITY                           ( tskIDLE_PRIORITY + 2 )\r
+#define mainUIP_TASK_PRIORITY                          ( tskIDLE_PRIORITY + 3 )\r
+#define mainINTEGER_TASK_PRIORITY           ( tskIDLE_PRIORITY )\r
+#define mainGEN_QUEUE_TASK_PRIORITY                    ( tskIDLE_PRIORITY )\r
+\r
+/* The WEB server has a larger stack as it utilises stack hungry string\r
+handling library calls. */\r
+#define mainBASIC_WEB_STACK_SIZE            ( configMINIMAL_STACK_SIZE * 4 )\r
+\r
+/* The message displayed by the WEB server when all tasks are executing\r
+without an error being reported. */\r
+#define mainPASS_STATUS_MESSAGE                                "All tasks are executing without error."\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure the hardware for the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * The task that handles the uIP stack.  All TCP/IP processing is performed in\r
+ * this task.\r
+ */\r
+extern void vuIP_Task( void *pvParameters );\r
+\r
+/*\r
+ * The task that handles the USB stack.\r
+ */\r
+extern void vUSBTask( void *pvParameters );\r
+\r
+/*\r
+ * Simply returns the current status message for display on served WEB pages.\r
+ */\r
+char *pcGetTaskStatusMessage( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Holds the status message displayed by the WEB server. */\r
+static char *pcStatusMessage = mainPASS_STATUS_MESSAGE;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+       /* Configure the hardware for use by this demo. */\r
+       prvSetupHardware();\r
+\r
+       /* Start the standard demo tasks.  These are just here to exercise the\r
+       kernel port and provide examples of how the FreeRTOS API can be used. */\r
+       vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );\r
+    vCreateBlockTimeTasks();\r
+    vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );\r
+    vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );\r
+    vStartIntegerMathTasks( mainINTEGER_TASK_PRIORITY );\r
+    vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );\r
+    vStartQueuePeekTasks();\r
+    vStartRecursiveMutexTasks();\r
+\r
+    /* Create the USB task. */\r
+//    xTaskCreate( vUSBTask, ( signed char * ) "USB", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL );\r
+       \r
+       /* Create the uIP task.  The WEB server runs in this task. */\r
+    xTaskCreate( vuIP_Task, ( signed char * ) "uIP", mainBASIC_WEB_STACK_SIZE, ( void * ) NULL, mainUIP_TASK_PRIORITY, NULL );\r
+\r
+    /* Start the scheduler. */\r
+       vTaskStartScheduler();\r
+\r
+    /* Will only get here if there was insufficient memory to create the idle\r
+    task.  The idle task is created within vTaskStartScheduler(). */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+static unsigned portLONG ulTicksSinceLastDisplay = 0;\r
+\r
+       /* Called from every tick interrupt as described in the comments at the top\r
+       of this file.\r
+\r
+       Have enough ticks passed to make it     time to perform our health status\r
+       check again? */\r
+       ulTicksSinceLastDisplay++;\r
+       if( ulTicksSinceLastDisplay >= mainCHECK_DELAY )\r
+       {\r
+               /* Reset the counter so these checks run again in mainCHECK_DELAY\r
+               ticks time. */\r
+               ulTicksSinceLastDisplay = 0;\r
+\r
+               /* Has an error been found in any task? */\r
+               if( xAreGenericQueueTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "An error has been detected in the Generic Queue test/demo.";\r
+               }\r
+               else if( xAreQueuePeekTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "An error has been detected in the Peek Queue test/demo.";\r
+               }\r
+               else if( xAreBlockingQueuesStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "An error has been detected in the Block Queue test/demo.";\r
+               }\r
+               else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )\r
+               {\r
+                       pcStatusMessage = "An error has been detected in the Block Time test/demo.";\r
+               }\r
+           else if( xAreSemaphoreTasksStillRunning() != pdTRUE )\r
+           {\r
+               pcStatusMessage = "An error has been detected in the Semaphore test/demo.";\r
+           }\r
+           else if( xArePollingQueuesStillRunning() != pdTRUE )\r
+           {\r
+               pcStatusMessage = "An error has been detected in the Poll Queue test/demo.";\r
+           }\r
+           else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )\r
+           {\r
+               pcStatusMessage = "An error has been detected in the Int Math test/demo.";\r
+           }\r
+           else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )\r
+           {\r
+               pcStatusMessage = "An error has been detected in the Mutex test/demo.";\r
+           }\r
+               \r
+               vParTestToggleLED( 0 );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+char *pcGetTaskStatusMessage( void )\r
+{\r
+       /* Not bothered about a critical section here. */\r
+       return pcStatusMessage;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvSetupHardware( void )\r
+{\r
+       /* Disable peripherals power. */\r
+       SC->PCONP = 0;\r
+\r
+       /* Enable GPIO power. */\r
+       SC->PCONP = PCONP_PCGPIO;\r
+\r
+       /* Disable TPIU. */\r
+       PINCON->PINSEL10 = 0;\r
+\r
+       if ( SC->PLL0STAT & ( 1 << 25 ) )\r
+       {\r
+               /* Enable PLL, disconnected. */\r
+               SC->PLL0CON = 1;                        \r
+               SC->PLL0FEED = PLLFEED_FEED1;\r
+               SC->PLL0FEED = PLLFEED_FEED2;\r
+       }\r
+       \r
+       /* Disable PLL, disconnected. */\r
+       SC->PLL0CON = 0;                                \r
+       SC->PLL0FEED = PLLFEED_FEED1;\r
+       SC->PLL0FEED = PLLFEED_FEED2;\r
+       \r
+       /* Enable main OSC. */\r
+       SC->SCS |= 0x20;                        \r
+       while( !( SC->SCS & 0x40 ) );\r
+       \r
+       /* select main OSC, 12MHz, as the PLL clock source. */\r
+       SC->CLKSRCSEL = 0x1;            \r
+       \r
+       SC->PLL0CFG = 0x0b;\r
+       SC->PLL0FEED = PLLFEED_FEED1;\r
+       SC->PLL0FEED = PLLFEED_FEED2;\r
+       \r
+       /* Enable PLL, disconnected. */\r
+       SC->PLL0CON = 1;                                \r
+       SC->PLL0FEED = PLLFEED_FEED1;\r
+       SC->PLL0FEED = PLLFEED_FEED2;\r
+       \r
+       /* Set clock divider. */\r
+       SC->CCLKCFG = 0x03;\r
+       \r
+       /* Configure flash accelerator. */\r
+       SC->FLASHCFG = 0x303a;\r
+       \r
+       /* Check lock bit status. */\r
+       while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) );       \r
+       \r
+       /* Enable and connect. */\r
+       SC->PLL0CON = 3;                                \r
+       SC->PLL0FEED = PLLFEED_FEED1;\r
+       SC->PLL0FEED = PLLFEED_FEED2;\r
+       while( ( ( SC->PLL0STAT & ( 1 << 25 ) ) == 0 ) );       \r
+\r
+       \r
+       \r
+       \r
+       /* Configure the clock for the USB. */\r
+       \r
+       if( SC->PLL1STAT & ( 1 << 9 ) )\r
+       {\r
+               /* Enable PLL, disconnected. */\r
+               SC->PLL1CON = 1;                        \r
+               SC->PLL1FEED = PLLFEED_FEED1;\r
+               SC->PLL1FEED = PLLFEED_FEED2;\r
+       }\r
+       \r
+       /* Disable PLL, disconnected. */\r
+       SC->PLL1CON = 0;                                \r
+       SC->PLL1FEED = PLLFEED_FEED1;\r
+       SC->PLL1FEED = PLLFEED_FEED2;\r
+       \r
+       SC->PLL1CFG = 0x23;\r
+       SC->PLL1FEED = PLLFEED_FEED1;\r
+       SC->PLL1FEED = PLLFEED_FEED2;\r
+       \r
+       /* Enable PLL, disconnected. */\r
+       SC->PLL1CON = 1;                                \r
+       SC->PLL1FEED = PLLFEED_FEED1;\r
+       SC->PLL1FEED = PLLFEED_FEED2;\r
+       while( ( ( SC->PLL1STAT & ( 1 << 10 ) ) == 0 ) );\r
+       \r
+       /* Enable and connect. */\r
+       SC->PLL1CON = 3;                                \r
+       SC->PLL1FEED = PLLFEED_FEED1;\r
+       SC->PLL1FEED = PLLFEED_FEED2;\r
+       while( ( ( SC->PLL1STAT & ( 1 << 9 ) ) == 0 ) );\r
+       \r
+       /*  Setup the peripheral bus to be the same as the PLL output (64 MHz). */\r
+       SC->PCLKSEL0 = 0x05555555;\r
+\r
+       /* Configure the LEDs. */\r
+       vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )\r
+{\r
+       /* This function will get called if a task overflows its stack. */\r
+\r
+       ( void ) pxTask;\r
+       ( void ) pcTaskName;\r
+\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vConfigureTimerForRunTimeStats( void )\r
+{\r
+const unsigned long TCR_COUNT_RESET = 2, CTCR_CTM_TIMER = 0x00, TCR_COUNT_ENABLE = 0x01;\r
+\r
+       /* This function configures a timer that is used as the time base when\r
+       collecting run time statistical information - basically the percentage\r
+       of CPU time that each task is utilising.  It is called automatically when\r
+       the scheduler is started (assuming configGENERATE_RUN_TIME_STATS is set\r
+       to 1). */\r
+\r
+       /* Power up and feed the timer. */\r
+       SC->PCONP |= 0x02UL;\r
+       SC->PCLKSEL0 = (SC->PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);\r
+\r
+       /* Reset Timer 0 */\r
+       TIM0->TCR = TCR_COUNT_RESET;\r
+\r
+       /* Just count up. */\r
+       TIM0->CTCR = CTCR_CTM_TIMER;\r
+\r
+       /* Prescale to a frequency that is good enough to get a decent resolution,\r
+       but not too fast so as to overflow all the time. */\r
+       TIM0->PR =  ( configCPU_CLOCK_HZ / 10000UL ) - 1UL;\r
+\r
+       /* Start the counter. */\r
+       TIM0->TCR = TCR_COUNT_ENABLE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/printf-stdarg.c b/Demo/CORTEX_LPC1768_IAR/printf-stdarg.c
new file mode 100644 (file)
index 0000000..b5ac41b
--- /dev/null
@@ -0,0 +1,293 @@
+/*\r
+       Copyright 2001, 2002 Georges Menie (www.menie.org)\r
+       stdarg version contributed by Christian Ettinger\r
+\r
+    This program is free software; you can redistribute it and/or modify\r
+    it under the terms of the GNU Lesser General Public License as published by\r
+    the Free Software Foundation; either version 2 of the License, or\r
+    (at your option) any later version.\r
+\r
+    This program is distributed in the hope that it will be useful,\r
+    but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+    GNU Lesser General Public License for more details.\r
+\r
+    You should have received a copy of the GNU Lesser General Public License\r
+    along with this program; if not, write to the Free Software\r
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+*/\r
+\r
+/*\r
+       putchar is the only external dependency for this file,\r
+       if you have a working putchar, leave it commented out.\r
+       If not, uncomment the define below and\r
+       replace outbyte(c) by your own function call.\r
+\r
+*/\r
+\r
+#define putchar(c) c\r
+\r
+#include <stdarg.h>\r
+\r
+static void printchar(char **str, int c)\r
+{\r
+       //extern int putchar(int c);\r
+       \r
+       if (str) {\r
+               **str = (char)c;\r
+               ++(*str);\r
+       }\r
+       else\r
+       { \r
+               (void)putchar(c);\r
+       }\r
+}\r
+\r
+#define PAD_RIGHT 1\r
+#define PAD_ZERO 2\r
+\r
+static int prints(char **out, const char *string, int width, int pad)\r
+{\r
+       register int pc = 0, padchar = ' ';\r
+\r
+       if (width > 0) {\r
+               register int len = 0;\r
+               register const char *ptr;\r
+               for (ptr = string; *ptr; ++ptr) ++len;\r
+               if (len >= width) width = 0;\r
+               else width -= len;\r
+               if (pad & PAD_ZERO) padchar = '0';\r
+       }\r
+       if (!(pad & PAD_RIGHT)) {\r
+               for ( ; width > 0; --width) {\r
+                       printchar (out, padchar);\r
+                       ++pc;\r
+               }\r
+       }\r
+       for ( ; *string ; ++string) {\r
+               printchar (out, *string);\r
+               ++pc;\r
+       }\r
+       for ( ; width > 0; --width) {\r
+               printchar (out, padchar);\r
+               ++pc;\r
+       }\r
+\r
+       return pc;\r
+}\r
+\r
+/* the following should be enough for 32 bit int */\r
+#define PRINT_BUF_LEN 12\r
+\r
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)\r
+{\r
+       char print_buf[PRINT_BUF_LEN];\r
+       register char *s;\r
+       register int t, neg = 0, pc = 0;\r
+       register unsigned int u = (unsigned int)i;\r
+\r
+       if (i == 0) {\r
+               print_buf[0] = '0';\r
+               print_buf[1] = '\0';\r
+               return prints (out, print_buf, width, pad);\r
+       }\r
+\r
+       if (sg && b == 10 && i < 0) {\r
+               neg = 1;\r
+               u = (unsigned int)-i;\r
+       }\r
+\r
+       s = print_buf + PRINT_BUF_LEN-1;\r
+       *s = '\0';\r
+\r
+       while (u) {\r
+               t = (unsigned int)u % b;\r
+               if( t >= 10 )\r
+                       t += letbase - '0' - 10;\r
+               *--s = (char)(t + '0');\r
+               u /= b;\r
+       }\r
+\r
+       if (neg) {\r
+               if( width && (pad & PAD_ZERO) ) {\r
+                       printchar (out, '-');\r
+                       ++pc;\r
+                       --width;\r
+               }\r
+               else {\r
+                       *--s = '-';\r
+               }\r
+       }\r
+\r
+       return pc + prints (out, s, width, pad);\r
+}\r
+\r
+static int print( char **out, const char *format, va_list args )\r
+{\r
+       register int width, pad;\r
+       register int pc = 0;\r
+       char scr[2];\r
+\r
+       for (; *format != 0; ++format) {\r
+               if (*format == '%') {\r
+                       ++format;\r
+                       width = pad = 0;\r
+                       if (*format == '\0') break;\r
+                       if (*format == '%') goto out;\r
+                       if (*format == '-') {\r
+                               ++format;\r
+                               pad = PAD_RIGHT;\r
+                       }\r
+                       while (*format == '0') {\r
+                               ++format;\r
+                               pad |= PAD_ZERO;\r
+                       }\r
+                       for ( ; *format >= '0' && *format <= '9'; ++format) {\r
+                               width *= 10;\r
+                               width += *format - '0';\r
+                       }\r
+                       if( *format == 's' ) {\r
+                               register char *s = (char *)va_arg( args, int );\r
+                               pc += prints (out, s?s:"(null)", width, pad);\r
+                               continue;\r
+                       }\r
+                       if( *format == 'd' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'x' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'X' ) {\r
+                               pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'u' ) {\r
+                               pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');\r
+                               continue;\r
+                       }\r
+                       if( *format == 'c' ) {\r
+                               /* char are converted to int then pushed on the stack */\r
+                               scr[0] = (char)va_arg( args, int );\r
+                               scr[1] = '\0';\r
+                               pc += prints (out, scr, width, pad);\r
+                               continue;\r
+                       }\r
+               }\r
+               else {\r
+               out:\r
+                       printchar (out, *format);\r
+                       ++pc;\r
+               }\r
+       }\r
+       if (out) **out = '\0';\r
+       va_end( args );\r
+       return pc;\r
+}\r
+\r
+int printf(const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( 0, format, args );\r
+}\r
+\r
+int sprintf(char *out, const char *format, ...)\r
+{\r
+        va_list args;\r
+        \r
+        va_start( args, format );\r
+        return print( &out, format, args );\r
+}\r
+\r
+\r
+int snprintf( char *buf, unsigned int count, const char *format, ... )\r
+{\r
+        va_list args;\r
+        \r
+        ( void ) count;\r
+        \r
+        va_start( args, format );\r
+        return print( &buf, format, args );\r
+}\r
+\r
+\r
+#ifdef TEST_PRINTF\r
+int main(void)\r
+{\r
+       char *ptr = "Hello world!";\r
+       char *np = 0;\r
+       int i = 5;\r
+       unsigned int bs = sizeof(int)*8;\r
+       int mi;\r
+       char buf[80];\r
+\r
+       mi = (1 << (bs-1)) + 1;\r
+       printf("%s\n", ptr);\r
+       printf("printf test\n");\r
+       printf("%s is null pointer\n", np);\r
+       printf("%d = 5\n", i);\r
+       printf("%d = - max int\n", mi);\r
+       printf("char %c = 'a'\n", 'a');\r
+       printf("hex %x = ff\n", 0xff);\r
+       printf("hex %02x = 00\n", 0);\r
+       printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);\r
+       printf("%d %s(s)%", 0, "message");\r
+       printf("\n");\r
+       printf("%d %s(s) with %%\n", 0, "message");\r
+       sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);\r
+       sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);\r
+       sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);\r
+       sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);\r
+       sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);\r
+\r
+       return 0;\r
+}\r
+\r
+/*\r
+ * if you compile this file with\r
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c\r
+ * you will get a normal warning:\r
+ *   printf.c:214: warning: spurious trailing `%' in format\r
+ * this line is testing an invalid % at the end of the format string.\r
+ *\r
+ * this should display (on 32bit int machine) :\r
+ *\r
+ * Hello world!\r
+ * printf test\r
+ * (null) is null pointer\r
+ * 5 = 5\r
+ * -2147483647 = - max int\r
+ * char a = 'a'\r
+ * hex ff = ff\r
+ * hex 00 = 00\r
+ * signed -3 = unsigned 4294967293 = hex fffffffd\r
+ * 0 message(s)\r
+ * 0 message(s) with %\r
+ * justif: "left      "\r
+ * justif: "     right"\r
+ *  3: 0003 zero padded\r
+ *  3: 3    left justif.\r
+ *  3:    3 right justif.\r
+ * -3: -003 zero padded\r
+ * -3: -3   left justif.\r
+ * -3:   -3 right justif.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/* To keep linker happy. */\r
+int    write( int i, char* c, int n)\r
+{\r
+       (void)i;\r
+       (void)n;\r
+       (void)c;\r
+       return 0;\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.cspy.bat b/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.cspy.bat
new file mode 100644 (file)
index 0000000..c96471c
--- /dev/null
@@ -0,0 +1,33 @@
+@REM This bat file has been generated by the IAR Embeddded Workbench\r
+@REM C-SPY interactive debugger,as an aid to preparing a command\r
+@REM line for running the cspybat command line utility with the\r
+@REM appropriate settings.\r
+@REM\r
+@REM After making some adjustments to this file, you can launch cspybat\r
+@REM by typing the name of this file followed by the name of the debug\r
+@REM file (usually an ubrof file). Note that this file is generated\r
+@REM every time a new debug session is initialized, so you may want to\r
+@REM move or rename the file before making changes.\r
+@REM\r
+@REM Note: some command line arguments cannot be properly generated\r
+@REM by this process. Specifically, the plugin which is responsible\r
+@REM for the Terminal I/O window (and other C runtime functionality)\r
+@REM comes in a special version for cspybat, and the name of that\r
+@REM plugin dll is not known when generating this file. It resides in\r
+@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or\r
+@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding\r
+@REM tool chain. Replace the '<libsupport_plugin>' parameter\r
+@REM below with the appropriate file name. Other plugins loaded by\r
+@REM C-SPY are usually not needed by, or will not work in, cspybat\r
+@REM but they are listed at the end of this file for reference.\r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 5.4\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armjlink.dll"  %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\<libsupport_plugin>" --macro "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\Flash.mac" --backend -B "--endian=little" "--cpu=Cortex-M3" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\CONFIG\debugger\NXP\iolpc1768.ddf" "--drv_verify_download" "--semihosting=none" "--device=LPC1768" "-d" "jlink" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" \r
+\r
+\r
+@REM Loaded plugins:\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\arm\bin\armlibsupport.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\CodeCoverage\CodeCoverage.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\Profiling\Profiling.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\stack\stack.dll\r
+@REM    C:\devtools\IAR Systems\Embedded Workbench 5.4\common\plugins\SymList\SymList.dll\r
diff --git a/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dbgdt
new file mode 100644 (file)
index 0000000..f2b037c
--- /dev/null
@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+  <Desktop>\r
+    <Static>\r
+      <Debug-Log>\r
+        \r
+        \r
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1342</ColumnWidth1></Debug-Log>\r
+      <Build>\r
+        <ColumnWidth0>20</ColumnWidth0>\r
+        <ColumnWidth1>1006</ColumnWidth1>\r
+        <ColumnWidth2>268</ColumnWidth2>\r
+        <ColumnWidth3>67</ColumnWidth3>\r
+      </Build>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>124</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Disassembly>\r
+        \r
+        \r
+        \r
+      <PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><MixedMode>1</MixedMode><CodeCovShow>0</CodeCovShow><InstrProfShow>0</InstrProfShow></Disassembly>\r
+    <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>100</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></Watch></Static>\r
+    <Windows>\r
+      \r
+      \r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-31842-26703</Identity>\r
+            <TabName>Debug Log</TabName>\r
+            <Factory>Debug-Log</Factory>\r
+            <Session/>\r
+          </Tab>\r
+          <Tab>\r
+            <Identity>TabID-31319-26713</Identity>\r
+            <TabName>Build</TabName>\r
+            <Factory>Build</Factory>\r
+            <Session/>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-9822-26706</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/WEB Server</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\main.c</Filename><XPos>0</XPos><YPos>138</YPos><SelStart>5151</SelStart><SelEnd>5151</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\ARM_CM3\port.c</Filename><XPos>0</XPos><YPos>145</YPos><SelStart>5821</SelStart><SelEnd>5821</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\ParTest.c</Filename><XPos>0</XPos><YPos>76</YPos><SelStart>3467</SelStart><SelEnd>3467</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Source\queue.c</Filename><XPos>0</XPos><YPos>1055</YPos><SelStart>34788</SelStart><SelEnd>34788</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\webserver\emac.c</Filename><XPos>0</XPos><YPos>130</YPos><SelStart>5273</SelStart><SelEnd>5273</SelEnd></Tab><ActiveTab>4</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\webserver\EthDev_LPC17xx.h</Filename><XPos>0</XPos><YPos>282</YPos><SelStart>17892</SelStart><SelEnd>17902</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00abab98><key>iaridepm.enu1</key></Toolbar-00abab98><Toolbar-0673c5d0><key>debuggergui.enu1</key></Toolbar-0673c5d0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>742</Bottom><Right>198</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>756098</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>200</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.dni
new file mode 100644 (file)
index 0000000..23207c4
--- /dev/null
@@ -0,0 +1,48 @@
+[DebugChecksum]\r
+Checksum=1859043743\r
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[InstructionProfiling]\r
+Enabled=_ 0\r
+[CodeCoverage]\r
+Enabled=_ 0\r
+[Profiling]\r
+Enabled=0\r
+[StackPlugin]\r
+Enabled=1\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Interrupts]\r
+Enabled=1\r
+[MemoryMap]\r
+Enabled=0\r
+Base=0\r
+UseAuto=0\r
+TypeViolation=1\r
+UnspecRange=1\r
+ActionState=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[DriverProfiling]\r
+Enabled=0\r
+Source=2\r
+Graph=0\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints]\r
+Count=0\r
diff --git a/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo.wsdt
new file mode 100644 (file)
index 0000000..ff734cf
--- /dev/null
@@ -0,0 +1,67 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>315</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Build>\r
+        \r
+        \r
+        \r
+        \r
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1006</ColumnWidth1><ColumnWidth2>268</ColumnWidth2><ColumnWidth3>67</ColumnWidth3></Build>\r
+      <TerminalIO/>\r
+    <Find-in-Files><ColumnWidth0>482</ColumnWidth0><ColumnWidth1>68</ColumnWidth1><ColumnWidth2>826</ColumnWidth2></Find-in-Files><Debug-Log><ColumnWidth0>19</ColumnWidth0><ColumnWidth1>1343</ColumnWidth1></Debug-Log></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-17246-25544</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-17664-26559</Identity>\r
+            <TabName>Build</TabName>\r
+            <Factory>Build</Factory>\r
+            <Session/>\r
+          </Tab>\r
+        <Tab><Identity>TabID-11527-1227</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-6216-4192</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\main.c</Filename><XPos>0</XPos><YPos>138</YPos><SelStart>5151</SelStart><SelEnd>5151</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Source\portable\IAR\ARM_CM3\port.c</Filename><XPos>0</XPos><YPos>145</YPos><SelStart>5821</SelStart><SelEnd>5821</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\ParTest.c</Filename><XPos>0</XPos><YPos>76</YPos><SelStart>3467</SelStart><SelEnd>3467</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Source\queue.c</Filename><XPos>0</XPos><YPos>1055</YPos><SelStart>34788</SelStart><SelEnd>34788</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\webserver\emac.c</Filename><XPos>0</XPos><YPos>130</YPos><SelStart>5273</SelStart><SelEnd>5273</SelEnd></Tab><ActiveTab>4</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\CORTEX_LPC1768_IAR\webserver\EthDev_LPC17xx.h</Filename><XPos>0</XPos><YPos>282</YPos><SelStart>17892</SelStart><SelEnd>17902</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00abab98><key>iaridepm.enu1</key></Toolbar-00abab98></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>640</Bottom><Right>389</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>203252</sizeHorzCY><sizeVertCX>279286</sizeVertCX><sizeVertCY>652439</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>300</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>302</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>306911</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>203252</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo_Debug.jlink b/Demo/CORTEX_LPC1768_IAR/settings/RTOSDemo_Debug.jlink
new file mode 100644 (file)
index 0000000..e499187
--- /dev/null
@@ -0,0 +1,14 @@
+[FLASH]\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="ADUC7020X62"\r
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
diff --git a/Demo/CORTEX_LPC1768_IAR/system_LPC17xx.h b/Demo/CORTEX_LPC1768_IAR/system_LPC17xx.h
new file mode 100644 (file)
index 0000000..a5c9727
--- /dev/null
@@ -0,0 +1,40 @@
+/******************************************************************************\r
+ * @file:    system_LPC17xx.h\r
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File\r
+ *           for the NXP LPC17xx Device Series \r
+ * @version: V1.0\r
+ * @date:    25. Nov. 2008\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2008 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 \r
+ * processor based microcontrollers.  This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+#ifndef __SYSTEM_LPC17xx_H\r
+#define __SYSTEM_LPC17xx_H\r
+\r
+extern uint32_t SystemFrequency;    /*!< System Clock Frequency (Core Clock)  */\r
+\r
+\r
+/**\r
+ * Initialize the system\r
+ *\r
+ * @param  none\r
+ * @return none\r
+ *\r
+ * @brief  Setup the microcontroller system.\r
+ *         Initialize the System and update the SystemFrequency variable.\r
+ */\r
+extern void SystemInit (void);\r
+#endif\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/EthDev.h b/Demo/CORTEX_LPC1768_IAR/webserver/EthDev.h
new file mode 100644 (file)
index 0000000..f67789f
--- /dev/null
@@ -0,0 +1,111 @@
+/*\r
+ * @file:    EthDev.h\r
+ * @purpose: Ethernet Device Definitions\r
+ * @version: V1.10\r
+ * @date:    24. Feb. 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
+ * processor based microcontrollers.  This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ */\r
+\r
+#ifndef _ETHDEV__H\r
+#define _ETHDEV__H\r
+\r
+#ifndef NULL\r
+ #define NULL   0\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+  Ethernet Device Defines\r
+ *----------------------------------------------------------------------------*/\r
+#define EthDev_ADDR_SIZE        6                      /*!< Ethernet Address size in bytes */\r
+#define EthDev_MTU_SIZE         1514                   /*!< Maximum Transmission Unit      */\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Ethernet Device Configuration and Control Command Defines\r
+ *----------------------------------------------------------------------------*/\r
+typedef enum {\r
+  EthDev_LINK_DOWN              = 0,                   /*!< Ethernet link not established */\r
+  EthDev_LINK_UP                = 1,                   /*!< Ethernet link established */\r
+} EthDev_LINK;\r
+\r
+typedef enum {\r
+  EthDev_SPEED_10M              = 0,                   /*!< 10.0 Mbps link speed  */\r
+  EthDev_SPEED_100M             = 1,                   /*!< 100.0 Mbps link speed */\r
+  EthDev_SPEED_1000M            = 2,                   /*!< 1.0 Gbps link speed   */\r
+} EthDev_SPEED;\r
+\r
+typedef enum {\r
+  EthDev_DUPLEX_HALF            = 0,                   /*!< Link half duplex */\r
+  EthDev_DUPLEX_FULL            = 1,                   /*!< Link full duplex */\r
+} EthDev_DUPLEX;\r
+\r
+typedef enum {\r
+  EthDev_MODE_AUTO              = 0,\r
+  EthDev_MODE_10M_FULL          = 1,\r
+  EthDev_MODE_10M_HALF          = 2,\r
+  EthDev_MODE_100M_FULL         = 3,\r
+  EthDev_MODE_100M_HALF         = 4,\r
+  EthDev_MODE_1000M_FULL        = 5,\r
+  EthDev_MODE_1000M_HALF        = 6,\r
+} EthDev_MODE;\r
+\r
+typedef struct {\r
+  EthDev_LINK   Link   : 1;\r
+  EthDev_DUPLEX Duplex : 1;\r
+  EthDev_SPEED  Speed  : 2;\r
+} EthDev_STATUS;\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+  Ethernet Device IO Block Structure\r
+ *----------------------------------------------------------------------------*/\r
+typedef struct {\r
+\r
+   /* Initialized by the user application before call to Init. */\r
+   EthDev_MODE   Mode;\r
+   unsigned char HwAddr[EthDev_ADDR_SIZE];\r
+   void         *(*RxFrame)      (int size);\r
+   void          (*RxFrameReady) (int size);\r
+\r
+   /* Initialized by Ethernet driver. */\r
+   int           (*Init)       (void);\r
+   int           (*UnInit)     (void);\r
+   int           (*SetMCFilter)(int NumHwAddr, unsigned char *pHwAddr);\r
+   int           (*TxFrame)    (void *pData, int size);\r
+   void          (*Lock)       (void);\r
+   void          (*UnLock)     (void);\r
+   EthDev_STATUS (*LinkChk)    (void);\r
+} EthDev_IOB;\r
+\r
+\r
+/*\r
+ * Look for received data.  If data is found then uip_buf is assigned to the\r
+ * new data and the length of the data is returned.  If no data is found then\r
+ * uip_buf is not updated and 0 is returned.\r
+ */\r
+unsigned long  ulGetEMACRxData( void );\r
+\r
+/*\r
+ * Send usTxDataLen bytes from uip_buf.\r
+ */\r
+void vSendEMACTxData( unsigned short usTxDataLen );\r
+\r
+/*\r
+ * Prepare the Ethernet hardware ready for TCP/IP comms.\r
+ */\r
+long lEMACInit(void);\r
+\r
+#endif\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/EthDev_LPC17xx.h b/Demo/CORTEX_LPC1768_IAR/webserver/EthDev_LPC17xx.h
new file mode 100644 (file)
index 0000000..03a875c
--- /dev/null
@@ -0,0 +1,321 @@
+/*\r
+ * @file:    EthDev_LPC17xx.h\r
+ * @purpose: Ethernet Device Definitions for NXP LPC17xx\r
+ * @version: V0.01\r
+ * @date:    14. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3\r
+ * processor based microcontrollers.  This file can be freely distributed\r
+ * within development tools that are supporting such ARM based processors.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ */\r
+\r
+#ifndef __ETHDEV_LPC17XX_H\r
+#define __ETHDEV_LPC17XX_H\r
+\r
+#include <stdint.h>\r
+\r
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */\r
+#define NUM_RX_FRAG         3           /* Num.of RX Fragments. */\r
+#define NUM_TX_FRAG         2           /* Num.of TX Fragments. */\r
+#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */\r
+\r
+#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */\r
+\r
+typedef struct {                        /* RX Descriptor struct              */\r
+   uint32_t Packet;\r
+   uint32_t Ctrl;\r
+} RX_DESC_TypeDef;\r
+\r
+typedef struct {                        /* RX Status struct                  */\r
+   uint32_t Info;\r
+   uint32_t HashCRC;\r
+} RX_STAT_TypeDef;\r
+\r
+typedef struct {                        /* TX Descriptor struct              */\r
+   uint32_t Packet;\r
+   uint32_t Ctrl;\r
+} TX_DESC_TypeDef;\r
+\r
+typedef struct {                        /* TX Status struct                  */\r
+   uint32_t Info;\r
+} TX_STAT_TypeDef;\r
+\r
+\r
+/* EMAC variables located in AHB SRAM bank 1*/\r
+#define AHB_SRAM_BANK1_BASE  0x2007c000UL\r
+#define RX_DESC_BASE        (AHB_SRAM_BANK1_BASE         )\r
+#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*(2*4))     /* 2 * uint32_t, see RX_DESC_TypeDef */\r
+#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*(2*4))     /* 2 * uint32_t, see RX_STAT_TypeDef */\r
+#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*(2*4))     /* 2 * uint32_t, see TX_DESC_TypeDef */\r
+#define ETH_BUF_BASE           (TX_STAT_BASE + NUM_TX_FRAG*(1*4))     /* 1 * uint32_t, see TX_STAT_TypeDef */\r
+\r
+/* RX and TX descriptor and status definitions. */\r
+#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))\r
+#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))\r
+#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))\r
+#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))\r
+#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))\r
+#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))\r
+#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))\r
+#define ETH_BUF(i)          ( ETH_BUF_BASE + ETH_FRAG_SIZE*i )\r
+#define ETH_NUM_BUFFERS                ( NUM_TX_FRAG + NUM_RX_FRAG + 1 ) /* There are in fact 2 more buffers than descriptors as the two Tx descriptors use the same buffer to speed up the uip Tx. */\r
+\r
+\r
+/* MAC Configuration Register 1 */\r
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */\r
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */\r
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */\r
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */\r
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */\r
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */\r
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */\r
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */\r
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */\r
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */\r
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */\r
+\r
+/* MAC Configuration Register 2 */\r
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */\r
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */\r
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */\r
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */\r
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */\r
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */\r
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */\r
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */\r
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */\r
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */\r
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */\r
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */\r
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */\r
+\r
+/* Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */\r
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */\r
+\r
+/* Non Back-to-Back Inter-Packet-Gap Register */\r
+#define IPGR_DEF            0x00000012  /* Recommended value                 */\r
+\r
+/* Collision Window/Retry Register */\r
+#define CLRT_DEF            0x0000370F  /* Default value                     */\r
+\r
+/* PHY Support Register */\r
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */\r
+#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */\r
+\r
+/* Test Register */\r
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */\r
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */\r
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */\r
+\r
+/* MII Management Configuration Register */\r
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */\r
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */\r
+#define MCFG_CLK_SEL        0x0000003C  /* Clock Select Mask                 */\r
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */\r
+\r
+/* MII Management Command Register */\r
+#define MCMD_READ           0x00000001  /* MII Read                          */\r
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */\r
+\r
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */\r
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */\r
+\r
+/* MII Management Address Register */\r
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */\r
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */\r
+\r
+/* MII Management Indicators Register */\r
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */\r
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */\r
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */\r
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */\r
+\r
+/* Command Register */\r
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */\r
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */\r
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */\r
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */\r
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */\r
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */\r
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */\r
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */\r
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */\r
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */\r
+\r
+/* Status Register */\r
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */\r
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */\r
+\r
+/* Transmit Status Vector 0 Register */\r
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */\r
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */\r
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */\r
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */\r
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */\r
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */\r
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */\r
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */\r
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */\r
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */\r
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */\r
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */\r
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */\r
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */\r
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */\r
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */\r
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */\r
+\r
+/* Transmit Status Vector 1 Register */\r
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */\r
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */\r
+\r
+/* Receive Status Vector Register */\r
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */\r
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */\r
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */\r
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */\r
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */\r
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */\r
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */\r
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */\r
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */\r
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */\r
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */\r
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */\r
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */\r
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */\r
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */\r
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */\r
+\r
+/* Flow Control Counter Register */\r
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */\r
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */\r
+\r
+/* Flow Control Status Register */\r
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */\r
+\r
+/* Receive Filter Control Register */\r
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */\r
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */\r
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */\r
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */\r
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/\r
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */\r
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */\r
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */\r
+\r
+/* Receive Filter WoL Status/Clear Registers */\r
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */\r
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */\r
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */\r
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */\r
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */\r
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */\r
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */\r
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */\r
+\r
+/* Interrupt Status/Enable/Clear/Set Registers */\r
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */\r
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */\r
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */\r
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */\r
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */\r
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */\r
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */\r
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */\r
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */\r
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */\r
+\r
+/* Power Down Register */\r
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */\r
+\r
+/* RX Descriptor Control Word */\r
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */\r
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */\r
+\r
+/* RX Status Hash CRC Word */\r
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */\r
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */\r
+\r
+/* RX Status Information Word */\r
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */\r
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */\r
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */\r
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */\r
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */\r
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */\r
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */\r
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */\r
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */\r
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */\r
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */\r
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */\r
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */\r
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */\r
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */\r
+\r
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \\r
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)\r
+\r
+/* TX Descriptor Control Word */\r
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */\r
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */\r
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */\r
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */\r
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */\r
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */\r
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */\r
+\r
+/* TX Status Information Word */\r
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */\r
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */\r
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */\r
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */\r
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */\r
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */\r
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */\r
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */\r
+\r
+/* ENET Device Revision ID */\r
+#define OLD_EMAC_MODULE_ID  0x39022000  /* Rev. ID for first rev '-'         */\r
+\r
+/* KSZ8721BL PHY Registers */\r
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */\r
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */\r
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */\r
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */\r
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */\r
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */\r
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */\r
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */\r
+\r
+/* PHY Extended Registers */\r
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */\r
+#define PHY_CTRLER                     0x1f            /* 100BASE-TX-PHY Controller            */\r
+\r
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */\r
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */\r
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */\r
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */\r
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */\r
+#define PHY_AUTO_NEG_COMPLETE 0x0020   /* Auto negotiation have finished.   */\r
+\r
+#define KS8721_DEF_ADR         0x0100      /* Default PHY device address        */\r
+#define KS8721_ID              0x00221619  /* PHY Identifier                    */\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+ * end of file\r
+ *---------------------------------------------------------------------------*/\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/clock-arch.h b/Demo/CORTEX_LPC1768_IAR/webserver/clock-arch.h
new file mode 100644 (file)
index 0000000..cde657b
--- /dev/null
@@ -0,0 +1,42 @@
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+#ifndef __CLOCK_ARCH_H__\r
+#define __CLOCK_ARCH_H__\r
+\r
+#include "FreeRTOS.h"\r
+\r
+typedef unsigned long clock_time_t;\r
+#define CLOCK_CONF_SECOND configTICK_RATE_HZ\r
+\r
+#endif /* __CLOCK_ARCH_H__ */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/emac.c b/Demo/CORTEX_LPC1768_IAR/webserver/emac.c
new file mode 100644 (file)
index 0000000..104aba5
--- /dev/null
@@ -0,0 +1,600 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under\r
+       the terms of the GNU General Public License (version 2) as published by the\r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the\r
+       source code for proprietary components outside of the FreeRTOS kernel.\r
+       Alternative commercial license and support terms are also available upon\r
+       request.  See the licensing section of http://www.FreeRTOS.org for full\r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/* Originally adapted from file written by Andreas Dannenberg.  Supplied with permission. */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* Hardware specific includes. */\r
+#include "EthDev_LPC17xx.h"\r
+\r
+/* Time to wait between each inspection of the link status. */\r
+#define emacWAIT_FOR_LINK_TO_ESTABLISH ( 500 / portTICK_RATE_MS )\r
+\r
+/* Short delay used in several places during the initialisation process. */\r
+#define emacSHORT_DELAY                                   ( 2 )\r
+\r
+/* Hardware specific bit definitions. */\r
+#define emacLINK_ESTABLISHED           ( 0x0020)\r
+#define emacFULL_DUPLEX_ENABLED                ( 0x0010 )\r
+#define emac10BASE_T_MODE                      ( 0x0004 )\r
+#define emacPINSEL2_VALUE                      ( 0x50150105 )\r
+#define emacDIV_44                                     ( 0x28 )\r
+\r
+/* If no buffers are available, then wait this long before looking again.... */\r
+#define emacBUFFER_WAIT_DELAY  ( 3 / portTICK_RATE_MS )\r
+\r
+/* ...and don't look more than this many times. */\r
+#define emacBUFFER_WAIT_ATTEMPTS       ( 30 )\r
+\r
+/* Index to the Tx descriptor that is always used first for every Tx.  The second\r
+descriptor is then used to re-send in order to speed up the uIP Tx process. */\r
+#define emacTX_DESC_INDEX                      ( 0 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Configure both the Rx and Tx descriptors during the init process.\r
+ */\r
+static void prvInitDescriptors( void );\r
+\r
+/*\r
+ * Setup the IO and peripherals required for Ethernet communication.\r
+ */\r
+static void prvSetupEMACHardware( void );\r
+\r
+/*\r
+ * Control the auto negotiate process.\r
+ */\r
+static void prvConfigurePHY( void );\r
+\r
+/*\r
+ * Wait for a link to be established, then setup the PHY according to the link\r
+ * parameters.\r
+ */\r
+static long prvSetupLinkStatus( void );\r
+\r
+/*\r
+ * Search the pool of buffers to find one that is free.  If a buffer is found\r
+ * mark it as in use before returning its address.\r
+ */\r
+static unsigned char *prvGetNextBuffer( void );\r
+\r
+/*\r
+ * Return an allocated buffer to the pool of free buffers.\r
+ */\r
+static void prvReturnBuffer( unsigned char *pucBuffer );\r
+\r
+/*\r
+ * Send lValue to the lPhyReg within the PHY.\r
+ */\r
+static long prvWritePHY( long lPhyReg, long lValue );\r
+\r
+/*\r
+ * Read a value from ucPhyReg within the PHY.  *plStatus will be set to\r
+ * pdFALSE if there is an error.\r
+ */\r
+static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used to wake the uIP task when data arrives. */\r
+extern xSemaphoreHandle xEMACSemaphore;\r
+\r
+/* Each ucBufferInUse index corresponds to a position in the pool of buffers.\r
+If the index contains a 1 then the buffer within pool is in use, if it\r
+contains a 0 then the buffer is free. */\r
+static unsigned char ucBufferInUse[ ETH_NUM_BUFFERS ] = { pdFALSE };\r
+\r
+/* The uip_buffer is not a fixed array, but instead gets pointed to the buffers\r
+allocated within this file. */\r
+unsigned char * uip_buf;\r
+\r
+/* Store the length of the data being sent so the data can be sent twice.  The\r
+value will be set back to 0 once the data has been sent twice. */\r
+static unsigned short usSendLen = 0;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+long lEMACInit( void )\r
+{\r
+long lReturn = pdPASS;\r
+unsigned long ulID1, ulID2;\r
+\r
+       /* Reset peripherals, configure port pins and registers. */\r
+       prvSetupEMACHardware();\r
+\r
+       /* Check the PHY part number is as expected. */\r
+       ulID1 = prvReadPHY( PHY_REG_IDR1, &lReturn );\r
+       ulID2 = prvReadPHY( PHY_REG_IDR2, &lReturn );\r
+       if( ( (ulID1 << 16UL ) | ( ulID2 & 0xFFFFUL ) ) == KS8721_ID )\r
+       {\r
+               /* Set the Ethernet MAC Address registers */\r
+               EMAC->SA0 = ( configMAC_ADDR0 << 8 ) | configMAC_ADDR1;\r
+               EMAC->SA1 = ( configMAC_ADDR2 << 8 ) | configMAC_ADDR3;\r
+               EMAC->SA2 = ( configMAC_ADDR4 << 8 ) | configMAC_ADDR5;\r
+\r
+               /* Initialize Tx and Rx DMA Descriptors */\r
+               prvInitDescriptors();\r
+\r
+               /* Receive broadcast and perfect match packets */\r
+               EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;\r
+\r
+               /* Setup the PHY. */\r
+               prvConfigurePHY();\r
+       }\r
+       else\r
+       {\r
+               lReturn = pdFAIL;\r
+       }\r
+\r
+       /* Check the link status. */\r
+       if( lReturn == pdPASS )\r
+       {\r
+               lReturn = prvSetupLinkStatus();\r
+       }\r
+\r
+       if( lReturn == pdPASS )\r
+       {\r
+               /* Initialise uip_buf to ensure it points somewhere valid. */\r
+               uip_buf = prvGetNextBuffer();\r
+\r
+               /* Reset all interrupts */\r
+               EMAC->IntClear = ( INT_RX_OVERRUN | INT_RX_ERR | INT_RX_FIN | INT_RX_DONE | INT_TX_UNDERRUN | INT_TX_ERR | INT_TX_FIN | INT_TX_DONE | INT_SOFT_INT | INT_WAKEUP );\r
+\r
+               /* Enable receive and transmit mode of MAC Ethernet core */\r
+               EMAC->Command |= ( CR_RX_EN | CR_TX_EN );\r
+               EMAC->MAC1 |= MAC1_REC_EN;\r
+       }\r
+\r
+       return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned char *prvGetNextBuffer( void )\r
+{\r
+long x;\r
+unsigned char *pucReturn = NULL;\r
+unsigned long ulAttempts = 0;\r
+\r
+       while( pucReturn == NULL )\r
+       {\r
+               /* Look through the buffers to find one that is not in use by\r
+               anything else. */\r
+               for( x = 0; x < ETH_NUM_BUFFERS; x++ )\r
+               {\r
+                       if( ucBufferInUse[ x ] == pdFALSE )\r
+                       {\r
+                               ucBufferInUse[ x ] = pdTRUE;\r
+                               pucReturn = ( unsigned char * ) ETH_BUF( x );\r
+                               break;\r
+                       }\r
+               }\r
+\r
+               /* Was a buffer found? */\r
+               if( pucReturn == NULL )\r
+               {\r
+                       ulAttempts++;\r
+\r
+                       if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )\r
+                       {\r
+                               break;\r
+                       }\r
+\r
+                       /* Wait then look again. */\r
+                       vTaskDelay( emacBUFFER_WAIT_DELAY );\r
+               }\r
+       }\r
+\r
+       return pucReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitDescriptors( void )\r
+{\r
+long x, lNextBuffer = 0;\r
+\r
+       for( x = 0; x < NUM_RX_FRAG; x++ )\r
+       {\r
+               /* Allocate the next Ethernet buffer to this descriptor. */\r
+               RX_DESC_PACKET( x ) = ETH_BUF( lNextBuffer );\r
+               RX_DESC_CTRL( x ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 );\r
+               RX_STAT_INFO( x ) = 0;\r
+               RX_STAT_HASHCRC( x ) = 0;\r
+\r
+               /* The Ethernet buffer is now in use. */\r
+               ucBufferInUse[ lNextBuffer ] = pdTRUE;\r
+               lNextBuffer++;\r
+       }\r
+\r
+       /* Set EMAC Receive Descriptor Registers. */\r
+       EMAC->RxDescriptor = RX_DESC_BASE;\r
+       EMAC->RxStatus = RX_STAT_BASE;\r
+       EMAC->RxDescriptorNumber = NUM_RX_FRAG - 1;\r
+\r
+       /* Rx Descriptors Point to 0 */\r
+       EMAC->RxConsumeIndex = 0;\r
+\r
+       /* A buffer is not allocated to the Tx descriptors until they are actually\r
+       used. */\r
+       for( x = 0; x < NUM_TX_FRAG; x++ )\r
+       {\r
+               TX_DESC_PACKET( x ) = ( unsigned long ) NULL;\r
+               TX_DESC_CTRL( x ) = 0;\r
+               TX_STAT_INFO( x ) = 0;\r
+       }\r
+\r
+       /* Set EMAC Transmit Descriptor Registers. */\r
+       EMAC->TxDescriptor = TX_DESC_BASE;\r
+       EMAC->TxStatus = TX_STAT_BASE;\r
+       EMAC->TxDescriptorNumber = NUM_TX_FRAG - 1;\r
+\r
+       /* Tx Descriptors Point to 0 */\r
+       EMAC->TxProduceIndex = 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupEMACHardware( void )\r
+{\r
+unsigned short us;\r
+long x, lDummy;\r
+\r
+       /* Enable P1 Ethernet Pins. */\r
+       PINCON->PINSEL2 = emacPINSEL2_VALUE;\r
+       PINCON->PINSEL3 = ( PINCON->PINSEL3 & ~0x0000000F ) | 0x00000005;\r
+\r
+       /* Power Up the EMAC controller. */\r
+       SC->PCONP |= PCONP_PCENET;\r
+       vTaskDelay( emacSHORT_DELAY );\r
+\r
+       /* Reset all EMAC internal modules. */\r
+       EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;\r
+       EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;\r
+\r
+       /* A short delay after reset. */\r
+       vTaskDelay( emacSHORT_DELAY );\r
+\r
+       /* Initialize MAC control registers. */\r
+       EMAC->MAC1 = MAC1_PASS_ALL;\r
+       EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;\r
+       EMAC->MAXF = ETH_MAX_FLEN;\r
+       EMAC->CLRT = CLRT_DEF;\r
+       EMAC->IPGR = IPGR_DEF;\r
+       EMAC->MCFG = emacDIV_44;\r
+\r
+       /* Enable Reduced MII interface. */\r
+       EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;\r
+\r
+       /* Reset Reduced MII Logic. */\r
+       EMAC->SUPP = SUPP_RES_RMII;\r
+       vTaskDelay( emacSHORT_DELAY );\r
+       EMAC->SUPP = 0;\r
+\r
+       /* Put the PHY in reset mode */\r
+       prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
+       prvWritePHY( PHY_REG_BMCR, MCFG_RES_MII );\r
+\r
+       /* Wait for hardware reset to end. */\r
+       for( x = 0; x < 100; x++ )\r
+       {\r
+               vTaskDelay( emacSHORT_DELAY * 5 );\r
+               us = prvReadPHY( PHY_REG_BMCR, &lDummy );\r
+               if( !( us & MCFG_RES_MII ) )\r
+               {\r
+                       /* Reset complete */\r
+                       break;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvConfigurePHY( void )\r
+{\r
+unsigned short us;\r
+long x, lDummy;\r
+\r
+       /* Auto negotiate the configuration. */\r
+       if( prvWritePHY( PHY_REG_BMCR, PHY_AUTO_NEG ) )\r
+       {\r
+               vTaskDelay( emacSHORT_DELAY * 5 );\r
+\r
+               for( x = 0; x < 10; x++ )\r
+               {\r
+                       us = prvReadPHY( PHY_REG_BMSR, &lDummy );\r
+\r
+                       if( us & PHY_AUTO_NEG_COMPLETE )\r
+                       {\r
+                               break;\r
+                       }\r
+\r
+                       vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static long prvSetupLinkStatus( void )\r
+{\r
+long lReturn = pdFAIL, x;\r
+unsigned short usLinkStatus;\r
+\r
+       /* Wait with timeout for the link to be established. */\r
+       for( x = 0; x < 10; x++ )\r
+       {\r
+               usLinkStatus = prvReadPHY( PHY_CTRLER, &lReturn );\r
+               if( usLinkStatus != 0x00 )\r
+               {\r
+                       /* Link is established. */\r
+                       lReturn = pdPASS;\r
+                       break;\r
+               }\r
+\r
+        vTaskDelay( emacWAIT_FOR_LINK_TO_ESTABLISH );\r
+       }\r
+\r
+       if( lReturn == pdPASS )\r
+       {\r
+               /* Configure Full/Half Duplex mode. */\r
+               if( usLinkStatus & emacFULL_DUPLEX_ENABLED )\r
+               {\r
+                       /* Full duplex is enabled. */\r
+                       EMAC->MAC2 |= MAC2_FULL_DUP;\r
+                       EMAC->Command |= CR_FULL_DUP;\r
+                       EMAC->IPGT = IPGT_FULL_DUP;\r
+               }\r
+               else\r
+               {\r
+                       /* Half duplex mode. */\r
+                       EMAC->IPGT = IPGT_HALF_DUP;\r
+               }\r
+\r
+               /* Configure 100MBit/10MBit mode. */\r
+               if( usLinkStatus & emac10BASE_T_MODE )\r
+               {\r
+                       /* 10MBit mode. */\r
+                       EMAC->SUPP = 0;\r
+               }\r
+               else\r
+               {\r
+                       /* 100MBit mode. */\r
+                       EMAC->SUPP = SUPP_SPEED;\r
+               }\r
+       }\r
+\r
+       return lReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvReturnBuffer( unsigned char *pucBuffer )\r
+{\r
+unsigned long ul;\r
+\r
+       /* Return a buffer to the pool of free buffers. */\r
+       for( ul = 0; ul < ETH_NUM_BUFFERS; ul++ )\r
+       {\r
+               if( ETH_BUF( ul ) == ( unsigned long ) pucBuffer )\r
+               {\r
+                       ucBufferInUse[ ul ] = pdFALSE;\r
+                       break;\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned long ulGetEMACRxData( void )\r
+{\r
+unsigned long ulLen = 0;\r
+long lIndex;\r
+\r
+       if( EMAC->RxProduceIndex != EMAC->RxConsumeIndex )\r
+       {\r
+               /* Mark the current buffer as free as uip_buf is going to be set to\r
+               the buffer that contains the received data. */\r
+               prvReturnBuffer( uip_buf );\r
+\r
+               ulLen = ( RX_STAT_INFO( EMAC->RxConsumeIndex ) & RINFO_SIZE ) - 3;\r
+               uip_buf = ( unsigned char * ) RX_DESC_PACKET( EMAC->RxConsumeIndex );\r
+\r
+               /* Allocate a new buffer to the descriptor. */\r
+        RX_DESC_PACKET( EMAC->RxConsumeIndex ) = ( unsigned long ) prvGetNextBuffer();\r
+\r
+               /* Move the consume index onto the next position, ensuring it wraps to\r
+               the beginning at the appropriate place. */\r
+               lIndex = EMAC->RxConsumeIndex;\r
+\r
+               lIndex++;\r
+               if( lIndex >= NUM_RX_FRAG )\r
+               {\r
+                       lIndex = 0;\r
+               }\r
+\r
+               EMAC->RxConsumeIndex = lIndex;\r
+       }\r
+\r
+       return ulLen;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSendEMACTxData( unsigned short usTxDataLen )\r
+{\r
+unsigned long ulAttempts = 0UL;\r
+\r
+       /* Check to see if the Tx descriptor is free, indicated by its buffer being\r
+       NULL. */\r
+       while( TX_DESC_PACKET( emacTX_DESC_INDEX ) != ( unsigned long ) NULL )\r
+       {\r
+               /* Wait for the Tx descriptor to become available. */\r
+               vTaskDelay( emacBUFFER_WAIT_DELAY );\r
+\r
+               ulAttempts++;\r
+               if( ulAttempts > emacBUFFER_WAIT_ATTEMPTS )\r
+               {\r
+                       /* Something has gone wrong as the Tx descriptor is still in use.\r
+                       Clear it down manually, the data it was sending will probably be\r
+                       lost. */\r
+                       prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );\r
+                       break;\r
+               }\r
+       }\r
+\r
+       /* Setup the Tx descriptor for transmission.  Remember the length of the\r
+       data being sent so the second descriptor can be used to send it again from\r
+       within the ISR. */\r
+       usSendLen = usTxDataLen;\r
+       TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) uip_buf;\r
+       TX_DESC_CTRL( emacTX_DESC_INDEX ) = ( usTxDataLen | TCTRL_LAST | TCTRL_INT );\r
+       EMAC->TxProduceIndex = ( emacTX_DESC_INDEX + 1 );\r
+\r
+       /* uip_buf is being sent by the Tx descriptor.  Allocate a new buffer. */\r
+       uip_buf = prvGetNextBuffer();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static long prvWritePHY( long lPhyReg, long lValue )\r
+{\r
+const long lMaxTime = 10;\r
+long x;\r
+\r
+       EMAC->MADR = KS8721_DEF_ADR | lPhyReg;\r
+       EMAC->MWTD = lValue;\r
+\r
+       x = 0;\r
+       for( x = 0; x < lMaxTime; x++ )\r
+       {\r
+               if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
+               {\r
+                       /* Operation has finished. */\r
+                       break;\r
+               }\r
+\r
+               vTaskDelay( emacSHORT_DELAY );\r
+       }\r
+\r
+       if( x < lMaxTime )\r
+       {\r
+               return pdPASS;\r
+       }\r
+       else\r
+       {\r
+               return pdFAIL;\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static unsigned short prvReadPHY( unsigned char ucPhyReg, long *plStatus )\r
+{\r
+long x;\r
+const long lMaxTime = 10;\r
+\r
+       EMAC->MADR = KS8721_DEF_ADR | ucPhyReg;\r
+       EMAC->MCMD = MCMD_READ;\r
+\r
+       for( x = 0; x < lMaxTime; x++ )\r
+       {\r
+               /* Operation has finished. */\r
+               if( ( EMAC->MIND & MIND_BUSY ) == 0 )\r
+               {\r
+                       break;\r
+               }\r
+\r
+               vTaskDelay( emacSHORT_DELAY );\r
+       }\r
+\r
+       EMAC->MCMD = 0;\r
+\r
+       if( x >= lMaxTime )\r
+       {\r
+               *plStatus = pdFAIL;\r
+       }\r
+\r
+       return( EMAC->MRDD );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vEMAC_ISR( void )\r
+{\r
+unsigned long ulStatus;\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+       ulStatus = EMAC->IntStatus;\r
+\r
+       /* Clear the interrupt. */\r
+       EMAC->IntClear = ulStatus;\r
+\r
+       if( ulStatus & INT_RX_DONE )\r
+       {\r
+               /* Ensure the uIP task is not blocked as data has arrived. */\r
+               xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );\r
+       }\r
+\r
+       if( ulStatus & INT_TX_DONE )\r
+       {\r
+               if( usSendLen > 0 )\r
+               {\r
+                       /* Send the data again, using the second descriptor.  As there are\r
+                       only two descriptors the index is set back to 0. */\r
+                       TX_DESC_PACKET( ( emacTX_DESC_INDEX + 1 ) ) = TX_DESC_PACKET( emacTX_DESC_INDEX );\r
+                       TX_DESC_CTRL( ( emacTX_DESC_INDEX + 1 ) ) = ( usSendLen | TCTRL_LAST | TCTRL_INT );\r
+                       EMAC->TxProduceIndex = ( emacTX_DESC_INDEX );\r
+\r
+                       /* This is the second Tx so set usSendLen to 0 to indicate that the\r
+                       Tx descriptors will be free again. */\r
+                       usSendLen = 0UL;\r
+               }\r
+               else\r
+               {\r
+                       /* The Tx buffer is no longer required. */\r
+                       prvReturnBuffer( ( unsigned char * ) TX_DESC_PACKET( emacTX_DESC_INDEX ) );\r
+            TX_DESC_PACKET( emacTX_DESC_INDEX ) = ( unsigned long ) NULL;\r
+               }\r
+       }\r
+\r
+       portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/http-strings b/Demo/CORTEX_LPC1768_IAR/webserver/http-strings
new file mode 100644 (file)
index 0000000..0d3c30c
--- /dev/null
@@ -0,0 +1,35 @@
+http_http "http://"\r
+http_200 "200 "\r
+http_301 "301 "\r
+http_302 "302 "\r
+http_get "GET "\r
+http_10 "HTTP/1.0"\r
+http_11 "HTTP/1.1"\r
+http_content_type "content-type: "\r
+http_texthtml "text/html"\r
+http_location "location: "\r
+http_host "host: "\r
+http_crnl "\r\n"\r
+http_index_html "/index.html"\r
+http_404_html "/404.html"\r
+http_referer "Referer:"\r
+http_header_200 "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_header_404 "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n"\r
+http_content_type_plain "Content-type: text/plain\r\n\r\n"\r
+http_content_type_html "Content-type: text/html\r\n\r\n"\r
+http_content_type_css  "Content-type: text/css\r\n\r\n"\r
+http_content_type_text "Content-type: text/text\r\n\r\n"\r
+http_content_type_png  "Content-type: image/png\r\n\r\n"\r
+http_content_type_gif  "Content-type: image/gif\r\n\r\n"\r
+http_content_type_jpg  "Content-type: image/jpeg\r\n\r\n"\r
+http_content_type_binary "Content-type: application/octet-stream\r\n\r\n"\r
+http_html ".html"\r
+http_shtml ".shtml"\r
+http_htm ".htm"\r
+http_css ".css"\r
+http_png ".png"\r
+http_gif ".gif"\r
+http_jpg ".jpg"\r
+http_text ".txt"\r
+http_txt ".txt"\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/http-strings.c b/Demo/CORTEX_LPC1768_IAR/webserver/http-strings.c
new file mode 100644 (file)
index 0000000..ef7a41c
--- /dev/null
@@ -0,0 +1,102 @@
+const char http_http[8] = \r
+/* "http://" */\r
+{0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, };\r
+const char http_200[5] = \r
+/* "200 " */\r
+{0x32, 0x30, 0x30, 0x20, };\r
+const char http_301[5] = \r
+/* "301 " */\r
+{0x33, 0x30, 0x31, 0x20, };\r
+const char http_302[5] = \r
+/* "302 " */\r
+{0x33, 0x30, 0x32, 0x20, };\r
+const char http_get[5] = \r
+/* "GET " */\r
+{0x47, 0x45, 0x54, 0x20, };\r
+const char http_10[9] = \r
+/* "HTTP/1.0" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, };\r
+const char http_11[9] = \r
+/* "HTTP/1.1" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x31, };\r
+const char http_content_type[15] = \r
+/* "content-type: " */\r
+{0x63, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, };\r
+const char http_texthtml[10] = \r
+/* "text/html" */\r
+{0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_location[11] = \r
+/* "location: " */\r
+{0x6c, 0x6f, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, };\r
+const char http_host[7] = \r
+/* "host: " */\r
+{0x68, 0x6f, 0x73, 0x74, 0x3a, 0x20, };\r
+const char http_crnl[3] = \r
+/* "\r\n" */\r
+{0xd, 0xa, };\r
+const char http_index_html[12] = \r
+/* "/index.html" */\r
+{0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_404_html[10] = \r
+/* "/404.html" */\r
+{0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_referer[9] = \r
+/* "Referer:" */\r
+{0x52, 0x65, 0x66, 0x65, 0x72, 0x65, 0x72, 0x3a, };\r
+const char http_header_200[84] = \r
+/* "HTTP/1.0 200 OK\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x32, 0x30, 0x30, 0x20, 0x4f, 0x4b, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_header_404[91] = \r
+/* "HTTP/1.0 404 Not found\r\nServer: uIP/1.0 http://www.sics.se/~adam/uip/\r\nConnection: close\r\n" */\r
+{0x48, 0x54, 0x54, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x34, 0x30, 0x34, 0x20, 0x4e, 0x6f, 0x74, 0x20, 0x66, 0x6f, 0x75, 0x6e, 0x64, 0xd, 0xa, 0x53, 0x65, 0x72, 0x76, 0x65, 0x72, 0x3a, 0x20, 0x75, 0x49, 0x50, 0x2f, 0x31, 0x2e, 0x30, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x73, 0x69, 0x63, 0x73, 0x2e, 0x73, 0x65, 0x2f, 0x7e, 0x61, 0x64, 0x61, 0x6d, 0x2f, 0x75, 0x69, 0x70, 0x2f, 0xd, 0xa, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x69, 0x6f, 0x6e, 0x3a, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0xd, 0xa, };\r
+const char http_content_type_plain[29] = \r
+/* "Content-type: text/plain\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x70, 0x6c, 0x61, 0x69, 0x6e, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_html[28] = \r
+/* "Content-type: text/html\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_css [27] = \r
+/* "Content-type: text/css\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x63, 0x73, 0x73, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_text[28] = \r
+/* "Content-type: text/text\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x74, 0x65, 0x78, 0x74, 0x2f, 0x74, 0x65, 0x78, 0x74, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_png [28] = \r
+/* "Content-type: image/png\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x70, 0x6e, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_gif [28] = \r
+/* "Content-type: image/gif\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x67, 0x69, 0x66, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_jpg [29] = \r
+/* "Content-type: image/jpeg\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x69, 0x6d, 0x61, 0x67, 0x65, 0x2f, 0x6a, 0x70, 0x65, 0x67, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_content_type_binary[43] = \r
+/* "Content-type: application/octet-stream\r\n\r\n" */\r
+{0x43, 0x6f, 0x6e, 0x74, 0x65, 0x6e, 0x74, 0x2d, 0x74, 0x79, 0x70, 0x65, 0x3a, 0x20, 0x61, 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x2f, 0x6f, 0x63, 0x74, 0x65, 0x74, 0x2d, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d, 0xd, 0xa, 0xd, 0xa, };\r
+const char http_html[6] = \r
+/* ".html" */\r
+{0x2e, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_shtml[7] = \r
+/* ".shtml" */\r
+{0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, };\r
+const char http_htm[5] = \r
+/* ".htm" */\r
+{0x2e, 0x68, 0x74, 0x6d, };\r
+const char http_css[5] = \r
+/* ".css" */\r
+{0x2e, 0x63, 0x73, 0x73, };\r
+const char http_png[5] = \r
+/* ".png" */\r
+{0x2e, 0x70, 0x6e, 0x67, };\r
+const char http_gif[5] = \r
+/* ".gif" */\r
+{0x2e, 0x67, 0x69, 0x66, };\r
+const char http_jpg[5] = \r
+/* ".jpg" */\r
+{0x2e, 0x6a, 0x70, 0x67, };\r
+const char http_text[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
+const char http_txt[5] = \r
+/* ".txt" */\r
+{0x2e, 0x74, 0x78, 0x74, };\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/http-strings.h b/Demo/CORTEX_LPC1768_IAR/webserver/http-strings.h
new file mode 100644 (file)
index 0000000..acbe7e1
--- /dev/null
@@ -0,0 +1,34 @@
+extern const char http_http[8];\r
+extern const char http_200[5];\r
+extern const char http_301[5];\r
+extern const char http_302[5];\r
+extern const char http_get[5];\r
+extern const char http_10[9];\r
+extern const char http_11[9];\r
+extern const char http_content_type[15];\r
+extern const char http_texthtml[10];\r
+extern const char http_location[11];\r
+extern const char http_host[7];\r
+extern const char http_crnl[3];\r
+extern const char http_index_html[12];\r
+extern const char http_404_html[10];\r
+extern const char http_referer[9];\r
+extern const char http_header_200[84];\r
+extern const char http_header_404[91];\r
+extern const char http_content_type_plain[29];\r
+extern const char http_content_type_html[28];\r
+extern const char http_content_type_css [27];\r
+extern const char http_content_type_text[28];\r
+extern const char http_content_type_png [28];\r
+extern const char http_content_type_gif [28];\r
+extern const char http_content_type_jpg [29];\r
+extern const char http_content_type_binary[43];\r
+extern const char http_html[6];\r
+extern const char http_shtml[7];\r
+extern const char http_htm[5];\r
+extern const char http_css[5];\r
+extern const char http_png[5];\r
+extern const char http_gif[5];\r
+extern const char http_jpg[5];\r
+extern const char http_text[5];\r
+extern const char http_txt[5];\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.c b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.c
new file mode 100644 (file)
index 0000000..dfcedb8
--- /dev/null
@@ -0,0 +1,304 @@
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server script interface\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2001-2006, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.c,v 1.2 2006/06/11 21:46:37 adam Exp $\r
+ *\r
+ */\r
+\r
+#include "uip.h"\r
+#include "psock.h"\r
+#include "httpd.h"\r
+#include "httpd-cgi.h"\r
+#include "httpd-fs.h"\r
+\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+HTTPD_CGI_CALL(file, "file-stats", file_stats);\r
+HTTPD_CGI_CALL(tcp, "tcp-connections", tcp_stats);\r
+HTTPD_CGI_CALL(net, "net-stats", net_stats);\r
+HTTPD_CGI_CALL(rtos, "rtos-stats", rtos_stats );\r
+HTTPD_CGI_CALL(run, "run-time", run_time );\r
+HTTPD_CGI_CALL(io, "led-io", led_io );\r
+\r
+\r
+static const struct httpd_cgi_call *calls[] = { &file, &tcp, &net, &rtos, &run, &io, NULL };\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(nullfunction(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+httpd_cgifunction\r
+httpd_cgi(char *name)\r
+{\r
+  const struct httpd_cgi_call **f;\r
+\r
+  /* Find the matching name in the table, return the function. */\r
+  for(f = calls; *f != NULL; ++f) {\r
+    if(strncmp((*f)->name, name, strlen((*f)->name)) == 0) {\r
+      return (*f)->function;\r
+    }\r
+  }\r
+  return nullfunction;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_file_stats(void *arg)\r
+{\r
+  char *f = (char *)arg;\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE, "%5u", httpd_fs_count(f));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(file_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_file_stats, strchr(ptr, ' ') + 1);\r
+\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static const char closed[] =   /*  "CLOSED",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x45, 0x44, 0};\r
+static const char syn_rcvd[] = /*  "SYN-RCVD",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x52, 0x43, 0x56,\r
+ 0x44,  0};\r
+static const char syn_sent[] = /*  "SYN-SENT",*/\r
+{0x53, 0x59, 0x4e, 0x2d, 0x53, 0x45, 0x4e,\r
+ 0x54,  0};\r
+static const char established[] = /*  "ESTABLISHED",*/\r
+{0x45, 0x53, 0x54, 0x41, 0x42, 0x4c, 0x49, 0x53, 0x48,\r
+ 0x45, 0x44, 0};\r
+static const char fin_wait_1[] = /*  "FIN-WAIT-1",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x31, 0};\r
+static const char fin_wait_2[] = /*  "FIN-WAIT-2",*/\r
+{0x46, 0x49, 0x4e, 0x2d, 0x57, 0x41, 0x49,\r
+ 0x54, 0x2d, 0x32, 0};\r
+static const char closing[] = /*  "CLOSING",*/\r
+{0x43, 0x4c, 0x4f, 0x53, 0x49,\r
+ 0x4e, 0x47, 0};\r
+static const char time_wait[] = /*  "TIME-WAIT,"*/\r
+{0x54, 0x49, 0x4d, 0x45, 0x2d, 0x57, 0x41,\r
+ 0x49, 0x54, 0};\r
+static const char last_ack[] = /*  "LAST-ACK"*/\r
+{0x4c, 0x41, 0x53, 0x54, 0x2d, 0x41, 0x43,\r
+ 0x4b, 0};\r
+\r
+static const char *states[] = {\r
+  closed,\r
+  syn_rcvd,\r
+  syn_sent,\r
+  established,\r
+  fin_wait_1,\r
+  fin_wait_2,\r
+  closing,\r
+  time_wait,\r
+  last_ack};\r
+\r
+\r
+static unsigned short\r
+generate_tcp_stats(void *arg)\r
+{\r
+  struct uip_conn *conn;\r
+  struct httpd_state *s = (struct httpd_state *)arg;\r
+\r
+  conn = &uip_conns[s->count];\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+                "<tr><td>%d</td><td>%u.%u.%u.%u:%u</td><td>%s</td><td>%u</td><td>%u</td><td>%c %c</td></tr>\r\n",\r
+                htons(conn->lport),\r
+                htons(conn->ripaddr[0]) >> 8,\r
+                htons(conn->ripaddr[0]) & 0xff,\r
+                htons(conn->ripaddr[1]) >> 8,\r
+                htons(conn->ripaddr[1]) & 0xff,\r
+                htons(conn->rport),\r
+                states[conn->tcpstateflags & UIP_TS_MASK],\r
+                conn->nrtx,\r
+                conn->timer,\r
+                (uip_outstanding(conn))? '*':' ',\r
+                (uip_stopped(conn))? '!':' ');\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(tcp_stats(struct httpd_state *s, char *ptr))\r
+{\r
+\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  for(s->count = 0; s->count < UIP_CONNS; ++s->count) {\r
+    if((uip_conns[s->count].tcpstateflags & UIP_TS_MASK) != UIP_CLOSED) {\r
+      PSOCK_GENERATOR_SEND(&s->sout, generate_tcp_stats, s);\r
+    }\r
+  }\r
+\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_net_stats(void *arg)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)arg;\r
+  return snprintf((char *)uip_appdata, UIP_APPDATA_SIZE,\r
+                 "%5u\n", ((uip_stats_t *)&uip_stat)[s->count]);\r
+}\r
+\r
+static\r
+PT_THREAD(net_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  ( void ) ptr;\r
+#if UIP_STATISTICS\r
+\r
+  for(s->count = 0; s->count < sizeof(uip_stat) / sizeof(uip_stats_t);\r
+      ++s->count) {\r
+    PSOCK_GENERATOR_SEND(&s->sout, generate_net_stats, s);\r
+  }\r
+\r
+#endif /* UIP_STATISTICS */\r
+\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskList( signed char *pcWriteBuffer );\r
+extern char *pcGetTaskStatusMessage( void );\r
+static char cCountBuf[ 128 ];\r
+long lRefreshCount = 0;\r
+static unsigned short\r
+generate_rtos_stats(void *arg)\r
+{\r
+       ( void ) arg;\r
+       lRefreshCount++;\r
+       sprintf( cCountBuf, "<p><br>Refresh count = %d<p><br>%s", (int)lRefreshCount, pcGetTaskStatusMessage() );\r
+    vTaskList( uip_appdata );\r
+       strcat( uip_appdata, cCountBuf );\r
+\r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(rtos_stats(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_rtos_stats, NULL);\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+char *pcStatus;\r
+unsigned long ulString;\r
+\r
+static unsigned short generate_io_state( void *arg )\r
+{\r
+extern long lParTestGetLEDState( void );\r
+\r
+       ( void ) arg;\r
+\r
+       /* Get the state of the LEDs that are on the FIO1 port. */\r
+       if( lParTestGetLEDState() )\r
+       {\r
+               pcStatus = "";\r
+       }\r
+       else\r
+       {\r
+               pcStatus = "checked";\r
+       }\r
+\r
+       sprintf( uip_appdata,\r
+               "<input type=\"checkbox\" name=\"LED0\" value=\"1\" %s>LED<p><p>", pcStatus );\r
+\r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+extern void vTaskGetRunTimeStats( signed char *pcWriteBuffer );\r
+static unsigned short\r
+generate_runtime_stats(void *arg)\r
+{\r
+       ( void ) arg;\r
+       lRefreshCount++;\r
+       sprintf( cCountBuf, "<p><br>Refresh count = %d", (int)lRefreshCount );\r
+    vTaskGetRunTimeStats( uip_appdata );\r
+       strcat( uip_appdata, cCountBuf );\r
+\r
+       return strlen( uip_appdata );\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static\r
+PT_THREAD(run_time(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_runtime_stats, NULL);\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+\r
+\r
+static PT_THREAD(led_io(struct httpd_state *s, char *ptr))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  ( void ) ptr;\r
+  PSOCK_GENERATOR_SEND(&s->sout, generate_io_state, NULL);\r
+  PSOCK_END(&s->sout);\r
+}\r
+\r
+/** @} */\r
+\r
+\r
+\r
+\r
+\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.h b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-cgi.h
new file mode 100644 (file)
index 0000000..7ae9283
--- /dev/null
@@ -0,0 +1,84 @@
+/**\r
+ * \addtogroup httpd\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server script interface header file\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ *\r
+ */\r
+\r
+\r
+\r
+/*\r
+ * Copyright (c) 2001, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd-cgi.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_CGI_H__\r
+#define __HTTPD_CGI_H__\r
+\r
+#include "psock.h"\r
+#include "httpd.h"\r
+\r
+typedef PT_THREAD((* httpd_cgifunction)(struct httpd_state *, char *));\r
+\r
+httpd_cgifunction httpd_cgi(char *name);\r
+\r
+struct httpd_cgi_call {\r
+  const char *name;\r
+  const httpd_cgifunction function;\r
+};\r
+\r
+/**\r
+ * \brief      HTTPD CGI function declaration\r
+ * \param name The C variable name of the function\r
+ * \param str  The string name of the function, used in the script file\r
+ * \param function A pointer to the function that implements it\r
+ *\r
+ *             This macro is used for declaring a HTTPD CGI\r
+ *             function. This function is then added to the list of\r
+ *             HTTPD CGI functions with the httpd_cgi_add() function.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define HTTPD_CGI_CALL(name, str, function) \\r
+static PT_THREAD(function(struct httpd_state *, char *)); \\r
+static const struct httpd_cgi_call name = {str, function}\r
+\r
+void httpd_cgi_init(void);\r
+#endif /* __HTTPD_CGI_H__ */\r
+\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.c b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.c
new file mode 100644 (file)
index 0000000..dc4aef0
--- /dev/null
@@ -0,0 +1,132 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.c,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-fsdata.h"\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif /* NULL */\r
+\r
+#include "httpd-fsdata.c"\r
+\r
+#if HTTPD_FS_STATISTICS\r
+static u16_t count[HTTPD_FS_NUMFILES];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+/*-----------------------------------------------------------------------------------*/\r
+static u8_t\r
+httpd_fs_strcmp(const char *str1, const char *str2)\r
+{\r
+  u8_t i;\r
+  i = 0;\r
+ loop:\r
+\r
+  if(str2[i] == 0 ||\r
+     str1[i] == '\r' ||\r
+     str1[i] == '\n') {\r
+    return 0;\r
+  }\r
+\r
+  if(str1[i] != str2[i]) {\r
+    return 1;\r
+  }\r
+\r
+\r
+  ++i;\r
+  goto loop;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+int\r
+httpd_fs_open(const char *name, struct httpd_fs_file *file)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+  u16_t i = 0;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+  struct httpd_fsdata_file_noconst *f;\r
+\r
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+      f != NULL;\r
+      f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+    if(httpd_fs_strcmp(name, f->name) == 0) {\r
+      file->data = f->data;\r
+      file->len = f->len;\r
+#if HTTPD_FS_STATISTICS\r
+      ++count[i];\r
+#endif /* HTTPD_FS_STATISTICS */\r
+      return 1;\r
+    }\r
+#if HTTPD_FS_STATISTICS\r
+    ++i;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+  }\r
+  return 0;\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+void\r
+httpd_fs_init(void)\r
+{\r
+#if HTTPD_FS_STATISTICS\r
+  u16_t i;\r
+  for(i = 0; i < HTTPD_FS_NUMFILES; i++) {\r
+    count[i] = 0;\r
+  }\r
+#endif /* HTTPD_FS_STATISTICS */\r
+}\r
+/*-----------------------------------------------------------------------------------*/\r
+#if HTTPD_FS_STATISTICS\r
+u16_t httpd_fs_count\r
+(char *name)\r
+{\r
+  struct httpd_fsdata_file_noconst *f;\r
+  u16_t i;\r
+\r
+  i = 0;\r
+  for(f = (struct httpd_fsdata_file_noconst *)HTTPD_FS_ROOT;\r
+      f != NULL;\r
+      f = (struct httpd_fsdata_file_noconst *)f->next) {\r
+\r
+    if(httpd_fs_strcmp(name, f->name) == 0) {\r
+      return count[i];\r
+    }\r
+    ++i;\r
+  }\r
+  return 0;\r
+}\r
+#endif /* HTTPD_FS_STATISTICS */\r
+/*-----------------------------------------------------------------------------------*/\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.h b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs.h
new file mode 100644 (file)
index 0000000..b594eea
--- /dev/null
@@ -0,0 +1,57 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fs.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FS_H__\r
+#define __HTTPD_FS_H__\r
+\r
+#define HTTPD_FS_STATISTICS 1\r
+\r
+struct httpd_fs_file {\r
+  char *data;\r
+  int len;\r
+};\r
+\r
+/* file must be allocated by caller and will be filled in\r
+   by the function. */\r
+int httpd_fs_open(const char *name, struct httpd_fs_file *file);\r
+\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+u16_t httpd_fs_count(char *name);\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+\r
+void httpd_fs_init(void);\r
+\r
+#endif /* __HTTPD_FS_H__ */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/404.html b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/404.html
new file mode 100644 (file)
index 0000000..43e7f4c
--- /dev/null
@@ -0,0 +1,8 @@
+<html>\r
+  <body bgcolor="white">\r
+    <center>\r
+      <h1>404 - file not found</h1>\r
+      <h3>Go <a href="/">here</a> instead.</h3>\r
+    </center>\r
+  </body>\r
+</html>
\ No newline at end of file
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.html b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.html
new file mode 100644 (file)
index 0000000..4937dc6
--- /dev/null
@@ -0,0 +1,13 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,100)">\r
+<font face="arial">\r
+Loading index.shtml.  Click <a href="index.shtml">here</a> if not automatically redirected.\r
+</font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.shtml b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/index.shtml
new file mode 100644 (file)
index 0000000..29d242c
--- /dev/null
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='index.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Task statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task          State  Priority  Stack #<br>************************************************<br>\r
+%! rtos-stats\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/io.shtml b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/io.shtml
new file mode 100644 (file)
index 0000000..fd0697d
--- /dev/null
@@ -0,0 +1,28 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<b>LED and LCD IO</b><br>\r
+\r
+<p>\r
+\r
+Use the check box to turn on or off the LED, enter text to display on the OLED display, then click "Update IO".\r
+\r
+\r
+<p>\r
+<form name="aForm" action="/io.shtml" method="get">\r
+%! led-io\r
+<p>\r
+<input type="submit" value="Update IO">\r
+</form>\r
+<br><p>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/runtime.shtml b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/runtime.shtml
new file mode 100644 (file)
index 0000000..67cae46
--- /dev/null
@@ -0,0 +1,20 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY onLoad="window.setTimeout(&quot;location.href='runtime.shtml'&quot;,2000)">\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Run-time statistics</h2>\r
+Page will refresh every 2 seconds.<p>\r
+<font face="courier"><pre>Task            Abs Time      % Time<br>****************************************<br>\r
+%! run-time\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/stats.shtml b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/stats.shtml
new file mode 100644 (file)
index 0000000..d95a693
--- /dev/null
@@ -0,0 +1,41 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br><p>\r
+<h2>Network statistics</h2>\r
+<table width="300" border="0">\r
+<tr><td align="left"><font face="courier"><pre>\r
+IP           Packets dropped\r
+             Packets received\r
+             Packets sent\r
+IP errors    IP version/header length\r
+             IP length, high byte\r
+             IP length, low byte\r
+             IP fragments\r
+             Header checksum\r
+             Wrong protocol\r
+ICMP        Packets dropped\r
+             Packets received\r
+             Packets sent\r
+             Type errors\r
+TCP          Packets dropped\r
+             Packets received\r
+             Packets sent\r
+             Checksum errors\r
+             Data packets without ACKs\r
+             Resets\r
+             Retransmissions\r
+            No connection avaliable\r
+            Connection attempts to closed ports\r
+</pre></font></td><td><pre>%! net-stats\r
+</pre></table>\r
+</font>\r
+</body>\r
+</html>\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/tcp.shtml b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fs/tcp.shtml
new file mode 100644 (file)
index 0000000..4105367
--- /dev/null
@@ -0,0 +1,21 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">\r
+<html>\r
+  <head>\r
+    <title>FreeRTOS.org uIP WEB server demo</title>\r
+  </head>\r
+  <BODY>\r
+<font face="arial">\r
+<a href="index.shtml">Task Stats</a> <b>|</b> <a href="runtime.shtml">Run Time Stats</a> <b>|</b> <a href="stats.shtml">TCP Stats</a> <b>|</b> <a href="tcp.shtml">Connections</a> <b>|</b> <a href="http://www.freertos.org/">FreeRTOS.org Homepage</a> <b>|</b> <a href="io.shtml">IO</a>\r
+<br><p>\r
+<hr>\r
+<br>\r
+<h2>Network connections</h2>\r
+<p>\r
+<table>\r
+<tr><th>Local</th><th>Remote</th><th>State</th><th>Retransmissions</th><th>Timer</th><th>Flags</th></tr>\r
+%! tcp-connections\r
+</pre></font>\r
+</font>\r
+</body>\r
+</html>\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.c b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.c
new file mode 100644 (file)
index 0000000..c8b2a80
--- /dev/null
@@ -0,0 +1,557 @@
+static const char data_404_html[] = {\r
+       /* /404.html */\r
+       0x2f, 0x34, 0x30, 0x34, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+       0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, 0x20, 0x20, 0x3c, \r
+       0x62, 0x6f, 0x64, 0x79, 0x20, 0x62, 0x67, 0x63, 0x6f, 0x6c, \r
+       0x6f, 0x72, 0x3d, 0x22, 0x77, 0x68, 0x69, 0x74, 0x65, 0x22, \r
+       0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x63, 0x65, 0x6e, \r
+       0x74, 0x65, 0x72, 0x3e, 0xa, 0x20, 0x20, 0x20, 0x20, 0x20, \r
+       0x20, 0x3c, 0x68, 0x31, 0x3e, 0x34, 0x30, 0x34, 0x20, 0x2d, \r
+       0x20, 0x66, 0x69, 0x6c, 0x65, 0x20, 0x6e, 0x6f, 0x74, 0x20, \r
+       0x66, 0x6f, 0x75, 0x6e, 0x64, 0x3c, 0x2f, 0x68, 0x31, 0x3e, \r
+       0xa, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x3c, 0x68, 0x33, \r
+       0x3e, 0x47, 0x6f, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, \r
+       0x66, 0x3d, 0x22, 0x2f, 0x22, 0x3e, 0x68, 0x65, 0x72, 0x65, \r
+       0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x69, 0x6e, 0x73, 0x74, 0x65, \r
+       0x61, 0x64, 0x2e, 0x3c, 0x2f, 0x68, 0x33, 0x3e, 0xa, 0x20, \r
+       0x20, 0x20, 0x20, 0x3c, 0x2f, 0x63, 0x65, 0x6e, 0x74, 0x65, \r
+       0x72, 0x3e, 0xa, 0x20, 0x20, 0x3c, 0x2f, 0x62, 0x6f, 0x64, \r
+       0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x3e, \r
+0};\r
+\r
+static const char data_index_html[] = {\r
+       /* /index.html */\r
+       0x2f, 0x69, 0x6e, 0x64, 0x65, 0x78, 0x2e, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+       0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+       0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+       0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+       0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+       0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+       0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+       0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+       0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+       0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+       0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+       0x22, 0x3e, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, \r
+       0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x20, \r
+       0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, \r
+       0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, \r
+       0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, 0x57, 0x45, 0x42, \r
+       0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x64, 0x65, \r
+       0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, \r
+       0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+       0xa, 0x20, 0x20, 0x3c, 0x42, 0x4f, 0x44, 0x59, 0x20, 0x6f, \r
+       0x6e, 0x4c, 0x6f, 0x61, 0x64, 0x3d, 0x22, 0x77, 0x69, 0x6e, \r
+       0x64, 0x6f, 0x77, 0x2e, 0x73, 0x65, 0x74, 0x54, 0x69, 0x6d, \r
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+\r
+static const char data_index_shtml[] = {\r
+       /* /index.shtml */\r
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+\r
+static const char data_io_shtml[] = {\r
+       /* /io.shtml */\r
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+\r
+static const char data_runtime_shtml[] = {\r
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+\r
+static const char data_stats_shtml[] = {\r
+       /* /stats.shtml */\r
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+       0x74, 0x6f, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65, 0x64, 0x20, \r
+       0x70, 0x6f, 0x72, 0x74, 0x73, 0xa, 0x3c, 0x2f, 0x70, 0x72, \r
+       0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0x3c, \r
+       0x2f, 0x74, 0x64, 0x3e, 0x3c, 0x74, 0x64, 0x3e, 0x3c, 0x70, \r
+       0x72, 0x65, 0x3e, 0x25, 0x21, 0x20, 0x6e, 0x65, 0x74, 0x2d, \r
+       0x73, 0x74, 0x61, 0x74, 0x73, 0xa, 0x3c, 0x2f, 0x70, 0x72, \r
+       0x65, 0x3e, 0x3c, 0x2f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x3e, \r
+       0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, 0x3c, \r
+       0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, \r
+       0x74, 0x6d, 0x6c, 0x3e, 0xa, 0};\r
+\r
+static const char data_tcp_shtml[] = {\r
+       /* /tcp.shtml */\r
+       0x2f, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0,\r
+       0x3c, 0x21, 0x44, 0x4f, 0x43, 0x54, 0x59, 0x50, 0x45, 0x20, \r
+       0x48, 0x54, 0x4d, 0x4c, 0x20, 0x50, 0x55, 0x42, 0x4c, 0x49, \r
+       0x43, 0x20, 0x22, 0x2d, 0x2f, 0x2f, 0x57, 0x33, 0x43, 0x2f, \r
+       0x2f, 0x44, 0x54, 0x44, 0x20, 0x48, 0x54, 0x4d, 0x4c, 0x20, \r
+       0x34, 0x2e, 0x30, 0x31, 0x20, 0x54, 0x72, 0x61, 0x6e, 0x73, \r
+       0x69, 0x74, 0x69, 0x6f, 0x6e, 0x61, 0x6c, 0x2f, 0x2f, 0x45, \r
+       0x4e, 0x22, 0x20, 0x22, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, \r
+       0x2f, 0x77, 0x77, 0x77, 0x2e, 0x77, 0x33, 0x2e, 0x6f, 0x72, \r
+       0x67, 0x2f, 0x54, 0x52, 0x2f, 0x68, 0x74, 0x6d, 0x6c, 0x34, \r
+       0x2f, 0x6c, 0x6f, 0x6f, 0x73, 0x65, 0x2e, 0x64, 0x74, 0x64, \r
+       0x22, 0x3e, 0xa, 0x3c, 0x68, 0x74, 0x6d, 0x6c, 0x3e, 0xa, \r
+       0x20, 0x20, 0x3c, 0x68, 0x65, 0x61, 0x64, 0x3e, 0xa, 0x20, \r
+       0x20, 0x20, 0x20, 0x3c, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, \r
+       0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, 0x53, 0x2e, 0x6f, \r
+       0x72, 0x67, 0x20, 0x75, 0x49, 0x50, 0x20, 0x57, 0x45, 0x42, \r
+       0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x64, 0x65, \r
+       0x6d, 0x6f, 0x3c, 0x2f, 0x74, 0x69, 0x74, 0x6c, 0x65, 0x3e, \r
+       0xa, 0x20, 0x20, 0x3c, 0x2f, 0x68, 0x65, 0x61, 0x64, 0x3e, \r
+       0xa, 0x20, 0x20, 0x3c, 0x42, 0x4f, 0x44, 0x59, 0x3e, 0xa, \r
+       0x3c, 0x66, 0x6f, 0x6e, 0x74, 0x20, 0x66, 0x61, 0x63, 0x65, \r
+       0x3d, 0x22, 0x61, 0x72, 0x69, 0x61, 0x6c, 0x22, 0x3e, 0xa, \r
+       0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, \r
+       0x6e, 0x64, 0x65, 0x78, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, \r
+       0x22, 0x3e, 0x54, 0x61, 0x73, 0x6b, 0x20, 0x53, 0x74, 0x61, \r
+       0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, \r
+       0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, \r
+       0x72, 0x65, 0x66, 0x3d, 0x22, 0x72, 0x75, 0x6e, 0x74, 0x69, \r
+       0x6d, 0x65, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+       0x52, 0x75, 0x6e, 0x20, 0x54, 0x69, 0x6d, 0x65, 0x20, 0x53, \r
+       0x74, 0x61, 0x74, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+       0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+       0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x73, 0x74, 0x61, \r
+       0x74, 0x73, 0x2e, 0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, \r
+       0x54, 0x43, 0x50, 0x20, 0x53, 0x74, 0x61, 0x74, 0x73, 0x3c, \r
+       0x2f, 0x61, 0x3e, 0x20, 0x3c, 0x62, 0x3e, 0x7c, 0x3c, 0x2f, \r
+       0x62, 0x3e, 0x20, 0x3c, 0x61, 0x20, 0x68, 0x72, 0x65, 0x66, \r
+       0x3d, 0x22, 0x74, 0x63, 0x70, 0x2e, 0x73, 0x68, 0x74, 0x6d, \r
+       0x6c, 0x22, 0x3e, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63, 0x74, \r
+       0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+       0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+       0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x68, 0x74, 0x74, \r
+       0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x66, 0x72, \r
+       0x65, 0x65, 0x72, 0x74, 0x6f, 0x73, 0x2e, 0x6f, 0x72, 0x67, \r
+       0x2f, 0x22, 0x3e, 0x46, 0x72, 0x65, 0x65, 0x52, 0x54, 0x4f, \r
+       0x53, 0x2e, 0x6f, 0x72, 0x67, 0x20, 0x48, 0x6f, 0x6d, 0x65, \r
+       0x70, 0x61, 0x67, 0x65, 0x3c, 0x2f, 0x61, 0x3e, 0x20, 0x3c, \r
+       0x62, 0x3e, 0x7c, 0x3c, 0x2f, 0x62, 0x3e, 0x20, 0x3c, 0x61, \r
+       0x20, 0x68, 0x72, 0x65, 0x66, 0x3d, 0x22, 0x69, 0x6f, 0x2e, \r
+       0x73, 0x68, 0x74, 0x6d, 0x6c, 0x22, 0x3e, 0x49, 0x4f, 0x3c, \r
+       0x2f, 0x61, 0x3e, 0xa, 0x3c, 0x62, 0x72, 0x3e, 0x3c, 0x70, \r
+       0x3e, 0xa, 0x3c, 0x68, 0x72, 0x3e, 0xa, 0x3c, 0x62, 0x72, \r
+       0x3e, 0xa, 0x3c, 0x68, 0x32, 0x3e, 0x4e, 0x65, 0x74, 0x77, \r
+       0x6f, 0x72, 0x6b, 0x20, 0x63, 0x6f, 0x6e, 0x6e, 0x65, 0x63, \r
+       0x74, 0x69, 0x6f, 0x6e, 0x73, 0x3c, 0x2f, 0x68, 0x32, 0x3e, \r
+       0xa, 0x3c, 0x70, 0x3e, 0xa, 0x3c, 0x74, 0x61, 0x62, 0x6c, \r
+       0x65, 0x3e, 0xa, 0x3c, 0x74, 0x72, 0x3e, 0x3c, 0x74, 0x68, \r
+       0x3e, 0x4c, 0x6f, 0x63, 0x61, 0x6c, 0x3c, 0x2f, 0x74, 0x68, \r
+       0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x6d, 0x6f, 0x74, \r
+       0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, \r
+       0x53, 0x74, 0x61, 0x74, 0x65, 0x3c, 0x2f, 0x74, 0x68, 0x3e, \r
+       0x3c, 0x74, 0x68, 0x3e, 0x52, 0x65, 0x74, 0x72, 0x61, 0x6e, \r
+       0x73, 0x6d, 0x69, 0x73, 0x73, 0x69, 0x6f, 0x6e, 0x73, 0x3c, \r
+       0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, 0x68, 0x3e, 0x54, 0x69, \r
+       0x6d, 0x65, 0x72, 0x3c, 0x2f, 0x74, 0x68, 0x3e, 0x3c, 0x74, \r
+       0x68, 0x3e, 0x46, 0x6c, 0x61, 0x67, 0x73, 0x3c, 0x2f, 0x74, \r
+       0x68, 0x3e, 0x3c, 0x2f, 0x74, 0x72, 0x3e, 0xa, 0x25, 0x21, \r
+       0x20, 0x74, 0x63, 0x70, 0x2d, 0x63, 0x6f, 0x6e, 0x6e, 0x65, \r
+       0x63, 0x74, 0x69, 0x6f, 0x6e, 0x73, 0xa, 0x3c, 0x2f, 0x70, \r
+       0x72, 0x65, 0x3e, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, \r
+       0xa, 0x3c, 0x2f, 0x66, 0x6f, 0x6e, 0x74, 0x3e, 0xa, 0x3c, \r
+       0x2f, 0x62, 0x6f, 0x64, 0x79, 0x3e, 0xa, 0x3c, 0x2f, 0x68, \r
+       0x74, 0x6d, 0x6c, 0x3e, 0xa, 0xa, 0};\r
+\r
+const struct httpd_fsdata_file file_404_html[] = {{NULL, data_404_html, data_404_html + 10, sizeof(data_404_html) - 10, 0}};\r
+\r
+const struct httpd_fsdata_file file_index_html[] = {{file_404_html, data_index_html, data_index_html + 12, sizeof(data_index_html) - 12, 0}};\r
+\r
+const struct httpd_fsdata_file file_index_shtml[] = {{file_index_html, data_index_shtml, data_index_shtml + 13, sizeof(data_index_shtml) - 13, 0}};\r
+\r
+const struct httpd_fsdata_file file_io_shtml[] = {{file_index_shtml, data_io_shtml, data_io_shtml + 10, sizeof(data_io_shtml) - 10, 0}};\r
+\r
+const struct httpd_fsdata_file file_runtime_shtml[] = {{file_io_shtml, data_runtime_shtml, data_runtime_shtml + 15, sizeof(data_runtime_shtml) - 15, 0}};\r
+\r
+const struct httpd_fsdata_file file_stats_shtml[] = {{file_runtime_shtml, data_stats_shtml, data_stats_shtml + 13, sizeof(data_stats_shtml) - 13, 0}};\r
+\r
+const struct httpd_fsdata_file file_tcp_shtml[] = {{file_stats_shtml, data_tcp_shtml, data_tcp_shtml + 11, sizeof(data_tcp_shtml) - 11, 0}};\r
+\r
+#define HTTPD_FS_ROOT file_tcp_shtml\r
+\r
+#define HTTPD_FS_NUMFILES 7\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.h b/Demo/CORTEX_LPC1768_IAR/webserver/httpd-fsdata.h
new file mode 100644 (file)
index 0000000..52d35c2
--- /dev/null
@@ -0,0 +1,64 @@
+/*\r
+ * Copyright (c) 2001, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the lwIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd-fsdata.h,v 1.1 2006/06/07 09:13:08 adam Exp $\r
+ */\r
+#ifndef __HTTPD_FSDATA_H__\r
+#define __HTTPD_FSDATA_H__\r
+\r
+#include "uip.h"\r
+\r
+struct httpd_fsdata_file {\r
+  const struct httpd_fsdata_file *next;\r
+  const char *name;\r
+  const char *data;\r
+  const int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+  u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+struct httpd_fsdata_file_noconst {\r
+  struct httpd_fsdata_file *next;\r
+  char *name;\r
+  char *data;\r
+  int len;\r
+#ifdef HTTPD_FS_STATISTICS\r
+#if HTTPD_FS_STATISTICS == 1\r
+  u16_t count;\r
+#endif /* HTTPD_FS_STATISTICS */\r
+#endif /* HTTPD_FS_STATISTICS */\r
+};\r
+\r
+#endif /* __HTTPD_FSDATA_H__ */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd.c b/Demo/CORTEX_LPC1768_IAR/webserver/httpd.c
new file mode 100644 (file)
index 0000000..c416cc1
--- /dev/null
@@ -0,0 +1,346 @@
+/**\r
+ * \addtogroup apps\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \defgroup httpd Web server\r
+ * @{\r
+ * The uIP web server is a very simplistic implementation of an HTTP\r
+ * server. It can serve web pages and files from a read-only ROM\r
+ * filesystem, and provides a very small scripting language.\r
+\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         Web server\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+\r
+/*\r
+ * Copyright (c) 2004, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * Author: Adam Dunkels <adam@sics.se>\r
+ *\r
+ * $Id: httpd.c,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ */\r
+\r
+#include "uip.h"\r
+#include "httpd.h"\r
+#include "httpd-fs.h"\r
+#include "httpd-cgi.h"\r
+#include "http-strings.h"\r
+\r
+#include <string.h>\r
+\r
+#define STATE_WAITING 0\r
+#define STATE_OUTPUT  1\r
+\r
+#define ISO_nl      0x0a\r
+#define ISO_space   0x20\r
+#define ISO_bang    0x21\r
+#define ISO_percent 0x25\r
+#define ISO_period  0x2e\r
+#define ISO_slash   0x2f\r
+#define ISO_colon   0x3a\r
+\r
+\r
+/*---------------------------------------------------------------------------*/\r
+static unsigned short\r
+generate_part_of_file(void *state)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)state;\r
+\r
+  if(s->file.len > uip_mss()) {\r
+    s->len = uip_mss();\r
+  } else {\r
+    s->len = s->file.len;\r
+  }\r
+  memcpy(uip_appdata, s->file.data, s->len);\r
+  \r
+  return s->len;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_file(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+  \r
+  do {\r
+    PSOCK_GENERATOR_SEND(&s->sout, generate_part_of_file, s);\r
+    s->file.len -= s->len;\r
+    s->file.data += s->len;\r
+  } while(s->file.len > 0);\r
+      \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_part_of_file(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_SEND(&s->sout, s->file.data, s->len);\r
+  \r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+next_scriptstate(struct httpd_state *s)\r
+{\r
+  char *p;\r
+  p = strchr(s->scriptptr, ISO_nl) + 1;\r
+  s->scriptlen -= (unsigned short)(p - s->scriptptr);\r
+  s->scriptptr = p;\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_script(struct httpd_state *s))\r
+{\r
+  char *ptr;\r
+  \r
+  PT_BEGIN(&s->scriptpt);\r
+\r
+\r
+  while(s->file.len > 0) {\r
+\r
+    /* Check if we should start executing a script. */\r
+    if(*s->file.data == ISO_percent &&\r
+       *(s->file.data + 1) == ISO_bang) {\r
+      s->scriptptr = s->file.data + 3;\r
+      s->scriptlen = s->file.len - 3;\r
+      if(*(s->scriptptr - 1) == ISO_colon) {\r
+       httpd_fs_open(s->scriptptr + 1, &s->file);\r
+       PT_WAIT_THREAD(&s->scriptpt, send_file(s));\r
+      } else {\r
+       PT_WAIT_THREAD(&s->scriptpt,\r
+                      httpd_cgi(s->scriptptr)(s, s->scriptptr));\r
+      }\r
+      next_scriptstate(s);\r
+      \r
+      /* The script is over, so we reset the pointers and continue\r
+        sending the rest of the file. */\r
+      s->file.data = s->scriptptr;\r
+      s->file.len = s->scriptlen;\r
+    } else {\r
+      /* See if we find the start of script marker in the block of HTML\r
+        to be sent. */\r
+\r
+      if(s->file.len > uip_mss()) {\r
+       s->len = uip_mss();\r
+      } else {\r
+       s->len = s->file.len;\r
+      }\r
+\r
+      if(*s->file.data == ISO_percent) {\r
+       ptr = strchr(s->file.data + 1, ISO_percent);\r
+      } else {\r
+       ptr = strchr(s->file.data, ISO_percent);\r
+      }\r
+      if(ptr != NULL &&\r
+        ptr != s->file.data) {\r
+       s->len = (int)(ptr - s->file.data);\r
+       if(s->len >= uip_mss()) {\r
+         s->len = uip_mss();\r
+       }\r
+      }\r
+      PT_WAIT_THREAD(&s->scriptpt, send_part_of_file(s));\r
+      s->file.data += s->len;\r
+      s->file.len -= s->len;\r
+      \r
+    }\r
+  }\r
+  \r
+  PT_END(&s->scriptpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(send_headers(struct httpd_state *s, const char *statushdr))\r
+{\r
+  char *ptr;\r
+\r
+  PSOCK_BEGIN(&s->sout);\r
+\r
+  PSOCK_SEND_STR(&s->sout, statushdr);\r
+\r
+  ptr = strrchr(s->filename, ISO_period);\r
+  if(ptr == NULL) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_binary);\r
+  } else if(strncmp(http_html, ptr, 5) == 0 ||\r
+           strncmp(http_shtml, ptr, 6) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_html);\r
+  } else if(strncmp(http_css, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_css);\r
+  } else if(strncmp(http_png, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_png);\r
+  } else if(strncmp(http_gif, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_gif);\r
+  } else if(strncmp(http_jpg, ptr, 4) == 0) {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_jpg);\r
+  } else {\r
+    PSOCK_SEND_STR(&s->sout, http_content_type_plain);\r
+  }\r
+  PSOCK_END(&s->sout);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_output(struct httpd_state *s))\r
+{\r
+  char *ptr;\r
+  \r
+  PT_BEGIN(&s->outputpt);\r
\r
+  if(!httpd_fs_open(s->filename, &s->file)) {\r
+    httpd_fs_open(http_404_html, &s->file);\r
+    strcpy(s->filename, http_404_html);\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_headers(s,\r
+                  http_header_404));\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_file(s));\r
+  } else {\r
+    PT_WAIT_THREAD(&s->outputpt,\r
+                  send_headers(s,\r
+                  http_header_200));\r
+    ptr = strchr(s->filename, ISO_period);\r
+    if(ptr != NULL && strncmp(ptr, http_shtml, 6) == 0) {\r
+      PT_INIT(&s->scriptpt);\r
+      PT_WAIT_THREAD(&s->outputpt, handle_script(s));\r
+    } else {\r
+      PT_WAIT_THREAD(&s->outputpt,\r
+                    send_file(s));\r
+    }\r
+  }\r
+  PSOCK_CLOSE(&s->sout);\r
+  PT_END(&s->outputpt);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static\r
+PT_THREAD(handle_input(struct httpd_state *s))\r
+{\r
+  PSOCK_BEGIN(&s->sin);\r
+\r
+  PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+  \r
+  if(strncmp(s->inputbuf, http_get, 4) != 0) {\r
+    PSOCK_CLOSE_EXIT(&s->sin);\r
+  }\r
+  PSOCK_READTO(&s->sin, ISO_space);\r
+\r
+  if(s->inputbuf[0] != ISO_slash) {\r
+    PSOCK_CLOSE_EXIT(&s->sin);\r
+  }\r
+\r
+  if(s->inputbuf[1] == ISO_space) {\r
+    strncpy(s->filename, http_index_html, sizeof(s->filename));\r
+  } else {\r
+\r
+    s->inputbuf[PSOCK_DATALEN(&s->sin) - 1] = 0;\r
+\r
+    /* Process any form input being sent to the server. */\r
+    {\r
+        extern void vApplicationProcessFormInput( char *pcInputString );\r
+        vApplicationProcessFormInput( s->inputbuf );\r
+    }\r
+\r
+    strncpy(s->filename, &s->inputbuf[0], sizeof(s->filename));\r
+  }\r
+\r
+  /*  httpd_log_file(uip_conn->ripaddr, s->filename);*/\r
+  \r
+  s->state = STATE_OUTPUT;\r
+\r
+  while(1) {\r
+    PSOCK_READTO(&s->sin, ISO_nl);\r
+\r
+    if(strncmp(s->inputbuf, http_referer, 8) == 0) {\r
+      s->inputbuf[PSOCK_DATALEN(&s->sin) - 2] = 0;\r
+      /*      httpd_log(&s->inputbuf[9]);*/\r
+    }\r
+  }\r
+  \r
+  PSOCK_END(&s->sin);\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+static void\r
+handle_connection(struct httpd_state *s)\r
+{\r
+  handle_input(s);\r
+  if(s->state == STATE_OUTPUT) {\r
+    handle_output(s);\r
+  }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+void\r
+httpd_appcall(void)\r
+{\r
+  struct httpd_state *s = (struct httpd_state *)&(uip_conn->appstate);\r
+\r
+  if(uip_closed() || uip_aborted() || uip_timedout()) {\r
+  } else if(uip_connected()) {\r
+    PSOCK_INIT(&s->sin, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+    PSOCK_INIT(&s->sout, s->inputbuf, sizeof(s->inputbuf) - 1);\r
+    PT_INIT(&s->outputpt);\r
+    s->state = STATE_WAITING;\r
+    /*    timer_set(&s->timer, CLOCK_SECOND * 100);*/\r
+    s->timer = 0;\r
+    handle_connection(s);\r
+  } else if(s != NULL) {\r
+    if(uip_poll()) {\r
+      ++s->timer;\r
+      if(s->timer >= 20) {\r
+       uip_abort();\r
+      }\r
+    } else {\r
+      s->timer = 0;\r
+    }\r
+    handle_connection(s);\r
+  } else {\r
+    uip_abort();\r
+  }\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/**\r
+ * \brief      Initialize the web server\r
+ *\r
+ *             This function initializes the web server and should be\r
+ *             called at system boot-up.\r
+ */\r
+void\r
+httpd_init(void)\r
+{\r
+  uip_listen(HTONS(80));\r
+}\r
+/*---------------------------------------------------------------------------*/\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/httpd.h b/Demo/CORTEX_LPC1768_IAR/webserver/httpd.h
new file mode 100644 (file)
index 0000000..7f7a666
--- /dev/null
@@ -0,0 +1,62 @@
+/*\r
+ * Copyright (c) 2001-2005, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack.\r
+ *\r
+ * $Id: httpd.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+\r
+#ifndef __HTTPD_H__\r
+#define __HTTPD_H__\r
+\r
+#include "psock.h"\r
+#include "httpd-fs.h"\r
+\r
+struct httpd_state {\r
+  unsigned char timer;\r
+  struct psock sin, sout;\r
+  struct pt outputpt, scriptpt;\r
+  char inputbuf[50];\r
+  char filename[20];\r
+  char state;\r
+  struct httpd_fs_file file;\r
+  int len;\r
+  char *scriptptr;\r
+  int scriptlen;\r
+  \r
+  unsigned short count;\r
+};\r
+\r
+void httpd_init(void);\r
+void httpd_appcall(void);\r
+\r
+void httpd_log(char *msg);\r
+void httpd_log_file(u16_t *requester, char *file);\r
+\r
+#endif /* __HTTPD_H__ */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/makefsdata b/Demo/CORTEX_LPC1768_IAR/webserver/makefsdata
new file mode 100644 (file)
index 0000000..8d2715a
--- /dev/null
@@ -0,0 +1,78 @@
+#!/usr/bin/perl\r
+\r
+open(OUTPUT, "> httpd-fsdata.c");\r
+\r
+chdir("httpd-fs");\r
+\r
+opendir(DIR, ".");\r
+@files =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+closedir(DIR);\r
+\r
+foreach $file (@files) {  \r
+   \r
+    if(-d $file && $file !~ /^\./) {\r
+       print "Processing directory $file\n";\r
+       opendir(DIR, $file);\r
+       @newfiles =  grep { !/^\./ && !/(CVS|~)/ } readdir(DIR);\r
+       closedir(DIR);\r
+       printf "Adding files @newfiles\n";\r
+       @files = (@files, map { $_ = "$file/$_" } @newfiles);\r
+       next;\r
+    }\r
+}\r
+\r
+foreach $file (@files) {\r
+    if(-f $file) {\r
+       \r
+       print "Adding file $file\n";\r
+       \r
+       open(FILE, $file) || die "Could not open file $file\n";\r
+\r
+       $file =~ s-^-/-;\r
+       $fvar = $file;\r
+       $fvar =~ s-/-_-g;\r
+       $fvar =~ s-\.-_-g;\r
+       # for AVR, add PROGMEM here\r
+       print(OUTPUT "static const unsigned char data".$fvar."[] = {\n");\r
+       print(OUTPUT "\t/* $file */\n\t");\r
+       for($j = 0; $j < length($file); $j++) {\r
+           printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1)));\r
+       }\r
+       printf(OUTPUT "0,\n");\r
+       \r
+       \r
+       $i = 0;        \r
+       while(read(FILE, $data, 1)) {\r
+           if($i == 0) {\r
+               print(OUTPUT "\t");\r
+           }\r
+           printf(OUTPUT "%#02x, ", unpack("C", $data));\r
+           $i++;\r
+           if($i == 10) {\r
+               print(OUTPUT "\n");\r
+               $i = 0;\r
+           }\r
+       }\r
+       print(OUTPUT "0};\n\n");\r
+       close(FILE);\r
+       push(@fvars, $fvar);\r
+       push(@pfiles, $file);\r
+    }\r
+}\r
+\r
+for($i = 0; $i < @fvars; $i++) {\r
+    $file = $pfiles[$i];\r
+    $fvar = $fvars[$i];\r
+\r
+    if($i == 0) {\r
+        $prevfile = "NULL";\r
+    } else {\r
+        $prevfile = "file" . $fvars[$i - 1];\r
+    }\r
+    print(OUTPUT "const struct httpd_fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, ");\r
+    print(OUTPUT "data$fvar + ". (length($file) + 1) .", ");\r
+    print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n");\r
+}\r
+\r
+print(OUTPUT "#define HTTPD_FS_ROOT file$fvars[$i - 1]\n\n");\r
+print(OUTPUT "#define HTTPD_FS_NUMFILES $i\n");\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/makestrings b/Demo/CORTEX_LPC1768_IAR/webserver/makestrings
new file mode 100644 (file)
index 0000000..8a13c6d
--- /dev/null
@@ -0,0 +1,40 @@
+#!/usr/bin/perl\r
+\r
+\r
+sub stringify {\r
+  my $name = shift(@_);\r
+  open(OUTPUTC, "> $name.c");\r
+  open(OUTPUTH, "> $name.h");\r
+  \r
+  open(FILE, "$name");\r
+  \r
+  while(<FILE>) {\r
+    if(/(.+) "(.+)"/) {\r
+      $var = $1;\r
+      $data = $2;\r
+      \r
+      $datan = $data;\r
+      $datan =~ s/\\r/\r/g;\r
+      $datan =~ s/\\n/\n/g;\r
+      $datan =~ s/\\01/\01/g;      \r
+      $datan =~ s/\\0/\0/g;\r
+      \r
+      printf(OUTPUTC "const char $var\[%d] = \n", length($datan) + 1);\r
+      printf(OUTPUTC "/* \"$data\" */\n");\r
+      printf(OUTPUTC "{");\r
+      for($j = 0; $j < length($datan); $j++) {\r
+       printf(OUTPUTC "%#02x, ", unpack("C", substr($datan, $j, 1)));\r
+      }\r
+      printf(OUTPUTC "};\n");\r
+      \r
+      printf(OUTPUTH "extern const char $var\[%d];\n", length($datan) + 1);\r
+      \r
+    }\r
+  }\r
+  close(OUTPUTC);\r
+  close(OUTPUTH);\r
+}\r
+stringify("http-strings");\r
+\r
+exit 0;\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_IAR/webserver/uIP_Task.c
new file mode 100644 (file)
index 0000000..94f0cc1
--- /dev/null
@@ -0,0 +1,264 @@
+/*\r
+       FreeRTOS V5.4.1 - Copyright (C) 2009 Real Time Engineers Ltd.\r
+\r
+       This file is part of the FreeRTOS distribution.\r
+\r
+       FreeRTOS is free software; you can redistribute it and/or modify it     under \r
+       the terms of the GNU General Public License (version 2) as published by the \r
+       Free Software Foundation and modified by the FreeRTOS exception.\r
+       **NOTE** The exception to the GPL is included to allow you to distribute a\r
+       combined work that includes FreeRTOS without being obliged to provide the \r
+       source code for proprietary components outside of the FreeRTOS kernel.  \r
+       Alternative commercial license and support terms are also available upon \r
+       request.  See the licensing section of http://www.FreeRTOS.org for full \r
+       license details.\r
+\r
+       FreeRTOS is distributed in the hope that it will be useful,     but WITHOUT\r
+       ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+       FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
+       more details.\r
+\r
+       You should have received a copy of the GNU General Public License along\r
+       with FreeRTOS; if not, write to the Free Software Foundation, Inc., 59\r
+       Temple Place, Suite 330, Boston, MA  02111-1307  USA.\r
+\r
+\r
+       ***************************************************************************\r
+       *                                                                         *\r
+       * Looking for a quick start?  Then check out the FreeRTOS eBook!          *\r
+       * See http://www.FreeRTOS.org/Documentation for details                   *\r
+       *                                                                         *\r
+       ***************************************************************************\r
+\r
+       1 tab == 4 spaces!\r
+\r
+       Please ensure to read the configuration and relevant port sections of the\r
+       online documentation.\r
+\r
+       http://www.FreeRTOS.org - Documentation, latest information, license and\r
+       contact details.\r
+\r
+       http://www.SafeRTOS.com - A version that is certified for use in safety\r
+       critical systems.\r
+\r
+       http://www.OpenRTOS.com - Commercial support, development, porting,\r
+       licensing and training services.\r
+*/\r
+\r
+/* Standard includes. */\r
+#include <string.h>\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+\r
+/* uip includes. */\r
+#include "uip.h"\r
+#include "uip_arp.h"\r
+#include "httpd.h"\r
+#include "timer.h"\r
+#include "clock-arch.h"\r
+\r
+/* Demo includes. */\r
+#include "EthDev_LPC17xx.h"\r
+#include "EthDev.h"\r
+#include "ParTest.h"\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* How long to wait before attempting to connect the MAC again. */\r
+#define uipINIT_WAIT    ( 100 / portTICK_RATE_MS )\r
+\r
+/* Shortcut to the header within the Rx buffer. */\r
+#define xHeader ((struct uip_eth_hdr *) &uip_buf[ 0 ])\r
+\r
+/* Standard constant. */\r
+#define uipTOTAL_FRAME_HEADER_SIZE     54\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the MAC address in the MAC itself, and in the uIP stack.\r
+ */\r
+static void prvSetMACAddress( void );\r
+\r
+/*\r
+ * Port functions required by the uIP stack.\r
+ */\r
+void clock_init( void );\r
+clock_time_t clock_time( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The semaphore used by the ISR to wake the uIP task. */\r
+xSemaphoreHandle xEMACSemaphore = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void clock_init(void)\r
+{\r
+       /* This is done when the scheduler starts. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+clock_time_t clock_time( void )\r
+{\r
+       return xTaskGetTickCount();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vuIP_Task( void *pvParameters )\r
+{\r
+portBASE_TYPE i;\r
+uip_ipaddr_t xIPAddr;\r
+struct timer periodic_timer, arp_timer;\r
+extern void ( vEMAC_ISR_Wrapper )( void );\r
+\r
+       ( void ) pvParameters;\r
+\r
+       /* Initialise the uIP stack. */\r
+       timer_set( &periodic_timer, configTICK_RATE_HZ / 2 );\r
+       timer_set( &arp_timer, configTICK_RATE_HZ * 10 );\r
+       uip_init();\r
+       uip_ipaddr( xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 );\r
+       uip_sethostaddr( xIPAddr );\r
+       uip_ipaddr( xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 );\r
+       uip_setnetmask( xIPAddr );\r
+       httpd_init();\r
+\r
+       /* Create the semaphore used to wake the uIP task. */\r
+       vSemaphoreCreateBinary( xEMACSemaphore );\r
+\r
+       /* Initialise the MAC. */\r
+       while( lEMACInit() != pdPASS )\r
+    {\r
+        vTaskDelay( uipINIT_WAIT );\r
+    }\r
+\r
+       portENTER_CRITICAL();\r
+       {\r
+               EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE );\r
+\r
+               /* Set the interrupt priority to the max permissible to cause some\r
+               interrupt nesting. */\r
+               NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY );\r
+\r
+               /* Enable the interrupt. */\r
+               NVIC_EnableIRQ( ENET_IRQn );\r
+               prvSetMACAddress();\r
+       }\r
+       portEXIT_CRITICAL();\r
+\r
+\r
+       for( ;; )\r
+       {\r
+               /* Is there received data ready to be processed? */\r
+               uip_len = ulGetEMACRxData();\r
+\r
+               if( ( uip_len > 0 ) && ( uip_buf != NULL ) )\r
+               {\r
+                       /* Standard uIP loop taken from the uIP manual. */\r
+                       if( xHeader->type == htons( UIP_ETHTYPE_IP ) )\r
+                       {\r
+                               uip_arp_ipin();\r
+                               uip_input();\r
+\r
+                               /* If the above function invocation resulted in data that\r
+                               should be sent out on the network, the global variable\r
+                               uip_len is set to a value > 0. */\r
+                               if( uip_len > 0 )\r
+                               {\r
+                                       uip_arp_out();\r
+                                       vSendEMACTxData( uip_len );\r
+                               }\r
+                       }\r
+                       else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) )\r
+                       {\r
+                               uip_arp_arpin();\r
+\r
+                               /* If the above function invocation resulted in data that\r
+                               should be sent out on the network, the global variable\r
+                               uip_len is set to a value > 0. */\r
+                               if( uip_len > 0 )\r
+                               {\r
+                                       vSendEMACTxData( uip_len );\r
+                               }\r
+                       }\r
+               }\r
+               else\r
+               {\r
+                       if( timer_expired( &periodic_timer ) && ( uip_buf != NULL ) )\r
+                       {\r
+                               timer_reset( &periodic_timer );\r
+                               for( i = 0; i < UIP_CONNS; i++ )\r
+                               {\r
+                                       uip_periodic( i );\r
+\r
+                                       /* If the above function invocation resulted in data that\r
+                                       should be sent out on the network, the global variable\r
+                                       uip_len is set to a value > 0. */\r
+                                       if( uip_len > 0 )\r
+                                       {\r
+                                               uip_arp_out();\r
+                                               vSendEMACTxData( uip_len );\r
+                                       }\r
+                               }\r
+\r
+                               /* Call the ARP timer function every 10 seconds. */\r
+                               if( timer_expired( &arp_timer ) )\r
+                               {\r
+                                       timer_reset( &arp_timer );\r
+                                       uip_arp_timer();\r
+                               }\r
+                       }\r
+                       else\r
+                       {\r
+                               /* We did not receive a packet, and there was no periodic\r
+                               processing to perform.  Block for a fixed period.  If a packet\r
+                               is received during this period we will be woken by the ISR\r
+                               giving us the Semaphore. */\r
+                               xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 );\r
+                       }\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetMACAddress( void )\r
+{\r
+struct uip_eth_addr xAddr;\r
+\r
+       /* Configure the MAC address in the uIP stack. */\r
+       xAddr.addr[ 0 ] = configMAC_ADDR0;\r
+       xAddr.addr[ 1 ] = configMAC_ADDR1;\r
+       xAddr.addr[ 2 ] = configMAC_ADDR2;\r
+       xAddr.addr[ 3 ] = configMAC_ADDR3;\r
+       xAddr.addr[ 4 ] = configMAC_ADDR4;\r
+       xAddr.addr[ 5 ] = configMAC_ADDR5;\r
+       uip_setethaddr( xAddr );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationProcessFormInput( portCHAR *pcInputString )\r
+{\r
+char *c;\r
+extern void vParTestSetLEDState( long lState );\r
+\r
+       /* Process the form input sent by the IO page of the served HTML. */\r
+\r
+       c = strstr( pcInputString, "?" );\r
+    if( c )\r
+    {\r
+               /* Turn the FIO1 LED's on or off in accordance with the check box status. */\r
+               if( strstr( c, "LED0=1" ) != NULL )\r
+               {\r
+                       vParTestSetLEDState( pdTRUE );\r
+               }\r
+               else\r
+               {\r
+                       vParTestSetLEDState( pdFALSE );\r
+               }\r
+    }\r
+}\r
+\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/uip-conf.h b/Demo/CORTEX_LPC1768_IAR/webserver/uip-conf.h
new file mode 100644 (file)
index 0000000..b52b23f
--- /dev/null
@@ -0,0 +1,159 @@
+/**\r
+ * \addtogroup uipopt\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * \name Project-specific configuration options\r
+ * @{\r
+ *\r
+ * uIP has a number of configuration options that can be overridden\r
+ * for each project. These are kept in a project-specific uip-conf.h\r
+ * file and all configuration names have the prefix UIP_CONF.\r
+ */\r
+\r
+/*\r
+ * Copyright (c) 2006, Swedish Institute of Computer Science.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the distribution.\r
+ * 3. Neither the name of the Institute nor the names of its contributors\r
+ *    may be used to endorse or promote products derived from this software\r
+ *    without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND\r
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE\r
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\r
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\r
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\r
+ * SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $\r
+ */\r
+\r
+/**\r
+ * \file\r
+ *         An example uIP configuration file\r
+ * \author\r
+ *         Adam Dunkels <adam@sics.se>\r
+ */\r
+\r
+#ifndef __UIP_CONF_H__\r
+#define __UIP_CONF_H__\r
+\r
+#include <stdint.h>\r
+\r
+#define UIP_CONF_EXTERNAL_BUFFER\r
+\r
+/**\r
+ * 8 bit datatype\r
+ *\r
+ * This typedef defines the 8-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint8_t u8_t;\r
+\r
+/**\r
+ * 16 bit datatype\r
+ *\r
+ * This typedef defines the 16-bit type used throughout uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef uint16_t u16_t;\r
+\r
+/**\r
+ * Statistics datatype\r
+ *\r
+ * This typedef defines the dataype used for keeping statistics in\r
+ * uIP.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+typedef unsigned short uip_stats_t;\r
+\r
+/**\r
+ * Maximum number of TCP connections.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_CONNECTIONS 40\r
+\r
+/**\r
+ * Maximum number of listening TCP ports.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_MAX_LISTENPORTS 40\r
+\r
+/**\r
+ * uIP buffer size.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BUFFER_SIZE     1480\r
+\r
+/**\r
+ * CPU byte order.\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_BYTE_ORDER      LITTLE_ENDIAN\r
+\r
+/**\r
+ * Logging on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_LOGGING         0\r
+\r
+/**\r
+ * UDP support on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP             0\r
+\r
+/**\r
+ * UDP checksums on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_UDP_CHECKSUMS   1\r
+\r
+/**\r
+ * uIP statistics on or off\r
+ *\r
+ * \hideinitializer\r
+ */\r
+#define UIP_CONF_STATISTICS      1\r
+\r
+/* Here we include the header file for the application(s) we use in\r
+   our project. */\r
+/*#include "smtp.h"*/\r
+/*#include "hello-world.h"*/\r
+/*#include "telnetd.h"*/\r
+#include "webserver.h"\r
+/*#include "dhcpc.h"*/\r
+/*#include "resolv.h"*/\r
+/*#include "webclient.h"*/\r
+\r
+#endif /* __UIP_CONF_H__ */\r
+\r
+/** @} */\r
+/** @} */\r
diff --git a/Demo/CORTEX_LPC1768_IAR/webserver/webserver.h b/Demo/CORTEX_LPC1768_IAR/webserver/webserver.h
new file mode 100644 (file)
index 0000000..1acb290
--- /dev/null
@@ -0,0 +1,49 @@
+/*\r
+ * Copyright (c) 2002, Adam Dunkels.\r
+ * All rights reserved.\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ * 1. Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
+ * 2. Redistributions in binary form must reproduce the above\r
+ *    copyright notice, this list of conditions and the following\r
+ *    disclaimer in the documentation and/or other materials provided\r
+ *    with the distribution.\r
+ * 3. The name of the author may not be used to endorse or promote\r
+ *    products derived from this software without specific prior\r
+ *    written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\r
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\r
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\r
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ * This file is part of the uIP TCP/IP stack\r
+ *\r
+ * $Id: webserver.h,v 1.2 2006/06/11 21:46:38 adam Exp $\r
+ *\r
+ */\r
+#ifndef __WEBSERVER_H__\r
+#define __WEBSERVER_H__\r
+\r
+#include "httpd.h"\r
+\r
+typedef struct httpd_state uip_tcp_appstate_t;\r
+/* UIP_APPCALL: the name of the application function. This function\r
+   must return void and take no arguments (i.e., C type "void\r
+   appfunc(void)"). */\r
+#ifndef UIP_APPCALL\r
+#define UIP_APPCALL     httpd_appcall\r
+#endif\r
+\r
+\r
+#endif /* __WEBSERVER_H__ */\r